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1 2 marcus.erl
/*------------------------------------------------------------------------
2
 . smc91111.h
3
 . This is a driver for SMSC's 91C111 single-chip Ethernet device.
4
 .
5
 . (C) Copyright 2005
6
 .
7
 . Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
8
 .       Developed by Simple Network Magic Corporation (SNMC)
9
 . Copyright (C) 1996 by Erik Stahlman (ES)
10
 .
11
 . This program is free software; you can redistribute it and/or modify
12
 . it under the terms of the GNU General Public License as published by
13
 . the Free Software Foundation; either version 2 of the License, or
14
 . (at your option) any later version.
15
 .
16
 . This program is distributed in the hope that it will be useful,
17
 . but WITHOUT ANY WARRANTY; without even the implied warranty of
18
 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19
 . GNU General Public License for more details.
20
 .
21
 . You should have received a copy of the GNU General Public License
22
 . along with this program; if not, write to the Free Software
23
 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
24
 .
25
 . Information contained in this file was obtained from the LAN91C111
26
 . manual from SMC.  To get a copy, if you really want one, you can find
27
 . information under www.smsc.com.
28
 .
29
 .
30
 . "Features" of the SMC chip:
31
 .   Integrated PHY/MAC for 10/100BaseT Operation
32
 .   Supports internal and external MII
33
 .   Integrated 8K packet memory
34
 .   EEPROM interface for configuration
35
 .
36
 .
37
 . author:
38
 .      Javier Castillo                 ( javier.castillo@urjc.es )
39
 .
40
 . Sources:
41
 .    o   smc91111.c by Erik Stahlman
42
 .
43
 . History:
44
 . 06/05/05  Javier Castillo  Modified smc91111.h to work with OR1200
45
 ----------------------------------------------------------------------------*/
46
 
47
#ifndef _SMC91111_H_
48
#define _SMC91111_H_
49
 
50
/*
51
 * This function may be called by the board specific initialisation code
52
 * in order to override the default mac address.
53
 */
54
 
55
extern void eth_init (void (*rec)(volatile unsigned char *, int));
56
extern void eth_send(void *buf, unsigned long len);
57
extern unsigned long eth_rx (void);
58
extern void eth_halt(void);
59
 
60
 
61
#define BANK_SELECT     14
62
#define SMC_SELECT_BANK(bank) REG16(ETH_BASE+BANK_SELECT)=bank
63
#define SMC_PHY_ADDR    0x0000
64
 
65
/* Transmit Control Register */
66
/* BANK 0  */
67
#define TCR_REG         0x0000 
68
#define TCR_ENABLE      0x0001  /* When 1 we can transmit */
69
#define TCR_LOOP        0x0002  /* Controls output pin LBK */
70
#define TCR_FORCOL      0x0004  /* When 1 will force a collision */
71
#define TCR_PAD_EN      0x0080  /* When 1 will pad tx frames < 64 bytes w/0 */
72
#define TCR_NOCRC       0x0100  /* When 1 will not append CRC to tx frames */
73
#define TCR_MON_CSN     0x0400  /* When 1 tx monitors carrier */
74
#define TCR_FDUPLX      0x0800  /* When 1 enables full duplex operation */
75
#define TCR_STP_SQET    0x1000  /* When 1 stops tx if Signal Quality Error */
76
#define TCR_EPH_LOOP    0x2000  /* When 1 enables EPH block loopback */
77
#define TCR_SWFDUP      0x8000  /* When 1 enables Switched Full Duplex mode */
78
#define TCR_CLEAR       0
79
#define TCR_DEFAULT     TCR_ENABLE | TCR_SWFDUP
80
 
81
/* EPH Status Register */
82
/* BANK 0  */
83
#define EPH_STATUS_REG  0x0002
84
#define ES_TX_SUC       0x0001  /* Last TX was successful */
85
#define ES_SNGL_COL     0x0002  /* Single collision detected for last tx */
86
#define ES_MUL_COL      0x0004  /* Multiple collisions detected for last tx */
87
#define ES_LTX_MULT     0x0008  /* Last tx was a multicast */
88
#define ES_16COL        0x0010  /* 16 Collisions Reached */
89
#define ES_SQET         0x0020  /* Signal Quality Error Test */
90
#define ES_LTXBRD       0x0040  /* Last tx was a broadcast */
91
#define ES_TXDEFR       0x0080  /* Transmit Deferred */
92
#define ES_LATCOL       0x0200  /* Late collision detected on last tx */
93
#define ES_LOSTCARR     0x0400  /* Lost Carrier Sense */
94
#define ES_EXC_DEF      0x0800  /* Excessive Deferral */
95
#define ES_CTR_ROL      0x1000  /* Counter Roll Over indication */
96
#define ES_LINK_OK      0x4000  /* Driven by inverted value of nLNK pin */
97
#define ES_TXUNRN       0x8000  /* Tx Underrun */
98
 
99
 
100
/* Receive Control Register */
101
/* BANK 0  */
102
#define RCR_REG         0x0004
103
#define RCR_RX_ABORT    0x0001  /* Set if a rx frame was aborted */
104
#define RCR_PRMS        0x0002  /* Enable promiscuous mode */
105
#define RCR_ALMUL       0x0004  /* When set accepts all multicast frames */
106
#define RCR_RXEN        0x0100  /* IFF this is set, we can receive packets */
107
#define RCR_STRIP_CRC   0x0200  /* When set strips CRC from rx packets */
108
#define RCR_ABORT_ENB   0x0200  /* When set will abort rx on collision */
109
#define RCR_FILT_CAR    0x0400  /* When set filters leading 12 bit s of carrier */
110
#define RCR_SOFTRST     0x8000  /* resets the chip */
111
#define RCR_CLEAR       0x0
112
#define RCR_DEFAULT     RCR_RXEN
113
 
114
/* Counter Register */
115
/* BANK 0  */
116
#define COUNTER_REG     0x0006
117
 
118
/* Memory Information Register */
119
/* BANK 0  */
120
#define MIR_REG         0x0008
121
 
122
/* Receive/Phy Control Register */
123
/* BANK 0  */
124
#define RPC_REG         0x000A
125
#define RPC_SPEED       0x2000  /* When 1 PHY is in 100Mbps mode. */
126
#define RPC_DPLX        0x1000  /* When 1 PHY is in Full-Duplex Mode */
127
#define RPC_ANEG        0x0800  /* When 1 PHY is in Auto-Negotiate Mode */
128
#define RPC_LSXA_SHFT   5       /* Bits to shift LS2A,LS1A,LS0A to lsb */
129
#define RPC_LSXB_SHFT   2       /* Bits to get LS2B,LS1B,LS0B to lsb */
130
#define RPC_LED_100_10  (0x00)  /* LED = 100Mbps OR's with 10Mbps link detect */
131
#define RPC_LED_RES     (0x01)  /* LED = Reserved */
132
#define RPC_LED_10      (0x02)  /* LED = 10Mbps link detect */
133
#define RPC_LED_FD      (0x03)  /* LED = Full Duplex Mode */
134
#define RPC_LED_TX_RX   (0x04)  /* LED = TX or RX packet occurred */
135
#define RPC_LED_100     (0x05)  /* LED = 100Mbps link dectect */
136
#define RPC_LED_TX      (0x06)  /* LED = TX packet occurred */
137
#define RPC_LED_RX      (0x07)  /* LED = RX packet occurred */
138
 
139
#define RPC_DEFAULT     RPC_ANEG | (RPC_LED_100 << RPC_LSXA_SHFT) | (RPC_LED_FD << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX
140
 
141
/* Bank 0 0x000C is reserved */
142
 
143
/* Bank Select Register */
144
/* All Banks */
145
#define BSR_REG 0x000E
146
 
147
 
148
/* Configuration Reg */
149
/* BANK 1 */
150
#define CONFIG_REG      0x0000
151
#define CONFIG_EXT_PHY  0x0200  /* 1=external MII, 0=internal Phy */
152
#define CONFIG_GPCNTRL  0x0400  /* Inverse value drives pin nCNTRL */
153
#define CONFIG_NO_WAIT  0x1000  /* When 1 no extra wait states on ISA bus */
154
#define CONFIG_EPH_POWER_EN 0x8000 /* When 0 EPH is placed into low power mode. */
155
/* Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low */
156
#define CONFIG_DEFAULT  (CONFIG_EPH_POWER_EN)
157
 
158
/* Base Address Register */
159
/* BANK 1 */
160
#define BASE_REG        0x0002
161
 
162
 
163
/* Individual Address Registers */
164
/* BANK 1 */
165
#define ADDR0_REG       0x0004
166
#define ADDR1_REG       0x0006
167
#define ADDR2_REG       0x0008
168
 
169
 
170
/* General Purpose Register */
171
/* BANK 1 */
172
#define GP_REG          0x000A
173
 
174
 
175
/* Control Register */
176
/* BANK 1 */
177
#define CTL_REG         0x000C
178
#define CTL_RCV_BAD     0x4000 /* When 1 bad CRC packets are received */
179
#define CTL_AUTO_RELEASE 0x0800 /* When 1 tx pages are released automatically */
180
#define CTL_LE_ENABLE   0x0080 /* When 1 enables Link Error interrupt */
181
#define CTL_CR_ENABLE   0x0040 /* When 1 enables Counter Rollover interrupt */
182
#define CTL_TE_ENABLE   0x0020 /* When 1 enables Transmit Error interrupt */
183
#define CTL_EEPROM_SELECT 0x0004 /* Controls EEPROM reload & store */
184
#define CTL_RELOAD      0x0002 /* When set reads EEPROM into registers */
185
#define CTL_STORE       0x0001 /* When set stores registers into EEPROM */
186
#define CTL_DEFAULT     (0x1A10) /* Autorelease enabled*/
187
 
188
/* MMU Command Register */
189
/* BANK 2 */
190
#define MMU_CMD_REG     0x0000
191
#define MC_BUSY         1       /* When 1 the last release has not completed */
192
#define MC_NOP          (0<<5)  /* No Op */
193
#define MC_ALLOC        (1<<5)  /* OR with number of 256 byte packets */
194
#define MC_RESET        (2<<5)  /* Reset MMU to initial state */
195
#define MC_REMOVE       (3<<5)  /* Remove the current rx packet */
196
#define MC_RELEASE      (4<<5)  /* Remove and release the current rx packet */
197
#define MC_FREEPKT      (5<<5)  /* Release packet in PNR register */
198
#define MC_ENQUEUE      (6<<5)  /* Enqueue the packet for transmit */
199
#define MC_RSTTXFIFO    (7<<5)  /* Reset the TX FIFOs */
200
 
201
 
202
/* Packet Number Register */
203
/* BANK 2 */
204
#define PN_REG          0x0002
205
 
206
 
207
/* Allocation Result Register */
208
/* BANK 2 */
209
#define AR_REG          0x0003
210
#define AR_FAILED       0x80    /* Alocation Failed */
211
 
212
 
213
/* RX FIFO Ports Register */
214
/* BANK 2 */
215
#define RXFIFO_REG      0x0004  /* Must be read as a word */
216
#define RXFIFO_REMPTY   0x8000  /* RX FIFO Empty */
217
 
218
 
219
/* TX FIFO Ports Register */
220
/* BANK 2 */
221
#define TXFIFO_REG      RXFIFO_REG      /* Must be read as a word */
222
#define TXFIFO_TEMPTY   0x80    /* TX FIFO Empty */
223
 
224
 
225
/* Pointer Register */
226
/* BANK 2 */
227
#define PTR_REG         0x0006
228
#define PTR_RCV         0x8000 /* 1=Receive area, 0=Transmit area */
229
#define PTR_AUTOINC     0x4000 /* Auto increment the pointer on each access */
230
#define PTR_READ        0x2000 /* When 1 the operation is a read */
231
#define PTR_NOTEMPTY    0x0800 /* When 1 _do not_ write fifo DATA REG */
232
 
233
 
234
/* Data Register */
235
/* BANK 2 */
236
#define SMC91111_DATA_REG       0x0008
237
 
238
 
239
/* Interrupt Status/Acknowledge Register */
240
/* BANK 2 */
241
#define SMC91111_INT_REG        0x000C
242
 
243
 
244
/* Interrupt Mask Register */
245
/* BANK 2 */
246
#define IM_REG          0x000D
247
#define IM_MDINT        0x80 /* PHY MI Register 18 Interrupt */
248
#define IM_ERCV_INT     0x40 /* Early Receive Interrupt */
249
#define IM_EPH_INT      0x20 /* Set by Etheret Protocol Handler section */
250
#define IM_RX_OVRN_INT  0x10 /* Set by Receiver Overruns */
251
#define IM_ALLOC_INT    0x08 /* Set when allocation request is completed */
252
#define IM_TX_EMPTY_INT 0x04 /* Set if the TX FIFO goes empty */
253
#define IM_TX_INT       0x02 /* Transmit Interrrupt */
254
#define IM_RCV_INT      0x01 /* Receive Interrupt */
255
 
256
 
257
/* Multicast Table Registers */
258
/* BANK 3 */
259
#define MCAST_REG1      0x0000
260
#define MCAST_REG2      0x0002
261
#define MCAST_REG3      0x0004
262
#define MCAST_REG4      0x0006
263
 
264
 
265
/* Management Interface Register (MII) */
266
/* BANK 3 */
267
#define MII_REG         0x0008
268
#define MII_MSK_CRS100  0x4000 /* Disables CRS100 detection during tx half dup */
269
#define MII_MDOE        0x0008 /* MII Output Enable */
270
#define MII_MCLK        0x0004 /* MII Clock, pin MDCLK */
271
#define MII_MDI         0x0002 /* MII Input, pin MDI */
272
#define MII_MDO         0x0001 /* MII Output, pin MDO */
273
 
274
 
275
/* Revision Register */
276
/* BANK 3 */
277
#define REV_REG         0x000A /* ( hi: chip id   low: rev # ) */
278
 
279
 
280
/* Early RCV Register */
281
/* BANK 3 */
282
/* this is NOT on SMC9192 */
283
#define ERCV_REG        0x000C
284
#define ERCV_RCV_DISCRD 0x0080 /* When 1 discards a packet being received */
285
#define ERCV_THRESHOLD  0x001F /* ERCV Threshold Mask */
286
 
287
/* External Register */
288
/* BANK 7 */
289
#define EXT_REG         0x0000
290
 
291
/*
292
 . Transmit status bits
293
*/
294
#define TS_SUCCESS 0x0001
295
#define TS_LOSTCAR 0x0400
296
#define TS_LATCOL  0x0200
297
#define TS_16COL   0x0010
298
 
299
/*
300
 . Receive status bits
301
*/
302
#define RS_ALGNERR      0x8000
303
#define RS_BRODCAST     0x4000
304
#define RS_BADCRC       0x2000
305
#define RS_ODDFRAME     0x1000  /* bug: the LAN91C111 never sets this on receive */
306
#define RS_TOOLONG      0x0800
307
#define RS_TOOSHORT     0x0400
308
#define RS_MULTICAST    0x0001
309
#define RS_ERRORS       (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
310
 
311
 
312
/* PHY Register Addresses (LAN91C111 Internal PHY) */
313
 
314
/* PHY Control Register */
315
#define PHY_CNTL_REG            0x00
316
#define PHY_CNTL_RST            0x8000  /* 1=PHY Reset */
317
#define PHY_CNTL_LPBK           0x4000  /* 1=PHY Loopback */
318
#define PHY_CNTL_SPEED          0x2000  /* 1=100Mbps, 0=10Mpbs */
319
#define PHY_CNTL_ANEG_EN        0x1000 /* 1=Enable Auto negotiation */
320
#define PHY_CNTL_PDN            0x0800  /* 1=PHY Power Down mode */
321
#define PHY_CNTL_MII_DIS        0x0400  /* 1=MII 4 bit interface disabled */
322
#define PHY_CNTL_ANEG_RST       0x0200 /* 1=Reset Auto negotiate */
323
#define PHY_CNTL_DPLX           0x0100  /* 1=Full Duplex, 0=Half Duplex */
324
#define PHY_CNTL_COLTST         0x0080  /* 1= MII Colision Test */
325
 
326
/* PHY Status Register */
327
#define PHY_STAT_REG            0x01
328
#define PHY_STAT_CAP_T4         0x8000  /* 1=100Base-T4 capable */
329
#define PHY_STAT_CAP_TXF        0x4000  /* 1=100Base-X full duplex capable */
330
#define PHY_STAT_CAP_TXH        0x2000  /* 1=100Base-X half duplex capable */
331
#define PHY_STAT_CAP_TF         0x1000  /* 1=10Mbps full duplex capable */
332
#define PHY_STAT_CAP_TH         0x0800  /* 1=10Mbps half duplex capable */
333
#define PHY_STAT_CAP_SUPR       0x0040  /* 1=recv mgmt frames with not preamble */
334
#define PHY_STAT_ANEG_ACK       0x0020  /* 1=ANEG has completed */
335
#define PHY_STAT_REM_FLT        0x0010  /* 1=Remote Fault detected */
336
#define PHY_STAT_CAP_ANEG       0x0008  /* 1=Auto negotiate capable */
337
#define PHY_STAT_LINK           0x0004  /* 1=valid link */
338
#define PHY_STAT_JAB            0x0002  /* 1=10Mbps jabber condition */
339
#define PHY_STAT_EXREG          0x0001  /* 1=extended registers implemented */
340
 
341
/* PHY Identifier Registers */
342
#define PHY_ID1_REG             0x02    /* PHY Identifier 1 */
343
#define PHY_ID2_REG             0x03    /* PHY Identifier 2 */
344
 
345
/* PHY Auto-Negotiation Advertisement Register */
346
#define PHY_AD_REG              0x04
347
#define PHY_AD_NP               0x8000  /* 1=PHY requests exchange of Next Page */
348
#define PHY_AD_ACK              0x4000  /* 1=got link code word from remote */
349
#define PHY_AD_RF               0x2000  /* 1=advertise remote fault */
350
#define PHY_AD_T4               0x0200  /* 1=PHY is capable of 100Base-T4 */
351
#define PHY_AD_TX_FDX           0x0100  /* 1=PHY is capable of 100Base-TX FDPLX */
352
#define PHY_AD_TX_HDX           0x0080  /* 1=PHY is capable of 100Base-TX HDPLX */
353
#define PHY_AD_10_FDX           0x0040  /* 1=PHY is capable of 10Base-T FDPLX */
354
#define PHY_AD_10_HDX           0x0020  /* 1=PHY is capable of 10Base-T HDPLX */
355
#define PHY_AD_CSMA             0x0001  /* 1=PHY is capable of 802.3 CMSA */
356
 
357
/* PHY Auto-negotiation Remote End Capability Register */
358
#define PHY_RMT_REG             0x05
359
/* Uses same bit definitions as PHY_AD_REG */
360
 
361
/* PHY Configuration Register 1 */
362
#define PHY_CFG1_REG            0x10
363
#define PHY_CFG1_LNKDIS         0x8000  /* 1=Rx Link Detect Function disabled */
364
#define PHY_CFG1_XMTDIS         0x4000  /* 1=TP Transmitter Disabled */
365
#define PHY_CFG1_XMTPDN         0x2000  /* 1=TP Transmitter Powered Down */
366
#define PHY_CFG1_BYPSCR         0x0400  /* 1=Bypass scrambler/descrambler */
367
#define PHY_CFG1_UNSCDS         0x0200  /* 1=Unscramble Idle Reception Disable */
368
#define PHY_CFG1_EQLZR          0x0100  /* 1=Rx Equalizer Disabled */
369
#define PHY_CFG1_CABLE          0x0080  /* 1=STP(150ohm), 0=UTP(100ohm) */
370
#define PHY_CFG1_RLVL0          0x0040  /* 1=Rx Squelch level reduced by 4.5db */
371
#define PHY_CFG1_TLVL_SHIFT     2       /* Transmit Output Level Adjust */
372
#define PHY_CFG1_TLVL_MASK      0x003C
373
#define PHY_CFG1_TRF_MASK       0x0003  /* Transmitter Rise/Fall time */
374
 
375
 
376
/* PHY Configuration Register 2 */
377
#define PHY_CFG2_REG            0x11
378
#define PHY_CFG2_APOLDIS        0x0020  /* 1=Auto Polarity Correction disabled */
379
#define PHY_CFG2_JABDIS         0x0010  /* 1=Jabber disabled */
380
#define PHY_CFG2_MREG           0x0008  /* 1=Multiple register access (MII mgt) */
381
#define PHY_CFG2_INTMDIO        0x0004  /* 1=Interrupt signaled with MDIO pulseo */
382
 
383
/* PHY Status Output (and Interrupt status) Register */
384
#define PHY_INT_REG             0x12    /* Status Output (Interrupt Status) */
385
#define PHY_INT_INT             0x8000  /* 1=bits have changed since last read */
386
#define PHY_INT_LNKFAIL         0x4000  /* 1=Link Not detected */
387
#define PHY_INT_LOSSSYNC        0x2000  /* 1=Descrambler has lost sync */
388
#define PHY_INT_CWRD            0x1000  /* 1=Invalid 4B5B code detected on rx */
389
#define PHY_INT_SSD             0x0800  /* 1=No Start Of Stream detected on rx */
390
#define PHY_INT_ESD             0x0400  /* 1=No End Of Stream detected on rx */
391
#define PHY_INT_RPOL            0x0200  /* 1=Reverse Polarity detected */
392
#define PHY_INT_JAB             0x0100  /* 1=Jabber detected */
393
#define PHY_INT_SPDDET          0x0080  /* 1=100Base-TX mode, 0=10Base-T mode */
394
#define PHY_INT_DPLXDET         0x0040  /* 1=Device in Full Duplex */
395
 
396
/* PHY Interrupt/Status Mask Register */
397
#define PHY_MASK_REG            0x13    /* Interrupt Mask */
398
/* Uses the same bit definitions as PHY_INT_REG */
399
 
400
 
401
#endif  /* _SMC_91111_H_ */

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