OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [bootloaders/] [orpmon/] [ram.ld] - Blame information for rev 292

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 140 julius
 
2
/* Seen 3 bad pages, 180-182 (0xb400-0xb6ff), so put text after these pages */
3 246 julius
 
4 2 marcus.erl
MEMORY
5
        {
6
        vectors : ORIGIN = 0x00000000, LENGTH = 0x00002000
7 246 julius
        ram     : ORIGIN = 0x00002000, LENGTH = 0x02000000 - 0x00002000
8
 
9
        /* Uncomment the following to work around bad pages in a flash mem */
10
        /*
11 140 julius
        ram     : ORIGIN = 0x00001200, LENGTH = 0xB400 - 0x1200
12
        ram2     : ORIGIN = 0xb700, LENGTH = 0x02000000 - 0xb700
13 246 julius
        */
14 140 julius
        /*flash   : ORIGIN = 0xf0000000, LENGTH = 0x04000000*/
15 2 marcus.erl
        }
16
 
17 140 julius
 
18
 
19 2 marcus.erl
SECTIONS
20
{
21
        .vectors :
22
        {
23
        *(.crc)
24
        *(.vectors)
25
        } > vectors
26
 
27
        .text :
28
        {
29
        _text_begin = .;
30
        *(.text)
31
        _text_end = .;
32 246 julius
        } > ram
33 2 marcus.erl
 
34
        .data :
35 140 julius
/*      AT ( ADDR (.text) + SIZEOF(.text) + SIZEOF(.mytext))*/
36 2 marcus.erl
        {
37
        *(.data)
38
        } > ram
39
 
40
        .rodata :
41
        {
42
        *(.rodata)
43
        *(.rodata.*)
44
        } > ram
45
 
46
        .bss :
47
        {
48
        *(.bss)
49
        } > ram
50
 
51
        .stack :
52
        {
53
        *(.stack)
54 246 julius
        src_addr = .;
55
        } > ram
56 140 julius
/*
57
        .monitor :
58
        {
59
        *(.monitor)
60
        } > ram
61
*/
62 2 marcus.erl
 
63 140 julius
/*
64
        . += 0x100000;
65
 
66
// This section was in cmds/load.c, but we don't need it -jb
67
        .config :
68
        {
69
        _cfg_start = .;
70
        *(.config)
71
        _cfg_end = .;
72
        } > ram
73
*/
74
/*
75 2 marcus.erl
        . = 0xf0000100;
76
 
77
        .monitor ALIGN(0x40000) :
78
        {
79
        *(.monitor)
80
        } > flash
81
 
82
        . += 0x100000;
83
 
84
        .config ALIGN(0x40000) :
85
        {
86
        _cfg_start = .;
87
        *(.config)
88
        _cfg_end = .;
89
        } > flash
90 140 julius
*/
91 2 marcus.erl
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.