OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [bootloaders/] [orpmon/] [ram.ld] - Blame information for rev 452

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 140 julius
 
2 246 julius
 
3 2 marcus.erl
MEMORY
4
        {
5
        vectors : ORIGIN = 0x00000000, LENGTH = 0x00002000
6 375 julius
        /* Use all RAM */
7
        /* Put all sections into ram */
8 419 julius
 
9 246 julius
        ram     : ORIGIN = 0x00002000, LENGTH = 0x02000000 - 0x00002000
10 419 julius
 
11 375 julius
        /* Uncomment the following to work around bad pages in a flash mem */
12
        /* Put all sections except data, rodata into ram2 */
13
        /* On ORSoC dev board devices, for pages 132-134 (256Byte pages) */
14 419 julius
        /*
15 375 julius
        ram     : ORIGIN = 0x00001200, LENGTH = 0x8400 - 0x1200
16
        ram2     : ORIGIN = 0x8700, LENGTH = 0x02000000 - 0x8700
17 419 julius
        */
18 246 julius
        /* Uncomment the following to work around bad pages in a flash mem */
19 375 julius
        /* Put all sections except data, rodata into ram2 */
20
        /* On ORSoC dev board devices, for pages 180-182 (256Byte pages) */
21 246 julius
        /*
22 140 julius
        ram     : ORIGIN = 0x00001200, LENGTH = 0xB400 - 0x1200
23
        ram2     : ORIGIN = 0xb700, LENGTH = 0x02000000 - 0xb700
24 246 julius
        */
25 140 julius
        /*flash   : ORIGIN = 0xf0000000, LENGTH = 0x04000000*/
26 2 marcus.erl
        }
27
 
28 140 julius
 
29
 
30 2 marcus.erl
SECTIONS
31
{
32
        .vectors :
33
        {
34
        *(.crc)
35
        *(.vectors)
36
        } > vectors
37
 
38
        .text :
39
        {
40
        _text_begin = .;
41
        *(.text)
42
        _text_end = .;
43 419 julius
        } > ram
44
/*        } > ram2*/
45 2 marcus.erl
 
46
        .data :
47 140 julius
/*      AT ( ADDR (.text) + SIZEOF(.text) + SIZEOF(.mytext))*/
48 2 marcus.erl
        {
49
        *(.data)
50
        } > ram
51
 
52
        .rodata :
53
        {
54
        *(.rodata)
55
        *(.rodata.*)
56
        } > ram
57
 
58
        .bss :
59
        {
60
        *(.bss)
61 419 julius
        } > ram
62
/*        } > ram2 */
63 2 marcus.erl
 
64
        .stack :
65
        {
66
        *(.stack)
67 353 julius
        _src_addr = .;
68 419 julius
        } > ram
69
/*        } > ram2 */
70 140 julius
/*
71
        .monitor :
72
        {
73
        *(.monitor)
74
        } > ram
75
*/
76 2 marcus.erl
 
77 140 julius
/*
78
        . += 0x100000;
79
 
80
// This section was in cmds/load.c, but we don't need it -jb
81
        .config :
82
        {
83
        _cfg_start = .;
84
        *(.config)
85
        _cfg_end = .;
86
        } > ram
87
*/
88
/*
89 2 marcus.erl
        . = 0xf0000100;
90
 
91
        .monitor ALIGN(0x40000) :
92
        {
93
        *(.monitor)
94
        } > flash
95
 
96
        . += 0x100000;
97
 
98
        .config ALIGN(0x40000) :
99
        {
100
        _cfg_start = .;
101
        *(.config)
102
        _cfg_end = .;
103
        } > flash
104 140 julius
*/
105 2 marcus.erl
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.