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[/] [openrisc/] [trunk/] [bootloaders/] [orpmon/] [reset.S] - Blame information for rev 355

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#include "spr-defs.h"
#include "board.h"
#include "mc.h"
 
        .extern _reset_support
        .extern _eth_int
        .extern _src_beg
        .extern _dst_beg
        .extern _dst_end
        .extern _c_reset
        .extern _int_main
        .extern _tick_interrupt
        .extern _crc32
 
        /* Used by global.src_addr for default value */
        .extern _src_addr
 
        .global _align
        .global _calc_mycrc32
        .global _mycrc32
        .global _mysize
 
        .section .stack, "aw", @nobits
.space  STACK_SIZE
_stack:
        .section .crc
_mycrc32:
        .word   0xcccccccc
_mysize:
        .word 0xdddddddd
 
.if SELF_CHECK
_calc_mycrc32:
        l.addi  r3,r0,0
        l.movhi r4,hi(_calc_mycrc32)
        l.ori   r4,r4,lo(_calc_mycrc32)
        l.movhi r5,hi(_mysize)
        l.ori   r5,r5,lo(_mysize)
        l.lwz   r5,0(r5)
        l.addi  r1,r1,-4
        l.sw    0(r1),r9
 
        /* unsigned long crc32 (unsigned long crc, const unsigned char *buf, unsigned long len); */
        l.jal           _crc32
        l.nop
 
        l.movhi r3,hi(_mycrc32)
        l.ori   r3,r3,lo(_mycrc32)
        l.lwz   r3,0(r3)
 
        l.xor     r11,r3,r11
        l.lwz   r9,0(r1)
        l.jr    r9
        l.addi  r1,r1,4
.endif
 
        .org 0x100
 
.if IN_FLASH
        .section .reset, "ax"
.else
        .section .vectors, "ax"
.endif
 
_reset:
.if IN_FLASH
        l.movhi r3,hi(MC_BASE_ADDR)
        l.ori   r3,r3,MC_BA_MASK
        l.addi  r5,r0,0x00
        l.sw    0(r3),r5
.endif
        l.movhi r0, 0
        /* Clear status register, set supervisor mode */
        l.ori r1, r0, SPR_SR_SM
        l.mtspr r0, r1, SPR_SR
        /* Clear timer  */
        l.mtspr r0, r0, SPR_TTMR
        /* Jump to start routine */
        l.movhi r3,hi(_start)
        l.ori   r3,r3,lo(_start)
        l.jr    r3
        l.nop
 
.if IN_FLASH
        .section .vectors, "ax"
        .org 0x200
.else
        .org (0x200 - 0x100 + _reset)
.endif
_buserr:
.if 0
        /* Just trap */
        l.trap 0
.endif
        l.nop 0x1
        l.j 0
        l.nop
 
 
.if IN_FLASH
        .section .vectors, "ax"
        .org 0x500
.else
        .org (0x500 - 0x100 + _reset)
.endif
_tickint:
#define TIMER_RELOAD_VALUE (SPR_TTMR_IE | SPR_TTMR_RT | ((IN_CLK/TICKS_PER_SEC) & SPR_TTMR_PERIOD))
        //UNHANDLED_EXCEPTION
        /* Simply load timer_ticks variable and increment */
        .extern _timer_ticks
        l.addi  r1, r1, -8
        l.sw    0(r1), r25
        l.sw    4(r1), r26
        l.movhi r25, hi(_timestamp)
        l.ori   r25, r25, lo(_timestamp)
        l.lwz   r26, 0(r25)                     /* Load variable addr.*/
        l.addi  r26, r26, 1                     /* Increment variable */
        l.sw    0(r25), r26                     /* Store variable */
        l.movhi r25, hi(TIMER_RELOAD_VALUE)     /* Load timer value */
        l.ori   r25, r25, lo(TIMER_RELOAD_VALUE)
        l.mtspr r0, r25, SPR_TTMR               /* Reset timer */
        l.lwz   r25, 0(r1)
        l.lwz   r26, 4(r1)
        l.addi  r1, r1, 8
        l.rfe
/*
        l.addi  r1,r1,-128
        l.sw    0(r1), r2
        l.addi  r2, r1, 128
        l.sw    0x4(r1),r3
        l.movhi r3,hi(_tick)
        l.ori   r3,r3,lo(_tick)
        l.jr    r3
        l.nop
*/
.if IN_FLASH
        .section .vectors, "ax"
        .org 0x600
.else
        .org (0x600 - 0x100 + _reset)
.endif
_alignerr:
.if 0
        l.trap 0
.endif
        l.nop 0x1
        l.j 0
        l.nop
 
.if IN_FLASH
        .org 0x700
.else
        .org (0x700 - 0x100 + _reset)
.endif
_illinsn:
.if 0
        /* Just trap */
        l.trap 0
.endif
        l.nop 0x1
        l.j 0
        l.nop
 
 
.if IN_FLASH
        .org 0x800
.else
        .org (0x800 - 0x100 + _reset)
.endif
_userint:
        l.addi  r1,r1,-128
        l.sw    0x0(r1),r2
        l.addi  r2, r1, 128
        l.sw    0x4(r1), r3
        l.movhi r3,hi(_int_wrapper)
        l.ori   r3,r3,lo(_int_wrapper)
        l.jr    r3
        l.nop
 
        .section .text
_start:
.if IN_FLASH
/*        l.jal   _init_mc
        l.nop
*/
        /* Wait for SDRAM */
        l.addi  r3,r0,0x1000
1:      l.sfeqi r3,0
        l.bnf   1b
        l.addi  r3,r3,-1
.endif
        /* Copy form flash to sram */
.if IN_FLASH
        l.movhi r3,hi(_src_beg)
        l.ori   r3,r3,lo(_src_beg)
        l.movhi r4,hi(_vec_start)
        l.ori   r4,r4,lo(_vec_start)
        l.movhi r5,hi(_vec_end)
        l.ori   r5,r5,lo(_vec_end)
        l.sub   r5,r5,r4
        l.sfeqi r5,0
        l.bf    2f
        l.nop
1:      l.lwz   r6,0(r3)
        l.sw    0(r4),r6
        l.addi  r3,r3,4
        l.addi  r4,r4,4
        l.addi  r5,r5,-4
        l.sfgtsi r5,0
        l.bf    1b
        l.nop
2:
        l.movhi r4,hi(_dst_beg)
        l.ori   r4,r4,lo(_dst_beg)
        l.movhi r5,hi(_dst_end)
        l.ori   r5,r5,lo(_dst_end)
1:      l.sfgeu r4,r5
        l.bf    1f
        l.nop
        l.lwz   r8,0(r3)
        l.sw    0(r4),r8
        l.addi  r3,r3,4
        l.bnf   1b
        l.addi  r4,r4,4
1:
        l.addi  r3,r0,0
        l.addi  r4,r0,0
3:
.endif
 
 
        /* Instruction cache enable */
        /* Check if IC present and skip enabling otherwise */
        l.mfspr r24,r0,SPR_UPR
        l.andi  r26,r24,SPR_UPR_ICP
        l.sfeq  r26,r0
        l.bf    .L8
        l.nop
 
        /* Disable IC */
        l.mfspr r6,r0,SPR_SR
        l.addi  r5,r0,-1
        l.xori  r5,r5,SPR_SR_ICE
        l.and   r5,r6,r5
        l.mtspr r0,r5,SPR_SR
 
        /* Establish cache block size
        If BS=0, 16;
        If BS=1, 32;
        r14 contain block size
        */
        l.mfspr r24,r0,SPR_ICCFGR
        l.andi  r26,r24,SPR_ICCFGR_CBS
        l.srli  r28,r26,7
        l.ori   r30,r0,16
        l.sll   r14,r30,r28
 
        /* Establish number of cache sets
        r16 contains number of cache sets
        r28 contains log(# of cache sets)
        */
        l.andi  r26,r24,SPR_ICCFGR_NCS
        l.srli  r28,r26,3
        l.ori   r30,r0,1
        l.sll   r16,r30,r28
 
        /* Invalidate IC */
        l.addi  r6,r0,0
        l.sll   r5,r14,r28
 
.L7:
        l.mtspr r0,r6,SPR_ICBIR
        l.sfne  r6,r5
        l.bf    .L7
        l.add   r6,r6,r14
 
        /* Enable IC */
        l.mfspr r6,r0,SPR_SR
        l.ori   r6,r6,SPR_SR_ICE
        l.mtspr r0,r6,SPR_SR
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
.L8:
        /* Data cache enable */
        /* Check if DC present and skip enabling otherwise */
        l.mfspr r24,r0,SPR_UPR
        l.andi  r26,r24,SPR_UPR_DCP
        l.sfeq  r26,r0
        l.bf    .L10
        l.nop
        /* Disable DC */
        l.mfspr r6,r0,SPR_SR
        l.addi  r5,r0,-1
        l.xori  r5,r5,SPR_SR_DCE
        l.and   r5,r6,r5
        l.mtspr r0,r5,SPR_SR
        /* Establish cache block size
           If BS=0, 16;
           If BS=1, 32;
           r14 contain block size
        */
        l.mfspr r24,r0,SPR_DCCFGR
        l.andi  r26,r24,SPR_DCCFGR_CBS
        l.srli  r28,r26,7
        l.ori   r30,r0,16
        l.sll   r14,r30,r28
        /* Establish number of cache sets
           r16 contains number of cache sets
           r28 contains log(# of cache sets)
        */
        l.andi  r26,r24,SPR_DCCFGR_NCS
        l.srli  r28,r26,3
        l.ori   r30,r0,1
        l.sll   r16,r30,r28
        /* Invalidate DC */
        l.addi  r6,r0,0
        l.sll   r5,r14,r28
.L9:
        l.mtspr r0,r6,SPR_DCBIR
        l.sfne  r6,r5
        l.bf    .L9
        l.add   r6,r6,r14
        /* Enable DC */
        l.mfspr r6,r0,SPR_SR
        l.ori   r6,r6,SPR_SR_DCE
        l.mtspr r0,r6,SPR_SR
 
.L10:
        /* Set up stack */
        l.movhi r1,hi(_stack-4)
        l.ori   r1,r1,lo(_stack-4)
        l.addi  r2,r0,-3
        l.and   r1,r1,r2
/*      l.or    r2, r1, r1 - remove this helped with odd UART output problem?!*/
 
        l.movhi r3,hi(_main)
        l.ori   r3,r3,lo(_main)
        l.jr    r3
        l.nop
 
 
_tick:
 
        l.sw    0x8(r1), r4
        l.sw    0xc(r1), r5
        l.sw    0x10(r1), r6
        l.sw    0x14(r1), r7
        l.sw    0x18(r1), r8
        l.sw    0x1c(r1), r9
        l.sw    0x20(r1), r10
        l.sw    0x24(r1), r11
        l.sw    0x28(r1), r12
        l.sw    0x2c(r1), r13
        l.sw    0x30(r1), r14
        l.sw    0x34(r1), r15
        l.sw    0x38(r1), r16
        l.sw    0x3c(r1), r17
        l.sw    0x40(r1), r18
        l.sw    0x44(r1), r19
        l.sw    0x48(r1), r20
        l.sw    0x4c(r1), r21
        l.sw    0x50(r1), r22
        l.sw    0x54(r1), r23
        l.sw    0x58(r1), r24
        l.sw    0x5c(r1), r25
        l.sw    0x60(r1), r26
        l.sw    0x64(r1), r27
        l.sw    0x68(r1), r28
        l.sw    0x6c(r1), r29
        l.sw    0x70(r1), r30
        l.sw    0x74(r1), r31
 
        l.movhi r3,hi(_tick_interrupt)
        l.ori   r3,r3,lo(_tick_interrupt)
        l.jalr  r3
        l.nop
 
        l.lwz   r3,0x4(r1)
        l.lwz   r4,0x8(r1)
        l.lwz   r5,0xc(r1)
        l.lwz   r6,0x10(r1)
        l.lwz   r7,0x14(r1)
        l.lwz   r8,0x18(r1)
        l.lwz   r9,0x1c(r1)
        l.lwz   r10,0x20(r1)
        l.lwz   r11,0x24(r1)
        l.lwz   r12,0x28(r1)
        l.lwz   r13,0x2c(r1)
        l.lwz   r14,0x30(r1)
        l.lwz   r15,0x34(r1)
        l.lwz   r16,0x38(r1)
        l.lwz   r17,0x3c(r1)
        l.lwz   r18,0x40(r1)
        l.lwz   r19,0x44(r1)
        l.lwz   r20,0x48(r1)
        l.lwz   r21,0x4c(r1)
        l.lwz   r22,0x50(r1)
        l.lwz   r23,0x54(r1)
        l.lwz   r24,0x58(r1)
        l.lwz   r25,0x5c(r1)
        l.lwz   r26,0x60(r1)
        l.lwz   r27,0x64(r1)
        l.lwz   r28,0x68(r1)
        l.lwz   r29,0x6c(r1)
        l.lwz   r30,0x70(r1)
        l.lwz   r31,0x74(r1)
 
        l.lwz   r2, 0x0(r1)
        l.addi  r1,r1,128
        l.rfe
        l.nop
 
_int_wrapper:
 
        l.sw    0x8(r1), r4
        l.sw    0xc(r1), r5
        l.sw    0x10(r1), r6
        l.sw    0x14(r1), r7
        l.sw    0x18(r1), r8
        l.sw    0x1c(r1), r9
        l.sw    0x20(r1), r10
        l.sw    0x24(r1), r11
        l.sw    0x28(r1), r12
        l.sw    0x2c(r1), r13
        l.sw    0x30(r1), r14
        l.sw    0x34(r1), r15
        l.sw    0x38(r1), r16
        l.sw    0x3c(r1), r17
        l.sw    0x40(r1), r18
        l.sw    0x44(r1), r19
        l.sw    0x48(r1), r20
        l.sw    0x4c(r1), r21
        l.sw    0x50(r1), r22
        l.sw    0x54(r1), r23
        l.sw    0x58(r1), r24
        l.sw    0x5c(r1), r25
        l.sw    0x60(r1), r26
        l.sw    0x64(r1), r27
        l.sw    0x68(r1), r28
        l.sw    0x6c(r1), r29
        l.sw    0x70(r1), r30
        l.sw    0x74(r1), r31
 
        l.movhi r3,hi(_int_main)
        l.ori   r3,r3,lo(_int_main)
        l.jalr  r3
        l.nop
 
        l.lwz   r3,0x4(r1)
        l.lwz   r4,0x8(r1)
        l.lwz   r5,0xc(r1)
        l.lwz   r6,0x10(r1)
        l.lwz   r7,0x14(r1)
        l.lwz   r8,0x18(r1)
        l.lwz   r9,0x1c(r1)
        l.lwz   r10,0x20(r1)
        l.lwz   r11,0x24(r1)
        l.lwz   r12,0x28(r1)
        l.lwz   r13,0x2c(r1)
        l.lwz   r14,0x30(r1)
        l.lwz   r15,0x34(r1)
        l.lwz   r16,0x38(r1)
        l.lwz   r17,0x3c(r1)
        l.lwz   r18,0x40(r1)
        l.lwz   r19,0x44(r1)
        l.lwz   r20,0x48(r1)
        l.lwz   r21,0x4c(r1)
        l.lwz   r22,0x50(r1)
        l.lwz   r23,0x54(r1)
        l.lwz   r24,0x58(r1)
        l.lwz   r25,0x5c(r1)
        l.lwz   r26,0x60(r1)
        l.lwz   r27,0x64(r1)
        l.lwz   r28,0x68(r1)
        l.lwz   r29,0x6c(r1)
        l.lwz   r30,0x70(r1)
        l.lwz   r31,0x74(r1)
 
        l.lwz   r2, 0x0(r1)
        l.addi  r1,r1,128
        l.rfe
        l.nop
 
 
_align:
        l.sw    0x0c(r1),r3
        l.sw    0x10(r1),r4
        l.sw    0x14(r1),r5
        l.sw    0x18(r1),r6
        l.sw    0x1c(r1),r7
        l.sw    0x20(r1),r8
        l.sw    0x24(r1),r9
        l.sw    0x28(r1),r10
        l.sw    0x2c(r1),r11
        l.sw    0x30(r1),r12
        l.sw    0x34(r1),r13
        l.sw    0x38(r1),r14
        l.sw    0x3c(r1),r15
        l.sw    0x40(r1),r16
        l.sw    0x44(r1),r17
        l.sw    0x48(r1),r18
        l.sw    0x4c(r1),r19
        l.sw    0x50(r1),r20
        l.sw    0x54(r1),r21
        l.sw    0x58(r1),r22
        l.sw    0x5c(r1),r23
        l.sw    0x60(r1),r24
        l.sw    0x64(r1),r25
        l.sw    0x68(r1),r26
        l.sw    0x6c(r1),r27
        l.sw    0x70(r1),r28
        l.sw    0x74(r1),r29
        l.sw    0x78(r1),r30
        l.sw    0x7c(r1),r31
 
        l.mfspr r2,r0,SPR_EEAR_BASE /* Load the efective addres */
        l.mfspr r5,r0,SPR_EPCR_BASE /* Load the insn address */
 
        l.lwz   r3,0(r5)    /* Load insn */
        l.srli  r4,r3,26    /* Shift left to get the insn opcode */
 
        l.sfeqi r4,0x00     /* Check if the load/store insn is in delay slot */
        l.bf    jmp
        l.sfeqi r4,0x01
        l.bf    jmp
        l.sfeqi r4,0x03
        l.bf    jmp
        l.sfeqi r4,0x04
        l.bf    jmp
        l.sfeqi r4,0x11
        l.bf    jr
        l.sfeqi r4,0x12
        l.bf    jr
        l.nop
        l.j     1f
        l.addi  r5,r5,4     /* Increment PC to get return insn address */
 
jmp:
        l.slli  r4,r3,6     /* Get the signed extended jump length */
        l.srai  r4,r4,4
 
        l.lwz   r3,4(r5)      /* Load the real load/store insn */
 
        l.add   r5,r5,r4      /* Calculate jump target address */
 
        l.j     1f
        l.srli  r4,r3,26    /* Shift left to get the insn opcode */
 
jr:
        l.slli  r4,r3,9     /* Shift to get the reg nb */
        l.andi  r4,r4,0x7c
 
        l.lwz   r3,4(r5)    /* Load the real load/store insn */
 
        l.add   r4,r4,r1    /* Load the jump register value from the stack */
        l.lwz   r5,0(r4)
 
        l.srli  r4,r3,26    /* Shift left to get the insn opcode */
 
 
1:      l.mtspr r0,r5,SPR_EPCR_BASE
 
        l.sfeqi r4,0x26
        l.bf    lhs
        l.sfeqi r4,0x25
        l.bf    lhz
        l.sfeqi r4,0x22
        l.bf    lws
        l.sfeqi r4,0x21
        l.bf    lwz
        l.sfeqi r4,0x37
        l.bf    sh
        l.sfeqi r4,0x35
        l.bf    sw
        l.nop
 
1:      l.j     1b      /* I don't know what to do */
        l.nop
 
lhs:    l.lbs   r5,0(r2)
        l.slli  r5,r5,8
        l.lbz   r6,1(r2)
        l.or    r5,r5,r6
        l.srli  r4,r3,19
        l.andi  r4,r4,0x7c
        l.add   r4,r4,r1
        l.j     align_end
        l.sw    0(r4),r5
 
lhz:    l.lbz   r5,0(r2)
        l.slli  r5,r5,8
        l.lbz   r6,1(r2)
        l.or    r5,r5,r6
        l.srli  r4,r3,19
        l.andi  r4,r4,0x7c
        l.add   r4,r4,r1
        l.j     align_end
        l.sw    0(r4),r5
 
lws:    l.lbs   r5,0(r2)
        l.slli  r5,r5,24
        l.lbz   r6,1(r2)
        l.slli  r6,r6,16
        l.or    r5,r5,r6
        l.lbz   r6,2(r2)
        l.slli  r6,r6,8
        l.or    r5,r5,r6
        l.lbz   r6,3(r2)
        l.or    r5,r5,r6
        l.srli  r4,r3,19
        l.andi  r4,r4,0x7c
        l.add   r4,r4,r1
        l.j     align_end
        l.sw    0(r4),r5
 
lwz:    l.lbz   r5,0(r2)
        l.slli  r5,r5,24
        l.lbz   r6,1(r2)
        l.slli  r6,r6,16
        l.or    r5,r5,r6
        l.lbz   r6,2(r2)
        l.slli  r6,r6,8
        l.or    r5,r5,r6
        l.lbz   r6,3(r2)
        l.or    r5,r5,r6
        l.srli  r4,r3,19
        l.andi  r4,r4,0x7c
        l.add   r4,r4,r1
        l.j     align_end
        l.sw    0(r4),r5
 
sh:
        l.srli  r4,r3,9
        l.andi  r4,r4,0x7c
        l.add   r4,r4,r1
        l.lwz   r5,0(r4)
        l.sb    1(r2),r5
        l.srli  r5,r5,8
        l.j     align_end
        l.sb    0(r2),r5
 
sw:
        l.srli  r4,r3,9
        l.andi  r4,r4,0x7c
        l.add   r4,r4,r1
        l.lwz   r5,0(r4)
        l.sb    3(r2),r5
        l.srli  r5,r5,8
        l.sb    2(r2),r5
        l.srli  r5,r5,8
        l.sb    1(r2),r5
        l.srli  r5,r5,8
        l.j     align_end
        l.sb    0(r2),r5
 
align_end:
        l.lwz   r2,0x08(r1)
        l.lwz   r3,0x0c(r1)
        l.lwz   r4,0x10(r1)
        l.lwz   r5,0x14(r1)
        l.lwz   r6,0x18(r1)
        l.lwz   r7,0x1c(r1)
        l.lwz   r8,0x20(r1)
        l.lwz   r9,0x24(r1)
        l.lwz   r10,0x28(r1)
        l.lwz   r11,0x2c(r1)
        l.lwz   r12,0x30(r1)
        l.lwz   r13,0x34(r1)
        l.lwz   r14,0x38(r1)
        l.lwz   r15,0x3c(r1)
        l.lwz   r16,0x40(r1)
        l.lwz   r17,0x44(r1)
        l.lwz   r18,0x48(r1)
        l.lwz   r19,0x4c(r1)
        l.lwz   r20,0x50(r1)
        l.lwz   r21,0x54(r1)
        l.lwz   r22,0x58(r1)
        l.lwz   r23,0x5c(r1)
        l.lwz   r24,0x60(r1)
        l.lwz   r25,0x64(r1)
        l.lwz   r26,0x68(r1)
        l.lwz   r27,0x6c(r1)
        l.lwz   r28,0x70(r1)
        l.lwz   r29,0x74(r1)
        l.lwz   r30,0x78(r1)
        l.mfspr r31,r0,0x40
        l.lwz   r31,0x7c(r1)
        l.addi  r1,r1,128
        l.rfe

Line No.	Rev	Author	Line
1	246	julius	`#include "spr-defs.h"`
2	2	marcus.erl	`#include "board.h"`
3			`#include "mc.h"`
4
5			`.extern _reset_support`
6			`.extern _eth_int`
7			`.extern _src_beg`
8			`.extern _dst_beg`
9			`.extern _dst_end`
10			`.extern _c_reset`
11			`.extern _int_main`
12			`.extern _tick_interrupt`
13			`.extern _crc32`
14
15			`/* Used by global.src_addr for default value */`
16			`.extern _src_addr`
17
18			`.global _align`
19			`.global _calc_mycrc32`
20			`.global _mycrc32`
21			`.global _mysize`
22
23			`.section .stack, "aw", @nobits`
24			`.space STACK_SIZE`
25			`_stack:`
26			`.section .crc`
27			`_mycrc32:`
28			`.word 0xcccccccc`
29			`_mysize:`
30			`.word 0xdddddddd`
31
32			`.if SELF_CHECK`
33			`_calc_mycrc32:`
34			`l.addi r3,r0,0`
35			`l.movhi r4,hi(_calc_mycrc32)`
36			`l.ori r4,r4,lo(_calc_mycrc32)`
37			`l.movhi r5,hi(_mysize)`
38			`l.ori r5,r5,lo(_mysize)`
39			`l.lwz r5,0(r5)`
40			`l.addi r1,r1,-4`
41			`l.sw 0(r1),r9`
42
43			`/* unsigned long crc32 (unsigned long crc, const unsigned char buf, unsigned long len); /`
44			`l.jal _crc32`
45			`l.nop`
46
47			`l.movhi r3,hi(_mycrc32)`
48			`l.ori r3,r3,lo(_mycrc32)`
49			`l.lwz r3,0(r3)`
50
51			`l.xor r11,r3,r11`
52			`l.lwz r9,0(r1)`
53			`l.jr r9`
54			`l.addi r1,r1,4`
55			`.endif`
56
57			`.org 0x100`
58	140	julius
59	2	marcus.erl	`.if IN_FLASH`
60			`.section .reset, "ax"`
61			`.else`
62			`.section .vectors, "ax"`
63			`.endif`
64
65			`_reset:`
66			`.if IN_FLASH`
67			`l.movhi r3,hi(MC_BASE_ADDR)`
68			`l.ori r3,r3,MC_BA_MASK`
69			`l.addi r5,r0,0x00`
70			`l.sw 0(r3),r5`
71			`.endif`
72	246	julius	`l.movhi r0, 0`
73			`/* Clear status register, set supervisor mode */`
74			`l.ori r1, r0, SPR_SR_SM`
75			`l.mtspr r0, r1, SPR_SR`
76			`/* Clear timer */`
77			`l.mtspr r0, r0, SPR_TTMR`
78			`/* Jump to start routine */`
79	2	marcus.erl	`l.movhi r3,hi(_start)`
80			`l.ori r3,r3,lo(_start)`
81			`l.jr r3`
82			`l.nop`
83
84			`.if IN_FLASH`
85			`.section .vectors, "ax"`
86	140	julius	`.org 0x200`
87			`.else`
88			`.org (0x200 - 0x100 + _reset)`
89			`.endif`
90			`_buserr:`
91	246	julius	`.if 0`
92			`/* Just trap */`
93	140	julius	`l.trap 0`
94	246	julius	`.endif`
95			`l.nop 0x1`
96	140	julius	`l.j 0`
97			`l.nop`
98
99
100			`.if IN_FLASH`
101			`.section .vectors, "ax"`
102	2	marcus.erl	`.org 0x500`
103			`.else`
104			`.org (0x500 - 0x100 + _reset)`
105			`.endif`
106	355	julius	`_tickint:`
107			`#define TIMER_RELOAD_VALUE (SPR_TTMR_IE \| SPR_TTMR_RT \| ((IN_CLK/TICKS_PER_SEC) & SPR_TTMR_PERIOD))`
108			`//UNHANDLED_EXCEPTION`
109			`/* Simply load timer_ticks variable and increment */`
110			`.extern _timer_ticks`
111			`l.addi r1, r1, -8`
112			`l.sw 0(r1), r25`
113			`l.sw 4(r1), r26`
114			`l.movhi r25, hi(_timestamp)`
115			`l.ori r25, r25, lo(_timestamp)`
116			`l.lwz r26, 0(r25) /* Load variable addr.*/`
117			`l.addi r26, r26, 1 /* Increment variable */`
118			`l.sw 0(r25), r26 /* Store variable */`
119			`l.movhi r25, hi(TIMER_RELOAD_VALUE) /* Load timer value */`
120			`l.ori r25, r25, lo(TIMER_RELOAD_VALUE)`
121			`l.mtspr r0, r25, SPR_TTMR /* Reset timer */`
122			`l.lwz r25, 0(r1)`
123			`l.lwz r26, 4(r1)`
124			`l.addi r1, r1, 8`
125			`l.rfe`
126			`/*`
127	2	marcus.erl	`l.addi r1,r1,-128`
128	246	julius	`l.sw 0(r1), r2`
129			`l.addi r2, r1, 128`
130			`l.sw 0x4(r1),r3`
131			`l.movhi r3,hi(_tick)`
132			`l.ori r3,r3,lo(_tick)`
133			`l.jr r3`
134	2	marcus.erl	`l.nop`
135	355	julius	`*/`
136	2	marcus.erl	`.if IN_FLASH`
137			`.section .vectors, "ax"`
138			`.org 0x600`
139			`.else`
140			`.org (0x600 - 0x100 + _reset)`
141			`.endif`
142	140	julius	`_alignerr:`
143	246	julius	`.if 0`
144	140	julius	`l.trap 0`
145	246	julius	`.endif`
146			`l.nop 0x1`
147	140	julius	`l.j 0`
148			`l.nop`
149
150			`.if IN_FLASH`
151			`.org 0x700`
152			`.else`
153			`.org (0x700 - 0x100 + _reset)`
154			`.endif`
155	246	julius	`_illinsn:`
156			`.if 0`
157	140	julius	`/* Just trap */`
158			`l.trap 0`
159	246	julius	`.endif`
160			`l.nop 0x1`
161	140	julius	`l.j 0`
162			`l.nop`
163	2	marcus.erl
164	140	julius
165	2	marcus.erl	`.if IN_FLASH`
166			`.org 0x800`
167			`.else`
168			`.org (0x800 - 0x100 + _reset)`
169			`.endif`
170	140	julius	`_userint:`
171	2	marcus.erl	`l.addi r1,r1,-128`
172	246	julius	`l.sw 0x0(r1),r2`
173			`l.addi r2, r1, 128`
174			`l.sw 0x4(r1), r3`
175			`l.movhi r3,hi(_int_wrapper)`
176			`l.ori r3,r3,lo(_int_wrapper)`
177			`l.jr r3`
178	2	marcus.erl	`l.nop`
179
180			`.section .text`
181			`_start:`
182			`.if IN_FLASH`
183	140	julius	`/* l.jal _init_mc`
184	2	marcus.erl	`l.nop`
185	140	julius	`*/`
186	2	marcus.erl	`/* Wait for SDRAM */`
187			`l.addi r3,r0,0x1000`
188			`1: l.sfeqi r3,0`
189			`l.bnf 1b`
190			`l.addi r3,r3,-1`
191			`.endif`
192			`/* Copy form flash to sram */`
193			`.if IN_FLASH`
194			`l.movhi r3,hi(_src_beg)`
195			`l.ori r3,r3,lo(_src_beg)`
196			`l.movhi r4,hi(_vec_start)`
197			`l.ori r4,r4,lo(_vec_start)`
198			`l.movhi r5,hi(_vec_end)`
199			`l.ori r5,r5,lo(_vec_end)`
200			`l.sub r5,r5,r4`
201			`l.sfeqi r5,0`
202			`l.bf 2f`
203			`l.nop`
204			`1: l.lwz r6,0(r3)`
205			`l.sw 0(r4),r6`
206			`l.addi r3,r3,4`
207			`l.addi r4,r4,4`
208			`l.addi r5,r5,-4`
209			`l.sfgtsi r5,0`
210			`l.bf 1b`
211			`l.nop`
212			`2:`
213			`l.movhi r4,hi(_dst_beg)`
214			`l.ori r4,r4,lo(_dst_beg)`
215			`l.movhi r5,hi(_dst_end)`
216			`l.ori r5,r5,lo(_dst_end)`
217			`1: l.sfgeu r4,r5`
218			`l.bf 1f`
219			`l.nop`
220			`l.lwz r8,0(r3)`
221			`l.sw 0(r4),r8`
222			`l.addi r3,r3,4`
223			`l.bnf 1b`
224			`l.addi r4,r4,4`
225			`1:`
226			`l.addi r3,r0,0`
227			`l.addi r4,r0,0`
228			`3:`
229			`.endif`
230
231	246	julius
232			`/* Instruction cache enable */`
233			`/* Check if IC present and skip enabling otherwise */`
234			`l.mfspr r24,r0,SPR_UPR`
235			`l.andi r26,r24,SPR_UPR_ICP`
236			`l.sfeq r26,r0`
237			`l.bf .L8`
238			`l.nop`
239
240			`/* Disable IC */`
241			`l.mfspr r6,r0,SPR_SR`
242			`l.addi r5,r0,-1`
243			`l.xori r5,r5,SPR_SR_ICE`
244			`l.and r5,r6,r5`
245			`l.mtspr r0,r5,SPR_SR`
246
247			`/* Establish cache block size`
248			`If BS=0, 16;`
249			`If BS=1, 32;`
250			`r14 contain block size`
251			`*/`
252			`l.mfspr r24,r0,SPR_ICCFGR`
253			`l.andi r26,r24,SPR_ICCFGR_CBS`
254			`l.srli r28,r26,7`
255			`l.ori r30,r0,16`
256			`l.sll r14,r30,r28`
257
258			`/* Establish number of cache sets`
259			`r16 contains number of cache sets`
260			`r28 contains log(# of cache sets)`
261			`*/`
262			`l.andi r26,r24,SPR_ICCFGR_NCS`
263			`l.srli r28,r26,3`
264			`l.ori r30,r0,1`
265			`l.sll r16,r30,r28`
266
267			`/* Invalidate IC */`
268			`l.addi r6,r0,0`
269			`l.sll r5,r14,r28`
270
271			`.L7:`
272			`l.mtspr r0,r6,SPR_ICBIR`
273			`l.sfne r6,r5`
274			`l.bf .L7`
275			`l.add r6,r6,r14`
276
277			`/* Enable IC */`
278			`l.mfspr r6,r0,SPR_SR`
279			`l.ori r6,r6,SPR_SR_ICE`
280			`l.mtspr r0,r6,SPR_SR`
281			`l.nop`
282			`l.nop`
283			`l.nop`
284			`l.nop`
285			`l.nop`
286			`l.nop`
287			`l.nop`
288			`l.nop`
289
290			`.L8:`
291			`/* Data cache enable */`
292			`/* Check if DC present and skip enabling otherwise */`
293			`l.mfspr r24,r0,SPR_UPR`
294			`l.andi r26,r24,SPR_UPR_DCP`
295			`l.sfeq r26,r0`
296			`l.bf .L10`
297	2	marcus.erl	`l.nop`
298	246	julius	`/* Disable DC */`
299			`l.mfspr r6,r0,SPR_SR`
300			`l.addi r5,r0,-1`
301			`l.xori r5,r5,SPR_SR_DCE`
302			`l.and r5,r6,r5`
303			`l.mtspr r0,r5,SPR_SR`
304			`/* Establish cache block size`
305			`If BS=0, 16;`
306			`If BS=1, 32;`
307			`r14 contain block size`
308			`*/`
309			`l.mfspr r24,r0,SPR_DCCFGR`
310			`l.andi r26,r24,SPR_DCCFGR_CBS`
311			`l.srli r28,r26,7`
312			`l.ori r30,r0,16`
313			`l.sll r14,r30,r28`
314			`/* Establish number of cache sets`
315			`r16 contains number of cache sets`
316			`r28 contains log(# of cache sets)`
317			`*/`
318			`l.andi r26,r24,SPR_DCCFGR_NCS`
319			`l.srli r28,r26,3`
320			`l.ori r30,r0,1`
321			`l.sll r16,r30,r28`
322			`/* Invalidate DC */`
323			`l.addi r6,r0,0`
324			`l.sll r5,r14,r28`
325			`.L9:`
326			`l.mtspr r0,r6,SPR_DCBIR`
327			`l.sfne r6,r5`
328			`l.bf .L9`
329			`l.add r6,r6,r14`
330			`/* Enable DC */`
331			`l.mfspr r6,r0,SPR_SR`
332			`l.ori r6,r6,SPR_SR_DCE`
333			`l.mtspr r0,r6,SPR_SR`
334	2	marcus.erl
335	246	julius	`.L10:`
336			`/* Set up stack */`
337	2	marcus.erl	`l.movhi r1,hi(_stack-4)`
338			`l.ori r1,r1,lo(_stack-4)`
339			`l.addi r2,r0,-3`
340			`l.and r1,r1,r2`
341	246	julius	`/* l.or r2, r1, r1 - remove this helped with odd UART output problem?!*/`
342	140	julius
343	353	julius	`l.movhi r3,hi(_main)`
344			`l.ori r3,r3,lo(_main)`
345	246	julius	`l.jr r3`
346			`l.nop`
347	140	julius
348
349	2	marcus.erl	`_tick:`
350
351	246	julius	`l.sw 0x8(r1), r4`
352			`l.sw 0xc(r1), r5`
353			`l.sw 0x10(r1), r6`
354			`l.sw 0x14(r1), r7`
355			`l.sw 0x18(r1), r8`
356			`l.sw 0x1c(r1), r9`
357			`l.sw 0x20(r1), r10`
358			`l.sw 0x24(r1), r11`
359			`l.sw 0x28(r1), r12`
360			`l.sw 0x2c(r1), r13`
361			`l.sw 0x30(r1), r14`
362			`l.sw 0x34(r1), r15`
363			`l.sw 0x38(r1), r16`
364			`l.sw 0x3c(r1), r17`
365			`l.sw 0x40(r1), r18`
366			`l.sw 0x44(r1), r19`
367			`l.sw 0x48(r1), r20`
368			`l.sw 0x4c(r1), r21`
369			`l.sw 0x50(r1), r22`
370			`l.sw 0x54(r1), r23`
371			`l.sw 0x58(r1), r24`
372			`l.sw 0x5c(r1), r25`
373			`l.sw 0x60(r1), r26`
374			`l.sw 0x64(r1), r27`
375			`l.sw 0x68(r1), r28`
376			`l.sw 0x6c(r1), r29`
377			`l.sw 0x70(r1), r30`
378			`l.sw 0x74(r1), r31`
379
380	353	julius	`l.movhi r3,hi(_tick_interrupt)`
381			`l.ori r3,r3,lo(_tick_interrupt)`
382	2	marcus.erl	`l.jalr r3`
383			`l.nop`
384
385	246	julius	`l.lwz r3,0x4(r1)`
386	2	marcus.erl	`l.lwz r4,0x8(r1)`
387			`l.lwz r5,0xc(r1)`
388			`l.lwz r6,0x10(r1)`
389			`l.lwz r7,0x14(r1)`
390			`l.lwz r8,0x18(r1)`
391			`l.lwz r9,0x1c(r1)`
392			`l.lwz r10,0x20(r1)`
393			`l.lwz r11,0x24(r1)`
394			`l.lwz r12,0x28(r1)`
395			`l.lwz r13,0x2c(r1)`
396			`l.lwz r14,0x30(r1)`
397			`l.lwz r15,0x34(r1)`
398			`l.lwz r16,0x38(r1)`
399			`l.lwz r17,0x3c(r1)`
400			`l.lwz r18,0x40(r1)`
401			`l.lwz r19,0x44(r1)`
402			`l.lwz r20,0x48(r1)`
403			`l.lwz r21,0x4c(r1)`
404			`l.lwz r22,0x50(r1)`
405			`l.lwz r23,0x54(r1)`
406			`l.lwz r24,0x58(r1)`
407			`l.lwz r25,0x5c(r1)`
408			`l.lwz r26,0x60(r1)`
409			`l.lwz r27,0x64(r1)`
410			`l.lwz r28,0x68(r1)`
411			`l.lwz r29,0x6c(r1)`
412			`l.lwz r30,0x70(r1)`
413	246	julius	`l.lwz r31,0x74(r1)`
414	2	marcus.erl
415	246	julius	`l.lwz r2, 0x0(r1)`
416	2	marcus.erl	`l.addi r1,r1,128`
417			`l.rfe`
418			`l.nop`
419
420			`_int_wrapper:`
421
422	246	julius	`l.sw 0x8(r1), r4`
423			`l.sw 0xc(r1), r5`
424			`l.sw 0x10(r1), r6`
425			`l.sw 0x14(r1), r7`
426			`l.sw 0x18(r1), r8`
427			`l.sw 0x1c(r1), r9`
428			`l.sw 0x20(r1), r10`
429			`l.sw 0x24(r1), r11`
430			`l.sw 0x28(r1), r12`
431			`l.sw 0x2c(r1), r13`
432			`l.sw 0x30(r1), r14`
433			`l.sw 0x34(r1), r15`
434			`l.sw 0x38(r1), r16`
435			`l.sw 0x3c(r1), r17`
436			`l.sw 0x40(r1), r18`
437			`l.sw 0x44(r1), r19`
438			`l.sw 0x48(r1), r20`
439			`l.sw 0x4c(r1), r21`
440			`l.sw 0x50(r1), r22`
441			`l.sw 0x54(r1), r23`
442			`l.sw 0x58(r1), r24`
443			`l.sw 0x5c(r1), r25`
444			`l.sw 0x60(r1), r26`
445			`l.sw 0x64(r1), r27`
446			`l.sw 0x68(r1), r28`
447			`l.sw 0x6c(r1), r29`
448			`l.sw 0x70(r1), r30`
449			`l.sw 0x74(r1), r31`
450
451	353	julius	`l.movhi r3,hi(_int_main)`
452			`l.ori r3,r3,lo(_int_main)`
453	2	marcus.erl	`l.jalr r3`
454			`l.nop`
455
456	246	julius	`l.lwz r3,0x4(r1)`
457	2	marcus.erl	`l.lwz r4,0x8(r1)`
458			`l.lwz r5,0xc(r1)`
459			`l.lwz r6,0x10(r1)`
460			`l.lwz r7,0x14(r1)`
461			`l.lwz r8,0x18(r1)`
462			`l.lwz r9,0x1c(r1)`
463			`l.lwz r10,0x20(r1)`
464			`l.lwz r11,0x24(r1)`
465			`l.lwz r12,0x28(r1)`
466			`l.lwz r13,0x2c(r1)`
467			`l.lwz r14,0x30(r1)`
468			`l.lwz r15,0x34(r1)`
469			`l.lwz r16,0x38(r1)`
470			`l.lwz r17,0x3c(r1)`
471			`l.lwz r18,0x40(r1)`
472			`l.lwz r19,0x44(r1)`
473			`l.lwz r20,0x48(r1)`
474			`l.lwz r21,0x4c(r1)`
475			`l.lwz r22,0x50(r1)`
476			`l.lwz r23,0x54(r1)`
477			`l.lwz r24,0x58(r1)`
478			`l.lwz r25,0x5c(r1)`
479			`l.lwz r26,0x60(r1)`
480			`l.lwz r27,0x64(r1)`
481			`l.lwz r28,0x68(r1)`
482			`l.lwz r29,0x6c(r1)`
483			`l.lwz r30,0x70(r1)`
484	246	julius	`l.lwz r31,0x74(r1)`
485	2	marcus.erl
486	246	julius	`l.lwz r2, 0x0(r1)`
487	2	marcus.erl	`l.addi r1,r1,128`
488			`l.rfe`
489			`l.nop`
490	246	julius
491	2	marcus.erl
492			`_align:`
493			`l.sw 0x0c(r1),r3`
494			`l.sw 0x10(r1),r4`
495			`l.sw 0x14(r1),r5`
496			`l.sw 0x18(r1),r6`
497			`l.sw 0x1c(r1),r7`
498			`l.sw 0x20(r1),r8`
499			`l.sw 0x24(r1),r9`
500			`l.sw 0x28(r1),r10`

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