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[/] [openrisc/] [trunk/] [bootloaders/] [orpmon/] [reset.S] - Blame information for rev 763

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Line No. Rev Author Line
1 246 julius
#include "spr-defs.h"
2 2 marcus.erl
#include "board.h"
3
 
4 419 julius
#define TRAP_ON_ERROR 0
5
#define LOOP_ON_ERROR 0
6
#define EXIT_NOP_ON_ERROR 1
7
#define PRINT_AND_RESET_ON_ERROR 1
8
 
9 375 julius
        .extern int_main
10 406 julius
        .extern int_error
11 463 julius
        .extern _bstart
12
        .extern _bend
13 2 marcus.erl
 
14
        .section .stack, "aw", @nobits
15
.space  STACK_SIZE
16
_stack:
17
 
18
 
19
        .section .vectors, "ax"
20
 
21 467 julius
        .org 0x100
22 2 marcus.erl
_reset:
23 246 julius
        l.movhi r0, 0
24
        /* Clear status register, set supervisor mode */
25
        l.ori r1, r0, SPR_SR_SM
26
        l.mtspr r0, r1, SPR_SR
27
        /* Clear timer  */
28
        l.mtspr r0, r0, SPR_TTMR
29
        /* Jump to start routine */
30 2 marcus.erl
        l.movhi r3,hi(_start)
31
        l.ori   r3,r3,lo(_start)
32
        l.jr    r3
33
        l.nop
34
 
35 140 julius
        .org (0x200 - 0x100 + _reset)
36 463 julius
 
37 140 julius
_buserr:
38 419 julius
.if TRAP_ON_ERROR
39 246 julius
        /* Just trap */
40 140 julius
        l.trap 0
41 246 julius
.endif
42 419 julius
.if EXIT_NOP_ON_ERROR
43 246 julius
        l.nop 0x1
44 419 julius
.endif
45
.if LOOP_ON_ERROR
46 140 julius
        l.j 0
47
        l.nop
48 406 julius
.endif
49 419 julius
.if PRINT_AND_RESET_ON_ERROR
50
        l.mfspr r4, r0, SPR_EPCR_BASE
51
        l.j     _int_error /* This will reset */
52
        l.ori   r3, r0, 0x2
53
.endif
54 2 marcus.erl
        .org (0x500 - 0x100 + _reset)
55 463 julius
 
56 355 julius
_tickint:
57
#define TIMER_RELOAD_VALUE (SPR_TTMR_IE | SPR_TTMR_RT | ((IN_CLK/TICKS_PER_SEC) & SPR_TTMR_PERIOD))
58
        /* Simply load timer_ticks variable and increment */
59
        .extern _timer_ticks
60 419 julius
        l.addi  r1, r1, -136 /* 128 + what we need (8),avoid area used by gcc*/
61 355 julius
        l.sw    0(r1), r25
62
        l.sw    4(r1), r26
63 375 julius
        l.movhi r25, hi(timestamp)
64
        l.ori   r25, r25, lo(timestamp)
65 355 julius
        l.lwz   r26, 0(r25)                     /* Load variable addr.*/
66
        l.addi  r26, r26, 1                     /* Increment variable */
67
        l.sw    0(r25), r26                     /* Store variable */
68
        l.movhi r25, hi(TIMER_RELOAD_VALUE)     /* Load timer value */
69
        l.ori   r25, r25, lo(TIMER_RELOAD_VALUE)
70
        l.mtspr r0, r25, SPR_TTMR               /* Reset timer */
71
        l.lwz   r25, 0(r1)
72
        l.lwz   r26, 4(r1)
73 419 julius
        l.addi  r1, r1, 136
74 355 julius
        l.rfe
75 375 julius
 
76 2 marcus.erl
        .org (0x600 - 0x100 + _reset)
77 463 julius
 
78 140 julius
_alignerr:
79 419 julius
.if TRAP_ON_ERROR
80
        /* Just trap */
81 140 julius
        l.trap 0
82 246 julius
.endif
83 419 julius
.if EXIT_NOP_ON_ERROR
84 246 julius
        l.nop 0x1
85 419 julius
.endif
86
.if LOOP_ON_ERROR
87 140 julius
        l.j 0
88
        l.nop
89 406 julius
.endif
90 419 julius
.if PRINT_AND_RESET_ON_ERROR
91
        l.mfspr r4, r0, SPR_EPCR_BASE
92
        l.j _int_error /* This will reset */
93 406 julius
        l.ori r3, r0, 0x6
94 419 julius
.endif
95 140 julius
 
96
        .org (0x700 - 0x100 + _reset)
97 463 julius
 
98 246 julius
_illinsn:
99 419 julius
.if TRAP_ON_ERROR
100
        /* Just trap */
101 140 julius
        l.trap 0
102 246 julius
.endif
103 419 julius
.if EXIT_NOP_ON_ERROR
104 246 julius
        l.nop 0x1
105 419 julius
.endif
106
.if LOOP_ON_ERROR
107 140 julius
        l.j 0
108
        l.nop
109 406 julius
.endif
110 419 julius
.if PRINT_AND_RESET_ON_ERROR
111
        l.mfspr r4, r0, SPR_EPCR_BASE
112
        l.j _int_error /* This will reset */
113 406 julius
        l.ori r3, r0, 0x7
114 419 julius
.endif
115 2 marcus.erl
        .org (0x800 - 0x100 + _reset)
116 463 julius
 
117 140 julius
_userint:
118 419 julius
        l.addi  r1,r1,-256  /*(128 + 128) */
119 246 julius
        l.sw    0x0(r1),r2
120 419 julius
        l.addi  r2, r1, 256
121 246 julius
        l.sw    0x4(r1), r3
122
        l.movhi r3,hi(_int_wrapper)
123
        l.ori   r3,r3,lo(_int_wrapper)
124
        l.jr    r3
125 2 marcus.erl
        l.nop
126
 
127
        .section .text
128
_start:
129
 
130 246 julius
        /* Instruction cache enable */
131
        /* Check if IC present and skip enabling otherwise */
132
        l.mfspr r24,r0,SPR_UPR
133
        l.andi  r26,r24,SPR_UPR_ICP
134
        l.sfeq  r26,r0
135
        l.bf    .L8
136
        l.nop
137
 
138
        /* Disable IC */
139
        l.mfspr r6,r0,SPR_SR
140
        l.addi  r5,r0,-1
141
        l.xori  r5,r5,SPR_SR_ICE
142
        l.and   r5,r6,r5
143
        l.mtspr r0,r5,SPR_SR
144
 
145
        /* Establish cache block size
146
        If BS=0, 16;
147
        If BS=1, 32;
148
        r14 contain block size
149
        */
150
        l.mfspr r24,r0,SPR_ICCFGR
151
        l.andi  r26,r24,SPR_ICCFGR_CBS
152
        l.srli  r28,r26,7
153
        l.ori   r30,r0,16
154
        l.sll   r14,r30,r28
155
 
156
        /* Establish number of cache sets
157
        r16 contains number of cache sets
158
        r28 contains log(# of cache sets)
159
        */
160
        l.andi  r26,r24,SPR_ICCFGR_NCS
161
        l.srli  r28,r26,3
162
        l.ori   r30,r0,1
163
        l.sll   r16,r30,r28
164
 
165
        /* Invalidate IC */
166
        l.addi  r6,r0,0
167
        l.sll   r5,r14,r28
168
 
169
.L7:
170
        l.mtspr r0,r6,SPR_ICBIR
171
        l.sfne  r6,r5
172
        l.bf    .L7
173
        l.add   r6,r6,r14
174
 
175
        /* Enable IC */
176
        l.mfspr r6,r0,SPR_SR
177
        l.ori   r6,r6,SPR_SR_ICE
178
        l.mtspr r0,r6,SPR_SR
179
        l.nop
180
        l.nop
181
        l.nop
182
        l.nop
183
        l.nop
184
        l.nop
185
        l.nop
186
        l.nop
187
 
188
.L8:
189
        /* Data cache enable */
190
        /* Check if DC present and skip enabling otherwise */
191
        l.mfspr r24,r0,SPR_UPR
192
        l.andi  r26,r24,SPR_UPR_DCP
193
        l.sfeq  r26,r0
194
        l.bf    .L10
195 2 marcus.erl
        l.nop
196 246 julius
        /* Disable DC */
197
        l.mfspr r6,r0,SPR_SR
198
        l.addi  r5,r0,-1
199
        l.xori  r5,r5,SPR_SR_DCE
200
        l.and   r5,r6,r5
201
        l.mtspr r0,r5,SPR_SR
202
        /* Establish cache block size
203
           If BS=0, 16;
204
           If BS=1, 32;
205
           r14 contain block size
206
        */
207
        l.mfspr r24,r0,SPR_DCCFGR
208
        l.andi  r26,r24,SPR_DCCFGR_CBS
209
        l.srli  r28,r26,7
210
        l.ori   r30,r0,16
211
        l.sll   r14,r30,r28
212
        /* Establish number of cache sets
213
           r16 contains number of cache sets
214
           r28 contains log(# of cache sets)
215
        */
216
        l.andi  r26,r24,SPR_DCCFGR_NCS
217
        l.srli  r28,r26,3
218
        l.ori   r30,r0,1
219
        l.sll   r16,r30,r28
220
        /* Invalidate DC */
221
        l.addi  r6,r0,0
222
        l.sll   r5,r14,r28
223
.L9:
224
        l.mtspr r0,r6,SPR_DCBIR
225
        l.sfne  r6,r5
226
        l.bf    .L9
227
        l.add   r6,r6,r14
228
        /* Enable DC */
229
        l.mfspr r6,r0,SPR_SR
230
        l.ori   r6,r6,SPR_SR_DCE
231
        l.mtspr r0,r6,SPR_SR
232 2 marcus.erl
 
233 246 julius
.L10:
234
        /* Set up stack */
235 2 marcus.erl
        l.movhi r1,hi(_stack-4)
236
        l.ori   r1,r1,lo(_stack-4)
237
        l.addi  r2,r0,-3
238
        l.and   r1,r1,r2
239 467 julius
        l.or    r2,r1,r1
240 463 julius
 
241
        /* Clear BSS */
242
        l.movhi r3, hi(_bstart)
243
        l.ori   r3, r3, lo(_bstart)
244
        l.movhi r4, hi(_bend)
245
        l.ori   r4, r4, lo(_bend)
246
.L11:
247
        l.sw    0(r3),r0
248
        l.sfgtu r3, r4
249
        l.bnf   .L11
250
        l.addi  r3, r3, 4
251
 
252 140 julius
 
253 375 julius
        l.movhi r3,hi(main)
254
        l.ori   r3,r3,lo(main)
255 246 julius
        l.jr    r3
256
        l.nop
257 140 julius
 
258 2 marcus.erl
_int_wrapper:
259
 
260 246 julius
        l.sw    0x8(r1), r4
261
        l.sw    0xc(r1), r5
262
        l.sw    0x10(r1), r6
263
        l.sw    0x14(r1), r7
264
        l.sw    0x18(r1), r8
265
        l.sw    0x1c(r1), r9
266
        l.sw    0x20(r1), r10
267
        l.sw    0x24(r1), r11
268
        l.sw    0x28(r1), r12
269
        l.sw    0x2c(r1), r13
270
        l.sw    0x30(r1), r14
271
        l.sw    0x34(r1), r15
272
        l.sw    0x38(r1), r16
273
        l.sw    0x3c(r1), r17
274
        l.sw    0x40(r1), r18
275
        l.sw    0x44(r1), r19
276
        l.sw    0x48(r1), r20
277
        l.sw    0x4c(r1), r21
278
        l.sw    0x50(r1), r22
279
        l.sw    0x54(r1), r23
280
        l.sw    0x58(r1), r24
281
        l.sw    0x5c(r1), r25
282
        l.sw    0x60(r1), r26
283
        l.sw    0x64(r1), r27
284
        l.sw    0x68(r1), r28
285
        l.sw    0x6c(r1), r29
286
        l.sw    0x70(r1), r30
287
        l.sw    0x74(r1), r31
288
 
289 375 julius
        l.movhi r3,hi(int_main)
290
        l.ori   r3,r3,lo(int_main)
291 2 marcus.erl
        l.jalr  r3
292
        l.nop
293
 
294 246 julius
        l.lwz   r3,0x4(r1)
295 2 marcus.erl
        l.lwz   r4,0x8(r1)
296
        l.lwz   r5,0xc(r1)
297
        l.lwz   r6,0x10(r1)
298
        l.lwz   r7,0x14(r1)
299
        l.lwz   r8,0x18(r1)
300
        l.lwz   r9,0x1c(r1)
301
        l.lwz   r10,0x20(r1)
302
        l.lwz   r11,0x24(r1)
303
        l.lwz   r12,0x28(r1)
304
        l.lwz   r13,0x2c(r1)
305
        l.lwz   r14,0x30(r1)
306
        l.lwz   r15,0x34(r1)
307
        l.lwz   r16,0x38(r1)
308
        l.lwz   r17,0x3c(r1)
309
        l.lwz   r18,0x40(r1)
310
        l.lwz   r19,0x44(r1)
311
        l.lwz   r20,0x48(r1)
312
        l.lwz   r21,0x4c(r1)
313
        l.lwz   r22,0x50(r1)
314
        l.lwz   r23,0x54(r1)
315
        l.lwz   r24,0x58(r1)
316
        l.lwz   r25,0x5c(r1)
317
        l.lwz   r26,0x60(r1)
318
        l.lwz   r27,0x64(r1)
319
        l.lwz   r28,0x68(r1)
320
        l.lwz   r29,0x6c(r1)
321
        l.lwz   r30,0x70(r1)
322 246 julius
        l.lwz   r31,0x74(r1)
323 2 marcus.erl
 
324 246 julius
        l.lwz   r2, 0x0(r1)
325 419 julius
        l.addi  r1,r1,256
326 2 marcus.erl
        l.rfe
327
        l.nop
328 246 julius
 
329 2 marcus.erl
 
330 406 julius
        /* Jump to error function. Clobber r2 */
331
_int_error:
332
        l.movhi r2,hi(int_error)
333
        l.ori   r2,r2,lo(int_error)
334
        l.jr  r2
335
        l.nop

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