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[/] [openrisc/] [trunk/] [bootloaders/] [orpmon/] [reset.S] - Blame information for rev 179

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#include "spr_defs.h"
#include "board.h"
#include "mc.h"
 
        .extern _reset_support
        .extern _eth_int
        .extern _src_beg
        .extern _dst_beg
        .extern _dst_end
        .extern _c_reset
        .extern _int_main
        .extern _tick_interrupt
        .extern _crc32
 
        /* Used by global.src_addr for default value */
        .extern _src_addr
 
        .global _align
        .global _calc_mycrc32
        .global _mycrc32
        .global _mysize
 
        .section .stack, "aw", @nobits
.space  STACK_SIZE
_stack:
        .section .crc
_mycrc32:
        .word   0xcccccccc
_mysize:
        .word 0xdddddddd
 
.if SELF_CHECK
_calc_mycrc32:
        l.addi  r3,r0,0
        l.movhi r4,hi(_calc_mycrc32)
        l.ori   r4,r4,lo(_calc_mycrc32)
        l.movhi r5,hi(_mysize)
        l.ori   r5,r5,lo(_mysize)
        l.lwz   r5,0(r5)
        l.addi  r1,r1,-4
        l.sw    0(r1),r9
 
        /* unsigned long crc32 (unsigned long crc, const unsigned char *buf, unsigned long len); */
        l.jal           _crc32
        l.nop
 
        l.movhi r3,hi(_mycrc32)
        l.ori   r3,r3,lo(_mycrc32)
        l.lwz   r3,0(r3)
 
        l.xor     r11,r3,r11
        l.lwz   r9,0(r1)
        l.jr    r9
        l.addi  r1,r1,4
.endif
 
        .org 0x100
 
.if IN_FLASH
        .section .reset, "ax"
.else
        .section .vectors, "ax"
.endif
 
_reset:
.if IN_FLASH
        l.movhi r3,hi(MC_BASE_ADDR)
        l.ori   r3,r3,MC_BA_MASK
        l.addi  r5,r0,0x00
        l.sw    0(r3),r5
.endif
        l.addi  r3,r0,SPR_SR_SM
        l.mtspr r0,r3,SPR_SR
        l.movhi r3,hi(_start)
        l.ori   r3,r3,lo(_start)
        l.jr    r3
        l.nop
 
.if IN_FLASH
        .section .vectors, "ax"
        .org 0x200
.else
        .org (0x200 - 0x100 + _reset)
.endif
_buserr:
        /* Just trap */
        l.trap 0
        l.nop
        l.j 0
        l.nop
 
 
.if IN_FLASH
        .section .vectors, "ax"
        .org 0x500
.else
        .org (0x500 - 0x100 + _reset)
.endif
_tickint:
        l.addi  r1,r1,-128
        l.sw    0x4(r1),r2
        l.movhi r2,hi(_tick)
        l.ori   r2,r2,lo(_tick)
        l.jr    r2
        l.nop
 
.if IN_FLASH
        .section .vectors, "ax"
        .org 0x600
.else
        .org (0x600 - 0x100 + _reset)
.endif
_alignerr:
.if 0
        /* Let's crash on align errors */
        l.addi  r1,r1,-128
        l.sw    0x08(r1),r2
        l.movhi r2,hi(_align)
        l.ori   r2,r2,lo(_align)
        l.jr    r2
        l.nop
.endif
        l.trap 0
        l.nop
        l.j 0
        l.nop
 
.if IN_FLASH
        .org 0x700
.else
        .org (0x700 - 0x100 + _reset)
.endif
_illinsn:
        /* Just trap */
        l.trap 0
        l.nop
        l.j 0
        l.nop
 
 
.if IN_FLASH
        .org 0x800
.else
        .org (0x800 - 0x100 + _reset)
.endif
_userint:
        l.addi  r1,r1,-128
        l.sw    0x4(r1),r2
        l.movhi r2,hi(_int_wrapper)
        l.ori   r2,r2,lo(_int_wrapper)
        l.jr    r2
        l.nop
 
        .section .text
_start:
.if IN_FLASH
/*        l.jal   _init_mc
        l.nop
*/
        /* Wait for SDRAM */
        l.addi  r3,r0,0x1000
1:      l.sfeqi r3,0
        l.bnf   1b
        l.addi  r3,r3,-1
.endif
        /* Copy form flash to sram */
.if IN_FLASH
        l.movhi r3,hi(_src_beg)
        l.ori   r3,r3,lo(_src_beg)
        l.movhi r4,hi(_vec_start)
        l.ori   r4,r4,lo(_vec_start)
        l.movhi r5,hi(_vec_end)
        l.ori   r5,r5,lo(_vec_end)
        l.sub   r5,r5,r4
        l.sfeqi r5,0
        l.bf    2f
        l.nop
1:      l.lwz   r6,0(r3)
        l.sw    0(r4),r6
        l.addi  r3,r3,4
        l.addi  r4,r4,4
        l.addi  r5,r5,-4
        l.sfgtsi r5,0
        l.bf    1b
        l.nop
2:
        l.movhi r4,hi(_dst_beg)
        l.ori   r4,r4,lo(_dst_beg)
        l.movhi r5,hi(_dst_end)
        l.ori   r5,r5,lo(_dst_end)
1:      l.sfgeu r4,r5
        l.bf    1f
        l.nop
        l.lwz   r8,0(r3)
        l.sw    0(r4),r8
        l.addi  r3,r3,4
        l.bnf   1b
        l.addi  r4,r4,4
1:
        l.addi  r3,r0,0
        l.addi  r4,r0,0
3:
.endif
/*
        l.jal   _ic_disable
        l.nop
*/
.if IC_ENABLE
        l.jal   _ic_enable
        l.nop
.endif
 
.if DC_ENABLE
        l.jal   _dc_enable
        l.nop
.endif
 
        l.movhi r1,hi(_stack-4)
        l.ori   r1,r1,lo(_stack-4)
        l.addi  r2,r0,-3
        l.and   r1,r1,r2
 
        l.movhi r2,hi(_main)
        l.ori   r2,r2,lo(_main)
        l.jr    r2
        l.addi  r2,r0,0
 
_ic_enable:
 
        /* Flush IC */
        l.addi  r10,r0,0
        l.addi  r11,r0,IC_SIZE
1:
        l.mtspr r0,r10,SPR_ICBIR
        l.sfne  r10,r11
        l.bf    1b
        l.addi  r10,r10,16
 
        /* Enable IC */
        l.mfspr r10,r0,SPR_SR
        l.ori   r10,r10,(SPR_SR_ICE|SPR_SR_SM)
        l.mtspr r0,r10,SPR_SR
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
        l.jr    r9
        l.nop
 
_ic_disable:
 
        l.addi  r10,r0,0
        l.addi  r11,r0,IC_SIZE
1:
        l.mtspr r0,r10,SPR_ICBIR
        l.sfne  r10,r11
        l.bf    1b
        l.addi  r10,r10,16
 
 
        l.mfspr r10,r0,SPR_SR
        l.movhi r11, 0xffff
        l.ori   r11, r11, 0xffef
        l.and   r10, r10, r11
        l.ori   r10, r10, SPR_SR_SM
        l.mtspr r0,r10,SPR_SR
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
        l.jr    r9
        l.nop
 
_dc_enable:
 
        /* Flush DC */
        l.addi  r10,r0,0
        l.addi  r11,r0,DC_SIZE
1:
        l.mtspr r0,r10,SPR_DCBIR
        l.sfne  r10,r11
        l.bf    1b
        l.addi  r10,r10,16
 
        /* Enable DC */
        l.mfspr r10,r0,SPR_SR
        l.ori   r10,r10,(SPR_SR_DCE|SPR_SR_SM)
        l.mtspr r0,r10,SPR_SR
 
        l.jr    r9
        l.nop
 
 
_tick:
        l.sw    0x8(r1),r4
        l.sw    0xc(r1),r5
        l.sw    0x10(r1),r6
        l.sw    0x14(r1),r7
        l.sw    0x18(r1),r8
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.sw    0x24(r1),r11
        l.sw    0x28(r1),r12
        l.sw    0x2c(r1),r13
        l.sw    0x30(r1),r14
        l.sw    0x34(r1),r15
        l.sw    0x38(r1),r16
        l.sw    0x3c(r1),r17
        l.sw    0x40(r1),r18
        l.sw    0x44(r1),r19
        l.sw    0x48(r1),r20
        l.sw    0x4c(r1),r21
        l.sw    0x50(r1),r22
        l.sw    0x54(r1),r23
        l.sw    0x58(r1),r24
        l.sw    0x5c(r1),r25
        l.sw    0x60(r1),r26
        l.sw    0x64(r1),r27
        l.sw    0x68(r1),r28
        l.sw    0x6c(r1),r29
        l.sw    0x70(r1),r30
        l.sw    0x74(r1),r31
        l.sw    0x78(r1),r3
 
        l.movhi r3,hi(_tick_interrupt)
        l.ori   r3,r3,lo(_tick_interrupt)
        l.jalr  r3
        l.nop
 
        l.lwz   r2,0x4(r1)
        l.lwz   r4,0x8(r1)
        l.lwz   r5,0xc(r1)
        l.lwz   r6,0x10(r1)
        l.lwz   r7,0x14(r1)
        l.lwz   r8,0x18(r1)
        l.lwz   r9,0x1c(r1)
        l.lwz   r10,0x20(r1)
        l.lwz   r11,0x24(r1)
        l.lwz   r12,0x28(r1)
        l.lwz   r13,0x2c(r1)
        l.lwz   r14,0x30(r1)
        l.lwz   r15,0x34(r1)
        l.lwz   r16,0x38(r1)
        l.lwz   r17,0x3c(r1)
        l.lwz   r18,0x40(r1)
        l.lwz   r19,0x44(r1)
        l.lwz   r20,0x48(r1)
        l.lwz   r21,0x4c(r1)
        l.lwz   r22,0x50(r1)
        l.lwz   r23,0x54(r1)
        l.lwz   r24,0x58(r1)
        l.lwz   r25,0x5c(r1)
        l.lwz   r26,0x60(r1)
        l.lwz   r27,0x64(r1)
        l.lwz   r28,0x68(r1)
        l.lwz   r29,0x6c(r1)
        l.lwz   r30,0x70(r1)
        l.mfspr r31,r0,0x40
        l.lwz   r31,0x74(r1)
        l.lwz   r3,0x78(r1)
 
        l.addi  r1,r1,128
        l.rfe
        l.nop
 
_int_wrapper:
        l.sw    0x8(r1),r4
        l.sw    0xc(r1),r5
        l.sw    0x10(r1),r6
        l.sw    0x14(r1),r7
        l.sw    0x18(r1),r8
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.sw    0x24(r1),r11
        l.sw    0x28(r1),r12
        l.sw    0x2c(r1),r13
        l.sw    0x30(r1),r14
        l.sw    0x34(r1),r15
        l.sw    0x38(r1),r16
        l.sw    0x3c(r1),r17
        l.sw    0x40(r1),r18
        l.sw    0x44(r1),r19
        l.sw    0x48(r1),r20
        l.sw    0x4c(r1),r21
        l.sw    0x50(r1),r22
        l.sw    0x54(r1),r23
        l.sw    0x58(r1),r24
        l.sw    0x5c(r1),r25
        l.sw    0x60(r1),r26
        l.sw    0x64(r1),r27
        l.sw    0x68(r1),r28
        l.sw    0x6c(r1),r29
        l.sw    0x70(r1),r30
        l.sw    0x74(r1),r31
        l.sw    0x78(r1),r3
 
        l.movhi r3,hi(_int_main)
        l.ori   r3,r3,lo(_int_main)
        l.jalr  r3
        l.nop
 
        l.lwz   r2,0x4(r1)
        l.lwz   r4,0x8(r1)
        l.lwz   r5,0xc(r1)
        l.lwz   r6,0x10(r1)
        l.lwz   r7,0x14(r1)
        l.lwz   r8,0x18(r1)
        l.lwz   r9,0x1c(r1)
        l.lwz   r10,0x20(r1)
        l.lwz   r11,0x24(r1)
        l.lwz   r12,0x28(r1)
        l.lwz   r13,0x2c(r1)
        l.lwz   r14,0x30(r1)
        l.lwz   r15,0x34(r1)
        l.lwz   r16,0x38(r1)
        l.lwz   r17,0x3c(r1)
        l.lwz   r18,0x40(r1)
        l.lwz   r19,0x44(r1)
        l.lwz   r20,0x48(r1)
        l.lwz   r21,0x4c(r1)
        l.lwz   r22,0x50(r1)
        l.lwz   r23,0x54(r1)
        l.lwz   r24,0x58(r1)
        l.lwz   r25,0x5c(r1)
        l.lwz   r26,0x60(r1)
        l.lwz   r27,0x64(r1)
        l.lwz   r28,0x68(r1)
        l.lwz   r29,0x6c(r1)
        l.lwz   r30,0x70(r1)
        l.lwz   r31,0x74(r1)
        l.lwz   r3,0x78(r1)
 
        l.mtspr r0,r0,SPR_PICSR
 
        l.addi  r1,r1,128
        l.rfe
        l.nop
 
_align:
        l.sw    0x0c(r1),r3
        l.sw    0x10(r1),r4
        l.sw    0x14(r1),r5
        l.sw    0x18(r1),r6
        l.sw    0x1c(r1),r7
        l.sw    0x20(r1),r8
        l.sw    0x24(r1),r9
        l.sw    0x28(r1),r10
        l.sw    0x2c(r1),r11
        l.sw    0x30(r1),r12
        l.sw    0x34(r1),r13
        l.sw    0x38(r1),r14
        l.sw    0x3c(r1),r15
        l.sw    0x40(r1),r16
        l.sw    0x44(r1),r17
        l.sw    0x48(r1),r18
        l.sw    0x4c(r1),r19
        l.sw    0x50(r1),r20
        l.sw    0x54(r1),r21
        l.sw    0x58(r1),r22
        l.sw    0x5c(r1),r23
        l.sw    0x60(r1),r24
        l.sw    0x64(r1),r25
        l.sw    0x68(r1),r26
        l.sw    0x6c(r1),r27
        l.sw    0x70(r1),r28
        l.sw    0x74(r1),r29
        l.sw    0x78(r1),r30
        l.sw    0x7c(r1),r31
 
        l.mfspr r2,r0,SPR_EEAR_BASE /* Load the efective addres */
        l.mfspr r5,r0,SPR_EPCR_BASE /* Load the insn address */
 
        l.lwz   r3,0(r5)    /* Load insn */
        l.srli  r4,r3,26    /* Shift left to get the insn opcode */
 
        l.sfeqi r4,0x00     /* Check if the load/store insn is in delay slot */
        l.bf    jmp
        l.sfeqi r4,0x01
        l.bf    jmp
        l.sfeqi r4,0x03
        l.bf    jmp
        l.sfeqi r4,0x04
        l.bf    jmp
        l.sfeqi r4,0x11
        l.bf    jr
        l.sfeqi r4,0x12
        l.bf    jr
        l.nop
        l.j     1f
        l.addi  r5,r5,4     /* Increment PC to get return insn address */
 
jmp:
        l.slli  r4,r3,6     /* Get the signed extended jump length */
        l.srai  r4,r4,4
 
        l.lwz   r3,4(r5)      /* Load the real load/store insn */
 
        l.add   r5,r5,r4      /* Calculate jump target address */
 
        l.j     1f
        l.srli  r4,r3,26    /* Shift left to get the insn opcode */
 
jr:
        l.slli  r4,r3,9     /* Shift to get the reg nb */
        l.andi  r4,r4,0x7c
 
        l.lwz   r3,4(r5)    /* Load the real load/store insn */
 
        l.add   r4,r4,r1    /* Load the jump register value from the stack */
        l.lwz   r5,0(r4)
 
        l.srli  r4,r3,26    /* Shift left to get the insn opcode */
 
 
1:      l.mtspr r0,r5,SPR_EPCR_BASE
 
        l.sfeqi r4,0x26
        l.bf    lhs
        l.sfeqi r4,0x25
        l.bf    lhz
        l.sfeqi r4,0x22
        l.bf    lws
        l.sfeqi r4,0x21
        l.bf    lwz
        l.sfeqi r4,0x37
        l.bf    sh
        l.sfeqi r4,0x35
        l.bf    sw
        l.nop
 
1:      l.j     1b      /* I don't know what to do */
        l.nop
 
lhs:    l.lbs   r5,0(r2)
        l.slli  r5,r5,8
        l.lbz   r6,1(r2)
        l.or    r5,r5,r6
        l.srli  r4,r3,19
        l.andi  r4,r4,0x7c
        l.add   r4,r4,r1
        l.j     align_end
        l.sw    0(r4),r5
 
lhz:    l.lbz   r5,0(r2)
        l.slli  r5,r5,8
        l.lbz   r6,1(r2)
        l.or    r5,r5,r6
        l.srli  r4,r3,19
        l.andi  r4,r4,0x7c
        l.add   r4,r4,r1
        l.j     align_end
        l.sw    0(r4),r5
 
lws:    l.lbs   r5,0(r2)
        l.slli  r5,r5,24
        l.lbz   r6,1(r2)
        l.slli  r6,r6,16
        l.or    r5,r5,r6
        l.lbz   r6,2(r2)
        l.slli  r6,r6,8
        l.or    r5,r5,r6
        l.lbz   r6,3(r2)
        l.or    r5,r5,r6
        l.srli  r4,r3,19
        l.andi  r4,r4,0x7c
        l.add   r4,r4,r1
        l.j     align_end
        l.sw    0(r4),r5
 
lwz:    l.lbz   r5,0(r2)
        l.slli  r5,r5,24
        l.lbz   r6,1(r2)
        l.slli  r6,r6,16
        l.or    r5,r5,r6
        l.lbz   r6,2(r2)
        l.slli  r6,r6,8
        l.or    r5,r5,r6
        l.lbz   r6,3(r2)
        l.or    r5,r5,r6
        l.srli  r4,r3,19
        l.andi  r4,r4,0x7c
        l.add   r4,r4,r1
        l.j     align_end
        l.sw    0(r4),r5
 
sh:
        l.srli  r4,r3,9
        l.andi  r4,r4,0x7c
        l.add   r4,r4,r1
        l.lwz   r5,0(r4)
        l.sb    1(r2),r5
        l.srli  r5,r5,8
        l.j     align_end
        l.sb    0(r2),r5
 
sw:
        l.srli  r4,r3,9
        l.andi  r4,r4,0x7c
        l.add   r4,r4,r1
        l.lwz   r5,0(r4)
        l.sb    3(r2),r5
        l.srli  r5,r5,8
        l.sb    2(r2),r5
        l.srli  r5,r5,8
        l.sb    1(r2),r5
        l.srli  r5,r5,8
        l.j     align_end
        l.sb    0(r2),r5
 
align_end:
        l.lwz   r2,0x08(r1)
        l.lwz   r3,0x0c(r1)
        l.lwz   r4,0x10(r1)
        l.lwz   r5,0x14(r1)
        l.lwz   r6,0x18(r1)
        l.lwz   r7,0x1c(r1)
        l.lwz   r8,0x20(r1)
        l.lwz   r9,0x24(r1)
        l.lwz   r10,0x28(r1)
        l.lwz   r11,0x2c(r1)
        l.lwz   r12,0x30(r1)
        l.lwz   r13,0x34(r1)
        l.lwz   r14,0x38(r1)
        l.lwz   r15,0x3c(r1)
        l.lwz   r16,0x40(r1)
        l.lwz   r17,0x44(r1)
        l.lwz   r18,0x48(r1)
        l.lwz   r19,0x4c(r1)
        l.lwz   r20,0x50(r1)
        l.lwz   r21,0x54(r1)
        l.lwz   r22,0x58(r1)
        l.lwz   r23,0x5c(r1)
        l.lwz   r24,0x60(r1)
        l.lwz   r25,0x64(r1)
        l.lwz   r26,0x68(r1)
        l.lwz   r27,0x6c(r1)
        l.lwz   r28,0x70(r1)
        l.lwz   r29,0x74(r1)
        l.lwz   r30,0x78(r1)
        l.mfspr r31,r0,0x40
        l.lwz   r31,0x7c(r1)
        l.addi  r1,r1,128
        l.rfe

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[/] [openrisc/] [trunk/] [bootloaders/] [orpmon/] [reset.S] - Blame information for rev 179

Line No.	Rev	Author	Line
1	2	marcus.erl	`#include "spr_defs.h"`
2			`#include "board.h"`
3			`#include "mc.h"`
4
5			`.extern _reset_support`
6			`.extern _eth_int`
7			`.extern _src_beg`
8			`.extern _dst_beg`
9			`.extern _dst_end`
10			`.extern _c_reset`
11			`.extern _int_main`
12			`.extern _tick_interrupt`
13			`.extern _crc32`
14
15			`/* Used by global.src_addr for default value */`
16			`.extern _src_addr`
17
18			`.global _align`
19			`.global _calc_mycrc32`
20			`.global _mycrc32`
21			`.global _mysize`
22
23			`.section .stack, "aw", @nobits`
24			`.space STACK_SIZE`
25			`_stack:`
26			`.section .crc`
27			`_mycrc32:`
28			`.word 0xcccccccc`
29			`_mysize:`
30			`.word 0xdddddddd`
31
32			`.if SELF_CHECK`
33			`_calc_mycrc32:`
34			`l.addi r3,r0,0`
35			`l.movhi r4,hi(_calc_mycrc32)`
36			`l.ori r4,r4,lo(_calc_mycrc32)`
37			`l.movhi r5,hi(_mysize)`
38			`l.ori r5,r5,lo(_mysize)`
39			`l.lwz r5,0(r5)`
40			`l.addi r1,r1,-4`
41			`l.sw 0(r1),r9`
42
43			`/* unsigned long crc32 (unsigned long crc, const unsigned char buf, unsigned long len); /`
44			`l.jal _crc32`
45			`l.nop`
46
47			`l.movhi r3,hi(_mycrc32)`
48			`l.ori r3,r3,lo(_mycrc32)`
49			`l.lwz r3,0(r3)`
50
51			`l.xor r11,r3,r11`
52			`l.lwz r9,0(r1)`
53			`l.jr r9`
54			`l.addi r1,r1,4`
55			`.endif`
56
57			`.org 0x100`
58	140	julius
59	2	marcus.erl	`.if IN_FLASH`
60			`.section .reset, "ax"`
61			`.else`
62			`.section .vectors, "ax"`
63			`.endif`
64
65			`_reset:`
66			`.if IN_FLASH`
67			`l.movhi r3,hi(MC_BASE_ADDR)`
68			`l.ori r3,r3,MC_BA_MASK`
69			`l.addi r5,r0,0x00`
70			`l.sw 0(r3),r5`
71			`.endif`
72			`l.addi r3,r0,SPR_SR_SM`
73			`l.mtspr r0,r3,SPR_SR`
74			`l.movhi r3,hi(_start)`
75			`l.ori r3,r3,lo(_start)`
76			`l.jr r3`
77			`l.nop`
78
79			`.if IN_FLASH`
80			`.section .vectors, "ax"`
81	140	julius	`.org 0x200`
82			`.else`
83			`.org (0x200 - 0x100 + _reset)`
84			`.endif`
85			`_buserr:`
86			`/* Just trap */`
87			`l.trap 0`
88			`l.nop`
89			`l.j 0`
90			`l.nop`
91
92
93			`.if IN_FLASH`
94			`.section .vectors, "ax"`
95	2	marcus.erl	`.org 0x500`
96			`.else`
97			`.org (0x500 - 0x100 + _reset)`
98			`.endif`
99	140	julius	`_tickint:`
100	2	marcus.erl	`l.addi r1,r1,-128`
101			`l.sw 0x4(r1),r2`
102			`l.movhi r2,hi(_tick)`
103			`l.ori r2,r2,lo(_tick)`
104			`l.jr r2`
105			`l.nop`
106
107			`.if IN_FLASH`
108			`.section .vectors, "ax"`
109			`.org 0x600`
110			`.else`
111			`.org (0x600 - 0x100 + _reset)`
112			`.endif`
113	140	julius	`_alignerr:`
114			`.if 0`
115			`/* Let's crash on align errors */`
116	2	marcus.erl	`l.addi r1,r1,-128`
117			`l.sw 0x08(r1),r2`
118			`l.movhi r2,hi(_align)`
119			`l.ori r2,r2,lo(_align)`
120			`l.jr r2`
121			`l.nop`
122	140	julius	`.endif`
123			`l.trap 0`
124			`l.nop`
125			`l.j 0`
126			`l.nop`
127
128			`.if IN_FLASH`
129			`.org 0x700`
130			`.else`
131			`.org (0x700 - 0x100 + _reset)`
132			`.endif`
133			`_illinsn:`
134			`/* Just trap */`
135			`l.trap 0`
136			`l.nop`
137			`l.j 0`
138			`l.nop`
139	2	marcus.erl
140	140	julius
141	2	marcus.erl	`.if IN_FLASH`
142			`.org 0x800`
143			`.else`
144			`.org (0x800 - 0x100 + _reset)`
145			`.endif`
146	140	julius	`_userint:`
147	2	marcus.erl	`l.addi r1,r1,-128`
148			`l.sw 0x4(r1),r2`
149			`l.movhi r2,hi(_int_wrapper)`
150			`l.ori r2,r2,lo(_int_wrapper)`
151			`l.jr r2`
152			`l.nop`
153
154			`.section .text`
155			`_start:`
156			`.if IN_FLASH`
157	140	julius	`/* l.jal _init_mc`
158	2	marcus.erl	`l.nop`
159	140	julius	`*/`
160	2	marcus.erl	`/* Wait for SDRAM */`
161			`l.addi r3,r0,0x1000`
162			`1: l.sfeqi r3,0`
163			`l.bnf 1b`
164			`l.addi r3,r3,-1`
165			`.endif`
166			`/* Copy form flash to sram */`
167			`.if IN_FLASH`
168			`l.movhi r3,hi(_src_beg)`
169			`l.ori r3,r3,lo(_src_beg)`
170			`l.movhi r4,hi(_vec_start)`
171			`l.ori r4,r4,lo(_vec_start)`
172			`l.movhi r5,hi(_vec_end)`
173			`l.ori r5,r5,lo(_vec_end)`
174			`l.sub r5,r5,r4`
175			`l.sfeqi r5,0`
176			`l.bf 2f`
177			`l.nop`
178			`1: l.lwz r6,0(r3)`
179			`l.sw 0(r4),r6`
180			`l.addi r3,r3,4`
181			`l.addi r4,r4,4`
182			`l.addi r5,r5,-4`
183			`l.sfgtsi r5,0`
184			`l.bf 1b`
185			`l.nop`
186			`2:`
187			`l.movhi r4,hi(_dst_beg)`
188			`l.ori r4,r4,lo(_dst_beg)`
189			`l.movhi r5,hi(_dst_end)`
190			`l.ori r5,r5,lo(_dst_end)`
191			`1: l.sfgeu r4,r5`
192			`l.bf 1f`
193			`l.nop`
194			`l.lwz r8,0(r3)`
195			`l.sw 0(r4),r8`
196			`l.addi r3,r3,4`
197			`l.bnf 1b`
198			`l.addi r4,r4,4`
199			`1:`
200			`l.addi r3,r0,0`
201			`l.addi r4,r0,0`
202			`3:`
203			`.endif`
204	140	julius	`/*`
205			`l.jal _ic_disable`
206			`l.nop`
207			`*/`
208	2	marcus.erl	`.if IC_ENABLE`
209			`l.jal _ic_enable`
210			`l.nop`
211			`.endif`
212
213			`.if DC_ENABLE`
214			`l.jal _dc_enable`
215			`l.nop`
216			`.endif`
217
218			`l.movhi r1,hi(_stack-4)`
219			`l.ori r1,r1,lo(_stack-4)`
220			`l.addi r2,r0,-3`
221			`l.and r1,r1,r2`
222
223			`l.movhi r2,hi(_main)`
224			`l.ori r2,r2,lo(_main)`
225			`l.jr r2`
226			`l.addi r2,r0,0`
227
228			`_ic_enable:`
229
230			`/* Flush IC */`
231			`l.addi r10,r0,0`
232			`l.addi r11,r0,IC_SIZE`
233			`1:`
234			`l.mtspr r0,r10,SPR_ICBIR`
235			`l.sfne r10,r11`
236			`l.bf 1b`
237			`l.addi r10,r10,16`
238
239			`/* Enable IC */`
240			`l.mfspr r10,r0,SPR_SR`
241			`l.ori r10,r10,(SPR_SR_ICE\|SPR_SR_SM)`
242			`l.mtspr r0,r10,SPR_SR`
243			`l.nop`
244			`l.nop`
245			`l.nop`
246			`l.nop`
247			`l.nop`
248
249			`l.jr r9`
250			`l.nop`
251
252	140	julius	`_ic_disable:`
253
254			`l.addi r10,r0,0`
255			`l.addi r11,r0,IC_SIZE`
256			`1:`
257			`l.mtspr r0,r10,SPR_ICBIR`
258			`l.sfne r10,r11`
259			`l.bf 1b`
260			`l.addi r10,r10,16`
261
262
263			`l.mfspr r10,r0,SPR_SR`
264			`l.movhi r11, 0xffff`
265			`l.ori r11, r11, 0xffef`
266			`l.and r10, r10, r11`
267			`l.ori r10, r10, SPR_SR_SM`
268			`l.mtspr r0,r10,SPR_SR`
269			`l.nop`
270			`l.nop`
271			`l.nop`
272			`l.nop`
273			`l.nop`
274
275			`l.jr r9`
276			`l.nop`
277
278	2	marcus.erl	`_dc_enable:`
279
280			`/* Flush DC */`
281			`l.addi r10,r0,0`
282			`l.addi r11,r0,DC_SIZE`
283			`1:`
284			`l.mtspr r0,r10,SPR_DCBIR`
285			`l.sfne r10,r11`
286			`l.bf 1b`
287			`l.addi r10,r10,16`
288
289			`/* Enable DC */`
290			`l.mfspr r10,r0,SPR_SR`
291			`l.ori r10,r10,(SPR_SR_DCE\|SPR_SR_SM)`
292			`l.mtspr r0,r10,SPR_SR`
293
294			`l.jr r9`
295			`l.nop`
296
297
298			`_tick:`
299			`l.sw 0x8(r1),r4`
300			`l.sw 0xc(r1),r5`
301			`l.sw 0x10(r1),r6`
302			`l.sw 0x14(r1),r7`
303			`l.sw 0x18(r1),r8`
304			`l.sw 0x1c(r1),r9`
305			`l.sw 0x20(r1),r10`
306			`l.sw 0x24(r1),r11`
307			`l.sw 0x28(r1),r12`
308			`l.sw 0x2c(r1),r13`
309			`l.sw 0x30(r1),r14`
310			`l.sw 0x34(r1),r15`
311			`l.sw 0x38(r1),r16`
312			`l.sw 0x3c(r1),r17`
313			`l.sw 0x40(r1),r18`
314			`l.sw 0x44(r1),r19`
315			`l.sw 0x48(r1),r20`
316			`l.sw 0x4c(r1),r21`
317			`l.sw 0x50(r1),r22`
318			`l.sw 0x54(r1),r23`
319			`l.sw 0x58(r1),r24`
320			`l.sw 0x5c(r1),r25`
321			`l.sw 0x60(r1),r26`
322			`l.sw 0x64(r1),r27`
323			`l.sw 0x68(r1),r28`
324			`l.sw 0x6c(r1),r29`
325			`l.sw 0x70(r1),r30`
326			`l.sw 0x74(r1),r31`
327			`l.sw 0x78(r1),r3`
328
329			`l.movhi r3,hi(_tick_interrupt)`
330			`l.ori r3,r3,lo(_tick_interrupt)`
331			`l.jalr r3`
332			`l.nop`
333
334			`l.lwz r2,0x4(r1)`
335			`l.lwz r4,0x8(r1)`
336			`l.lwz r5,0xc(r1)`
337			`l.lwz r6,0x10(r1)`
338			`l.lwz r7,0x14(r1)`
339			`l.lwz r8,0x18(r1)`
340			`l.lwz r9,0x1c(r1)`
341			`l.lwz r10,0x20(r1)`
342			`l.lwz r11,0x24(r1)`
343			`l.lwz r12,0x28(r1)`
344			`l.lwz r13,0x2c(r1)`
345			`l.lwz r14,0x30(r1)`
346			`l.lwz r15,0x34(r1)`
347			`l.lwz r16,0x38(r1)`
348			`l.lwz r17,0x3c(r1)`
349			`l.lwz r18,0x40(r1)`
350			`l.lwz r19,0x44(r1)`
351			`l.lwz r20,0x48(r1)`
352			`l.lwz r21,0x4c(r1)`
353			`l.lwz r22,0x50(r1)`
354			`l.lwz r23,0x54(r1)`
355			`l.lwz r24,0x58(r1)`
356			`l.lwz r25,0x5c(r1)`
357			`l.lwz r26,0x60(r1)`
358			`l.lwz r27,0x64(r1)`
359			`l.lwz r28,0x68(r1)`
360			`l.lwz r29,0x6c(r1)`
361			`l.lwz r30,0x70(r1)`
362			`l.mfspr r31,r0,0x40`
363			`l.lwz r31,0x74(r1)`
364			`l.lwz r3,0x78(r1)`
365
366			`l.addi r1,r1,128`
367			`l.rfe`
368			`l.nop`
369
370			`_int_wrapper:`
371			`l.sw 0x8(r1),r4`
372			`l.sw 0xc(r1),r5`
373			`l.sw 0x10(r1),r6`
374			`l.sw 0x14(r1),r7`
375			`l.sw 0x18(r1),r8`
376			`l.sw 0x1c(r1),r9`
377			`l.sw 0x20(r1),r10`
378			`l.sw 0x24(r1),r11`
379			`l.sw 0x28(r1),r12`
380			`l.sw 0x2c(r1),r13`
381			`l.sw 0x30(r1),r14`
382			`l.sw 0x34(r1),r15`
383			`l.sw 0x38(r1),r16`
384			`l.sw 0x3c(r1),r17`
385			`l.sw 0x40(r1),r18`
386			`l.sw 0x44(r1),r19`
387			`l.sw 0x48(r1),r20`
388			`l.sw 0x4c(r1),r21`
389			`l.sw 0x50(r1),r22`
390			`l.sw 0x54(r1),r23`
391			`l.sw 0x58(r1),r24`
392			`l.sw 0x5c(r1),r25`
393			`l.sw 0x60(r1),r26`
394			`l.sw 0x64(r1),r27`
395			`l.sw 0x68(r1),r28`
396			`l.sw 0x6c(r1),r29`
397			`l.sw 0x70(r1),r30`
398			`l.sw 0x74(r1),r31`
399			`l.sw 0x78(r1),r3`
400
401			`l.movhi r3,hi(_int_main)`
402			`l.ori r3,r3,lo(_int_main)`
403			`l.jalr r3`
404			`l.nop`
405
406			`l.lwz r2,0x4(r1)`
407			`l.lwz r4,0x8(r1)`
408			`l.lwz r5,0xc(r1)`
409			`l.lwz r6,0x10(r1)`
410			`l.lwz r7,0x14(r1)`
411			`l.lwz r8,0x18(r1)`
412			`l.lwz r9,0x1c(r1)`
413			`l.lwz r10,0x20(r1)`
414			`l.lwz r11,0x24(r1)`
415			`l.lwz r12,0x28(r1)`
416			`l.lwz r13,0x2c(r1)`
417			`l.lwz r14,0x30(r1)`
418			`l.lwz r15,0x34(r1)`
419			`l.lwz r16,0x38(r1)`
420			`l.lwz r17,0x3c(r1)`
421			`l.lwz r18,0x40(r1)`
422			`l.lwz r19,0x44(r1)`
423			`l.lwz r20,0x48(r1)`
424			`l.lwz r21,0x4c(r1)`
425			`l.lwz r22,0x50(r1)`
426			`l.lwz r23,0x54(r1)`
427			`l.lwz r24,0x58(r1)`
428			`l.lwz r25,0x5c(r1)`
429			`l.lwz r26,0x60(r1)`
430			`l.lwz r27,0x64(r1)`
431			`l.lwz r28,0x68(r1)`
432			`l.lwz r29,0x6c(r1)`
433			`l.lwz r30,0x70(r1)`
434			`l.lwz r31,0x74(r1)`
435			`l.lwz r3,0x78(r1)`
436
437			`l.mtspr r0,r0,SPR_PICSR`
438
439			`l.addi r1,r1,128`
440			`l.rfe`
441			`l.nop`
442
443			`_align:`
444			`l.sw 0x0c(r1),r3`
445			`l.sw 0x10(r1),r4`
446			`l.sw 0x14(r1),r5`
447			`l.sw 0x18(r1),r6`
448			`l.sw 0x1c(r1),r7`
449			`l.sw 0x20(r1),r8`
450			`l.sw 0x24(r1),r9`
451			`l.sw 0x28(r1),r10`
452			`l.sw 0x2c(r1),r11`
453			`l.sw 0x30(r1),r12`
454			`l.sw 0x34(r1),r13`
455			`l.sw 0x38(r1),r14`
456			`l.sw 0x3c(r1),r15`
457			`l.sw 0x40(r1),r16`
458			`l.sw 0x44(r1),r17`
459			`l.sw 0x48(r1),r18`
460			`l.sw 0x4c(r1),r19`
461			`l.sw 0x50(r1),r20`
462			`l.sw 0x54(r1),r21`
463			`l.sw 0x58(r1),r22`
464			`l.sw 0x5c(r1),r23`
465			`l.sw 0x60(r1),r24`
466			`l.sw 0x64(r1),r25`
467			`l.sw 0x68(r1),r26`
468			`l.sw 0x6c(r1),r27`
469			`l.sw 0x70(r1),r28`
470			`l.sw 0x74(r1),r29`
471			`l.sw 0x78(r1),r30`
472			`l.sw 0x7c(r1),r31`
473
474			`l.mfspr r2,r0,SPR_EEAR_BASE /* Load the efective addres */`
475			`l.mfspr r5,r0,SPR_EPCR_BASE /* Load the insn address */`
476
477			`l.lwz r3,0(r5) /* Load insn */`
478			`l.srli r4,r3,26 /* Shift left to get the insn opcode */`
479
480			`l.sfeqi r4,0x00 /* Check if the load/store insn is in delay slot */`
481			`l.bf jmp`
482			`l.sfeqi r4,0x01`
483			`l.bf jmp`
484			`l.sfeqi r4,0x03`
485			`l.bf jmp`
486			`l.sfeqi r4,0x04`
487			`l.bf jmp`
488			`l.sfeqi r4,0x11`
489			`l.bf jr`
490			`l.sfeqi r4,0x12`
491			`l.bf jr`
492			`l.nop`
493			`l.j 1f`
494			`l.addi r5,r5,4 /* Increment PC to get return insn address */`
495
496			`jmp:`
497			`l.slli r4,r3,6 /* Get the signed extended jump length */`
498			`l.srai r4,r4,4`
499
500			`l.lwz r3,4(r5) /* Load the real load/store insn */`
501
502			`l.add r5,r5,r4 /* Calculate jump target address */`
503
504			`l.j 1f`
505			`l.srli r4,r3,26 /* Shift left to get the insn opcode */`
506
507			`jr:`
508			`l.slli r4,r3,9 /* Shift to get the reg nb */`
509			`l.andi r4,r4,0x7c`
510
511			`l.lwz r3,4(r5) /* Load the real load/store insn */`
512
513			`l.add r4,r4,r1 /* Load the jump register value from the stack */`
514			`l.lwz r5,0(r4)`
515
516			`l.srli r4,r3,26 /* Shift left to get the insn opcode */`
517
518
519			`1: l.mtspr r0,r5,SPR_EPCR_BASE`
520
521			`l.sfeqi r4,0x26`
522			`l.bf lhs`
523			`l.sfeqi r4,0x25`
524			`l.bf lhz`
525			`l.sfeqi r4,0x22`
526			`l.bf lws`
527			`l.sfeqi r4,0x21`
528			`l.bf lwz`
529			`l.sfeqi r4,0x37`
530			`l.bf sh`
531			`l.sfeqi r4,0x35`
532			`l.bf sw`
533			`l.nop`
534
535			`1: l.j 1b /* I don't know what to do */`
536			`l.nop`
537
538			`lhs: l.lbs r5,0(r2)`
539			`l.slli r5,r5,8`
540			`l.lbz r6,1(r2)`
541			`l.or r5,r5,r6`
542			`l.srli r4,r3,19`
543			`l.andi r4,r4,0x7c`
544			`l.add r4,r4,r1`
545			`l.j align_end`
546			`l.sw 0(r4),r5`
547
548			`lhz: l.lbz r5,0(r2)`
549			`l.slli r5,r5,8`
550			`l.lbz r6,1(r2)`
551			`l.or r5,r5,r6`
552			`l.srli r4,r3,19`
553			`l.andi r4,r4,0x7c`
554			`l.add r4,r4,r1`
555			`l.j align_end`
556			`l.sw 0(r4),r5`
557
558			`lws: l.lbs r5,0(r2)`
559			`l.slli r5,r5,24`
560			`l.lbz r6,1(r2)`
561			`l.slli r6,r6,16`
562			`l.or r5,r5,r6`
563			`l.lbz r6,2(r2)`
564			`l.slli r6,r6,8`
565			`l.or r5,r5,r6`
566			`l.lbz r6,3(r2)`
567			`l.or r5,r5,r6`
568			`l.srli r4,r3,19`
569			`l.andi r4,r4,0x7c`
570			`l.add r4,r4,r1`
571			`l.j align_end`
572			`l.sw 0(r4),r5`
573
574			`lwz: l.lbz r5,0(r2)`
575			`l.slli r5,r5,24`
576			`l.lbz r6,1(r2)`
577			`l.slli r6,r6,16`
578			`l.or r5,r5,r6`
579			`l.lbz r6,2(r2)`
580			`l.slli r6,r6,8`
581			`l.or r5,r5,r6`
582			`l.lbz r6,3(r2)`
583			`l.or r5,r5,r6`
584			`l.srli r4,r3,19`
585			`l.andi r4,r4,0x7c`
586			`l.add r4,r4,r1`
587			`l.j align_end`
588			`l.sw 0(r4),r5`
589
590			`sh:`
591			`l.srli r4,r3,9`
592			`l.andi r4,r4,0x7c`
593			`l.add r4,r4,r1`
594			`l.lwz r5,0(r4)`
595			`l.sb 1(r2),r5`
596			`l.srli r5,r5,8`
597			`l.j align_end`
598			`l.sb 0(r2),r5`
599
600			`sw:`
601			`l.srli r4,r3,9`
602			`l.andi r4,r4,0x7c`
603			`l.add r4,r4,r1`
604			`l.lwz r5,0(r4)`
605			`l.sb 3(r2),r5`
606			`l.srli r5,r5,8`
607			`l.sb 2(r2),r5`
608			`l.srli r5,r5,8`
609			`l.sb 1(r2),r5`
610			`l.srli r5,r5,8`
611			`l.j align_end`
612			`l.sb 0(r2),r5`
613
614			`align_end:`
615			`l.lwz r2,0x08(r1)`
616			`l.lwz r3,0x0c(r1)`
617			`l.lwz r4,0x10(r1)`
618			`l.lwz r5,0x14(r1)`
619			`l.lwz r6,0x18(r1)`
620			`l.lwz r7,0x1c(r1)`
621			`l.lwz r8,0x20(r1)`
622			`l.lwz r9,0x24(r1)`
623			`l.lwz r10,0x28(r1)`
624			`l.lwz r11,0x2c(r1)`
625			`l.lwz r12,0x30(r1)`
626			`l.lwz r13,0x34(r1)`
627			`l.lwz r14,0x38(r1)`
628			`l.lwz r15,0x3c(r1)`
629			`l.lwz r16,0x40(r1)`
630			`l.lwz r17,0x44(r1)`
631			`l.lwz r18,0x48(r1)`
632			`l.lwz r19,0x4c(r1)`
633			`l.lwz r20,0x50(r1)`
634			`l.lwz r21,0x54(r1)`
635			`l.lwz r22,0x58(r1)`
636			`l.lwz r23,0x5c(r1)`
637			`l.lwz r24,0x60(r1)`
638			`l.lwz r25,0x64(r1)`
639			`l.lwz r26,0x68(r1)`
640			`l.lwz r27,0x6c(r1)`
641			`l.lwz r28,0x70(r1)`
642			`l.lwz r29,0x74(r1)`
643			`l.lwz r30,0x78(r1)`
644			`l.mfspr r31,r0,0x40`
645			`l.lwz r31,0x7c(r1)`
646			`l.addi r1,r1,128`
647			`l.rfe`