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1 2 marcus.erl
/* sim.cfg -- Simulator configuration script file
2
   Copyright (C) 2001-2002, Marko Mlinar, markom@opencores.org
3
 
4
This file is part of OpenRISC 1000 Architectural Simulator.
5
It contains the default configuration and help about configuring
6
the simulator.
7
 
8
This program is free software; you can redistribute it and/or modify
9
it under the terms of the GNU General Public License as published by
10
the Free Software Foundation; either version 2 of the License, or
11
(at your option) any later version.
12
 
13
This program is distributed in the hope that it will be useful,
14
but WITHOUT ANY WARRANTY; without even the implied warranty of
15
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16
GNU General Public License for more details.
17
 
18
You should have received a copy of the GNU General Public License
19
along with this program; if not, write to the Free Software
20
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
21
 
22
 
23
/* INTRODUCTION
24
 
25
   The ork1sim has various parameters, that are set in configuration files
26
   like this one. The user can switch between configurations at startup by
27
   specifying the required configuration file with the -f  option.
28
   If no configuration file is specified or1ksim searches for the default
29
   configuration file sim.cfg. First it searches for './sim.cfg'. If this
30
   file is not found, it searches for '~/or1k/sim.cfg'. If this file is
31
   not found too, it reverts to the built-in default configuration.
32
 
33
   NOTE: Users should not rely on the built-in configuration, since the
34
         default configuration may differ between version.
35
         Rather create a configuration file that sets all critical values.
36
 
37
   This file may contain (standard C) comments only - no // support.
38
 
39
   Configure files may be be included, using:
40
   include "file_name_to_include"
41
 
42
   Like normal configuration files, the included file is divided into
43
   sections. Each section is described in detail also.
44
 
45
   Some section have subsections. One example of such a subsection is:
46
 
47
   device 
48
     instance specific parameters...
49
   enddevice
50
 
51
   which creates a device instance.
52
*/
53
 
54
 
55
/* MEMORY SECTION
56
 
57
   This section specifies how the memory is generated and the blocks
58
   it consists of.
59
 
60
   type = random/unknown/pattern
61
      Specifies the initial memory values.
62
      'random' generates random memory using seed 'random_seed'.
63
      'pattern' fills memory with 'pattern'.
64
      'unknown' does not specify how memory should be generated,
65
      leaving the memory in a undefined state. This is the fastest
66
      option.
67
 
68
   random_seed = 
69
      random seed for randomizer, used if type = 'random'.
70
 
71
   pattern = 
72
      pattern to fill memory, used if type = 'pattern'.
73
 
74
   nmemories = 
75
      number of memory instances connected
76
 
77
   instance specific:
78
     baseaddr = 
79
        memory start address
80
 
81
     size = 
82
        memory size
83
 
84
     name = ""
85
        memory block name
86
 
87
     ce = 
88
        chip enable index of the memory instance
89
 
90
     delayr = 
91
        cycles, required for read access, -1 if instance does not support reading
92
 
93
     delayw = 
94
        cycles, required for write access, -1 if instance does not support writing
95
 
96
     log = ""
97
        filename, where to log memory accesses to, no log, if log command is not specified
98
*/
99
 
100
 
101
section memory
102
  /*random_seed = 12345
103
  type = random*/
104
  pattern = 0x00
105
  type = unknown /* Fastest */
106
 
107
 
108
  nmemories = 3
109
  device 0
110
    name = "FLASH"
111
    ce = 0
112
    baseaddr = 0xf0000000
113
    size = 0x00800000
114
    delayr = 10
115
    delayw = -1
116
  enddevice
117
 
118
  device 1
119
    name = "RAM"
120
    ce = 1
121
    baseaddr = 0x00000000
122
    size = 0x00400000
123
    delayr = 1
124
    delayw = 2
125
  enddevice
126
 
127
  device 2
128
    name = "SRAM"
129
    ce = 2
130
    baseaddr = 0x08000000
131
    size = 0x00400000
132
    delayr = 1
133
    delayw = 2
134
  enddevice
135
end
136
 
137
 
138
/* IMMU SECTION
139
 
140
    This section configures the Instruction Memory Manangement Unit
141
 
142
    enabled = 0/1
143
       '0': disabled
144
       '1': enabled
145
       (NOTE: UPR bit is set)
146
 
147
    nsets = 
148
       number of ITLB sets; must be power of two
149
 
150
    nways = 
151
       number of ITLB ways
152
 
153
    pagesize = 
154
       instruction page size; must be power of two
155
 
156
    entrysize = 
157
       instruction entry size in bytes
158
 
159
    ustates = 
160
       number of ITLB usage states (2, 3, 4 etc., max is 4)
161
 
162
    hitdelay = 
163
       number of cycles immu hit costs
164
 
165
    missdelay = 
166
       number of cycles immu miss costs
167
*/
168
 
169
section immu
170
  enabled = 1
171
  nsets = 64
172
  nways = 1
173
  pagesize = 8192
174
  hitdelay = 0
175
  missdelay = 0
176
end
177
 
178
 
179
/* DMMU SECTION
180
 
181
    This section configures the Data Memory Manangement Unit
182
 
183
    enabled = 0/1
184
       '0': disabled
185
       '1': enabled
186
       (NOTE: UPR bit is set)
187
 
188
    nsets = 
189
       number of DTLB sets; must be power of two
190
 
191
    nways = 
192
       number of DTLB ways
193
 
194
    pagesize = 
195
       data page size; must be power of two
196
 
197
    entrysize = 
198
       data entry size in bytes
199
 
200
    ustates = 
201
       number of DTLB usage states (2, 3, 4 etc., max is 4)
202
 
203
    hitdelay = 
204
       number of cycles dmmu hit costs
205
 
206
    missdelay = 
207
       number of cycles dmmu miss costs
208
*/
209
 
210
section dmmu
211
  enabled = 1
212
  nsets = 64
213
  nways = 1
214
  pagesize = 8192
215
  hitdelay = 0
216
  missdelay = 0
217
end
218
 
219
 
220
/* IC SECTION
221
 
222
   This section configures the Instruction Cache
223
 
224
   enabled = 0/1
225
       '0': disabled
226
       '1': enabled
227
      (NOTE: UPR bit is set)
228
 
229
   nsets = 
230
      number of IC sets; must be power of two
231
 
232
   nways = 
233
      number of IC ways
234
 
235
   blocksize = 
236
      IC block size in bytes; must be power of two
237
 
238
   ustates = 
239
      number of IC usage states (2, 3, 4 etc., max is 4)
240
 
241
   hitdelay = 
242
      number of cycles ic hit costs
243
 
244
    missdelay = 
245
      number of cycles ic miss costs
246
*/
247
 
248
section ic
249
  enabled = 1
250
  nsets = 256
251
  nways = 1
252
  blocksize = 16
253
  hitdelay = 0
254
  missdelay = 0
255
end
256
 
257
 
258
/* DC SECTION
259
 
260
   This section configures the Data Cache
261
 
262
   enabled = 0/1
263
       '0': disabled
264
       '1': enabled
265
      (NOTE: UPR bit is set)
266
 
267
   nsets = 
268
      number of DC sets; must be power of two
269
 
270
   nways = 
271
      number of DC ways
272
 
273
   blocksize = 
274
      DC block size in bytes; must be power of two
275
 
276
   ustates = 
277
      number of DC usage states (2, 3, 4 etc., max is 4)
278
 
279
   load_hitdelay = 
280
      number of cycles dc load hit costs
281
 
282
   load_missdelay = 
283
      number of cycles dc load miss costs
284
 
285
   store_hitdelay = 
286
      number of cycles dc load hit costs
287
 
288
   store_missdelay = 
289
      number of cycles dc load miss costs
290
*/
291
 
292
section dc
293
  enabled = 1
294
  nsets = 256
295
  nways = 1
296
  blocksize = 16
297
  load_hitdelay = 0
298
  load_missdelay = 0
299
  store_hitdelay = 0
300
  store_missdelay = 0
301
end
302
 
303
 
304
/* SIM SECTION
305
 
306
  This section specifies how or1ksim should behave.
307
 
308
  verbose = 0/1
309
       '0': don't print extra messages
310
       '1': print extra messages
311
 
312
  debug = 0-9
313
 
314
      1-9: debug message level.
315
           higher numbers produce more messages
316
 
317
  profile = 0/1
318
      '0': don't generate profiling file 'sim.profile'
319
      '1': don't generate profiling file 'sim.profile'
320
 
321
  prof_fn = ""
322
      optional filename for the profiling file.
323
      valid only if 'profile' is set
324
 
325
  mprofile = 0/1
326
      '0': don't generate memory profiling file 'sim.mprofile'
327
      '1': generate memory profiling file 'sim.mprofile'
328
 
329
  mprof_fn = ""
330
      optional filename for the memory profiling file.
331
      valid only if 'mprofile' is set
332
 
333
  history = 0/1
334
      '0': don't track execution flow
335
      '1': track execution flow
336
      Execution flow can be tracked for the simulator's
337
      'hist' command. Useful for back-trace debugging.
338
 
339
  iprompt = 0/1
340
     '0': start in  (so what do we start in ???)
341
     '1': start in interactive prompt.
342
 
343
  exe_log = 0/1
344
      '0': don't generate execution log.
345
      '1': generate execution log.
346
 
347
  exe_log = default/hardware/simple/software
348
      type of execution log, default is used when not specified
349
 
350
  exe_log_start = 
351
      index of first instruction to start logging, default = 0
352
 
353
  exe_log_end = 
354
      index of last instruction to end logging; not limited, if omitted
355
 
356
  exe_log_marker = 
357
       specifies number of instructions before horizontal marker is
358
      printed; if zero, markers are disabled (default)
359
 
360
  exe_log_fn = ""
361
      filename for the exection log file.
362
      valid only if 'exe_log' is set
363
 
364
  spr_log = 0/1
365
      '0': log reads/writes to/from sprs
366
      '1': don't log reads/write to/from sprs
367
 
368
  spr_log_fn = ""
369
      filename for the sprs log file.
370
      valid only if 'spr_log' is set
371
 
372
  clkcycle = [ps|ns|us|ms]
373
      specifies time measurement for one cycle
374
*/
375
 
376
section sim
377
  /* verbose = 1 */
378
  debug = 0
379
  profile = 0
380
  prof_fn = "sim.profile"
381
 
382
  history = 1
383
  /* iprompt = 0 */
384
  exe_log = 0
385
  exe_log_type = software
386
  exe_log_start = 0
387
/*  exe_log_end = 20000000*/
388
  exe_log_marker = 10000
389
  exe_log_fn = "executed.log"
390
 
391
  spr_log = 0
392
  spr_log_fn = "spr.log"
393
  clkcycle = 100ns
394
end
395
 
396
 
397
/* SECTION VAPI
398
 
399
    This section configures the Verification API, used for Advanced
400
    Core Verification.
401
 
402
    enabled = 0/1
403
        '0': disbable VAPI server
404
        '1': enable/start VAPI server
405
 
406
    server_port = 
407
        TCP/IP port to start VAPI server on
408
 
409
    log_enabled = 0/1
410
       '0': disable VAPI requests logging
411
       '1': enable VAPI requests logging
412
 
413
    hide_device_id = 0/1
414
       '0': don't log device id (for compatability with old version)
415
       '1': log device id
416
 
417
 
418
    vapi_fn = 
419
       filename for the log file.
420
       valid only if log_enabled is set
421
*/
422
 
423
section VAPI
424
  enabled = 0
425
  server_port = 9998
426
  log_enabled = 0
427
  vapi_log_fn = "vapi.log"
428
end
429
 
430
 
431
/* CPU SECTION
432
 
433
   This section specifies various CPU parameters.
434
 
435
   ver = 
436
   rev = 
437
      specifies version and revision of the CPU used
438
 
439
   upr = 
440
      changes the upr register
441
 
442
   sr = 
443
      sets the initial Supervision Register value
444
 
445
   superscalar = 0/1
446
      '0': CPU is scalar
447
      '1': CPU is superscalar
448
      (modify cpu/or32/execute.c to tune superscalar model)
449
 
450
   hazards = 0/1
451
      '0': don't track data hazards in superscalar CPU
452
      '1': track data hazards in superscalar CPU
453
      If tracked, data hazards can be displayed using the
454
      simulator's 'r' command.
455
 
456
   dependstats = 0/1
457
      '0': don't calculate inter-instruction dependencies.
458
      '1': calculate inter-instruction dependencies.
459
      If calculated, inter-instruction dependencies can be
460
      displayed using the simulator's 'stat' command.
461
 
462
   sbuf_len = 
463
      length of store buffer (<= 256), 0 = disabled
464
*/
465
 
466
section cpu
467
  ver = 0x1200
468
  rev = 0x0001
469
  /* upr = */
470
  superscalar = 0
471
  hazards = 0
472
  dependstats = 0
473
  sbuf_len = 0
474
end
475
 
476
 
477
/* PM SECTION
478
 
479
   This section specifies Power Management parameters
480
 
481
   enabled = 0/1
482
      '0': disable power management
483
      '1': enable power management
484
*/
485
 
486
section pm
487
  enabled = 0
488
end
489
 
490
 
491
/* BPB SECTION
492
 
493
   This section specifies how branch prediction should behave.
494
 
495
   enabled = 0/1
496
     '0': disable branch prediction
497
     '1': enable branch prediction
498
 
499
   btic = 0/1
500
     '0': disable branch target instruction cache model
501
     '1': enable branch target instruction cache model
502
 
503
   sbp_bf_fwd = 0/1
504
     Static branch prediction for 'l.bf'
505
     '0': don't use forward prediction
506
     '1': use forward prediction
507
 
508
   sbp_bnf_fwd = 0/1
509
     Static branch prediction for 'l.bnf'
510
     '0': don't use forward prediction
511
     '1': use forward prediction
512
 
513
   hitdelay = 
514
       number of cycles bpb hit costs
515
 
516
   missdelay = 
517
       number of cycles bpb miss costs
518
*/
519
 
520
section bpb
521
  enabled = 0
522
  btic = 0
523
  sbp_bf_fwd = 0
524
  sbp_bnf_fwd = 0
525
  hitdelay = 0
526
  missdelay = 0
527
end
528
 
529
 
530
/* DEBUG SECTION
531
 
532
   This sections specifies how the debug unit should behave.
533
 
534
   enabled = 0/1
535
      '0': disable debug unit
536
      '1': enable debug unit
537
 
538
   gdb_enabled = 0/1
539
      '0': don't start gdb server
540
      '1': start gdb server at port 'server_port'
541
 
542
   server_port = 
543
      TCP/IP port to start gdb server on
544
      valid only if gdb_enabled is set
545
 
546
   vapi_id = 
547
      Used to create "fake" vapi log file containing the JTAG proxy messages.
548
*/
549
 
550
section debug
551
  enabled = 0
552
  gdb_enabled = 0
553
  server_port = 9999
554
end
555
 
556
 
557
/* MC SECTION
558
 
559
   This section configures the memory controller
560
 
561
   enabled = 0/1
562
     '0': disable memory controller
563
     '1': enable memory controller
564
 
565
   baseaddr = 
566
      address of first MC register
567
 
568
   POC = 
569
      Power On Configuration register
570
*/
571
 
572
section mc
573
  enabled = 0
574
  baseaddr = 0x93000000
575
  POC = 0x00000008                 /* Power on configuration register */
576
end
577
 
578
 
579
/* UART SECTION
580
 
581
   This section configures the UARTs
582
 
583
     enabled = <0|1>
584
        Enable/disable the peripheral.  By default if it is enabled.
585
 
586
     baseaddr = 
587
        address of first UART register for this device
588
 
589
 
590
     channel = :
591
 
592
        The channel parameter indicates the source of received UART characters
593
        and the sink for transmitted UART characters.
594
 
595
        The  can be either "file", "xterm", "tcp", "fd", or "tty"
596
        (without quotes).
597
 
598
          A) To send/receive characters from a pair of files, use a file
599
             channel:
600
 
601
               channel=file:,
602
 
603
          B) To create an interactive terminal window, use an xterm channel:
604
 
605
               channel=xterm:[]*
606
 
607
          C) To create a bidirectional tcp socket which one could, for example,
608
             access via telnet, use a tcp channel:
609
 
610
               channel=tcp:
611
 
612
          D) To cause the UART to read/write from existing numeric file
613
             descriptors, use an fd channel:
614
 
615
               channel=fd:,
616
 
617
          E) To connect the UART to a physical serial port, create a tty
618
             channel:
619
 
620
               channel=tty:device=/dev/ttyS0,baud=9600
621
 
622
     irq = 
623
        irq number for this device
624
 
625
     16550 = 0/1
626
        '0': this device is a UART16450
627
        '1': this device is a UART16550
628
 
629
     jitter = 
630
        in msecs... time to block, -1 to disable it
631
 
632
     vapi_id = 
633
        VAPI id of this instance
634
*/
635
 
636
section uart
637
  enabled = 1
638
  baseaddr = 0x90000000
639
  irq = 2
640
  channel = "file:uart0.rx,uart0.tx"
641
  jitter = -1                     /* async behaviour */
642
  16550 = 1
643
end
644
 
645
 
646
/* DMA SECTION
647
 
648
   This section configures the DMAs
649
 
650
     enabled = <0|1>
651
        Enable/disable the peripheral.  By default if it is enabled.
652
 
653
     baseaddr = 
654
        address of first DMA register for this device
655
 
656
     irq = 
657
        irq number for this device
658
 
659
     vapi_id = 
660
        VAPI id of this instance
661
*/
662
 
663
section dma
664
  enabled = 1
665
  baseaddr = 0x9a000000
666
  irq = 11
667
end
668
 
669
 
670
/* ETHERNET SECTION
671
 
672
   This section configures the ETHERNETs
673
 
674
     enabled = <0|1>
675
        Enable/disable the peripheral.  By default if it is enabled.
676
 
677
     baseaddr = 
678
        address of first ethernet register for this device
679
 
680
     dma = 
681
        which controller is this ethernet "connected" to
682
 
683
     irq = 
684
        ethernet mac IRQ level
685
 
686
     rtx_type = 
687
        use 0 - file interface, 1 - socket interface
688
 
689
     rx_channel = 
690
        DMA channel used for RX
691
 
692
     tx_channel = 
693
        DMA channel used for TX
694
 
695
     rxfile = ""
696
        filename, where to read data from
697
 
698
     txfile = ""
699
        filename, where to write data to
700
 
701
     sockif = ""
702
        interface name of ethernet socket
703
 
704
     vapi_id = 
705
        VAPI id of this instance
706
*/
707
 
708
section ethernet
709
  baseaddr = 0x92000000
710
  dma = 0
711
  irq = 4
712
  rtx_type = 0
713
  tx_channel = 0
714
  rx_channel = 1
715
  rxfile = "eth0.rx"
716
  txfile = "eth0.tx"
717
  sockif = "eth0"
718
end
719
 
720
 
721
/* GPIO SECTION
722
 
723
   This section configures the GPIOs
724
 
725
     enabled = <0|1>
726
        Enable/disable the peripheral.  By default if it is enabled.
727
 
728
     baseaddr = 
729
        address of first GPIO register for this device
730
 
731
     irq = 
732
        irq number for this device
733
 
734
     base_vapi_id = 
735
        first VAPI id of this instance
736
        GPIO uses 8 consecutive VAPI IDs
737
*/
738
 
739
section gpio
740
  enabled = 1
741
  baseaddr = 0x91000000
742
  irq = 3
743
  base_vapi_id = 0x0200
744
end
745
 
746
/* VGA SECTION
747
 
748
    This section configures the VGA/LCD controller
749
 
750
      enabled = <0|1>
751
        Enable/disable the peripheral.  By default if it is enabled.
752
 
753
      baseaddr = 
754
        address of first VGA register
755
 
756
      irq = 
757
        irq number for this device
758
 
759
      refresh_rate = 
760
        number of cycles between screen dumps
761
 
762
      filename = ""
763
        template name for generated names (e.g. "primary" produces "primary0023.bmp")
764
*/
765
 
766
section vga
767
  enabled = 1
768
  baseaddr = 0x97100000
769
  irq = 8
770
  refresh_rate = 100000
771
  filename = "primary"
772
end
773
 
774
 
775
/* TICK TIMER SECTION
776
 
777
    This section configures tick timer
778
 
779
    enabled = 0/1
780
      whether tick timer is enabled
781
 
782
    irq = 
783
      irq number
784
*/
785
/*
786
section tick
787
  enabled = 1
788
  irq = 0
789
end
790
*/
791
 
792
/* FB SECTION
793
 
794
    This section configures the frame buffer
795
 
796
    enabled = <0|1>
797
      Enable/disable the peripheral.  By default if it is enabled.
798
 
799
    baseaddr = 
800
      base address of frame buffer
801
 
802
    paladdr = 
803
      base address of first palette entry
804
 
805
    refresh_rate = 
806
      number of cycles between screen dumps
807
 
808
    filename = ""
809
      template name for generated names (e.g. "primary" produces "primary0023.bmp")
810
*/
811
 
812
section fb
813
  enabled = 1
814
  baseaddr = 0x97000000
815
  refresh_rate = 1000000
816
  filename = "primary"
817
end
818
 
819
 
820
/* KBD SECTION
821
 
822
    This section configures the PS/2 compatible keyboard
823
 
824
    baseaddr = 
825
      base address of the keyboard device
826
 
827
    rxfile = ""
828
      filename, where to read data from
829
*/
830
 
831
section kbd
832
  enabled = 1
833
  irq = 5
834
  baseaddr = 0x94000000
835
  rxfile = "kbd.rx"
836
end
837
 
838
 
839
/* ATA SECTION
840
 
841
    This section configures the ATA/ATAPI host controller
842
 
843
      baseaddr = 
844
        address of first ATA register
845
 
846
      enabled = <0|1>
847
        Enable/disable the peripheral.  By default if it is enabled.
848
 
849
      irq = 
850
        irq number for this device
851
 
852
      debug = 
853
        debug level for ata models.
854
        0: no debug messages
855
        1: verbose messages
856
        3: normal messages (more messages than verbose)
857
        5: debug messages (normal debug messages)
858
        7: flow control messages (debug statemachine flows)
859
        9: low priority message (display everything the code does)
860
 
861
      dev_type0/1 = 
862
        ata device 0 type
863
        0: NO_CONNeCT: none (not connected)
864
        1: FILE      : simulated harddisk
865
        2: LOCAL     : local system harddisk
866
 
867
      dev_file0/1 = ""
868
        filename for simulated ATA device
869
        valid only if dev_type0 == 1
870
 
871
      dev_size0/1 = 
872
        size of simulated hard-disk (in MBytes)
873
        valid only if dev_type0 == 1
874
 
875
      dev_packet0/1 = 
876
        0: simulated ATA device does NOT implement PACKET command feature set
877
        1: simulated ATA device does implement PACKET command feature set
878
 
879
   FIXME: irq number
880
*/
881
 
882
section ata
883
  enabled = 1
884
  baseaddr = 0x9e000000
885
  irq = 15
886
 
887
  dev_type0   = 1
888
  dev_file0   = "/tmp/sim_atadev0"
889
  dev_size0   = 1
890
  dev_packet0 = 0
891
 
892
  dev_type1   = 0
893
  dev_file1   = ""
894
  dev_size1   = 0
895
  dev_packet1 = 0
896
end
897
 
898
 
899
/* CUC SECTION
900
 
901
    This section configures the OpenRISC Custom Unit Compiler
902
 
903
    memory_order = none/weak/strong/exact
904
      none   different memory ordering, even if there are dependencies,
905
             burst can be made, width can change
906
      weak   different memory ordering, if there cannot be dependencies
907
             burst can be made, width can change
908
      strong same memory ordering, burst can be made, width can change
909
      exact  exacltly the same memory ordering and widths
910
 
911
    calling_convention = 0/1
912
      whether programs follow OpenRISC calling conventions
913
 
914
    enable_bursts = 0/1
915
      whether burst are detected
916
 
917
    no_multicycle = 0/1
918
      if selected no multicycle logic paths will be generated
919
 
920
    timings_fn = ""
921
*/
922
 
923
section cuc
924
  memory_order = weak
925
  calling_convention = 1
926
  enable_bursts = 1
927
  no_multicycle = 1
928
  timings_fn = "virtex.tim"
929
end
930
 

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