OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [bootloaders/] [orpmon/] [sim.cfg] - Blame information for rev 569

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 marcus.erl
/* sim.cfg -- Simulator configuration script file
2
   Copyright (C) 2001-2002, Marko Mlinar, markom@opencores.org
3
 
4
This file is part of OpenRISC 1000 Architectural Simulator.
5
It contains the default configuration and help about configuring
6
the simulator.
7
 
8
This program is free software; you can redistribute it and/or modify
9
it under the terms of the GNU General Public License as published by
10
the Free Software Foundation; either version 2 of the License, or
11
(at your option) any later version.
12
 
13
This program is distributed in the hope that it will be useful,
14
but WITHOUT ANY WARRANTY; without even the implied warranty of
15
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16
GNU General Public License for more details.
17
 
18
You should have received a copy of the GNU General Public License
19
along with this program; if not, write to the Free Software
20
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
21
 
22
 
23
/* INTRODUCTION
24
 
25
   The ork1sim has various parameters, that are set in configuration files
26
   like this one. The user can switch between configurations at startup by
27
   specifying the required configuration file with the -f  option.
28
   If no configuration file is specified or1ksim searches for the default
29
   configuration file sim.cfg. First it searches for './sim.cfg'. If this
30
   file is not found, it searches for '~/or1k/sim.cfg'. If this file is
31
   not found too, it reverts to the built-in default configuration.
32
 
33
   NOTE: Users should not rely on the built-in configuration, since the
34
         default configuration may differ between version.
35
         Rather create a configuration file that sets all critical values.
36
 
37
   This file may contain (standard C) comments only - no // support.
38
 
39
   Configure files may be be included, using:
40
   include "file_name_to_include"
41
 
42
   Like normal configuration files, the included file is divided into
43
   sections. Each section is described in detail also.
44
 
45
   Some section have subsections. One example of such a subsection is:
46
 
47
   device 
48
     instance specific parameters...
49
   enddevice
50
 
51
   which creates a device instance.
52
*/
53
 
54
 
55
/* MEMORY SECTION
56
 
57
   This section specifies how the memory is generated and the blocks
58
   it consists of.
59
 
60
   type = random/unknown/pattern
61
      Specifies the initial memory values.
62
      'random' generates random memory using seed 'random_seed'.
63
      'pattern' fills memory with 'pattern'.
64
      'unknown' does not specify how memory should be generated,
65
      leaving the memory in a undefined state. This is the fastest
66
      option.
67
 
68
   random_seed = 
69
      random seed for randomizer, used if type = 'random'.
70
 
71
   pattern = 
72
      pattern to fill memory, used if type = 'pattern'.
73
 
74
   nmemories = 
75
      number of memory instances connected
76
 
77 246 julius
   baseaddr = 
78
      memory start address
79 2 marcus.erl
 
80 246 julius
   size = 
81
      memory size
82 2 marcus.erl
 
83 246 julius
   name = ""
84
      memory block name
85 2 marcus.erl
 
86 246 julius
   ce = 
87
      chip enable index of the memory instance
88 2 marcus.erl
 
89 246 julius
   mc = 
90
      memory controller this memory is connected to
91 2 marcus.erl
 
92 246 julius
   delayr = 
93
      cycles, required for read access, -1 if instance does not support reading
94 2 marcus.erl
 
95 246 julius
   delayw = 
96
      cycles, required for write access, -1 if instance does not support writing
97
 
98
   log = ""
99
      filename, where to log memory accesses to, no log, if log command is not specified
100 2 marcus.erl
*/
101
 
102
 
103
section memory
104
  /*random_seed = 12345
105
  type = random*/
106
  pattern = 0x00
107
  type = unknown /* Fastest */
108
 
109 246 julius
  name = "FLASH"
110
  ce = 0
111
  mc = 0
112
  baseaddr = 0xf0000000
113
  size = 0x01000000
114
  delayr = 1
115
  delayw = -1
116
end
117 2 marcus.erl
 
118 246 julius
section memory
119
  /*random_seed = 12345
120
  type = random*/
121 419 julius
  /*pattern = 0x00
122
  type = unknown */
123 2 marcus.erl
 
124 467 julius
  /*type = exitnops*/
125 419 julius
 
126 246 julius
  name = "RAM"
127
  ce = 1
128
  mc = 0
129
  baseaddr = 0x00000000
130
  size = 0x02000000
131
  delayr = 1
132
  delayw = 1
133
end
134 2 marcus.erl
 
135 246 julius
section memory
136
  /*random_seed = 12345
137
  type = random*/
138
  pattern = 0x00
139
  type = unknown /* Fastest */
140
 
141
  name = "SRAM"
142
  mc = 0
143
  ce = 2
144
  baseaddr = 0xa4000000
145
  size = 0x00100000
146
  delayr = 1
147
  delayw = 1
148 2 marcus.erl
end
149
 
150
 
151
/* IMMU SECTION
152
 
153
    This section configures the Instruction Memory Manangement Unit
154
 
155
    enabled = 0/1
156
       '0': disabled
157
       '1': enabled
158
       (NOTE: UPR bit is set)
159
 
160
    nsets = 
161
       number of ITLB sets; must be power of two
162
 
163
    nways = 
164
       number of ITLB ways
165
 
166
    pagesize = 
167
       instruction page size; must be power of two
168
 
169
    entrysize = 
170
       instruction entry size in bytes
171
 
172
    ustates = 
173
       number of ITLB usage states (2, 3, 4 etc., max is 4)
174
 
175
    hitdelay = 
176
       number of cycles immu hit costs
177
 
178
    missdelay = 
179
       number of cycles immu miss costs
180
*/
181
 
182
section immu
183
  enabled = 1
184
  nsets = 64
185
  nways = 1
186
  pagesize = 8192
187
  hitdelay = 0
188
  missdelay = 0
189
end
190
 
191
 
192
/* DMMU SECTION
193
 
194
    This section configures the Data Memory Manangement Unit
195
 
196
    enabled = 0/1
197
       '0': disabled
198
       '1': enabled
199
       (NOTE: UPR bit is set)
200
 
201
    nsets = 
202
       number of DTLB sets; must be power of two
203
 
204
    nways = 
205
       number of DTLB ways
206
 
207
    pagesize = 
208
       data page size; must be power of two
209
 
210
    entrysize = 
211
       data entry size in bytes
212
 
213
    ustates = 
214
       number of DTLB usage states (2, 3, 4 etc., max is 4)
215
 
216
    hitdelay = 
217
       number of cycles dmmu hit costs
218
 
219
    missdelay = 
220
       number of cycles dmmu miss costs
221
*/
222
 
223
section dmmu
224
  enabled = 1
225
  nsets = 64
226
  nways = 1
227
  pagesize = 8192
228
  hitdelay = 0
229
  missdelay = 0
230
end
231
 
232
 
233
/* IC SECTION
234
 
235
   This section configures the Instruction Cache
236
 
237
   enabled = 0/1
238
       '0': disabled
239
       '1': enabled
240
      (NOTE: UPR bit is set)
241
 
242
   nsets = 
243
      number of IC sets; must be power of two
244
 
245
   nways = 
246
      number of IC ways
247
 
248
   blocksize = 
249
      IC block size in bytes; must be power of two
250
 
251
   ustates = 
252
      number of IC usage states (2, 3, 4 etc., max is 4)
253
 
254
   hitdelay = 
255
      number of cycles ic hit costs
256
 
257
    missdelay = 
258
      number of cycles ic miss costs
259
*/
260
 
261
section ic
262 246 julius
  enabled = 0
263
  nsets = 512
264 2 marcus.erl
  nways = 1
265
  blocksize = 16
266 246 julius
  hitdelay = 20
267
  missdelay = 20
268 2 marcus.erl
end
269
 
270
 
271
/* DC SECTION
272
 
273
   This section configures the Data Cache
274
 
275
   enabled = 0/1
276
       '0': disabled
277
       '1': enabled
278
      (NOTE: UPR bit is set)
279
 
280
   nsets = 
281
      number of DC sets; must be power of two
282
 
283
   nways = 
284
      number of DC ways
285
 
286
   blocksize = 
287
      DC block size in bytes; must be power of two
288
 
289
   ustates = 
290
      number of DC usage states (2, 3, 4 etc., max is 4)
291
 
292
   load_hitdelay = 
293
      number of cycles dc load hit costs
294
 
295
   load_missdelay = 
296
      number of cycles dc load miss costs
297
 
298
   store_hitdelay = 
299
      number of cycles dc load hit costs
300
 
301
   store_missdelay = 
302
      number of cycles dc load miss costs
303
*/
304
 
305
section dc
306 246 julius
  enabled = 0
307
  nsets = 512
308 2 marcus.erl
  nways = 1
309
  blocksize = 16
310 246 julius
  load_hitdelay = 20
311
  load_missdelay = 20
312
  store_hitdelay = 20
313
  store_missdelay = 20
314 2 marcus.erl
end
315
 
316
 
317
/* SIM SECTION
318
 
319
  This section specifies how or1ksim should behave.
320
 
321
  verbose = 0/1
322
       '0': don't print extra messages
323
       '1': print extra messages
324
 
325
  debug = 0-9
326
 
327
      1-9: debug message level.
328
           higher numbers produce more messages
329
 
330
  profile = 0/1
331
      '0': don't generate profiling file 'sim.profile'
332
      '1': don't generate profiling file 'sim.profile'
333
 
334
  prof_fn = ""
335
      optional filename for the profiling file.
336
      valid only if 'profile' is set
337
 
338
  mprofile = 0/1
339
      '0': don't generate memory profiling file 'sim.mprofile'
340
      '1': generate memory profiling file 'sim.mprofile'
341
 
342
  mprof_fn = ""
343
      optional filename for the memory profiling file.
344
      valid only if 'mprofile' is set
345
 
346
  history = 0/1
347
      '0': don't track execution flow
348
      '1': track execution flow
349
      Execution flow can be tracked for the simulator's
350
      'hist' command. Useful for back-trace debugging.
351
 
352
  iprompt = 0/1
353
     '0': start in  (so what do we start in ???)
354
     '1': start in interactive prompt.
355
 
356
  exe_log = 0/1
357
      '0': don't generate execution log.
358
      '1': generate execution log.
359
 
360
  exe_log = default/hardware/simple/software
361
      type of execution log, default is used when not specified
362
 
363
  exe_log_start = 
364
      index of first instruction to start logging, default = 0
365
 
366
  exe_log_end = 
367
      index of last instruction to end logging; not limited, if omitted
368
 
369
  exe_log_marker = 
370
       specifies number of instructions before horizontal marker is
371
      printed; if zero, markers are disabled (default)
372
 
373
  exe_log_fn = ""
374
      filename for the exection log file.
375
      valid only if 'exe_log' is set
376
 
377
  clkcycle = [ps|ns|us|ms]
378
      specifies time measurement for one cycle
379
*/
380
 
381
section sim
382 246 julius
  verbose = 1
383 2 marcus.erl
  debug = 0
384
  profile = 0
385 246 julius
  history = 0
386
  /*exe_log = 1*/
387
  /*exe_log_fn = "exe.log"*/
388
  clkcycle = 10ns
389 2 marcus.erl
end
390
 
391
 
392
/* SECTION VAPI
393
 
394
    This section configures the Verification API, used for Advanced
395
    Core Verification.
396
 
397
    enabled = 0/1
398
        '0': disbable VAPI server
399
        '1': enable/start VAPI server
400
 
401
    server_port = 
402
        TCP/IP port to start VAPI server on
403
 
404
    log_enabled = 0/1
405
       '0': disable VAPI requests logging
406
       '1': enable VAPI requests logging
407
 
408
    hide_device_id = 0/1
409
       '0': don't log device id (for compatability with old version)
410
       '1': log device id
411
 
412
 
413
    vapi_fn = 
414
       filename for the log file.
415
       valid only if log_enabled is set
416
*/
417
 
418
section VAPI
419
  enabled = 0
420
  server_port = 9998
421
  log_enabled = 0
422
  vapi_log_fn = "vapi.log"
423
end
424
 
425
 
426
/* CPU SECTION
427
 
428
   This section specifies various CPU parameters.
429
 
430
   ver = 
431
   rev = 
432
      specifies version and revision of the CPU used
433
 
434
   upr = 
435
      changes the upr register
436
 
437
   sr = 
438
      sets the initial Supervision Register value
439 246 julius
      supervisor mode (SM) and fixed one (FO) set = 0x8001
440
      exception prefix high (EPH, vectors@0xf0000000) = 0x4000
441
      together, (SM | FO | EPH) = 0xc001
442 2 marcus.erl
   superscalar = 0/1
443
      '0': CPU is scalar
444
      '1': CPU is superscalar
445
      (modify cpu/or32/execute.c to tune superscalar model)
446
 
447
   hazards = 0/1
448
      '0': don't track data hazards in superscalar CPU
449
      '1': track data hazards in superscalar CPU
450
      If tracked, data hazards can be displayed using the
451
      simulator's 'r' command.
452
 
453
   dependstats = 0/1
454
      '0': don't calculate inter-instruction dependencies.
455
      '1': calculate inter-instruction dependencies.
456
      If calculated, inter-instruction dependencies can be
457
      displayed using the simulator's 'stat' command.
458
 
459
   sbuf_len = 
460
      length of store buffer (<= 256), 0 = disabled
461
*/
462
 
463
section cpu
464 246 julius
  ver = 0x12
465
  cfg = 0x00
466
  rev = 0x01
467
  sr =  0x8001 /*SPR_SR_FO  | SPR_SR_SM | SPR_SR_EPH */
468 2 marcus.erl
  /* upr = */
469
  superscalar = 0
470
  hazards = 0
471
  dependstats = 0
472
  sbuf_len = 0
473
end
474
 
475
 
476
/* PM SECTION
477
 
478
   This section specifies Power Management parameters
479
 
480
   enabled = 0/1
481
      '0': disable power management
482
      '1': enable power management
483
*/
484
 
485
section pm
486
  enabled = 0
487
end
488
 
489
 
490
/* BPB SECTION
491
 
492
   This section specifies how branch prediction should behave.
493
 
494
   enabled = 0/1
495
     '0': disable branch prediction
496
     '1': enable branch prediction
497
 
498
   btic = 0/1
499
     '0': disable branch target instruction cache model
500
     '1': enable branch target instruction cache model
501
 
502
   sbp_bf_fwd = 0/1
503
     Static branch prediction for 'l.bf'
504
     '0': don't use forward prediction
505
     '1': use forward prediction
506
 
507
   sbp_bnf_fwd = 0/1
508
     Static branch prediction for 'l.bnf'
509
     '0': don't use forward prediction
510
     '1': use forward prediction
511
 
512
   hitdelay = 
513
       number of cycles bpb hit costs
514
 
515
   missdelay = 
516
       number of cycles bpb miss costs
517
*/
518
 
519
section bpb
520
  enabled = 0
521
  btic = 0
522
  sbp_bf_fwd = 0
523
  sbp_bnf_fwd = 0
524
  hitdelay = 0
525
  missdelay = 0
526
end
527
 
528
 
529
/* DEBUG SECTION
530
 
531
   This sections specifies how the debug unit should behave.
532
 
533
   enabled = 0/1
534
      '0': disable debug unit
535
      '1': enable debug unit
536
 
537
   gdb_enabled = 0/1
538
      '0': don't start gdb server
539
      '1': start gdb server at port 'server_port'
540
 
541
   server_port = 
542
      TCP/IP port to start gdb server on
543
      valid only if gdb_enabled is set
544
 
545
   vapi_id = 
546
      Used to create "fake" vapi log file containing the JTAG proxy messages.
547
*/
548
section debug
549
  enabled = 0
550 246 julius
/*  gdb_enabled = 0 */
551
/*  server_port = 9999*/
552
  rsp_enabled = 1
553
  rsp_port = 50001
554 2 marcus.erl
end
555
 
556
 
557
/* MC SECTION
558
 
559
   This section configures the memory controller
560
 
561
   enabled = 0/1
562
     '0': disable memory controller
563
     '1': enable memory controller
564
 
565
   baseaddr = 
566
      address of first MC register
567
 
568
   POC = 
569
      Power On Configuration register
570 246 julius
 
571
   index = 
572
      Index of this memory controller amongst all the memory controllers
573 2 marcus.erl
*/
574
 
575
section mc
576
  enabled = 0
577
  baseaddr = 0x93000000
578
  POC = 0x00000008                 /* Power on configuration register */
579 246 julius
  index = 0
580 2 marcus.erl
end
581
 
582
 
583
/* UART SECTION
584
 
585
   This section configures the UARTs
586
 
587
     enabled = <0|1>
588
        Enable/disable the peripheral.  By default if it is enabled.
589
 
590
     baseaddr = 
591
        address of first UART register for this device
592
 
593
 
594
     channel = :
595
 
596
        The channel parameter indicates the source of received UART characters
597
        and the sink for transmitted UART characters.
598
 
599
        The  can be either "file", "xterm", "tcp", "fd", or "tty"
600
        (without quotes).
601
 
602
          A) To send/receive characters from a pair of files, use a file
603
             channel:
604
 
605
               channel=file:,
606
 
607
          B) To create an interactive terminal window, use an xterm channel:
608
 
609
               channel=xterm:[]*
610
 
611
          C) To create a bidirectional tcp socket which one could, for example,
612
             access via telnet, use a tcp channel:
613
 
614
               channel=tcp:
615
 
616
          D) To cause the UART to read/write from existing numeric file
617
             descriptors, use an fd channel:
618
 
619
               channel=fd:,
620
 
621
          E) To connect the UART to a physical serial port, create a tty
622
             channel:
623
 
624
               channel=tty:device=/dev/ttyS0,baud=9600
625
 
626
     irq = 
627
        irq number for this device
628
 
629
     16550 = 0/1
630
        '0': this device is a UART16450
631
        '1': this device is a UART16550
632
 
633
     jitter = 
634
        in msecs... time to block, -1 to disable it
635
 
636
     vapi_id = 
637
        VAPI id of this instance
638
*/
639
 
640
section uart
641
  enabled = 1
642
  baseaddr = 0x90000000
643
  irq = 2
644 246 julius
  /* channel = "file:uart0.rx,uart0.tx" */
645
  /* channel = "tcp:10084" */
646
   channel = "xterm:"
647 2 marcus.erl
  jitter = -1                     /* async behaviour */
648
  16550 = 1
649
end
650
 
651
 
652
/* DMA SECTION
653
 
654
   This section configures the DMAs
655
 
656
     enabled = <0|1>
657
        Enable/disable the peripheral.  By default if it is enabled.
658
 
659
     baseaddr = 
660
        address of first DMA register for this device
661
 
662
     irq = 
663
        irq number for this device
664
 
665
     vapi_id = 
666
        VAPI id of this instance
667
*/
668
 
669
section dma
670
  enabled = 1
671
  baseaddr = 0x9a000000
672
  irq = 11
673
end
674
 
675
 
676
/* ETHERNET SECTION
677
 
678
   This section configures the ETHERNETs
679
 
680
     enabled = <0|1>
681
        Enable/disable the peripheral.  By default if it is enabled.
682
 
683
     baseaddr = 
684
        address of first ethernet register for this device
685
 
686
     dma = 
687
        which controller is this ethernet "connected" to
688
 
689
     irq = 
690
        ethernet mac IRQ level
691
 
692
     rtx_type = 
693
        use 0 - file interface, 1 - socket interface
694
 
695
     rx_channel = 
696
        DMA channel used for RX
697
 
698
     tx_channel = 
699
        DMA channel used for TX
700
 
701
     rxfile = ""
702
        filename, where to read data from
703
 
704
     txfile = ""
705
        filename, where to write data to
706
 
707
     sockif = ""
708
        interface name of ethernet socket
709
 
710
     vapi_id = 
711
        VAPI id of this instance
712
*/
713
 
714
section ethernet
715 246 julius
  enabled = 1
716 2 marcus.erl
  baseaddr = 0x92000000
717 246 julius
  /* dma = 0 */
718 2 marcus.erl
  irq = 4
719 467 julius
  rtx_type = "tap"
720 246 julius
  /* tx_channel = 0 */
721
  /* rx_channel = 1 */
722 467 julius
  /*  rxfile = "eth0.rx"*/
723
  /*txfile = "eth0.tx"*/
724
  /*sockif = "eth0"*/
725
  phy_addr = 7
726
  tap_dev = "tap0"
727
 
728
 
729 2 marcus.erl
end
730
 
731
 
732
/* GPIO SECTION
733
 
734
   This section configures the GPIOs
735
 
736
     enabled = <0|1>
737
        Enable/disable the peripheral.  By default if it is enabled.
738
 
739
     baseaddr = 
740
        address of first GPIO register for this device
741
 
742
     irq = 
743
        irq number for this device
744
 
745
     base_vapi_id = 
746
        first VAPI id of this instance
747
        GPIO uses 8 consecutive VAPI IDs
748
*/
749
 
750
section gpio
751 246 julius
  enabled = 0
752 2 marcus.erl
  baseaddr = 0x91000000
753
  irq = 3
754
  base_vapi_id = 0x0200
755
end
756
 
757
/* VGA SECTION
758
 
759
    This section configures the VGA/LCD controller
760
 
761
      enabled = <0|1>
762
        Enable/disable the peripheral.  By default if it is enabled.
763
 
764
      baseaddr = 
765
        address of first VGA register
766
 
767
      irq = 
768
        irq number for this device
769
 
770
      refresh_rate = 
771
        number of cycles between screen dumps
772
 
773
      filename = ""
774
        template name for generated names (e.g. "primary" produces "primary0023.bmp")
775
*/
776
 
777
section vga
778 246 julius
  enabled = 0
779 2 marcus.erl
  baseaddr = 0x97100000
780
  irq = 8
781
  refresh_rate = 100000
782
  filename = "primary"
783
end
784
 
785
 
786
/* TICK TIMER SECTION
787
 
788
    This section configures tick timer
789
 
790
    enabled = 0/1
791
      whether tick timer is enabled
792 246 julius
*/
793 2 marcus.erl
 
794 246 julius
section pic
795 2 marcus.erl
  enabled = 1
796 246 julius
  edge_trigger = 1
797 2 marcus.erl
end
798
 
799
/* FB SECTION
800
 
801
    This section configures the frame buffer
802
 
803
    enabled = <0|1>
804
      Enable/disable the peripheral.  By default if it is enabled.
805
 
806
    baseaddr = 
807
      base address of frame buffer
808
 
809
    paladdr = 
810
      base address of first palette entry
811
 
812
    refresh_rate = 
813
      number of cycles between screen dumps
814
 
815
    filename = ""
816
      template name for generated names (e.g. "primary" produces "primary0023.bmp")
817
*/
818
 
819
section fb
820 246 julius
  enabled = 0
821 2 marcus.erl
  baseaddr = 0x97000000
822
  refresh_rate = 1000000
823
  filename = "primary"
824
end
825
 
826
 
827
/* KBD SECTION
828
 
829
    This section configures the PS/2 compatible keyboard
830
 
831
    baseaddr = 
832
      base address of the keyboard device
833
 
834
    rxfile = ""
835
      filename, where to read data from
836
*/
837
 
838
section kbd
839 246 julius
  enabled = 0
840 2 marcus.erl
  irq = 5
841
  baseaddr = 0x94000000
842
  rxfile = "kbd.rx"
843
end
844
 
845
 
846
/* ATA SECTION
847
 
848
    This section configures the ATA/ATAPI host controller
849
 
850
      baseaddr = 
851
        address of first ATA register
852
 
853
      enabled = <0|1>
854
        Enable/disable the peripheral.  By default if it is enabled.
855
 
856
      irq = 
857
        irq number for this device
858
 
859
      debug = 
860
        debug level for ata models.
861
        0: no debug messages
862
        1: verbose messages
863
        3: normal messages (more messages than verbose)
864
        5: debug messages (normal debug messages)
865
        7: flow control messages (debug statemachine flows)
866
        9: low priority message (display everything the code does)
867
 
868
      dev_type0/1 = 
869
        ata device 0 type
870
        0: NO_CONNeCT: none (not connected)
871
        1: FILE      : simulated harddisk
872
        2: LOCAL     : local system harddisk
873
 
874
      dev_file0/1 = ""
875
        filename for simulated ATA device
876
        valid only if dev_type0 == 1
877
 
878
      dev_size0/1 = 
879
        size of simulated hard-disk (in MBytes)
880
        valid only if dev_type0 == 1
881
 
882
      dev_packet0/1 = 
883
        0: simulated ATA device does NOT implement PACKET command feature set
884
        1: simulated ATA device does implement PACKET command feature set
885
 
886
   FIXME: irq number
887
*/
888
 
889
section ata
890 246 julius
  enabled = 0
891 2 marcus.erl
  baseaddr = 0x9e000000
892
  irq = 15
893
 
894
end
895
 
896
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.