OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [boehm-gc/] [rs6000_mach_dep.s] - Blame information for rev 801

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 721 jeremybenn
    .set   r0,0
2
    .set   r1,1
3
    .set   r2,2
4
    .set   r3,3
5
    .set   r4,4
6
    .set   r5,5
7
    .set   r6,6
8
    .set   r7,7
9
    .set   r8,8
10
    .set   r9,9
11
    .set   r10,10
12
    .set   r11,11
13
    .set   r12,12
14
    .set   r13,13
15
    .set   r14,14
16
    .set   r15,15
17
    .set   r16,16
18
    .set   r17,17
19
    .set   r18,18
20
    .set   r19,19
21
    .set   r20,20
22
    .set   r21,21
23
    .set   r22,22
24
    .set   r23,23
25
    .set   r24,24
26
    .set   r25,25
27
    .set   r26,26
28
    .set   r27,27
29
    .set   r28,28
30
    .set   r29,29
31
    .set   r30,30
32
    .set   r31,31
33
 
34
    .extern .GC_push_one
35
 # Mark from machine registers that are saved by C compiler
36
    .globl  .GC_push_regs
37
.csect .text[PR]
38
    .align 2
39
    .globl  GC_push_regs
40
    .globl  .GC_push_regs
41
.csect GC_push_regs[DS]
42
GC_push_regs:
43
    .long .GC_push_regs, TOC[tc0], 0
44
.csect .text[PR]
45
.GC_push_regs:
46
    stu     r1,-64(r1)  # reserve stack frame
47
    mflr    r0          # save link register
48
    st      r0,0x48(r1)
49
    oril    r3,r2,0x0   # mark from r2
50
    bl      .GC_push_one
51
    cror    15,15,15
52
    oril    r3,r13,0x0   # mark from r13-r31
53
    bl      .GC_push_one
54
    cror    15,15,15
55
    oril    r3,r14,0x0
56
    bl      .GC_push_one
57
    cror    15,15,15
58
    oril    r3,r15,0x0
59
    bl      .GC_push_one
60
    cror    15,15,15
61
    oril    r3,r16,0x0
62
    bl      .GC_push_one
63
    cror    15,15,15
64
    oril    r3,r17,0x0
65
    bl      .GC_push_one
66
    cror    15,15,15
67
    oril    r3,r18,0x0
68
    bl      .GC_push_one
69
    cror    15,15,15
70
    oril    r3,r19,0x0
71
    bl      .GC_push_one
72
    cror    15,15,15
73
    oril    r3,r20,0x0
74
    bl      .GC_push_one
75
    cror    15,15,15
76
    oril    r3,r21,0x0
77
    bl      .GC_push_one
78
    cror    15,15,15
79
    oril    r3,r22,0x0
80
    bl      .GC_push_one
81
    cror    15,15,15
82
    oril    r3,r23,0x0
83
    bl      .GC_push_one
84
    cror    15,15,15
85
    oril    r3,r24,0x0
86
    bl      .GC_push_one
87
    cror    15,15,15
88
    oril    r3,r25,0x0
89
    bl      .GC_push_one
90
    cror    15,15,15
91
    oril    r3,r26,0x0
92
    bl      .GC_push_one
93
    cror    15,15,15
94
    oril    r3,r27,0x0
95
    bl      .GC_push_one
96
    cror    15,15,15
97
    oril    r3,r28,0x0
98
    bl      .GC_push_one
99
    cror    15,15,15
100
    oril    r3,r29,0x0
101
    bl      .GC_push_one
102
    cror    15,15,15
103
    oril    r3,r30,0x0
104
    bl      .GC_push_one
105
    cror    15,15,15
106
    oril    r3,r31,0x0
107
    bl      .GC_push_one
108
    cror    15,15,15
109
    l       r0,0x48(r1)
110
    mtlr    r0
111
    ai      r1,r1,64
112
    br
113
    .long 0
114
    .byte 0,0,0,0,0,0,0,0

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.