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jeremybenn |
;; Copyright 2011 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;;
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; .
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;;
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;; This file contains ARM instructions that support fixed-point operations.
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(define_insn "add3"
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[(set (match_operand:FIXED 0 "s_register_operand" "=r")
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(plus:FIXED (match_operand:FIXED 1 "s_register_operand" "r")
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(match_operand:FIXED 2 "s_register_operand" "r")))]
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"TARGET_32BIT"
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"add%?\\t%0, %1, %2"
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[(set_attr "predicable" "yes")])
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(define_insn "add3"
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[(set (match_operand:ADDSUB 0 "s_register_operand" "=r")
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(plus:ADDSUB (match_operand:ADDSUB 1 "s_register_operand" "r")
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(match_operand:ADDSUB 2 "s_register_operand" "r")))]
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"TARGET_INT_SIMD"
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"sadd%?\\t%0, %1, %2"
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[(set_attr "predicable" "yes")])
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(define_insn "usadd3"
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[(set (match_operand:UQADDSUB 0 "s_register_operand" "=r")
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(us_plus:UQADDSUB (match_operand:UQADDSUB 1 "s_register_operand" "r")
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(match_operand:UQADDSUB 2 "s_register_operand" "r")))]
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"TARGET_INT_SIMD"
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"uqadd%?\\t%0, %1, %2"
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[(set_attr "predicable" "yes")])
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(define_insn "ssadd3"
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[(set (match_operand:QADDSUB 0 "s_register_operand" "=r")
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(ss_plus:QADDSUB (match_operand:QADDSUB 1 "s_register_operand" "r")
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(match_operand:QADDSUB 2 "s_register_operand" "r")))]
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"TARGET_INT_SIMD"
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"qadd%?\\t%0, %1, %2"
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[(set_attr "predicable" "yes")])
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(define_insn "sub3"
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[(set (match_operand:FIXED 0 "s_register_operand" "=r")
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(minus:FIXED (match_operand:FIXED 1 "s_register_operand" "r")
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(match_operand:FIXED 2 "s_register_operand" "r")))]
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"TARGET_32BIT"
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"sub%?\\t%0, %1, %2"
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[(set_attr "predicable" "yes")])
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(define_insn "sub3"
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[(set (match_operand:ADDSUB 0 "s_register_operand" "=r")
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(minus:ADDSUB (match_operand:ADDSUB 1 "s_register_operand" "r")
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(match_operand:ADDSUB 2 "s_register_operand" "r")))]
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"TARGET_INT_SIMD"
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"ssub%?\\t%0, %1, %2"
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[(set_attr "predicable" "yes")])
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(define_insn "ussub3"
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[(set (match_operand:UQADDSUB 0 "s_register_operand" "=r")
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(us_minus:UQADDSUB
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(match_operand:UQADDSUB 1 "s_register_operand" "r")
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(match_operand:UQADDSUB 2 "s_register_operand" "r")))]
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"TARGET_INT_SIMD"
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"uqsub%?\\t%0, %1, %2"
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[(set_attr "predicable" "yes")])
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(define_insn "sssub3"
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[(set (match_operand:QADDSUB 0 "s_register_operand" "=r")
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(ss_minus:QADDSUB (match_operand:QADDSUB 1 "s_register_operand" "r")
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(match_operand:QADDSUB 2 "s_register_operand" "r")))]
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"TARGET_INT_SIMD"
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"qsub%?\\t%0, %1, %2"
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[(set_attr "predicable" "yes")])
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;; Fractional multiplies.
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; Note: none of these do any rounding.
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(define_expand "mulqq3"
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[(set (match_operand:QQ 0 "s_register_operand" "")
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(mult:QQ (match_operand:QQ 1 "s_register_operand" "")
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(match_operand:QQ 2 "s_register_operand" "")))]
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"TARGET_DSP_MULTIPLY && arm_arch_thumb2"
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{
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rtx tmp1 = gen_reg_rtx (HImode);
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rtx tmp2 = gen_reg_rtx (HImode);
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rtx tmp3 = gen_reg_rtx (SImode);
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emit_insn (gen_extendqihi2 (tmp1, gen_lowpart (QImode, operands[1])));
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emit_insn (gen_extendqihi2 (tmp2, gen_lowpart (QImode, operands[2])));
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emit_insn (gen_mulhisi3 (tmp3, tmp1, tmp2));
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emit_insn (gen_extv (gen_lowpart (SImode, operands[0]), tmp3, GEN_INT (8),
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GEN_INT (7)));
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DONE;
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})
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(define_expand "mulhq3"
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[(set (match_operand:HQ 0 "s_register_operand" "")
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(mult:HQ (match_operand:HQ 1 "s_register_operand" "")
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(match_operand:HQ 2 "s_register_operand" "")))]
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"TARGET_DSP_MULTIPLY && arm_arch_thumb2"
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{
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rtx tmp = gen_reg_rtx (SImode);
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emit_insn (gen_mulhisi3 (tmp, gen_lowpart (HImode, operands[1]),
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gen_lowpart (HImode, operands[2])));
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/* We're doing a s.15 * s.15 multiplication, getting an s.30 result. Extract
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an s.15 value from that. This won't overflow/saturate for _Fract
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values. */
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emit_insn (gen_extv (gen_lowpart (SImode, operands[0]), tmp,
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GEN_INT (16), GEN_INT (15)));
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DONE;
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})
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(define_expand "mulsq3"
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[(set (match_operand:SQ 0 "s_register_operand" "")
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(mult:SQ (match_operand:SQ 1 "s_register_operand" "")
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(match_operand:SQ 2 "s_register_operand" "")))]
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"TARGET_32BIT && arm_arch3m"
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{
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rtx tmp1 = gen_reg_rtx (DImode);
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rtx tmp2 = gen_reg_rtx (SImode);
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rtx tmp3 = gen_reg_rtx (SImode);
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/* s.31 * s.31 -> s.62 multiplication. */
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emit_insn (gen_mulsidi3 (tmp1, gen_lowpart (SImode, operands[1]),
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gen_lowpart (SImode, operands[2])));
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emit_insn (gen_lshrsi3 (tmp2, gen_lowpart (SImode, tmp1), GEN_INT (31)));
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emit_insn (gen_ashlsi3 (tmp3, gen_highpart (SImode, tmp1), GEN_INT (1)));
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emit_insn (gen_iorsi3 (gen_lowpart (SImode, operands[0]), tmp2, tmp3));
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DONE;
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})
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;; Accumulator multiplies.
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(define_expand "mulsa3"
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[(set (match_operand:SA 0 "s_register_operand" "")
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(mult:SA (match_operand:SA 1 "s_register_operand" "")
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(match_operand:SA 2 "s_register_operand" "")))]
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"TARGET_32BIT && arm_arch3m"
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{
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rtx tmp1 = gen_reg_rtx (DImode);
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rtx tmp2 = gen_reg_rtx (SImode);
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rtx tmp3 = gen_reg_rtx (SImode);
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emit_insn (gen_mulsidi3 (tmp1, gen_lowpart (SImode, operands[1]),
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gen_lowpart (SImode, operands[2])));
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emit_insn (gen_lshrsi3 (tmp2, gen_lowpart (SImode, tmp1), GEN_INT (15)));
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emit_insn (gen_ashlsi3 (tmp3, gen_highpart (SImode, tmp1), GEN_INT (17)));
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emit_insn (gen_iorsi3 (gen_lowpart (SImode, operands[0]), tmp2, tmp3));
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DONE;
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})
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(define_expand "mulusa3"
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[(set (match_operand:USA 0 "s_register_operand" "")
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(mult:USA (match_operand:USA 1 "s_register_operand" "")
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(match_operand:USA 2 "s_register_operand" "")))]
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"TARGET_32BIT && arm_arch3m"
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{
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rtx tmp1 = gen_reg_rtx (DImode);
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rtx tmp2 = gen_reg_rtx (SImode);
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rtx tmp3 = gen_reg_rtx (SImode);
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emit_insn (gen_umulsidi3 (tmp1, gen_lowpart (SImode, operands[1]),
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gen_lowpart (SImode, operands[2])));
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emit_insn (gen_lshrsi3 (tmp2, gen_lowpart (SImode, tmp1), GEN_INT (16)));
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emit_insn (gen_ashlsi3 (tmp3, gen_highpart (SImode, tmp1), GEN_INT (16)));
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emit_insn (gen_iorsi3 (gen_lowpart (SImode, operands[0]), tmp2, tmp3));
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DONE;
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})
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;; The code sequence emitted by this insn pattern uses the Q flag, which GCC
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;; doesn't generally know about, so we don't bother expanding to individual
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;; instructions. It may be better to just use an out-of-line asm libcall for
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;; this.
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(define_insn "ssmulsa3"
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[(set (match_operand:SA 0 "s_register_operand" "=r")
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(ss_mult:SA (match_operand:SA 1 "s_register_operand" "r")
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(match_operand:SA 2 "s_register_operand" "r")))
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(clobber (match_scratch:DI 3 "=r"))
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(clobber (match_scratch:SI 4 "=r"))
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(clobber (reg:CC CC_REGNUM))]
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"TARGET_32BIT && arm_arch6"
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{
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/* s16.15 * s16.15 -> s32.30. */
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output_asm_insn ("smull\\t%Q3, %R3, %1, %2", operands);
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if (TARGET_ARM)
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output_asm_insn ("msr\\tAPSR_nzcvq, #0", operands);
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else
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{
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output_asm_insn ("mov\\t%4, #0", operands);
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output_asm_insn ("msr\\tAPSR_nzcvq, %4", operands);
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}
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/* We have:
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31 high word 0 31 low word 0
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[ S i i .... i i i ] [ i f f f ... f f ]
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v
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[ S i ... i f ... f f ]
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Need 16 integral bits, so saturate at 15th bit of high word. */
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output_asm_insn ("ssat\\t%R3, #15, %R3", operands);
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output_asm_insn ("mrs\\t%4, APSR", operands);
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output_asm_insn ("tst\\t%4, #1<<27", operands);
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if (TARGET_THUMB2)
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output_asm_insn ("it\\tne", operands);
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output_asm_insn ("mvnne\\t%Q3, %R3, asr #32", operands);
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output_asm_insn ("mov\\t%0, %Q3, lsr #15", operands);
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output_asm_insn ("orr\\t%0, %0, %R3, asl #17", operands);
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return "";
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}
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[(set_attr "conds" "clob")
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(set (attr "length")
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(if_then_else (eq_attr "is_thumb" "yes")
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(const_int 38)
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(const_int 32)))])
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;; Same goes for this.
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(define_insn "usmulusa3"
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[(set (match_operand:USA 0 "s_register_operand" "=r")
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(us_mult:USA (match_operand:USA 1 "s_register_operand" "r")
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(match_operand:USA 2 "s_register_operand" "r")))
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(clobber (match_scratch:DI 3 "=r"))
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(clobber (match_scratch:SI 4 "=r"))
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(clobber (reg:CC CC_REGNUM))]
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"TARGET_32BIT && arm_arch6"
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{
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/* 16.16 * 16.16 -> 32.32. */
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output_asm_insn ("umull\\t%Q3, %R3, %1, %2", operands);
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if (TARGET_ARM)
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output_asm_insn ("msr\\tAPSR_nzcvq, #0", operands);
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else
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{
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output_asm_insn ("mov\\t%4, #0", operands);
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output_asm_insn ("msr\\tAPSR_nzcvq, %4", operands);
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}
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/* We have:
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31 high word 0 31 low word 0
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[ i i i .... i i i ] [ f f f f ... f f ]
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v
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[ i i ... i f ... f f ]
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Need 16 integral bits, so saturate at 16th bit of high word. */
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output_asm_insn ("usat\\t%R3, #16, %R3", operands);
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output_asm_insn ("mrs\\t%4, APSR", operands);
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output_asm_insn ("tst\\t%4, #1<<27", operands);
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if (TARGET_THUMB2)
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output_asm_insn ("it\\tne", operands);
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output_asm_insn ("sbfxne\\t%Q3, %R3, #15, #1", operands);
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output_asm_insn ("lsr\\t%0, %Q3, #16", operands);
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output_asm_insn ("orr\\t%0, %0, %R3, asl #16", operands);
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return "";
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}
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[(set_attr "conds" "clob")
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(set (attr "length")
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(if_then_else (eq_attr "is_thumb" "yes")
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(const_int 38)
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(const_int 32)))])
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| 284 |
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| 285 |
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(define_expand "mulha3"
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[(set (match_operand:HA 0 "s_register_operand" "")
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(mult:HA (match_operand:HA 1 "s_register_operand" "")
|
| 288 |
|
|
(match_operand:HA 2 "s_register_operand" "")))]
|
| 289 |
|
|
"TARGET_DSP_MULTIPLY && arm_arch_thumb2"
|
| 290 |
|
|
{
|
| 291 |
|
|
rtx tmp = gen_reg_rtx (SImode);
|
| 292 |
|
|
|
| 293 |
|
|
emit_insn (gen_mulhisi3 (tmp, gen_lowpart (HImode, operands[1]),
|
| 294 |
|
|
gen_lowpart (HImode, operands[2])));
|
| 295 |
|
|
emit_insn (gen_extv (gen_lowpart (SImode, operands[0]), tmp, GEN_INT (16),
|
| 296 |
|
|
GEN_INT (7)));
|
| 297 |
|
|
|
| 298 |
|
|
DONE;
|
| 299 |
|
|
})
|
| 300 |
|
|
|
| 301 |
|
|
(define_expand "muluha3"
|
| 302 |
|
|
[(set (match_operand:UHA 0 "s_register_operand" "")
|
| 303 |
|
|
(mult:UHA (match_operand:UHA 1 "s_register_operand" "")
|
| 304 |
|
|
(match_operand:UHA 2 "s_register_operand" "")))]
|
| 305 |
|
|
"TARGET_DSP_MULTIPLY"
|
| 306 |
|
|
{
|
| 307 |
|
|
rtx tmp1 = gen_reg_rtx (SImode);
|
| 308 |
|
|
rtx tmp2 = gen_reg_rtx (SImode);
|
| 309 |
|
|
rtx tmp3 = gen_reg_rtx (SImode);
|
| 310 |
|
|
|
| 311 |
|
|
/* 8.8 * 8.8 -> 16.16 multiply. */
|
| 312 |
|
|
emit_insn (gen_zero_extendhisi2 (tmp1, gen_lowpart (HImode, operands[1])));
|
| 313 |
|
|
emit_insn (gen_zero_extendhisi2 (tmp2, gen_lowpart (HImode, operands[2])));
|
| 314 |
|
|
emit_insn (gen_mulsi3 (tmp3, tmp1, tmp2));
|
| 315 |
|
|
emit_insn (gen_extzv (gen_lowpart (SImode, operands[0]), tmp3,
|
| 316 |
|
|
GEN_INT (16), GEN_INT (8)));
|
| 317 |
|
|
|
| 318 |
|
|
DONE;
|
| 319 |
|
|
})
|
| 320 |
|
|
|
| 321 |
|
|
(define_expand "ssmulha3"
|
| 322 |
|
|
[(set (match_operand:HA 0 "s_register_operand" "")
|
| 323 |
|
|
(ss_mult:HA (match_operand:HA 1 "s_register_operand" "")
|
| 324 |
|
|
(match_operand:HA 2 "s_register_operand" "")))]
|
| 325 |
|
|
"TARGET_32BIT && TARGET_DSP_MULTIPLY && arm_arch6"
|
| 326 |
|
|
{
|
| 327 |
|
|
rtx tmp = gen_reg_rtx (SImode);
|
| 328 |
|
|
rtx rshift;
|
| 329 |
|
|
|
| 330 |
|
|
emit_insn (gen_mulhisi3 (tmp, gen_lowpart (HImode, operands[1]),
|
| 331 |
|
|
gen_lowpart (HImode, operands[2])));
|
| 332 |
|
|
|
| 333 |
|
|
rshift = gen_rtx_ASHIFTRT (SImode, tmp, GEN_INT (7));
|
| 334 |
|
|
|
| 335 |
|
|
emit_insn (gen_rtx_SET (VOIDmode, gen_lowpart (HImode, operands[0]),
|
| 336 |
|
|
gen_rtx_SS_TRUNCATE (HImode, rshift)));
|
| 337 |
|
|
|
| 338 |
|
|
DONE;
|
| 339 |
|
|
})
|
| 340 |
|
|
|
| 341 |
|
|
(define_expand "usmuluha3"
|
| 342 |
|
|
[(set (match_operand:UHA 0 "s_register_operand" "")
|
| 343 |
|
|
(us_mult:UHA (match_operand:UHA 1 "s_register_operand" "")
|
| 344 |
|
|
(match_operand:UHA 2 "s_register_operand" "")))]
|
| 345 |
|
|
"TARGET_INT_SIMD"
|
| 346 |
|
|
{
|
| 347 |
|
|
rtx tmp1 = gen_reg_rtx (SImode);
|
| 348 |
|
|
rtx tmp2 = gen_reg_rtx (SImode);
|
| 349 |
|
|
rtx tmp3 = gen_reg_rtx (SImode);
|
| 350 |
|
|
rtx rshift_tmp = gen_reg_rtx (SImode);
|
| 351 |
|
|
|
| 352 |
|
|
/* Note: there's no smul[bt][bt] equivalent for unsigned multiplies. Use a
|
| 353 |
|
|
normal 32x32->32-bit multiply instead. */
|
| 354 |
|
|
emit_insn (gen_zero_extendhisi2 (tmp1, gen_lowpart (HImode, operands[1])));
|
| 355 |
|
|
emit_insn (gen_zero_extendhisi2 (tmp2, gen_lowpart (HImode, operands[2])));
|
| 356 |
|
|
|
| 357 |
|
|
emit_insn (gen_mulsi3 (tmp3, tmp1, tmp2));
|
| 358 |
|
|
|
| 359 |
|
|
/* The operand to "usat" is signed, so we cannot use the "..., asr #8"
|
| 360 |
|
|
form of that instruction since the multiplication result TMP3 may have the
|
| 361 |
|
|
top bit set, thus be negative and saturate to zero. Use a separate
|
| 362 |
|
|
logical right-shift instead. */
|
| 363 |
|
|
emit_insn (gen_lshrsi3 (rshift_tmp, tmp3, GEN_INT (8)));
|
| 364 |
|
|
emit_insn (gen_arm_usatsihi (gen_lowpart (HImode, operands[0]), rshift_tmp));
|
| 365 |
|
|
|
| 366 |
|
|
DONE;
|
| 367 |
|
|
})
|
| 368 |
|
|
|
| 369 |
|
|
(define_insn "arm_ssatsihi_shift"
|
| 370 |
|
|
[(set (match_operand:HI 0 "s_register_operand" "=r")
|
| 371 |
|
|
(ss_truncate:HI (match_operator:SI 1 "sat_shift_operator"
|
| 372 |
|
|
[(match_operand:SI 2 "s_register_operand" "r")
|
| 373 |
|
|
(match_operand:SI 3 "immediate_operand" "I")])))]
|
| 374 |
|
|
"TARGET_32BIT && arm_arch6"
|
| 375 |
|
|
"ssat%?\\t%0, #16, %2%S1"
|
| 376 |
|
|
[(set_attr "predicable" "yes")
|
| 377 |
|
|
(set_attr "type" "alu_shift")])
|
| 378 |
|
|
|
| 379 |
|
|
(define_insn "arm_usatsihi"
|
| 380 |
|
|
[(set (match_operand:HI 0 "s_register_operand" "=r")
|
| 381 |
|
|
(us_truncate:HI (match_operand:SI 1 "s_register_operand")))]
|
| 382 |
|
|
"TARGET_INT_SIMD"
|
| 383 |
|
|
"usat%?\\t%0, #16, %1"
|
| 384 |
|
|
[(set_attr "predicable" "yes")])
|
