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;;- Machine description for ARM for GNU compiler

;;  Copyright 1991, 1993, 1994, 1995, 1996, 1996, 1997, 1998, 1999, 2000,

;;  2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012

;;  Free Software Foundation, Inc.

;;  Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)

;;  and Martin Simmons (@harleqn.co.uk).

;;  More major hacks by Richard Earnshaw (rearnsha@arm.com).

;; This file is part of GCC.

;; GCC is free software; you can redistribute it and/or modify it

;; under the terms of the GNU General Public License as published

;; by the Free Software Foundation; either version 3, or (at your

;; option) any later version.

;; GCC is distributed in the hope that it will be useful, but WITHOUT

;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY

;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public

;; License for more details.

;; You should have received a copy of the GNU General Public License

;; along with GCC; see the file COPYING3.  If not see

;; .

;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.

;;---------------------------------------------------------------------------

;; Constants

;; Register numbers

(define_constants

  [(R0_REGNUM        0)         ; First CORE register

   (R1_REGNUM        1)         ; Second CORE register

   (IP_REGNUM       12)         ; Scratch register

   (SP_REGNUM       13)         ; Stack pointer

   (LR_REGNUM       14)         ; Return address register

   (PC_REGNUM       15)         ; Program counter

   (CC_REGNUM       24)         ; Condition code pseudo register

   (LAST_ARM_REGNUM 15)         ;

   (FPA_F0_REGNUM   16)         ; FIRST_FPA_REGNUM

   (FPA_F7_REGNUM   23)         ; LAST_FPA_REGNUM

  ]

)

;; 3rd operand to select_dominance_cc_mode

(define_constants

  [(DOM_CC_X_AND_Y  0)

   (DOM_CC_NX_OR_Y  1)

   (DOM_CC_X_OR_Y   2)

  ]

)

;; conditional compare combination

(define_constants

  [(CMP_CMP 0)

   (CMN_CMP 1)

   (CMP_CMN 2)

   (CMN_CMN 3)

   (NUM_OF_COND_CMP 4)

  ]

)

;; UNSPEC Usage:

;; Note: sin and cos are no-longer used.

;; Unspec enumerators for Neon are defined in neon.md.

(define_c_enum "unspec" [

  UNSPEC_SIN            ; `sin' operation (MODE_FLOAT):

                        ;   operand 0 is the result,

                        ;   operand 1 the parameter.

  UNPSEC_COS            ; `cos' operation (MODE_FLOAT):

                        ;   operand 0 is the result,

                        ;   operand 1 the parameter.

  UNSPEC_PUSH_MULT      ; `push multiple' operation:

                        ;   operand 0 is the first register,

                        ;   subsequent registers are in parallel (use ...)

                        ;   expressions.

  UNSPEC_PIC_SYM        ; A symbol that has been treated properly for pic

                        ; usage, that is, we will add the pic_register

                        ; value to it before trying to dereference it.

  UNSPEC_PIC_BASE       ; Add PC and all but the last operand together,

                        ; The last operand is the number of a PIC_LABEL

                        ; that points at the containing instruction.

  UNSPEC_PRLG_STK       ; A special barrier that prevents frame accesses

                        ; being scheduled before the stack adjustment insn.

  UNSPEC_PROLOGUE_USE   ; As USE insns are not meaningful after reload,

                        ; this unspec is used to prevent the deletion of

                        ; instructions setting registers for EH handling

                        ; and stack frame generation.  Operand 0 is the

                        ; register to "use".

  UNSPEC_CHECK_ARCH     ; Set CCs to indicate 26-bit or 32-bit mode.

  UNSPEC_WSHUFH         ; Used by the intrinsic form of the iWMMXt WSHUFH instruction.

  UNSPEC_WACC           ; Used by the intrinsic form of the iWMMXt WACC instruction.

  UNSPEC_TMOVMSK        ; Used by the intrinsic form of the iWMMXt TMOVMSK instruction.

  UNSPEC_WSAD           ; Used by the intrinsic form of the iWMMXt WSAD instruction.

  UNSPEC_WSADZ          ; Used by the intrinsic form of the iWMMXt WSADZ instruction.

  UNSPEC_WMACS          ; Used by the intrinsic form of the iWMMXt WMACS instruction.

  UNSPEC_WMACU          ; Used by the intrinsic form of the iWMMXt WMACU instruction.

  UNSPEC_WMACSZ         ; Used by the intrinsic form of the iWMMXt WMACSZ instruction.

  UNSPEC_WMACUZ         ; Used by the intrinsic form of the iWMMXt WMACUZ instruction.

  UNSPEC_CLRDI          ; Used by the intrinsic form of the iWMMXt CLRDI instruction.

  UNSPEC_WMADDS         ; Used by the intrinsic form of the iWMMXt WMADDS instruction.

  UNSPEC_WMADDU         ; Used by the intrinsic form of the iWMMXt WMADDU instruction.

  UNSPEC_TLS            ; A symbol that has been treated properly for TLS usage.

  UNSPEC_PIC_LABEL      ; A label used for PIC access that does not appear in the

                        ; instruction stream.

  UNSPEC_PIC_OFFSET     ; A symbolic 12-bit OFFSET that has been treated

                        ; correctly for PIC usage.

  UNSPEC_GOTSYM_OFF     ; The offset of the start of the GOT from a

                        ; a given symbolic address.

  UNSPEC_THUMB1_CASESI  ; A Thumb1 compressed dispatch-table call.

  UNSPEC_RBIT           ; rbit operation.

  UNSPEC_SYMBOL_OFFSET  ; The offset of the start of the symbol from

                        ; another symbolic address.

  UNSPEC_MEMORY_BARRIER ; Represent a memory barrier.

  UNSPEC_UNALIGNED_LOAD ; Used to represent ldr/ldrh instructions that access

                        ; unaligned locations, on architectures which support

                        ; that.

  UNSPEC_UNALIGNED_STORE ; Same for str/strh.

  UNSPEC_PIC_UNIFIED    ; Create a common pic addressing form.

])

;; UNSPEC_VOLATILE Usage:

(define_c_enum "unspecv" [

  VUNSPEC_BLOCKAGE      ; `blockage' insn to prevent scheduling across an

                        ;   insn in the code.

  VUNSPEC_EPILOGUE      ; `epilogue' insn, used to represent any part of the

                        ;   instruction epilogue sequence that isn't expanded

                        ;   into normal RTL.  Used for both normal and sibcall

                        ;   epilogues.

  VUNSPEC_THUMB1_INTERWORK ; `prologue_thumb1_interwork' insn, used to swap

                        ;   modes from arm to thumb.

  VUNSPEC_ALIGN         ; `align' insn.  Used at the head of a minipool table

                        ;   for inlined constants.

  VUNSPEC_POOL_END      ; `end-of-table'.  Used to mark the end of a minipool

                        ;   table.

  VUNSPEC_POOL_1        ; `pool-entry(1)'.  An entry in the constant pool for

                        ;   an 8-bit object.

  VUNSPEC_POOL_2        ; `pool-entry(2)'.  An entry in the constant pool for

                        ;   a 16-bit object.

  VUNSPEC_POOL_4        ; `pool-entry(4)'.  An entry in the constant pool for

                        ;   a 32-bit object.

  VUNSPEC_POOL_8        ; `pool-entry(8)'.  An entry in the constant pool for

                        ;   a 64-bit object.

  VUNSPEC_POOL_16       ; `pool-entry(16)'.  An entry in the constant pool for

                        ;   a 128-bit object.

  VUNSPEC_TMRC          ; Used by the iWMMXt TMRC instruction.

  VUNSPEC_TMCR          ; Used by the iWMMXt TMCR instruction.

  VUNSPEC_ALIGN8        ; 8-byte alignment version of VUNSPEC_ALIGN

  VUNSPEC_WCMP_EQ       ; Used by the iWMMXt WCMPEQ instructions

  VUNSPEC_WCMP_GTU      ; Used by the iWMMXt WCMPGTU instructions

  VUNSPEC_WCMP_GT       ; Used by the iwMMXT WCMPGT instructions

  VUNSPEC_EH_RETURN     ; Use to override the return address for exception

                        ; handling.

  VUNSPEC_ATOMIC_CAS    ; Represent an atomic compare swap.

  VUNSPEC_ATOMIC_XCHG   ; Represent an atomic exchange.

  VUNSPEC_ATOMIC_OP     ; Represent an atomic operation.

  VUNSPEC_LL            ; Represent a load-register-exclusive.

  VUNSPEC_SC            ; Represent a store-register-exclusive.

])

;;---------------------------------------------------------------------------

;; Attributes

;; Processor type.  This is created automatically from arm-cores.def.

(include "arm-tune.md")

; IS_THUMB is set to 'yes' when we are generating Thumb code, and 'no' when

; generating ARM code.  This is used to control the length of some insn

; patterns that share the same RTL in both ARM and Thumb code.

(define_attr "is_thumb" "no,yes" (const (symbol_ref "thumb_code")))

; IS_ARCH6 is set to 'yes' when we are generating code form ARMv6.

(define_attr "is_arch6" "no,yes" (const (symbol_ref "arm_arch6")))

; IS_THUMB1 is set to 'yes' iff we are generating Thumb-1 code.

(define_attr "is_thumb1" "no,yes" (const (symbol_ref "thumb1_code")))

;; Operand number of an input operand that is shifted.  Zero if the

;; given instruction does not shift one of its input operands.

(define_attr "shift" "" (const_int 0))

; Floating Point Unit.  If we only have floating point emulation, then there

; is no point in scheduling the floating point insns.  (Well, for best

; performance we should try and group them together).

(define_attr "fpu" "none,fpa,fpe2,fpe3,maverick,vfp"

  (const (symbol_ref "arm_fpu_attr")))

; LENGTH of an instruction (in bytes)

(define_attr "length" ""

  (const_int 4))

; The architecture which supports the instruction (or alternative).

; This can be "a" for ARM, "t" for either of the Thumbs, "32" for

; TARGET_32BIT, "t1" or "t2" to specify a specific Thumb mode.  "v6"

; for ARM or Thumb-2 with arm_arch6, and nov6 for ARM without

; arm_arch6.  This attribute is used to compute attribute "enabled",

; use type "any" to enable an alternative in all cases.

(define_attr "arch" "any,a,t,32,t1,t2,v6,nov6,onlya8,nota8"

  (const_string "any"))

(define_attr "arch_enabled" "no,yes"

  (cond [(eq_attr "arch" "any")

         (const_string "yes")

         (and (eq_attr "arch" "a")

              (match_test "TARGET_ARM"))

         (const_string "yes")

         (and (eq_attr "arch" "t")

              (match_test "TARGET_THUMB"))

         (const_string "yes")

         (and (eq_attr "arch" "t1")

              (match_test "TARGET_THUMB1"))

         (const_string "yes")

         (and (eq_attr "arch" "t2")

              (match_test "TARGET_THUMB2"))

         (const_string "yes")

         (and (eq_attr "arch" "32")

              (match_test "TARGET_32BIT"))

         (const_string "yes")

         (and (eq_attr "arch" "v6")

              (match_test "TARGET_32BIT && arm_arch6"))

         (const_string "yes")

         (and (eq_attr "arch" "nov6")

              (match_test "TARGET_32BIT && !arm_arch6"))

         (const_string "yes")

         (and (eq_attr "arch" "onlya8")

              (eq_attr "tune" "cortexa8"))

         (const_string "yes")

         (and (eq_attr "arch" "nota8")

              (not (eq_attr "tune" "cortexa8")))

         (const_string "yes")]

        (const_string "no")))

; Allows an insn to disable certain alternatives for reasons other than

; arch support.

(define_attr "insn_enabled" "no,yes"

  (const_string "yes"))

; Enable all alternatives that are both arch_enabled and insn_enabled.

 (define_attr "enabled" "no,yes"

   (if_then_else (eq_attr "insn_enabled" "yes")

               (if_then_else (eq_attr "arch_enabled" "yes")

                             (const_string "yes")

                             (const_string "no"))

                (const_string "no")))

; POOL_RANGE is how far away from a constant pool entry that this insn

; can be placed.  If the distance is zero, then this insn will never

; reference the pool.

; NEG_POOL_RANGE is nonzero for insns that can reference a constant pool entry

; before its address.  It is set to  - (8 + ).

(define_attr "arm_pool_range" "" (const_int 0))

(define_attr "thumb2_pool_range" "" (const_int 0))

(define_attr "arm_neg_pool_range" "" (const_int 0))

(define_attr "thumb2_neg_pool_range" "" (const_int 0))

(define_attr "pool_range" ""

  (cond [(eq_attr "is_thumb" "yes") (attr "thumb2_pool_range")]

        (attr "arm_pool_range")))

(define_attr "neg_pool_range" ""

  (cond [(eq_attr "is_thumb" "yes") (attr "thumb2_neg_pool_range")]

        (attr "arm_neg_pool_range")))

; An assembler sequence may clobber the condition codes without us knowing.

; If such an insn references the pool, then we have no way of knowing how,

; so use the most conservative value for pool_range.

(define_asm_attributes

 [(set_attr "conds" "clob")

  (set_attr "length" "4")

  (set_attr "pool_range" "250")])

;; The instruction used to implement a particular pattern.  This

;; information is used by pipeline descriptions to provide accurate

;; scheduling information.

(define_attr "insn"

        "mov,mvn,smulxy,smlaxy,smlalxy,smulwy,smlawx,mul,muls,mla,mlas,umull,umulls,umlal,umlals,smull,smulls,smlal,smlals,smlawy,smuad,smuadx,smlad,smladx,smusd,smusdx,smlsd,smlsdx,smmul,smmulr,smmla,umaal,smlald,smlsld,clz,mrs,msr,xtab,sdiv,udiv,other"

        (const_string "other"))

; TYPE attribute is used to detect floating point instructions which, if

; running on a co-processor can run in parallel with other, basic instructions

; If write-buffer scheduling is enabled then it can also be used in the

; scheduling of writes.

; Classification of each insn

; Note: vfp.md has different meanings for some of these, and some further

; types as well.  See that file for details.

; alu           any alu  instruction that doesn't hit memory or fp

;               regs or have a shifted source operand

; alu_shift     any data instruction that doesn't hit memory or fp

;               regs, but has a source operand shifted by a constant

; alu_shift_reg any data instruction that doesn't hit memory or fp

;               regs, but has a source operand shifted by a register value

; mult          a multiply instruction

; block         blockage insn, this blocks all functional units

; float         a floating point arithmetic operation (subject to expansion)

; fdivd         DFmode floating point division

; fdivs         SFmode floating point division

; fmul          Floating point multiply

; ffmul         Fast floating point multiply

; farith        Floating point arithmetic (4 cycle)

; ffarith       Fast floating point arithmetic (2 cycle)

; float_em      a floating point arithmetic operation that is normally emulated

;               even on a machine with an fpa.

; f_fpa_load    a floating point load from memory. Only for the FPA.

; f_fpa_store   a floating point store to memory. Only for the FPA.

; f_load[sd]    A single/double load from memory. Used for VFP unit.

; f_store[sd]   A single/double store to memory. Used for VFP unit.

; f_flag        a transfer of co-processor flags to the CPSR

; f_mem_r       a transfer of a floating point register to a real reg via mem

; r_mem_f       the reverse of f_mem_r

; f_2_r         fast transfer float to arm (no memory needed)

; r_2_f         fast transfer arm to float

; f_cvt         convert floating<->integral

; branch        a branch

; call          a subroutine call

; load_byte     load byte(s) from memory to arm registers

; load1         load 1 word from memory to arm registers

; load2         load 2 words from memory to arm registers

; load3         load 3 words from memory to arm registers

; load4         load 4 words from memory to arm registers

; store         store 1 word to memory from arm registers

; store2        store 2 words

; store3        store 3 words

; store4        store 4 (or more) words

;  Additions for Cirrus Maverick co-processor:

; mav_farith    Floating point arithmetic (4 cycle)

; mav_dmult     Double multiplies (7 cycle)

;

(define_attr "type"

        "alu,alu_shift,alu_shift_reg,mult,block,float,fdivx,fdivd,fdivs,fmul,fmuls,fmuld,fmacs,fmacd,ffmul,farith,ffarith,f_flag,float_em,f_fpa_load,f_fpa_store,f_loads,f_loadd,f_stores,f_stored,f_mem_r,r_mem_f,f_2_r,r_2_f,f_cvt,branch,call,load_byte,load1,load2,load3,load4,store1,store2,store3,store4,mav_farith,mav_dmult,fconsts,fconstd,fadds,faddd,ffariths,ffarithd,fcmps,fcmpd,fcpys"

        (if_then_else

         (eq_attr "insn" "smulxy,smlaxy,smlalxy,smulwy,smlawx,mul,muls,mla,mlas,umull,umulls,umlal,umlals,smull,smulls,smlal,smlals")

         (const_string "mult")

         (const_string "alu")))

; Is this an (integer side) multiply with a 64-bit result?

(define_attr "mul64" "no,yes"

             (if_then_else

               (eq_attr "insn" "smlalxy,umull,umulls,umlal,umlals,smull,smulls,smlal,smlals")

               (const_string "yes")

               (const_string "no")))

; Load scheduling, set from the arm_ld_sched variable

; initialized by arm_option_override()

(define_attr "ldsched" "no,yes" (const (symbol_ref "arm_ld_sched")))

;; Classification of NEON instructions for scheduling purposes.

;; Do not set this attribute and the "type" attribute together in

;; any one instruction pattern.

(define_attr "neon_type"

   "neon_int_1,\

   neon_int_2,\

   neon_int_3,\

   neon_int_4,\

   neon_int_5,\

   neon_vqneg_vqabs,\

   neon_vmov,\

   neon_vaba,\

   neon_vsma,\

   neon_vaba_qqq,\

   neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\

   neon_mul_qqq_8_16_32_ddd_32,\

   neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar,\

   neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\

   neon_mla_qqq_8_16,\

   neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long,\

   neon_mla_qqq_32_qqd_32_scalar,\

   neon_mul_ddd_16_scalar_32_16_long_scalar,\

   neon_mul_qqd_32_scalar,\

   neon_mla_ddd_16_scalar_qdd_32_16_long_scalar,\

   neon_shift_1,\

   neon_shift_2,\

   neon_shift_3,\

   neon_vshl_ddd,\

   neon_vqshl_vrshl_vqrshl_qqq,\

   neon_vsra_vrsra,\

   neon_fp_vadd_ddd_vabs_dd,\

   neon_fp_vadd_qqq_vabs_qq,\

   neon_fp_vsum,\

   neon_fp_vmul_ddd,\

   neon_fp_vmul_qqd,\

   neon_fp_vmla_ddd,\

   neon_fp_vmla_qqq,\

   neon_fp_vmla_ddd_scalar,\

   neon_fp_vmla_qqq_scalar,\

   neon_fp_vrecps_vrsqrts_ddd,\

   neon_fp_vrecps_vrsqrts_qqq,\

   neon_bp_simple,\

   neon_bp_2cycle,\

   neon_bp_3cycle,\

   neon_ldr,\

   neon_str,\

   neon_vld1_1_2_regs,\

   neon_vld1_3_4_regs,\

   neon_vld2_2_regs_vld1_vld2_all_lanes,\

   neon_vld2_4_regs,\

   neon_vld3_vld4,\

   neon_vst1_1_2_regs_vst2_2_regs,\

   neon_vst1_3_4_regs,\

   neon_vst2_4_regs_vst3_vst4,\

   neon_vst3_vst4,\

   neon_vld1_vld2_lane,\

   neon_vld3_vld4_lane,\

   neon_vst1_vst2_lane,\

   neon_vst3_vst4_lane,\

   neon_vld3_vld4_all_lanes,\

   neon_mcr,\

   neon_mcr_2_mcrr,\

   neon_mrc,\

   neon_mrrc,\

   neon_ldm_2,\

   neon_stm_2,\

   none"

 (const_string "none"))

; condition codes: this one is used by final_prescan_insn to speed up

; conditionalizing instructions.  It saves having to scan the rtl to see if

; it uses or alters the condition codes.

;

; USE means that the condition codes are used by the insn in the process of

;   outputting code, this means (at present) that we can't use the insn in

;   inlined branches

;

; SET means that the purpose of the insn is to set the condition codes in a

;   well defined manner.

;

; CLOB means that the condition codes are altered in an undefined manner, if

;   they are altered at all

;

; UNCONDITIONAL means the instruction can not be conditionally executed and

;   that the instruction does not use or alter the condition codes.

;

; NOCOND means that the instruction does not use or alter the condition

;   codes but can be converted into a conditionally exectuted instruction.

(define_attr "conds" "use,set,clob,unconditional,nocond"

        (if_then_else

         (ior (eq_attr "is_thumb1" "yes")

              (eq_attr "type" "call"))

         (const_string "clob")

         (if_then_else (eq_attr "neon_type" "none")

          (const_string "nocond")

          (const_string "unconditional"))))

; Predicable means that the insn can be conditionally executed based on

; an automatically added predicate (additional patterns are generated by

; gen...).  We default to 'no' because no Thumb patterns match this rule

; and not all ARM patterns do.

(define_attr "predicable" "no,yes" (const_string "no"))

; Only model the write buffer for ARM6 and ARM7.  Earlier processors don't

; have one.  Later ones, such as StrongARM, have write-back caches, so don't

; suffer blockages enough to warrant modelling this (and it can adversely

; affect the schedule).

(define_attr "model_wbuf" "no,yes" (const (symbol_ref "arm_tune_wbuf")))

; WRITE_CONFLICT implies that a read following an unrelated write is likely

; to stall the processor.  Used with model_wbuf above.

(define_attr "write_conflict" "no,yes"

  (if_then_else (eq_attr "type"

                 "block,float_em,f_fpa_load,f_fpa_store,f_mem_r,r_mem_f,call,load1")

                (const_string "yes")

                (const_string "no")))

; Classify the insns into those that take one cycle and those that take more

; than one on the main cpu execution unit.

(define_attr "core_cycles" "single,multi"

  (if_then_else (eq_attr "type"

                 "alu,alu_shift,float,fdivx,fdivd,fdivs,fmul,ffmul,farith,ffarith")

                (const_string "single")

                (const_string "multi")))

;; FAR_JUMP is "yes" if a BL instruction is used to generate a branch to a

;; distant label.  Only applicable to Thumb code.

(define_attr "far_jump" "yes,no" (const_string "no"))

;; The number of machine instructions this pattern expands to.

;; Used for Thumb-2 conditional execution.

(define_attr "ce_count" "" (const_int 1))

;;---------------------------------------------------------------------------

;; Mode iterators

(include "iterators.md")

;;---------------------------------------------------------------------------

;; Predicates

(include "predicates.md")

(include "constraints.md")

;;---------------------------------------------------------------------------

;; Pipeline descriptions

(define_attr "tune_cortexr4" "yes,no"

  (const (if_then_else

          (eq_attr "tune" "cortexr4,cortexr4f,cortexr5")

          (const_string "yes")

          (const_string "no"))))

;; True if the generic scheduling description should be used.

(define_attr "generic_sched" "yes,no"

  (const (if_then_else

          (ior (eq_attr "tune" "fa526,fa626,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa5,cortexa8,cortexa9,cortexa15,cortexm4")

               (eq_attr "tune_cortexr4" "yes"))

          (const_string "no")

          (const_string "yes"))))

(define_attr "generic_vfp" "yes,no"

  (const (if_then_else

          (and (eq_attr "fpu" "vfp")

               (eq_attr "tune" "!arm1020e,arm1022e,cortexa5,cortexa8,cortexa9,cortexm4")

               (eq_attr "tune_cortexr4" "no"))

          (const_string "yes")

          (const_string "no"))))

(include "arm-generic.md")

(include "arm926ejs.md")

(include "arm1020e.md")

(include "arm1026ejs.md")

(include "arm1136jfs.md")

(include "fa526.md")

(include "fa606te.md")

(include "fa626te.md")

(include "fmp626.md")

(include "fa726te.md")

(include "cortex-a5.md")

(include "cortex-a8.md")

(include "cortex-a9.md")

(include "cortex-a15.md")

(include "cortex-r4.md")

(include "cortex-r4f.md")

(include "cortex-m4.md")

(include "cortex-m4-fpu.md")

(include "vfp11.md")

;;---------------------------------------------------------------------------

;; Insn patterns

;;

;; Addition insns.

;; Note: For DImode insns, there is normally no reason why operands should

;; not be in the same register, what we don't want is for something being

;; written to partially overlap something that is an input.

;; Cirrus 64bit additions should not be split because we have a native

;; 64bit addition instructions.

(define_expand "adddi3"

 [(parallel

   [(set (match_operand:DI           0 "s_register_operand" "")

          (plus:DI (match_operand:DI 1 "s_register_operand" "")

                   (match_operand:DI 2 "s_register_operand" "")))

    (clobber (reg:CC CC_REGNUM))])]

  "TARGET_EITHER"

  "

  if (TARGET_HARD_FLOAT && TARGET_MAVERICK)

    {

      if (!cirrus_fp_register (operands[0], DImode))

        operands[0] = force_reg (DImode, operands[0]);

      if (!cirrus_fp_register (operands[1], DImode))

        operands[1] = force_reg (DImode, operands[1]);

      emit_insn (gen_cirrus_adddi3 (operands[0], operands[1], operands[2]));

      DONE;

    }

  if (TARGET_THUMB1)

    {

      if (GET_CODE (operands[1]) != REG)

        operands[1] = force_reg (DImode, operands[1]);

      if (GET_CODE (operands[2]) != REG)

        operands[2] = force_reg (DImode, operands[2]);

     }

  "

)

(define_insn "*thumb1_adddi3"

  [(set (match_operand:DI          0 "register_operand" "=l")

        (plus:DI (match_operand:DI 1 "register_operand" "%0")

                 (match_operand:DI 2 "register_operand" "l")))

   (clobber (reg:CC CC_REGNUM))

  ]

  "TARGET_THUMB1"

  "add\\t%Q0, %Q0, %Q2\;adc\\t%R0, %R0, %R2"

  [(set_attr "length" "4")]

)

(define_insn_and_split "*arm_adddi3"

  [(set (match_operand:DI          0 "s_register_operand" "=&r,&r")

        (plus:DI (match_operand:DI 1 "s_register_operand" "%0, 0")

                 (match_operand:DI 2 "s_register_operand" "r,  0")))

   (clobber (reg:CC CC_REGNUM))]

  "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK) && !TARGET_NEON"

  "#"

  "TARGET_32BIT && reload_completed

   && ! (TARGET_NEON && IS_VFP_REGNUM (REGNO (operands[0])))"

  [(parallel [(set (reg:CC_C CC_REGNUM)

                   (compare:CC_C (plus:SI (match_dup 1) (match_dup 2))

                                 (match_dup 1)))

              (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])

   (set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5))

                               (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]

  "

  {

    operands[3] = gen_highpart (SImode, operands[0]);

    operands[0] = gen_lowpart (SImode, operands[0]);

    operands[4] = gen_highpart (SImode, operands[1]);

    operands[1] = gen_lowpart (SImode, operands[1]);

    operands[5] = gen_highpart (SImode, operands[2]);

    operands[2] = gen_lowpart (SImode, operands[2]);

  }"

  [(set_attr "conds" "clob")

   (set_attr "length" "8")]

)

(define_insn_and_split "*adddi_sesidi_di"

  [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")

        (plus:DI (sign_extend:DI

                  (match_operand:SI 2 "s_register_operand" "r,r"))

                 (match_operand:DI 1 "s_register_operand" "0,r")))

   (clobber (reg:CC CC_REGNUM))]

  "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)"

  "#"

  "TARGET_32BIT && reload_completed"

  [(parallel [(set (reg:CC_C CC_REGNUM)

                   (compare:CC_C (plus:SI (match_dup 1) (match_dup 2))

                                 (match_dup 1)))

              (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])

   (set (match_dup 3) (plus:SI (plus:SI (ashiftrt:SI (match_dup 2)

                                                     (const_int 31))

                                        (match_dup 4))

                               (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]

  "

  {

    operands[3] = gen_highpart (SImode, operands[0]);

    operands[0] = gen_lowpart (SImode, operands[0]);

    operands[4] = gen_highpart (SImode, operands[1]);

    operands[1] = gen_lowpart (SImode, operands[1]);

    operands[2] = gen_lowpart (SImode, operands[2]);

  }"

  [(set_attr "conds" "clob")

   (set_attr "length" "8")]

)

(define_insn_and_split "*adddi_zesidi_di"

  [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")

        (plus:DI (zero_extend:DI

                  (match_operand:SI 2 "s_register_operand" "r,r"))

                 (match_operand:DI 1 "s_register_operand" "0,r")))

   (clobber (reg:CC CC_REGNUM))]

  "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)"

  "#"

  "TARGET_32BIT && reload_completed"

  [(parallel [(set (reg:CC_C CC_REGNUM)

                   (compare:CC_C (plus:SI (match_dup 1) (match_dup 2))

                                 (match_dup 1)))

              (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])

   (set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (const_int 0))

                               (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]

  "

  {

    operands[3] = gen_highpart (SImode, operands[0]);

    operands[0] = gen_lowpart (SImode, operands[0]);

    operands[4] = gen_highpart (SImode, operands[1]);

    operands[1] = gen_lowpart (SImode, operands[1]);

    operands[2] = gen_lowpart (SImode, operands[2]);

  }"

  [(set_attr "conds" "clob")

   (set_attr "length" "8")]

)

(define_expand "addsi3"

  [(set (match_operand:SI          0 "s_register_operand" "")

        (plus:SI (match_operand:SI 1 "s_register_operand" "")

                 (match_operand:SI 2 "reg_or_int_operand" "")))]

  "TARGET_EITHER"

  "

  if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT)

    {

      arm_split_constant (PLUS, SImode, NULL_RTX,

                          INTVAL (operands[2]), operands[0], operands[1],

                          optimize && can_create_pseudo_p ());

      DONE;

    }

  "

)

; If there is a scratch available, this will be faster than synthesizing the

; addition.

(define_peephole2

  [(match_scratch:SI 3 "r")

   (set (match_operand:SI          0 "arm_general_register_operand" "")

        (plus:SI (match_operand:SI 1 "arm_general_register_operand" "")

                 (match_operand:SI 2 "const_int_operand"  "")))]

  "TARGET_32BIT &&

   !(const_ok_for_arm (INTVAL (operands[2]))

     || const_ok_for_arm (-INTVAL (operands[2])))

    && const_ok_for_arm (~INTVAL (operands[2]))"

  [(set (match_dup 3) (match_dup 2))

   (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))]

  ""

)

;; The r/r/k alternative is required when reloading the address

;;  (plus (reg rN) (reg sp)) into (reg rN).  In this case reload will

;; put the duplicated register first, and not try the commutative version.

(define_insn_and_split "*arm_addsi3"

  [(set (match_operand:SI          0 "s_register_operand" "=r, k,r,r, k, r, k,r, k, r")

        (plus:SI (match_operand:SI 1 "s_register_operand" "%rk,k,r,rk,k, rk,k,rk,k, rk")

                 (match_operand:SI 2 "reg_or_int_operand" "rI,rI,k,Pj,Pj,L, L,PJ,PJ,?n")))]

  "TARGET_32BIT"

  "@

   add%?\\t%0, %1, %2

   add%?\\t%0, %1, %2

   add%?\\t%0, %2, %1

   addw%?\\t%0, %1, %2

   addw%?\\t%0, %1, %2

   sub%?\\t%0, %1, #%n2

   sub%?\\t%0, %1, #%n2

   subw%?\\t%0, %1, #%n2

   subw%?\\t%0, %1, #%n2

   #"

  "TARGET_32BIT

   && GET_CODE (operands[2]) == CONST_INT

   && !const_ok_for_op (INTVAL (operands[2]), PLUS)

   && (reload_completed || !arm_eliminable_register (operands[1]))"

  [(clobber (const_int 0))]

  "

  arm_split_constant (PLUS, SImode, curr_insn,

                      INTVAL (operands[2]), operands[0],

                      operands[1], 0);

  DONE;

  "

  [(set_attr "length" "4,4,4,4,4,4,4,4,4,16")

   (set_attr "predicable" "yes")

   (set_attr "arch" "*,*,*,t2,t2,*,*,t2,t2,*")]

)

(define_insn_and_split "*thumb1_addsi3"

  [(set (match_operand:SI          0 "register_operand" "=l,l,l,*rk,*hk,l,k,l,l,l")

        (plus:SI (match_operand:SI 1 "register_operand" "%0,0,l,*0,*0,k,k,0,l,k")

                 (match_operand:SI 2 "nonmemory_operand" "I,J,lL,*hk,*rk,M,O,Pa,Pb,Pc")))]

  "TARGET_THUMB1"

  "*

   static const char * const asms[] =

   {

     \"add\\t%0, %0, %2\",

     \"sub\\t%0, %0, #%n2\",

     \"add\\t%0, %1, %2\",

     \"add\\t%0, %0, %2\",

     \"add\\t%0, %0, %2\",

     \"add\\t%0, %1, %2\",

     \"add\\t%0, %1, %2\",

     \"#\",

     \"#\",

     \"#\"

   };

   if ((which_alternative == 2 || which_alternative == 6)

       && GET_CODE (operands[2]) == CONST_INT

       && INTVAL (operands[2]) < 0)

     return \"sub\\t%0, %1, #%n2\";

   return asms[which_alternative];

  "

  "&& reload_completed && CONST_INT_P (operands[2])

   && ((operands[1] != stack_pointer_rtx

        && (INTVAL (operands[2]) > 255 || INTVAL (operands[2]) < -255))

       || (operands[1] == stack_pointer_rtx

           && INTVAL (operands[2]) > 1020))"

  [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))

   (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]

  {

    HOST_WIDE_INT offset = INTVAL (operands[2]);

    if (operands[1] == stack_pointer_rtx)

      offset -= 1020;

    else

      {

        if (offset > 255)

          offset = 255;

        else if (offset < -255)

          offset = -255;

      }

    operands[3] = GEN_INT (offset);

    operands[2] = GEN_INT (INTVAL (operands[2]) - offset);

  }

  [(set_attr "length" "2,2,2,2,2,2,2,4,4,4")]

)

;; Reloading and elimination of the frame pointer can

;; sometimes cause this optimization to be missed.

(define_peephole2

  [(set (match_operand:SI 0 "arm_general_register_operand" "")

        (match_operand:SI 1 "const_int_operand" ""))

   (set (match_dup 0)

        (plus:SI (match_dup 0) (reg:SI SP_REGNUM)))]

  "TARGET_THUMB1

   && (unsigned HOST_WIDE_INT) (INTVAL (operands[1])) < 1024

   && (INTVAL (operands[1]) & 3) == 0"

  [(set (match_dup 0) (plus:SI (reg:SI SP_REGNUM) (match_dup 1)))]

  ""

)

(define_insn "addsi3_compare0"

  [(set (reg:CC_NOOV CC_REGNUM)

        (compare:CC_NOOV

         (plus:SI (match_operand:SI 1 "s_register_operand" "r, r")

                  (match_operand:SI 2 "arm_add_operand"    "rI,L"))

         (const_int 0)))

   (set (match_operand:SI 0 "s_register_operand" "=r,r")

        (plus:SI (match_dup 1) (match_dup 2)))]

  "TARGET_ARM"

  "@

   add%.\\t%0, %1, %2

   sub%.\\t%0, %1, #%n2"

  [(set_attr "conds" "set")]

)

(define_insn "*addsi3_compare0_scratch"

  [(set (reg:CC_NOOV CC_REGNUM)

        (compare:CC_NOOV

         (plus:SI (match_operand:SI 0 "s_register_operand" "r, r")

                  (match_operand:SI 1 "arm_add_operand"    "rI,L"))

         (const_int 0)))]

  "TARGET_ARM"

  "@

   cmn%?\\t%0, %1

   cmp%?\\t%0, #%n1"

  [(set_attr "conds" "set")

   (set_attr "predicable" "yes")]

)

(define_insn "*compare_negsi_si"

  [(set (reg:CC_Z CC_REGNUM)

        (compare:CC_Z

         (neg:SI (match_operand:SI 0 "s_register_operand" "r"))

         (match_operand:SI 1 "s_register_operand" "r")))]

  "TARGET_32BIT"

  "cmn%?\\t%1, %0"

  [(set_attr "conds" "set")

   (set_attr "predicable" "yes")]

)

;; This is the canonicalization of addsi3_compare0_for_combiner when the

;; addend is a constant.

(define_insn "*cmpsi2_addneg"

  [(set (reg:CC CC_REGNUM)

        (compare:CC

         (match_operand:SI 1 "s_register_operand" "r,r")

         (match_operand:SI 2 "arm_addimm_operand" "L,I")))

   (set (match_operand:SI 0 "s_register_operand" "=r,r")

        (plus:SI (match_dup 1)

                 (match_operand:SI 3 "arm_addimm_operand" "I,L")))]

  "TARGET_32BIT && INTVAL (operands[2]) == -INTVAL (operands[3])"

  "@

   add%.\\t%0, %1, %3

   sub%.\\t%0, %1, #%n3"

  [(set_attr "conds" "set")]

)

;; Convert the sequence

;;  sub  rd, rn, #1

;;  cmn  rd, #1 (equivalent to cmp rd, #-1)

;;  bne  dest

;; into

;;  subs rd, rn, #1

;;  bcs  dest   ((unsigned)rn >= 1)

;; similarly for the beq variant using bcc.

;; This is a common looping idiom (while (n--))

(define_peephole2

  [(set (match_operand:SI 0 "arm_general_register_operand" "")

        (plus:SI (match_operand:SI 1 "arm_general_register_operand" "")

                 (const_int -1)))

   (set (match_operand 2 "cc_register" "")

        (compare (match_dup 0) (const_int -1)))

   (set (pc)

        (if_then_else (match_operator 3 "equality_operator"

                       [(match_dup 2) (const_int 0)])

                      (match_operand 4 "" "")

                      (match_operand 5 "" "")))]

  "TARGET_32BIT && peep2_reg_dead_p (3, operands[2])"

  [(parallel[

    (set (match_dup 2)

         (compare:CC

          (match_dup 1) (const_int 1)))

    (set (match_dup 0) (plus:SI (match_dup 1) (const_int -1)))])

   (set (pc)

        (if_then_else (match_op_dup 3 [(match_dup 2) (const_int 0)])

                      (match_dup 4)

                      (match_dup 5)))]

  "operands[2] = gen_rtx_REG (CCmode, CC_REGNUM);

   operands[3] = gen_rtx_fmt_ee ((GET_CODE (operands[3]) == NE

                                  ? GEU : LTU),

                                 VOIDmode,

                                 operands[2], const0_rtx);"

)

;; The next four insns work because they compare the result with one of

;; the operands, and we know that the use of the condition code is

;; either GEU or LTU, so we can use the carry flag from the addition

;; instead of doing the compare a second time.

(define_insn "*addsi3_compare_op1"

  [(set (reg:CC_C CC_REGNUM)

        (compare:CC_C

         (plus:SI (match_operand:SI 1 "s_register_operand" "r,r")

                  (match_operand:SI 2 "arm_add_operand" "rI,L"))

         (match_dup 1)))

   (set (match_operand:SI 0 "s_register_operand" "=r,r")

        (plus:SI (match_dup 1) (match_dup 2)))]

  "TARGET_32BIT"

  "@

   add%.\\t%0, %1, %2

   sub%.\\t%0, %1, #%n2"

  [(set_attr "conds" "set")]

)

(define_insn "*addsi3_compare_op2"

  [(set (reg:CC_C CC_REGNUM)

        (compare:CC_C

         (plus:SI (match_operand:SI 1 "s_register_operand" "r,r")

                  (match_operand:SI 2 "arm_add_operand" "rI,L"))

         (match_dup 2)))

   (set (match_operand:SI 0 "s_register_operand" "=r,r")

        (plus:SI (match_dup 1) (match_dup 2)))]

  "TARGET_32BIT"