OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [config/] [arm/] [arm.opt] - Blame information for rev 758

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 709 jeremybenn
; Options for the ARM port of the compiler.
2
 
3
; Copyright (C) 2005, 2007, 2008, 2009, 2011 Free Software Foundation, Inc.
4
;
5
; This file is part of GCC.
6
;
7
; GCC is free software; you can redistribute it and/or modify it under
8
; the terms of the GNU General Public License as published by the Free
9
; Software Foundation; either version 3, or (at your option) any later
10
; version.
11
;
12
; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13
; WARRANTY; without even the implied warranty of MERCHANTABILITY or
14
; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
15
; for more details.
16
;
17
; You should have received a copy of the GNU General Public License
18
; along with GCC; see the file COPYING3.  If not see
19
; .
20
 
21
HeaderInclude
22
config/arm/arm-opts.h
23
 
24
Enum
25
Name(tls_type) Type(enum arm_tls_type)
26
TLS dialect to use:
27
 
28
EnumValue
29
Enum(tls_type) String(gnu) Value(TLS_GNU)
30
 
31
EnumValue
32
Enum(tls_type) String(gnu2) Value(TLS_GNU2)
33
 
34
mabi=
35
Target RejectNegative Joined Enum(arm_abi_type) Var(arm_abi) Init(ARM_DEFAULT_ABI)
36
Specify an ABI
37
 
38
Enum
39
Name(arm_abi_type) Type(enum arm_abi_type)
40
Known ARM ABIs (for use with the -mabi= option):
41
 
42
EnumValue
43
Enum(arm_abi_type) String(apcs-gnu) Value(ARM_ABI_APCS)
44
 
45
EnumValue
46
Enum(arm_abi_type) String(atpcs) Value(ARM_ABI_ATPCS)
47
 
48
EnumValue
49
Enum(arm_abi_type) String(aapcs) Value(ARM_ABI_AAPCS)
50
 
51
EnumValue
52
Enum(arm_abi_type) String(iwmmxt) Value(ARM_ABI_IWMMXT)
53
 
54
EnumValue
55
Enum(arm_abi_type) String(aapcs-linux) Value(ARM_ABI_AAPCS_LINUX)
56
 
57
mabort-on-noreturn
58
Target Report Mask(ABORT_NORETURN)
59
Generate a call to abort if a noreturn function returns
60
 
61
mapcs
62
Target RejectNegative Mask(APCS_FRAME) MaskExists Undocumented
63
 
64
mapcs-float
65
Target Report Mask(APCS_FLOAT)
66
Pass FP arguments in FP registers
67
 
68
mapcs-frame
69
Target Report Mask(APCS_FRAME)
70
Generate APCS conformant stack frames
71
 
72
mapcs-reentrant
73
Target Report Mask(APCS_REENT)
74
Generate re-entrant, PIC code
75
 
76
mapcs-stack-check
77
Target Report Mask(APCS_STACK) Undocumented
78
 
79
march=
80
Target RejectNegative Joined Enum(arm_arch) Var(arm_arch_option)
81
Specify the name of the target architecture
82
 
83
; Other arm_arch values are loaded from arm-tables.opt
84
; but that is a generated file and this is an odd-one-out.
85
EnumValue
86
Enum(arm_arch) String(native) Value(-1) DriverOnly
87
 
88
marm
89
Target Report RejectNegative InverseMask(THUMB)
90
Generate code in 32 bit ARM state.
91
 
92
mbig-endian
93
Target Report RejectNegative Mask(BIG_END)
94
Assume target CPU is configured as big endian
95
 
96
mcallee-super-interworking
97
Target Report Mask(CALLEE_INTERWORKING)
98
Thumb: Assume non-static functions may be called from ARM code
99
 
100
mcaller-super-interworking
101
Target Report Mask(CALLER_INTERWORKING)
102
Thumb: Assume function pointers may go to non-Thumb aware code
103
 
104
mcirrus-fix-invalid-insns
105
Target Report Mask(CIRRUS_FIX_INVALID_INSNS)
106
Cirrus: Place NOPs to avoid invalid instruction combinations
107
 
108
mcpu=
109
Target RejectNegative Joined Enum(processor_type) Var(arm_cpu_option) Init(arm_none)
110
Specify the name of the target CPU
111
 
112
mfloat-abi=
113
Target RejectNegative Joined Enum(float_abi_type) Var(arm_float_abi) Init(TARGET_DEFAULT_FLOAT_ABI)
114
Specify if floating point hardware should be used
115
 
116
Enum
117
Name(float_abi_type) Type(enum float_abi_type)
118
Known floating-point ABIs (for use with the -mfloat-abi= option):
119
 
120
EnumValue
121
Enum(float_abi_type) String(soft) Value(ARM_FLOAT_ABI_SOFT)
122
 
123
EnumValue
124
Enum(float_abi_type) String(softfp) Value(ARM_FLOAT_ABI_SOFTFP)
125
 
126
EnumValue
127
Enum(float_abi_type) String(hard) Value(ARM_FLOAT_ABI_HARD)
128
 
129
mfp=2
130
Target RejectNegative Undocumented Alias(mfpu=, fpe2)
131
 
132
mfp=3
133
Target RejectNegative Undocumented Alias(mfpu=, fpe3)
134
 
135
mfp16-format=
136
Target RejectNegative Joined Enum(arm_fp16_format_type) Var(arm_fp16_format) Init(ARM_FP16_FORMAT_NONE)
137
Specify the __fp16 floating-point format
138
 
139
Enum
140
Name(arm_fp16_format_type) Type(enum arm_fp16_format_type)
141
Known __fp16 formats (for use with the -mfp16-format= option):
142
 
143
EnumValue
144
Enum(arm_fp16_format_type) String(none) Value(ARM_FP16_FORMAT_NONE)
145
 
146
EnumValue
147
Enum(arm_fp16_format_type) String(ieee) Value(ARM_FP16_FORMAT_IEEE)
148
 
149
EnumValue
150
Enum(arm_fp16_format_type) String(alternative) Value(ARM_FP16_FORMAT_ALTERNATIVE)
151
 
152
;; Now ignored.
153
mfpe
154
Target RejectNegative Mask(FPE) Undocumented
155
 
156
mfpe=2
157
Target RejectNegative Undocumented Alias(mfpu=, fpe2)
158
 
159
mfpe=3
160
Target RejectNegative Undocumented Alias(mfpu=, fpe3)
161
 
162
mfpu=
163
Target RejectNegative Joined Enum(arm_fpu) Var(arm_fpu_index)
164
Specify the name of the target floating point hardware/format
165
 
166
mhard-float
167
Target RejectNegative Alias(mfloat-abi=, hard) Undocumented
168
 
169
mlittle-endian
170
Target Report RejectNegative InverseMask(BIG_END)
171
Assume target CPU is configured as little endian
172
 
173
mlong-calls
174
Target Report Mask(LONG_CALLS)
175
Generate call insns as indirect calls, if necessary
176
 
177
mpic-register=
178
Target RejectNegative Joined Var(arm_pic_register_string)
179
Specify the register to be used for PIC addressing
180
 
181
mpoke-function-name
182
Target Report Mask(POKE_FUNCTION_NAME)
183
Store function names in object code
184
 
185
msched-prolog
186
Target Report Mask(SCHED_PROLOG)
187
Permit scheduling of a function's prologue sequence
188
 
189
msingle-pic-base
190
Target Report Mask(SINGLE_PIC_BASE)
191
Do not load the PIC register in function prologues
192
 
193
msoft-float
194
Target RejectNegative Alias(mfloat-abi=, soft) Undocumented
195
 
196
mstructure-size-boundary=
197
Target RejectNegative Joined UInteger Var(arm_structure_size_boundary) Init(DEFAULT_STRUCTURE_SIZE_BOUNDARY)
198
Specify the minimum bit alignment of structures
199
 
200
mthumb
201
Target Report RejectNegative Mask(THUMB)
202
Generate code for Thumb state
203
 
204
mthumb-interwork
205
Target Report Mask(INTERWORK)
206
Support calls between Thumb and ARM instruction sets
207
 
208
mtls-dialect=
209
Target RejectNegative Joined Enum(tls_type) Var(target_tls_dialect) Init(TLS_GNU)
210
Specify thread local storage scheme
211
 
212
mtp=
213
Target RejectNegative Joined Enum(arm_tp_type) Var(target_thread_pointer) Init(TP_AUTO)
214
Specify how to access the thread pointer
215
 
216
Enum
217
Name(arm_tp_type) Type(enum arm_tp_type)
218
Valid arguments to -mtp=:
219
 
220
EnumValue
221
Enum(arm_tp_type) String(soft) Value(TP_SOFT)
222
 
223
EnumValue
224
Enum(arm_tp_type) String(auto) Value(TP_AUTO)
225
 
226
EnumValue
227
Enum(arm_tp_type) String(cp15) Value(TP_CP15)
228
 
229
mtpcs-frame
230
Target Report Mask(TPCS_FRAME)
231
Thumb: Generate (non-leaf) stack frames even if not needed
232
 
233
mtpcs-leaf-frame
234
Target Report Mask(TPCS_LEAF_FRAME)
235
Thumb: Generate (leaf) stack frames even if not needed
236
 
237
mtune=
238
Target RejectNegative Joined Enum(processor_type) Var(arm_tune_option) Init(arm_none)
239
Tune code for the given processor
240
 
241
; Other processor_type values are loaded from arm-tables.opt
242
; but that is a generated file and this is an odd-one-out.
243
EnumValue
244
Enum(processor_type) String(native) Value(-1) DriverOnly
245
 
246
mwords-little-endian
247
Target Report RejectNegative Mask(LITTLE_WORDS)
248
Assume big endian bytes, little endian words.  This option is deprecated.
249
 
250
mvectorize-with-neon-quad
251
Target Report RejectNegative InverseMask(NEON_VECTORIZE_DOUBLE)
252
Use Neon quad-word (rather than double-word) registers for vectorization
253
 
254
mvectorize-with-neon-double
255
Target Report RejectNegative Mask(NEON_VECTORIZE_DOUBLE)
256
Use Neon double-word (rather than quad-word) registers for vectorization
257
 
258
mword-relocations
259
Target Report Var(target_word_relocations) Init(TARGET_DEFAULT_WORD_RELOCATIONS)
260
Only generate absolute relocations on word sized values.
261
 
262
mfix-cortex-m3-ldrd
263
Target Report Var(fix_cm3_ldrd) Init(2)
264
Avoid overlapping destination and address registers on LDRD instructions
265
that may trigger Cortex-M3 errata.
266
 
267
munaligned-access
268
Target Report Var(unaligned_access) Init(2)
269
Enable unaligned word and halfword accesses to packed data.

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.