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jeremybenn |
;; ARM Cortex-A15 pipeline description
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;; Copyright (C) 2011 Free Software Foundation, Inc.
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;;
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;; Written by Matthew Gretton-Dann
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful, but
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;; WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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;; General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; .
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(define_automaton "cortex_a15")
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;; The Cortex-A15 core is modelled as a triple issue pipeline that has
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;; the following dispatch units.
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;; 1. Two pipelines for simple integer operations: SX1, SX2
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;; 2. Two pipelines for Neon and FP data-processing operations: CX1, CX2
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;; 3. One pipeline for branch operations: BX
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;; 4. One pipeline for integer multiply and divide operations: MX
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;; 5. Two pipelines for load and store operations: LS1, LS2
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;;
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;; We can issue into three pipelines per-cycle.
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;;
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;; We assume that where we have unit pairs xx1 is always filled before xx2.
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;; The three issue units
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(define_cpu_unit "ca15_i0, ca15_i1, ca15_i2" "cortex_a15")
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(define_reservation "ca15_issue1" "(ca15_i0|ca15_i1|ca15_i2)")
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(define_reservation "ca15_issue2" "((ca15_i0+ca15_i1)|(ca15_i1+ca15_i2))")
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(define_reservation "ca15_issue3" "(ca15_i0+ca15_i1+ca15_i2)")
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(final_presence_set "ca15_i1" "ca15_i0")
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(final_presence_set "ca15_i2" "ca15_i1")
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;; The main dispatch units
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(define_cpu_unit "ca15_sx1, ca15_sx2" "cortex_a15")
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(define_cpu_unit "ca15_cx1, ca15_cx2" "cortex_a15")
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(define_cpu_unit "ca15_ls1, ca15_ls2" "cortex_a15")
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(define_cpu_unit "ca15_bx, ca15_mx" "cortex_a15")
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(define_reservation "ca15_ls" "(ca15_ls1|ca15_ls2)")
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;; The extended load-store pipeline
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(define_cpu_unit "ca15_ldr, ca15_str" "cortex_a15")
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;; The extended ALU pipeline
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(define_cpu_unit "ca15_sx1_alu, ca15_sx1_shf, ca15_sx1_sat" "cortex_a15")
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(define_cpu_unit "ca15_sx2_alu, ca15_sx2_shf, ca15_sx2_sat" "cortex_a15")
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;; Simple Execution Unit:
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;;
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;; Simple ALU without shift
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(define_insn_reservation "cortex_a15_alu" 2
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(and (eq_attr "tune" "cortexa15")
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(and (eq_attr "type" "alu")
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(eq_attr "neon_type" "none")))
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"ca15_issue1,(ca15_sx1,ca15_sx1_alu)|(ca15_sx2,ca15_sx2_alu)")
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;; ALU ops with immediate shift
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(define_insn_reservation "cortex_a15_alu_shift" 3
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(and (eq_attr "tune" "cortexa15")
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(and (eq_attr "type" "alu_shift")
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(eq_attr "neon_type" "none")))
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"ca15_issue1,(ca15_sx1,ca15_sx1+ca15_sx1_shf,ca15_sx1_alu)\
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|(ca15_sx2,ca15_sx2+ca15_sx2_shf,ca15_sx2_alu)")
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;; ALU ops with register controlled shift
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(define_insn_reservation "cortex_a15_alu_shift_reg" 3
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(and (eq_attr "tune" "cortexa15")
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(and (eq_attr "type" "alu_shift_reg")
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(eq_attr "neon_type" "none")))
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"(ca15_issue2,ca15_sx1+ca15_sx2,ca15_sx1_shf,ca15_sx2_alu)\
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|(ca15_issue1,(ca15_issue1+ca15_sx2,ca15_sx1+ca15_sx2_shf)\
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|(ca15_issue1+ca15_sx1,ca15_sx1+ca15_sx1_shf),ca15_sx1_alu)")
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;; Multiply Execution Unit:
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;;
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;; 32-bit multiplies
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(define_insn_reservation "cortex_a15_mult32" 3
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(and (eq_attr "tune" "cortexa15")
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(and (eq_attr "type" "mult")
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(and (eq_attr "neon_type" "none")
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(eq_attr "mul64" "no"))))
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"ca15_issue1,ca15_mx")
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;; 64-bit multiplies
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(define_insn_reservation "cortex_a15_mult64" 4
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(and (eq_attr "tune" "cortexa15")
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(and (eq_attr "type" "mult")
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(and (eq_attr "neon_type" "none")
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(eq_attr "mul64" "yes"))))
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"ca15_issue1,ca15_mx*2")
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;; Integer divide
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(define_insn_reservation "cortex_a15_udiv" 9
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(and (eq_attr "tune" "cortexa15")
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(eq_attr "insn" "udiv"))
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"ca15_issue1,ca15_mx")
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(define_insn_reservation "cortex_a15_sdiv" 10
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(and (eq_attr "tune" "cortexa15")
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(eq_attr "insn" "sdiv"))
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"ca15_issue1,ca15_mx")
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;; Block all issue pipes for a cycle
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(define_insn_reservation "cortex_a15_block" 1
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(and (eq_attr "tune" "cortexa15")
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(and (eq_attr "type" "block")
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(eq_attr "neon_type" "none")))
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"ca15_issue3")
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;; Branch execution Unit
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;;
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;; Branches take one issue slot.
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;; No latency as there is no result
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(define_insn_reservation "cortex_a15_branch" 0
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(and (eq_attr "tune" "cortexa15")
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(and (eq_attr "type" "branch")
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(eq_attr "neon_type" "none")))
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"ca15_issue1,ca15_bx")
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;; We lie with calls. They take up all issue slots, and form a block in the
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;; pipeline. The result however is available the next cycle.
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;;
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;; Addition of new units requires this to be updated.
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(define_insn_reservation "cortex_a15_call" 1
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(and (eq_attr "tune" "cortexa15")
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(and (eq_attr "type" "call")
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(eq_attr "neon_type" "none")))
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"ca15_issue3,\
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ca15_sx1+ca15_sx2+ca15_bx+ca15_mx+ca15_cx1+ca15_cx2+ca15_ls1+ca15_ls2,\
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ca15_sx1_alu+ca15_sx1_shf+ca15_sx1_sat+ca15_sx2_alu+ca15_sx2_shf\
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+ca15_sx2_sat+ca15_ldr+ca15_str")
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;; Load-store execution Unit
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;;
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;; Loads of up to two words.
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(define_insn_reservation "cortex_a15_load1" 4
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(and (eq_attr "tune" "cortexa15")
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(and (eq_attr "type" "load_byte,load1,load2")
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(eq_attr "neon_type" "none")))
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"ca15_issue1,ca15_ls,ca15_ldr,nothing")
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;; Loads of three or four words.
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(define_insn_reservation "cortex_a15_load3" 5
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(and (eq_attr "tune" "cortexa15")
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(and (eq_attr "type" "load3,load4")
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(eq_attr "neon_type" "none")))
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"ca15_issue2,ca15_ls1+ca15_ls2,ca15_ldr,ca15_ldr,nothing")
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;; Stores of up to two words.
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(define_insn_reservation "cortex_a15_store1" 0
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(and (eq_attr "tune" "cortexa15")
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(and (eq_attr "type" "store1,store2")
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(eq_attr "neon_type" "none")))
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"ca15_issue1,ca15_ls,ca15_str")
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;; Stores of three or four words.
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(define_insn_reservation "cortex_a15_store3" 0
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(and (eq_attr "tune" "cortexa15")
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(and (eq_attr "type" "store3,store4")
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(eq_attr "neon_type" "none")))
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"ca15_issue2,ca15_ls1+ca15_ls2,ca15_str,ca15_str")
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;; Simple execution unit bypasses
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(define_bypass 1 "cortex_a15_alu"
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"cortex_a15_alu,cortex_a15_alu_shift,cortex_a15_alu_shift_reg")
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(define_bypass 2 "cortex_a15_alu_shift"
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"cortex_a15_alu,cortex_a15_alu_shift,cortex_a15_alu_shift_reg")
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(define_bypass 2 "cortex_a15_alu_shift_reg"
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"cortex_a15_alu,cortex_a15_alu_shift,cortex_a15_alu_shift_reg")
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(define_bypass 1 "cortex_a15_alu" "cortex_a15_load1,cortex_a15_load3")
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(define_bypass 2 "cortex_a15_alu_shift" "cortex_a15_load1,cortex_a15_load3")
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(define_bypass 2 "cortex_a15_alu_shift_reg"
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"cortex_a15_load1,cortex_a15_load3")
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