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Line No. Rev Author Line
1 709 jeremybenn
;; ARM Cortex-A5 pipeline description
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;; Copyright (C) 2010 Free Software Foundation, Inc.
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;; Contributed by CodeSourcery.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful, but
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;; WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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;; General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3.  If not see
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;; .
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(define_automaton "cortex_a5")
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Functional units.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; The integer (ALU) pipeline.  There are five DPU pipeline
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;; stages. However the decode/issue stages operate the same for all
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;; instructions, so do not model them.  We only need to model the
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;; first execute stage because instructions always advance one stage
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;; per cycle in order.  Only branch instructions may dual-issue, so a
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;; single unit covers all of the LS, ALU, MAC and FPU pipelines.
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34
(define_cpu_unit "cortex_a5_ex1" "cortex_a5")
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;; The branch pipeline.  Branches can dual-issue with other instructions
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;; (except when those instructions take multiple cycles to issue).
38
 
39
(define_cpu_unit "cortex_a5_branch" "cortex_a5")
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;; Pseudo-unit for blocking the multiply pipeline when a double-precision
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;; multiply is in progress.
43
 
44
(define_cpu_unit "cortex_a5_fpmul_pipe" "cortex_a5")
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;; The floating-point add pipeline (ex1/f1 stage), used to model the usage
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;; of the add pipeline by fmac instructions, etc.
48
 
49
(define_cpu_unit "cortex_a5_fpadd_pipe" "cortex_a5")
50
 
51
;; Floating-point div/sqrt (long latency, out-of-order completion).
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53
(define_cpu_unit "cortex_a5_fp_div_sqrt" "cortex_a5")
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; ALU instructions.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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59
(define_insn_reservation "cortex_a5_alu" 2
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  (and (eq_attr "tune" "cortexa5")
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       (eq_attr "type" "alu"))
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  "cortex_a5_ex1")
63
 
64
(define_insn_reservation "cortex_a5_alu_shift" 2
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  (and (eq_attr "tune" "cortexa5")
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       (eq_attr "type" "alu_shift,alu_shift_reg"))
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  "cortex_a5_ex1")
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69
;; Forwarding path for unshifted operands.
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(define_bypass 1 "cortex_a5_alu,cortex_a5_alu_shift"
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  "cortex_a5_alu")
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74
(define_bypass 1 "cortex_a5_alu,cortex_a5_alu_shift"
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  "cortex_a5_alu_shift"
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  "arm_no_early_alu_shift_dep")
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78
;; The multiplier pipeline can forward results from wr stage only so
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;; there's no need to specify bypasses).
80
 
81
(define_insn_reservation "cortex_a5_mul" 2
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  (and (eq_attr "tune" "cortexa5")
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       (eq_attr "type" "mult"))
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  "cortex_a5_ex1")
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86
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Load/store instructions.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
89
 
90
;; Address-generation happens in the issue stage, which is one stage behind
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;; the ex1 stage (the first stage we care about for scheduling purposes). The
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;; dc1 stage is parallel with ex1, dc2 with ex2 and rot with wr.
93
 
94
(define_insn_reservation "cortex_a5_load1" 2
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  (and (eq_attr "tune" "cortexa5")
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       (eq_attr "type" "load_byte,load1"))
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  "cortex_a5_ex1")
98
 
99
(define_insn_reservation "cortex_a5_store1" 0
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  (and (eq_attr "tune" "cortexa5")
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       (eq_attr "type" "store1"))
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  "cortex_a5_ex1")
103
 
104
(define_insn_reservation "cortex_a5_load2" 3
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  (and (eq_attr "tune" "cortexa5")
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       (eq_attr "type" "load2"))
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  "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
108
 
109
(define_insn_reservation "cortex_a5_store2" 0
110
  (and (eq_attr "tune" "cortexa5")
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       (eq_attr "type" "store2"))
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  "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
113
 
114
(define_insn_reservation "cortex_a5_load3" 4
115
  (and (eq_attr "tune" "cortexa5")
116
       (eq_attr "type" "load3"))
117
  "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\
118
   cortex_a5_ex1")
119
 
120
(define_insn_reservation "cortex_a5_store3" 0
121
  (and (eq_attr "tune" "cortexa5")
122
       (eq_attr "type" "store3"))
123
  "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\
124
   cortex_a5_ex1")
125
 
126
(define_insn_reservation "cortex_a5_load4" 5
127
  (and (eq_attr "tune" "cortexa5")
128
       (eq_attr "type" "load3"))
129
  "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\
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   cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
131
 
132
(define_insn_reservation "cortex_a5_store4" 0
133
  (and (eq_attr "tune" "cortexa5")
134
       (eq_attr "type" "store3"))
135
  "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\
136
   cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
137
 
138
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
139
;; Branches.
140
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
141
 
142
;; Direct branches are the only instructions we can dual-issue (also IT and
143
;; nop, but those aren't very interesting for scheduling).  (The latency here
144
;; is meant to represent when the branch actually takes place, but may not be
145
;; entirely correct.)
146
 
147
(define_insn_reservation "cortex_a5_branch" 3
148
  (and (eq_attr "tune" "cortexa5")
149
       (eq_attr "type" "branch,call"))
150
  "cortex_a5_branch")
151
 
152
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Floating-point arithmetic.
154
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
155
 
156
(define_insn_reservation "cortex_a5_fpalu" 4
157
  (and (eq_attr "tune" "cortexa5")
158
       (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys, fmuls, f_cvt,\
159
                        fcmps, fcmpd"))
160
  "cortex_a5_ex1+cortex_a5_fpadd_pipe")
161
 
162
;; For fconsts and fconstd, 8-bit immediate data is passed directly from
163
;; f1 to f3 (which I think reduces the latency by one cycle).
164
 
165
(define_insn_reservation "cortex_a5_fconst" 3
166
  (and (eq_attr "tune" "cortexa5")
167
       (eq_attr "type" "fconsts,fconstd"))
168
  "cortex_a5_ex1+cortex_a5_fpadd_pipe")
169
 
170
;; We should try not to attempt to issue a single-precision multiplication in
171
;; the middle of a double-precision multiplication operation (the usage of
172
;; cortex_a5_fpmul_pipe).
173
 
174
(define_insn_reservation "cortex_a5_fpmuls" 4
175
  (and (eq_attr "tune" "cortexa5")
176
       (eq_attr "type" "fmuls"))
177
  "cortex_a5_ex1+cortex_a5_fpmul_pipe")
178
 
179
;; For single-precision multiply-accumulate, the add (accumulate) is issued
180
;; whilst the multiply is in F4.  The multiply result can then be forwarded
181
;; from F5 to F1.  The issue unit is only used once (when we first start
182
;; processing the instruction), but the usage of the FP add pipeline could
183
;; block other instructions attempting to use it simultaneously.  We try to
184
;; avoid that using cortex_a5_fpadd_pipe.
185
 
186
(define_insn_reservation "cortex_a5_fpmacs" 8
187
  (and (eq_attr "tune" "cortexa5")
188
       (eq_attr "type" "fmacs"))
189
  "cortex_a5_ex1+cortex_a5_fpmul_pipe, nothing*3, cortex_a5_fpadd_pipe")
190
 
191
;; Non-multiply instructions can issue in the middle two instructions of a
192
;; double-precision multiply.  Note that it isn't entirely clear when a branch
193
;; can dual-issue when a multi-cycle multiplication is in progress; we ignore
194
;; that for now though.
195
 
196
(define_insn_reservation "cortex_a5_fpmuld" 7
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  (and (eq_attr "tune" "cortexa5")
198
       (eq_attr "type" "fmuld"))
199
  "cortex_a5_ex1+cortex_a5_fpmul_pipe, cortex_a5_fpmul_pipe*2,\
200
   cortex_a5_ex1+cortex_a5_fpmul_pipe")
201
 
202
(define_insn_reservation "cortex_a5_fpmacd" 11
203
  (and (eq_attr "tune" "cortexa5")
204
       (eq_attr "type" "fmacd"))
205
  "cortex_a5_ex1+cortex_a5_fpmul_pipe, cortex_a5_fpmul_pipe*2,\
206
   cortex_a5_ex1+cortex_a5_fpmul_pipe, nothing*3, cortex_a5_fpadd_pipe")
207
 
208
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Floating-point divide/square root instructions.
210
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
211
 
212
;; ??? Not sure if the 14 cycles taken for single-precision divide to complete
213
;; includes the time taken for the special instruction used to collect the
214
;; result to travel down the multiply pipeline, or not.  Assuming so.  (If
215
;; that's wrong, the latency should be increased by a few cycles.)
216
 
217
;; fsqrt takes one cycle less, but that is not modelled, nor is the use of the
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;; multiply pipeline to collect the divide/square-root result.
219
 
220
(define_insn_reservation "cortex_a5_fdivs" 14
221
  (and (eq_attr "tune" "cortexa5")
222
       (eq_attr "type" "fdivs"))
223
  "cortex_a5_ex1, cortex_a5_fp_div_sqrt * 13")
224
 
225
;; ??? Similarly for fdivd.
226
 
227
(define_insn_reservation "cortex_a5_fdivd" 29
228
  (and (eq_attr "tune" "cortexa5")
229
       (eq_attr "type" "fdivd"))
230
  "cortex_a5_ex1, cortex_a5_fp_div_sqrt * 28")
231
 
232
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; VFP to/from core transfers.
234
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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236
;; FP loads take data from wr/rot/f3.
237
 
238
;; Core-to-VFP transfers use the multiply pipeline.
239
 
240
(define_insn_reservation "cortex_a5_r2f" 4
241
  (and (eq_attr "tune" "cortexa5")
242
       (eq_attr "type" "r_2_f"))
243
  "cortex_a5_ex1")
244
 
245
(define_insn_reservation "cortex_a5_f2r" 2
246
  (and (eq_attr "tune" "cortexa5")
247
       (eq_attr "type" "f_2_r"))
248
  "cortex_a5_ex1")
249
 
250
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
251
;; VFP flag transfer.
252
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
253
 
254
;; ??? The flag forwarding from fmstat to the ex2 stage of the second
255
;; instruction is not modeled at present.
256
 
257
(define_insn_reservation "cortex_a5_f_flags" 4
258
  (and (eq_attr "tune" "cortexa5")
259
       (eq_attr "type" "f_flag"))
260
  "cortex_a5_ex1")
261
 
262
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
263
;; VFP load/store.
264
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
265
 
266
(define_insn_reservation "cortex_a5_f_loads" 4
267
  (and (eq_attr "tune" "cortexa5")
268
       (eq_attr "type" "f_loads"))
269
  "cortex_a5_ex1")
270
 
271
(define_insn_reservation "cortex_a5_f_loadd" 5
272
  (and (eq_attr "tune" "cortexa5")
273
       (eq_attr "type" "f_loadd"))
274
  "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
275
 
276
(define_insn_reservation "cortex_a5_f_stores" 0
277
  (and (eq_attr "tune" "cortexa5")
278
       (eq_attr "type" "f_stores"))
279
  "cortex_a5_ex1")
280
 
281
(define_insn_reservation "cortex_a5_f_stored" 0
282
  (and (eq_attr "tune" "cortexa5")
283
       (eq_attr "type" "f_stored"))
284
  "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
285
 
286
;; Load-to-use for floating-point values has a penalty of one cycle,
287
;; i.e. a latency of two.
288
 
289
(define_bypass 2 "cortex_a5_f_loads"
290
                 "cortex_a5_fpalu, cortex_a5_fpmacs, cortex_a5_fpmuld,\
291
                  cortex_a5_fpmacd, cortex_a5_fdivs, cortex_a5_fdivd,\
292
                  cortex_a5_f2r")
293
 
294
(define_bypass 3 "cortex_a5_f_loadd"
295
                 "cortex_a5_fpalu, cortex_a5_fpmacs, cortex_a5_fpmuld,\
296
                  cortex_a5_fpmacd, cortex_a5_fdivs, cortex_a5_fdivd,\
297
                  cortex_a5_f2r")

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