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jeremybenn |
;; ARM Cortex-M4 FPU pipeline description
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;; Copyright (C) 2010 Free Software Foundation, Inc.
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;; Contributed by CodeSourcery.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful, but
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;; WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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;; General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; .
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;; Use an artifial unit to model FPU.
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(define_cpu_unit "cortex_m4_v" "cortex_m4")
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(define_reservation "cortex_m4_ex_v" "cortex_m4_ex+cortex_m4_v")
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;; Integer instructions following VDIV or VSQRT complete out-of-order.
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(define_insn_reservation "cortex_m4_fdivs" 15
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(and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "fdivs"))
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"cortex_m4_ex_v,cortex_m4_v*13")
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(define_insn_reservation "cortex_m4_vmov_1" 1
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(and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "fcpys,fconsts"))
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"cortex_m4_ex_v")
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(define_insn_reservation "cortex_m4_vmov_2" 2
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(and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "f_2_r,r_2_f"))
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"cortex_m4_ex_v*2")
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(define_insn_reservation "cortex_m4_fmuls" 2
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(and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "fmuls"))
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"cortex_m4_ex_v")
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(define_insn_reservation "cortex_m4_fmacs" 4
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(and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "fmacs"))
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"cortex_m4_ex_v*3")
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(define_insn_reservation "cortex_m4_ffariths" 1
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(and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "ffariths"))
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"cortex_m4_ex_v")
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(define_insn_reservation "cortex_m4_fadds" 2
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(and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "fadds"))
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"cortex_m4_ex_v")
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(define_insn_reservation "cortex_m4_fcmps" 1
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(and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "fcmps"))
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"cortex_m4_ex_v")
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(define_insn_reservation "cortex_m4_f_flag" 1
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(and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "f_flag"))
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"cortex_m4_ex_v")
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(define_insn_reservation "cortex_m4_f_cvt" 2
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(and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "f_cvt"))
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"cortex_m4_ex_v")
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(define_insn_reservation "cortex_m4_f_load" 2
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(and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "f_loads"))
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"cortex_m4_ex_v*2")
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(define_insn_reservation "cortex_m4_f_store" 2
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(and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "f_stores"))
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"cortex_m4_ex_v*2")
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(define_insn_reservation "cortex_m4_f_loadd" 3
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(and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "f_loadd"))
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"cortex_m4_ex_v*3")
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(define_insn_reservation "cortex_m4_f_stored" 3
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(and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "f_stored"))
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"cortex_m4_ex_v*3")
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;; MAC instructions consume their addend one cycle later. If the result
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;; of an arithmetic instruction is consumed as the addend of the following
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;; MAC instruction, the latency can be decreased by one.
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(define_bypass 1 "cortex_m4_fadds,cortex_m4_fmuls,cortex_m4_f_cvt"
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"cortex_m4_fmacs"
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"arm_no_early_mul_dep")
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(define_bypass 3 "cortex_m4_fmacs"
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"cortex_m4_fmacs"
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"arm_no_early_mul_dep")
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(define_bypass 14 "cortex_m4_fdivs"
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"cortex_m4_fmacs"
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"arm_no_early_mul_dep")
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