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jeremybenn |
;; ARM Cortex-M4 pipeline description
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;; Copyright (C) 2010 Free Software Foundation, Inc.
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;; Contributed by CodeSourcery.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful, but
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;; WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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;; General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; .
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(define_automaton "cortex_m4")
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;; We model the pipelining of LDR instructions by using two artificial units.
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(define_cpu_unit "cortex_m4_a" "cortex_m4")
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(define_cpu_unit "cortex_m4_b" "cortex_m4")
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(define_reservation "cortex_m4_ex" "cortex_m4_a+cortex_m4_b")
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;; ALU and multiply is one cycle.
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(define_insn_reservation "cortex_m4_alu" 1
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(and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "alu,alu_shift,alu_shift_reg,mult"))
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"cortex_m4_ex")
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;; Byte, half-word and word load is two cycles.
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(define_insn_reservation "cortex_m4_load1" 2
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(and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "load_byte,load1"))
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"cortex_m4_a, cortex_m4_b")
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;; str rx, [ry, #imm] is always one cycle.
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(define_insn_reservation "cortex_m4_store1_1" 1
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(and (and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "store1"))
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(match_test "arm_address_offset_is_imm (insn)"))
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"cortex_m4_a")
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;; Other byte, half-word and word load is two cycles.
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(define_insn_reservation "cortex_m4_store1_2" 2
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(and (and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "store1"))
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(not (match_test "arm_address_offset_is_imm (insn)")))
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"cortex_m4_a*2")
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(define_insn_reservation "cortex_m4_load2" 3
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(and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "load2"))
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"cortex_m4_ex*3")
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(define_insn_reservation "cortex_m4_store2" 3
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(and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "store2"))
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"cortex_m4_ex*3")
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(define_insn_reservation "cortex_m4_load3" 4
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(and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "load3"))
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"cortex_m4_ex*4")
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(define_insn_reservation "cortex_m4_store3" 4
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(and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "store3"))
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"cortex_m4_ex*4")
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(define_insn_reservation "cortex_m4_load4" 5
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(and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "load4"))
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"cortex_m4_ex*5")
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(define_insn_reservation "cortex_m4_store4" 5
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(and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "store4"))
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"cortex_m4_ex*5")
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;; If the address of load or store depends on the result of the preceding
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;; instruction, the latency is increased by one.
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(define_bypass 2 "cortex_m4_alu"
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"cortex_m4_load1"
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"arm_early_load_addr_dep")
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(define_bypass 2 "cortex_m4_alu"
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"cortex_m4_store1_1,cortex_m4_store1_2"
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"arm_early_store_addr_dep")
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(define_insn_reservation "cortex_m4_branch" 3
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(and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "branch"))
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"cortex_m4_ex*3")
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(define_insn_reservation "cortex_m4_call" 3
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(and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "call"))
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"cortex_m4_ex*3")
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(define_insn_reservation "cortex_m4_block" 1
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(and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "block"))
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"cortex_m4_ex")
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