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jeremybenn |
;; ARM Cortex-R4 scheduling description.
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;; Copyright (C) 2007, 2008 Free Software Foundation, Inc.
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;; Contributed by CodeSourcery.
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;; This file is part of GCC.
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; .
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(define_automaton "cortex_r4")
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;; We approximate the dual-issue constraints of this core using four
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;; "issue units" and a reservation matrix as follows. The numbers indicate
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;; the instruction groups' preferences in order. Multiple entries for
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;; the same numbered preference indicate units that must be reserved
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;; together.
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;;
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;; Issue unit: A B C ALU
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;;
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;; ALU w/o reg shift 1st 2nd 1st and 2nd
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;; ALU w/ reg shift 1st 2nd 2nd 1st and 2nd
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;; Moves 1st 2nd 2nd
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;; Multiplication 1st 1st
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;; Division 1st 1st
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;; Load/store single 1st 1st
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;; Other load/store 1st 1st
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;; Branches 1st
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(define_cpu_unit "cortex_r4_issue_a" "cortex_r4")
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(define_cpu_unit "cortex_r4_issue_b" "cortex_r4")
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(define_cpu_unit "cortex_r4_issue_c" "cortex_r4")
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(define_cpu_unit "cortex_r4_issue_alu" "cortex_r4")
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(define_reservation "cortex_r4_alu"
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"(cortex_r4_issue_a+cortex_r4_issue_alu)|\
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(cortex_r4_issue_b+cortex_r4_issue_alu)")
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(define_reservation "cortex_r4_alu_shift_reg"
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"(cortex_r4_issue_a+cortex_r4_issue_alu)|\
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(cortex_r4_issue_b+cortex_r4_issue_c+\
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cortex_r4_issue_alu)")
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(define_reservation "cortex_r4_mov"
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"cortex_r4_issue_a|(cortex_r4_issue_b+\
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cortex_r4_issue_alu)")
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(define_reservation "cortex_r4_mul" "cortex_r4_issue_a+cortex_r4_issue_alu")
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(define_reservation "cortex_r4_mul_2"
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"(cortex_r4_issue_a+cortex_r4_issue_alu)*2")
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;; Division instructions execute out-of-order with respect to the
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;; rest of the pipeline and only require reservations on their first and
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;; final cycles.
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(define_reservation "cortex_r4_div_9"
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"cortex_r4_issue_a+cortex_r4_issue_alu,\
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nothing*7,\
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cortex_r4_issue_a+cortex_r4_issue_alu")
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(define_reservation "cortex_r4_div_10"
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"cortex_r4_issue_a+cortex_r4_issue_alu,\
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nothing*8,\
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cortex_r4_issue_a+cortex_r4_issue_alu")
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(define_reservation "cortex_r4_load_store"
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"cortex_r4_issue_a+cortex_r4_issue_c")
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(define_reservation "cortex_r4_load_store_2"
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"(cortex_r4_issue_a+cortex_r4_issue_b)*2")
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(define_reservation "cortex_r4_branch" "cortex_r4_issue_b")
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;; We assume that all instructions are unconditional.
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;; Data processing instructions. Moves without shifts are kept separate
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;; for the purposes of the dual-issue constraints above.
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(define_insn_reservation "cortex_r4_alu" 2
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(and (eq_attr "tune_cortexr4" "yes")
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(and (eq_attr "type" "alu")
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(not (eq_attr "insn" "mov"))))
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"cortex_r4_alu")
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(define_insn_reservation "cortex_r4_mov" 2
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(and (eq_attr "tune_cortexr4" "yes")
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(and (eq_attr "type" "alu")
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(eq_attr "insn" "mov")))
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"cortex_r4_mov")
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(define_insn_reservation "cortex_r4_alu_shift" 2
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(and (eq_attr "tune_cortexr4" "yes")
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(eq_attr "type" "alu_shift"))
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"cortex_r4_alu")
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(define_insn_reservation "cortex_r4_alu_shift_reg" 2
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(and (eq_attr "tune_cortexr4" "yes")
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(eq_attr "type" "alu_shift_reg"))
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"cortex_r4_alu_shift_reg")
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;; An ALU instruction followed by an ALU instruction with no early dep.
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(define_bypass 1 "cortex_r4_alu,cortex_r4_alu_shift,cortex_r4_alu_shift_reg,\
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cortex_r4_mov"
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"cortex_r4_alu")
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(define_bypass 1 "cortex_r4_alu,cortex_r4_alu_shift,cortex_r4_alu_shift_reg,\
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cortex_r4_mov"
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"cortex_r4_alu_shift"
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"arm_no_early_alu_shift_dep")
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(define_bypass 1 "cortex_r4_alu,cortex_r4_alu_shift,cortex_r4_alu_shift_reg,\
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cortex_r4_mov"
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"cortex_r4_alu_shift_reg"
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"arm_no_early_alu_shift_value_dep")
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;; In terms of availabilities, a consumer mov could theoretically be
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;; issued together with a producer ALU instruction, without stalls.
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;; In practice this cannot happen because mov;add (in that order) is not
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;; eligible for dual issue and furthermore dual issue is not permitted
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;; when a dependency is involved. We therefore note it as latency one.
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;; A mov followed by another of the same is also latency one.
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(define_bypass 1 "cortex_r4_alu,cortex_r4_alu_shift,cortex_r4_alu_shift_reg,\
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cortex_r4_mov"
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"cortex_r4_mov")
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;; qadd, qdadd, qsub and qdsub are not currently emitted, and neither are
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;; media data processing instructions nor sad instructions.
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;; Multiplication instructions.
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(define_insn_reservation "cortex_r4_mul_4" 4
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(and (eq_attr "tune_cortexr4" "yes")
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(eq_attr "insn" "mul,smmul"))
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"cortex_r4_mul_2")
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(define_insn_reservation "cortex_r4_mul_3" 3
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(and (eq_attr "tune_cortexr4" "yes")
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(eq_attr "insn" "smulxy,smulwy,smuad,smusd"))
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"cortex_r4_mul")
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(define_insn_reservation "cortex_r4_mla_4" 4
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(and (eq_attr "tune_cortexr4" "yes")
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(eq_attr "insn" "mla,smmla"))
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"cortex_r4_mul_2")
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(define_insn_reservation "cortex_r4_mla_3" 3
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(and (eq_attr "tune_cortexr4" "yes")
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(eq_attr "insn" "smlaxy,smlawy,smlad,smlsd"))
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"cortex_r4_mul")
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(define_insn_reservation "cortex_r4_smlald" 3
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(and (eq_attr "tune_cortexr4" "yes")
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(eq_attr "insn" "smlald,smlsld"))
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"cortex_r4_mul")
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(define_insn_reservation "cortex_r4_mull" 4
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(and (eq_attr "tune_cortexr4" "yes")
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(eq_attr "insn" "smull,umull,umlal,umaal"))
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"cortex_r4_mul_2")
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;; A multiply or an MLA with a single-register result, followed by an
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;; MLA with an accumulator dependency, has its result forwarded.
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(define_bypass 2 "cortex_r4_mul_3,cortex_r4_mla_3"
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"cortex_r4_mla_3,cortex_r4_mla_4"
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"arm_mac_accumulator_is_mul_result")
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(define_bypass 3 "cortex_r4_mul_4,cortex_r4_mla_4"
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"cortex_r4_mla_3,cortex_r4_mla_4"
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"arm_mac_accumulator_is_mul_result")
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;; A multiply followed by an ALU instruction needing the multiply
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;; result only at ALU has lower latency than one needing it at Shift.
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(define_bypass 2 "cortex_r4_mul_3,cortex_r4_mla_3,cortex_r4_smlald"
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"cortex_r4_alu")
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(define_bypass 2 "cortex_r4_mul_3,cortex_r4_mla_3,cortex_r4_smlald"
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"cortex_r4_alu_shift"
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"arm_no_early_alu_shift_dep")
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(define_bypass 2 "cortex_r4_mul_3,cortex_r4_mla_3,cortex_r4_smlald"
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"cortex_r4_alu_shift_reg"
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"arm_no_early_alu_shift_value_dep")
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(define_bypass 3 "cortex_r4_mul_4,cortex_r4_mla_4,cortex_r4_mull"
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"cortex_r4_alu")
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(define_bypass 3 "cortex_r4_mul_4,cortex_r4_mla_4,cortex_r4_mull"
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"cortex_r4_alu_shift"
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"arm_no_early_alu_shift_dep")
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(define_bypass 3 "cortex_r4_mul_4,cortex_r4_mla_4,cortex_r4_mull"
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"cortex_r4_alu_shift_reg"
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"arm_no_early_alu_shift_value_dep")
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;; A multiply followed by a mov has one cycle lower latency again.
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(define_bypass 1 "cortex_r4_mul_3,cortex_r4_mla_3,cortex_r4_smlald"
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"cortex_r4_mov")
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(define_bypass 2 "cortex_r4_mul_4,cortex_r4_mla_4,cortex_r4_mull"
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"cortex_r4_mov")
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;; We guess that division of A/B using sdiv or udiv, on average,
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;; is performed with B having ten more leading zeros than A.
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;; This gives a latency of nine for udiv and ten for sdiv.
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(define_insn_reservation "cortex_r4_udiv" 9
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(and (eq_attr "tune_cortexr4" "yes")
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(eq_attr "insn" "udiv"))
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"cortex_r4_div_9")
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(define_insn_reservation "cortex_r4_sdiv" 10
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(and (eq_attr "tune_cortexr4" "yes")
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(eq_attr "insn" "sdiv"))
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"cortex_r4_div_10")
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;; Branches. We assume correct prediction.
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(define_insn_reservation "cortex_r4_branch" 0
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(and (eq_attr "tune_cortexr4" "yes")
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(eq_attr "type" "branch"))
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"cortex_r4_branch")
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;; Call latencies are not predictable. A semi-arbitrary very large
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;; number is used as "positive infinity" so that everything should be
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;; finished by the time of return.
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(define_insn_reservation "cortex_r4_call" 32
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(and (eq_attr "tune_cortexr4" "yes")
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(eq_attr "type" "call"))
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"nothing")
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;; Status register access instructions are not currently emitted.
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;; Load instructions.
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;; We do not model the "addr_md_3cycle" cases and assume that
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;; accesses following are correctly aligned.
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(define_insn_reservation "cortex_r4_load_1_2" 3
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(and (eq_attr "tune_cortexr4" "yes")
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(eq_attr "type" "load1,load2"))
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"cortex_r4_load_store")
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(define_insn_reservation "cortex_r4_load_3_4" 4
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(and (eq_attr "tune_cortexr4" "yes")
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(eq_attr "type" "load3,load4"))
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"cortex_r4_load_store_2")
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;; If a producing load is followed by an instruction consuming only
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;; as a Normal Reg, there is one fewer cycle of latency.
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(define_bypass 2 "cortex_r4_load_1_2"
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"cortex_r4_alu")
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(define_bypass 2 "cortex_r4_load_1_2"
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"cortex_r4_alu_shift"
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"arm_no_early_alu_shift_dep")
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(define_bypass 2 "cortex_r4_load_1_2"
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"cortex_r4_alu_shift_reg"
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"arm_no_early_alu_shift_value_dep")
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(define_bypass 3 "cortex_r4_load_3_4"
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"cortex_r4_alu")
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(define_bypass 3 "cortex_r4_load_3_4"
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"cortex_r4_alu_shift"
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"arm_no_early_alu_shift_dep")
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(define_bypass 3 "cortex_r4_load_3_4"
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"cortex_r4_alu_shift_reg"
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"arm_no_early_alu_shift_value_dep")
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;; If a producing load is followed by an instruction consuming only
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;; as a Late Reg, there are two fewer cycles of latency. Such consumer
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;; instructions are moves and stores.
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(define_bypass 1 "cortex_r4_load_1_2"
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"cortex_r4_mov,cortex_r4_store_1_2,cortex_r4_store_3_4")
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(define_bypass 2 "cortex_r4_load_3_4"
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"cortex_r4_mov,cortex_r4_store_1_2,cortex_r4_store_3_4")
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;; If a producer's result is required as the base or offset of a load,
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;; there is an extra cycle latency.
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(define_bypass 3 "cortex_r4_alu,cortex_r4_mov,cortex_r4_alu_shift,\
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cortex_r4_alu_shift_reg"
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"cortex_r4_load_1_2,cortex_r4_load_3_4")
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(define_bypass 4 "cortex_r4_mul_3,cortex_r4_mla_3,cortex_r4_smlald"
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"cortex_r4_load_1_2,cortex_r4_load_3_4")
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(define_bypass 5 "cortex_r4_mul_4,cortex_r4_mla_4,cortex_r4_mull"
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"cortex_r4_load_1_2,cortex_r4_load_3_4")
|
| 280 |
|
|
|
| 281 |
|
|
;; Store instructions.
|
| 282 |
|
|
|
| 283 |
|
|
(define_insn_reservation "cortex_r4_store_1_2" 0
|
| 284 |
|
|
(and (eq_attr "tune_cortexr4" "yes")
|
| 285 |
|
|
(eq_attr "type" "store1,store2"))
|
| 286 |
|
|
"cortex_r4_load_store")
|
| 287 |
|
|
|
| 288 |
|
|
(define_insn_reservation "cortex_r4_store_3_4" 0
|
| 289 |
|
|
(and (eq_attr "tune_cortexr4" "yes")
|
| 290 |
|
|
(eq_attr "type" "store3,store4"))
|
| 291 |
|
|
"cortex_r4_load_store_2")
|
| 292 |
|
|
|
