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jeremybenn |
;; Code and mode itertator and attribute definitions for the ARM backend
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;; Copyright (C) 2010 Free Software Foundation, Inc.
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;; Contributed by ARM Ltd.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; .
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;;----------------------------------------------------------------------------
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;; Mode iterators
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;;----------------------------------------------------------------------------
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;; A list of modes that are exactly 64 bits in size. This is used to expand
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;; some splits that are the same for all modes when operating on ARM
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;; registers.
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(define_mode_iterator ANY64 [DI DF V8QI V4HI V2SI V2SF])
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(define_mode_iterator ANY128 [V2DI V2DF V16QI V8HI V4SI V4SF])
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;; A list of integer modes that are up to one word long
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(define_mode_iterator QHSI [QI HI SI])
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;; A list of integer modes that are less than a word
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(define_mode_iterator NARROW [QI HI])
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;; A list of all the integer modes upto 64bit
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(define_mode_iterator QHSD [QI HI SI DI])
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;; A list of the 32bit and 64bit integer modes
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(define_mode_iterator SIDI [SI DI])
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;; Integer element sizes implemented by IWMMXT.
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(define_mode_iterator VMMX [V2SI V4HI V8QI])
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;; Integer element sizes for shifts.
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(define_mode_iterator VSHFT [V4HI V2SI DI])
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;; Integer and float modes supported by Neon and IWMMXT.
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(define_mode_iterator VALL [V2DI V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF])
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;; Integer and float modes supported by Neon and IWMMXT, except V2DI.
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(define_mode_iterator VALLW [V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF])
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;; Integer modes supported by Neon and IWMMXT
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(define_mode_iterator VINT [V2DI V2SI V4HI V8QI V4SI V8HI V16QI])
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;; Integer modes supported by Neon and IWMMXT, except V2DI
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(define_mode_iterator VINTW [V2SI V4HI V8QI V4SI V8HI V16QI])
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;; Double-width vector modes.
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(define_mode_iterator VD [V8QI V4HI V2SI V2SF])
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;; Double-width vector modes plus 64-bit elements.
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(define_mode_iterator VDX [V8QI V4HI V2SI V2SF DI])
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;; Double-width vector modes without floating-point elements.
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(define_mode_iterator VDI [V8QI V4HI V2SI])
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;; Quad-width vector modes.
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(define_mode_iterator VQ [V16QI V8HI V4SI V4SF])
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;; Quad-width vector modes plus 64-bit elements.
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(define_mode_iterator VQX [V16QI V8HI V4SI V4SF V2DI])
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;; Quad-width vector modes without floating-point elements.
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(define_mode_iterator VQI [V16QI V8HI V4SI])
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;; Quad-width vector modes, with TImode added, for moves.
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(define_mode_iterator VQXMOV [V16QI V8HI V4SI V4SF V2DI TI])
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;; Opaque structure types wider than TImode.
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(define_mode_iterator VSTRUCT [EI OI CI XI])
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;; Opaque structure types used in table lookups (except vtbl1/vtbx1).
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(define_mode_iterator VTAB [TI EI OI])
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;; Widenable modes.
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(define_mode_iterator VW [V8QI V4HI V2SI])
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;; Narrowable modes.
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(define_mode_iterator VN [V8HI V4SI V2DI])
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;; All supported vector modes (except singleton DImode).
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(define_mode_iterator VDQ [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DI])
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;; All supported vector modes (except those with 64-bit integer elements).
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(define_mode_iterator VDQW [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF])
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;; Supported integer vector modes (not 64 bit elements).
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(define_mode_iterator VDQIW [V8QI V16QI V4HI V8HI V2SI V4SI])
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;; Supported integer vector modes (not singleton DI)
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(define_mode_iterator VDQI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI])
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;; Vector modes, including 64-bit integer elements.
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(define_mode_iterator VDQX [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF DI V2DI])
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;; Vector modes including 64-bit integer elements, but no floats.
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(define_mode_iterator VDQIX [V8QI V16QI V4HI V8HI V2SI V4SI DI V2DI])
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;; Vector modes for float->int conversions.
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(define_mode_iterator VCVTF [V2SF V4SF])
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;; Vector modes form int->float conversions.
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(define_mode_iterator VCVTI [V2SI V4SI])
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;; Vector modes for doubleword multiply-accumulate, etc. insns.
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(define_mode_iterator VMD [V4HI V2SI V2SF])
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;; Vector modes for quadword multiply-accumulate, etc. insns.
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(define_mode_iterator VMQ [V8HI V4SI V4SF])
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;; Above modes combined.
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(define_mode_iterator VMDQ [V4HI V2SI V2SF V8HI V4SI V4SF])
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;; As VMD, but integer modes only.
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(define_mode_iterator VMDI [V4HI V2SI])
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;; As VMQ, but integer modes only.
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(define_mode_iterator VMQI [V8HI V4SI])
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;; Above modes combined.
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(define_mode_iterator VMDQI [V4HI V2SI V8HI V4SI])
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;; Modes with 8-bit and 16-bit elements.
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(define_mode_iterator VX [V8QI V4HI V16QI V8HI])
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;; Modes with 8-bit elements.
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(define_mode_iterator VE [V8QI V16QI])
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;; Modes with 64-bit elements only.
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(define_mode_iterator V64 [DI V2DI])
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;; Modes with 32-bit elements only.
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(define_mode_iterator V32 [V2SI V2SF V4SI V4SF])
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;; Modes with 8-bit, 16-bit and 32-bit elements.
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(define_mode_iterator VU [V16QI V8HI V4SI])
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;; Iterators used for fixed-point support.
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(define_mode_iterator FIXED [QQ HQ SQ UQQ UHQ USQ HA SA UHA USA])
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(define_mode_iterator ADDSUB [V4QQ V2HQ V2HA])
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(define_mode_iterator UQADDSUB [V4UQQ V2UHQ UQQ UHQ V2UHA UHA])
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(define_mode_iterator QADDSUB [V4QQ V2HQ QQ HQ V2HA HA SQ SA])
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(define_mode_iterator QMUL [HQ HA])
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;;----------------------------------------------------------------------------
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;; Code iterators
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;;----------------------------------------------------------------------------
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;; A list of condition codes used in compare instructions where
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;; the carry flag from the addition is used instead of doing the
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;; compare a second time.
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(define_code_iterator LTUGEU [ltu geu])
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;; A list of ...
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(define_code_iterator ior_xor [ior xor])
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;; Operations on two halves of a quadword vector.
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(define_code_iterator vqh_ops [plus smin smax umin umax])
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;; Operations on two halves of a quadword vector,
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;; without unsigned variants (for use with *SFmode pattern).
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(define_code_iterator vqhs_ops [plus smin smax])
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;; A list of widening operators
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(define_code_iterator SE [sign_extend zero_extend])
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;;----------------------------------------------------------------------------
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;; Mode attributes
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;;----------------------------------------------------------------------------
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;; Determine element size suffix from vector mode.
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(define_mode_attr MMX_char [(V8QI "b") (V4HI "h") (V2SI "w") (DI "d")])
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;; vtbl suffix for NEON vector modes.
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(define_mode_attr VTAB_n [(TI "2") (EI "3") (OI "4")])
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;; (Opposite) mode to convert to/from for NEON mode conversions.
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(define_mode_attr V_CVTTO [(V2SI "V2SF") (V2SF "V2SI")
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(V4SI "V4SF") (V4SF "V4SI")])
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;; As above but in lower case.
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(define_mode_attr V_cvtto [(V2SI "v2sf") (V2SF "v2si")
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(V4SI "v4sf") (V4SF "v4si")])
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;; Define element mode for each vector mode.
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(define_mode_attr V_elem [(V8QI "QI") (V16QI "QI")
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(V4HI "HI") (V8HI "HI")
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(V2SI "SI") (V4SI "SI")
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(V2SF "SF") (V4SF "SF")
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(DI "DI") (V2DI "DI")])
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;; Element modes for vector extraction, padded up to register size.
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(define_mode_attr V_ext [(V8QI "SI") (V16QI "SI")
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(V4HI "SI") (V8HI "SI")
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(V2SI "SI") (V4SI "SI")
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(V2SF "SF") (V4SF "SF")
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(DI "DI") (V2DI "DI")])
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;; Mode of pair of elements for each vector mode, to define transfer
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;; size for structure lane/dup loads and stores.
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(define_mode_attr V_two_elem [(V8QI "HI") (V16QI "HI")
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(V4HI "SI") (V8HI "SI")
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(V2SI "V2SI") (V4SI "V2SI")
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(V2SF "V2SF") (V4SF "V2SF")
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(DI "V2DI") (V2DI "V2DI")])
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;; Similar, for three elements.
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(define_mode_attr V_three_elem [(V8QI "BLK") (V16QI "BLK")
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(V4HI "BLK") (V8HI "BLK")
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(V2SI "BLK") (V4SI "BLK")
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(V2SF "BLK") (V4SF "BLK")
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(DI "EI") (V2DI "EI")])
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;; Similar, for four elements.
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(define_mode_attr V_four_elem [(V8QI "SI") (V16QI "SI")
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(V4HI "V4HI") (V8HI "V4HI")
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(V2SI "V4SI") (V4SI "V4SI")
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(V2SF "V4SF") (V4SF "V4SF")
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(DI "OI") (V2DI "OI")])
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;; Register width from element mode
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(define_mode_attr V_reg [(V8QI "P") (V16QI "q")
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(V4HI "P") (V8HI "q")
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(V2SI "P") (V4SI "q")
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(V2SF "P") (V4SF "q")
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(DI "P") (V2DI "q")])
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;; Wider modes with the same number of elements.
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(define_mode_attr V_widen [(V8QI "V8HI") (V4HI "V4SI") (V2SI "V2DI")])
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;; Narrower modes with the same number of elements.
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(define_mode_attr V_narrow [(V8HI "V8QI") (V4SI "V4HI") (V2DI "V2SI")])
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;; Narrower modes with double the number of elements.
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(define_mode_attr V_narrow_pack [(V4SI "V8HI") (V8HI "V16QI") (V2DI "V4SI")
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(V4HI "V8QI") (V2SI "V4HI") (DI "V2SI")])
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;; Modes with half the number of equal-sized elements.
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(define_mode_attr V_HALF [(V16QI "V8QI") (V8HI "V4HI")
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(V4SI "V2SI") (V4SF "V2SF") (V2DF "DF")
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(V2DI "DI")])
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;; Same, but lower-case.
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(define_mode_attr V_half [(V16QI "v8qi") (V8HI "v4hi")
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(V4SI "v2si") (V4SF "v2sf")
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(V2DI "di")])
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;; Modes with twice the number of equal-sized elements.
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(define_mode_attr V_DOUBLE [(V8QI "V16QI") (V4HI "V8HI")
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(V2SI "V4SI") (V2SF "V4SF") (DF "V2DF")
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(DI "V2DI")])
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;; Same, but lower-case.
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(define_mode_attr V_double [(V8QI "v16qi") (V4HI "v8hi")
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(V2SI "v4si") (V2SF "v4sf")
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(DI "v2di")])
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;; Modes with double-width elements.
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(define_mode_attr V_double_width [(V8QI "V4HI") (V16QI "V8HI")
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(V4HI "V2SI") (V8HI "V4SI")
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(V2SI "DI") (V4SI "V2DI")])
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;; Double-sized modes with the same element size.
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;; Used for neon_vdup_lane, where the second operand is double-sized
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;; even when the first one is quad.
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(define_mode_attr V_double_vector_mode [(V16QI "V8QI") (V8HI "V4HI")
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(V4SI "V2SI") (V4SF "V2SF")
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(V8QI "V8QI") (V4HI "V4HI")
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(V2SI "V2SI") (V2SF "V2SF")])
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;; Mode of result of comparison operations (and bit-select operand 1).
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(define_mode_attr V_cmp_result [(V8QI "V8QI") (V16QI "V16QI")
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(V4HI "V4HI") (V8HI "V8HI")
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(V2SI "V2SI") (V4SI "V4SI")
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(V2SF "V2SI") (V4SF "V4SI")
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(DI "DI") (V2DI "V2DI")])
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;; Get element type from double-width mode, for operations where we
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;; don't care about signedness.
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(define_mode_attr V_if_elem [(V8QI "i8") (V16QI "i8")
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| 301 |
|
|
(V4HI "i16") (V8HI "i16")
|
| 302 |
|
|
(V2SI "i32") (V4SI "i32")
|
| 303 |
|
|
(DI "i64") (V2DI "i64")
|
| 304 |
|
|
(V2SF "f32") (V4SF "f32")])
|
| 305 |
|
|
|
| 306 |
|
|
;; Same, but for operations which work on signed values.
|
| 307 |
|
|
(define_mode_attr V_s_elem [(V8QI "s8") (V16QI "s8")
|
| 308 |
|
|
(V4HI "s16") (V8HI "s16")
|
| 309 |
|
|
(V2SI "s32") (V4SI "s32")
|
| 310 |
|
|
(DI "s64") (V2DI "s64")
|
| 311 |
|
|
(V2SF "f32") (V4SF "f32")])
|
| 312 |
|
|
|
| 313 |
|
|
;; Same, but for operations which work on unsigned values.
|
| 314 |
|
|
(define_mode_attr V_u_elem [(V8QI "u8") (V16QI "u8")
|
| 315 |
|
|
(V4HI "u16") (V8HI "u16")
|
| 316 |
|
|
(V2SI "u32") (V4SI "u32")
|
| 317 |
|
|
(DI "u64") (V2DI "u64")
|
| 318 |
|
|
(V2SF "f32") (V4SF "f32")])
|
| 319 |
|
|
|
| 320 |
|
|
;; Element types for extraction of unsigned scalars.
|
| 321 |
|
|
(define_mode_attr V_uf_sclr [(V8QI "u8") (V16QI "u8")
|
| 322 |
|
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(V4HI "u16") (V8HI "u16")
|
| 323 |
|
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(V2SI "32") (V4SI "32")
|
| 324 |
|
|
(V2SF "32") (V4SF "32")])
|
| 325 |
|
|
|
| 326 |
|
|
(define_mode_attr V_sz_elem [(V8QI "8") (V16QI "8")
|
| 327 |
|
|
(V4HI "16") (V8HI "16")
|
| 328 |
|
|
(V2SI "32") (V4SI "32")
|
| 329 |
|
|
(DI "64") (V2DI "64")
|
| 330 |
|
|
(V2SF "32") (V4SF "32")])
|
| 331 |
|
|
|
| 332 |
|
|
;; Element sizes for duplicating ARM registers to all elements of a vector.
|
| 333 |
|
|
(define_mode_attr VD_dup [(V8QI "8") (V4HI "16") (V2SI "32") (V2SF "32")])
|
| 334 |
|
|
|
| 335 |
|
|
;; Opaque integer types for results of pair-forming intrinsics (vtrn, etc.)
|
| 336 |
|
|
(define_mode_attr V_PAIR [(V8QI "TI") (V16QI "OI")
|
| 337 |
|
|
(V4HI "TI") (V8HI "OI")
|
| 338 |
|
|
(V2SI "TI") (V4SI "OI")
|
| 339 |
|
|
(V2SF "TI") (V4SF "OI")
|
| 340 |
|
|
(DI "TI") (V2DI "OI")])
|
| 341 |
|
|
|
| 342 |
|
|
;; Same, but lower-case.
|
| 343 |
|
|
(define_mode_attr V_pair [(V8QI "ti") (V16QI "oi")
|
| 344 |
|
|
(V4HI "ti") (V8HI "oi")
|
| 345 |
|
|
(V2SI "ti") (V4SI "oi")
|
| 346 |
|
|
(V2SF "ti") (V4SF "oi")
|
| 347 |
|
|
(DI "ti") (V2DI "oi")])
|
| 348 |
|
|
|
| 349 |
|
|
;; Extra suffix on some 64-bit insn names (to avoid collision with standard
|
| 350 |
|
|
;; names which we don't want to define).
|
| 351 |
|
|
(define_mode_attr V_suf64 [(V8QI "") (V16QI "")
|
| 352 |
|
|
(V4HI "") (V8HI "")
|
| 353 |
|
|
(V2SI "") (V4SI "")
|
| 354 |
|
|
(V2SF "") (V4SF "")
|
| 355 |
|
|
(DI "_neon") (V2DI "")])
|
| 356 |
|
|
|
| 357 |
|
|
|
| 358 |
|
|
;; Scalars to be presented to scalar multiplication instructions
|
| 359 |
|
|
;; must satisfy the following constraints.
|
| 360 |
|
|
;; 1. If the mode specifies 16-bit elements, the scalar must be in D0-D7.
|
| 361 |
|
|
;; 2. If the mode specifies 32-bit elements, the scalar must be in D0-D15.
|
| 362 |
|
|
|
| 363 |
|
|
;; This mode attribute is used to obtain the correct register constraints.
|
| 364 |
|
|
|
| 365 |
|
|
(define_mode_attr scalar_mul_constraint [(V4HI "x") (V2SI "t") (V2SF "t")
|
| 366 |
|
|
(V8HI "x") (V4SI "t") (V4SF "t")])
|
| 367 |
|
|
|
| 368 |
|
|
;; Predicates used for setting neon_type
|
| 369 |
|
|
|
| 370 |
|
|
(define_mode_attr Is_float_mode [(V8QI "false") (V16QI "false")
|
| 371 |
|
|
(V4HI "false") (V8HI "false")
|
| 372 |
|
|
(V2SI "false") (V4SI "false")
|
| 373 |
|
|
(V2SF "true") (V4SF "true")
|
| 374 |
|
|
(DI "false") (V2DI "false")])
|
| 375 |
|
|
|
| 376 |
|
|
(define_mode_attr Scalar_mul_8_16 [(V8QI "true") (V16QI "true")
|
| 377 |
|
|
(V4HI "true") (V8HI "true")
|
| 378 |
|
|
(V2SI "false") (V4SI "false")
|
| 379 |
|
|
(V2SF "false") (V4SF "false")
|
| 380 |
|
|
(DI "false") (V2DI "false")])
|
| 381 |
|
|
|
| 382 |
|
|
|
| 383 |
|
|
(define_mode_attr Is_d_reg [(V8QI "true") (V16QI "false")
|
| 384 |
|
|
(V4HI "true") (V8HI "false")
|
| 385 |
|
|
(V2SI "true") (V4SI "false")
|
| 386 |
|
|
(V2SF "true") (V4SF "false")
|
| 387 |
|
|
(DI "true") (V2DI "false")])
|
| 388 |
|
|
|
| 389 |
|
|
(define_mode_attr V_mode_nunits [(V8QI "8") (V16QI "16")
|
| 390 |
|
|
(V4HI "4") (V8HI "8")
|
| 391 |
|
|
(V2SI "2") (V4SI "4")
|
| 392 |
|
|
(V2SF "2") (V4SF "4")
|
| 393 |
|
|
(DI "1") (V2DI "2")
|
| 394 |
|
|
(DF "1") (V2DF "2")])
|
| 395 |
|
|
|
| 396 |
|
|
;; Same as V_widen, but lower-case.
|
| 397 |
|
|
(define_mode_attr V_widen_l [(V8QI "v8hi") (V4HI "v4si") ( V2SI "v2di")])
|
| 398 |
|
|
|
| 399 |
|
|
;; Widen. Result is half the number of elements, but widened to double-width.
|
| 400 |
|
|
(define_mode_attr V_unpack [(V16QI "V8HI") (V8HI "V4SI") (V4SI "V2DI")])
|
| 401 |
|
|
|
| 402 |
|
|
;; Conditions to be used in extenddi patterns.
|
| 403 |
|
|
(define_mode_attr qhs_zextenddi_cond [(SI "") (HI "&& arm_arch6") (QI "")])
|
| 404 |
|
|
(define_mode_attr qhs_sextenddi_cond [(SI "") (HI "&& arm_arch6")
|
| 405 |
|
|
(QI "&& arm_arch6")])
|
| 406 |
|
|
(define_mode_attr qhs_zextenddi_op [(SI "s_register_operand")
|
| 407 |
|
|
(HI "nonimmediate_operand")
|
| 408 |
|
|
(QI "nonimmediate_operand")])
|
| 409 |
|
|
(define_mode_attr qhs_extenddi_op [(SI "s_register_operand")
|
| 410 |
|
|
(HI "nonimmediate_operand")
|
| 411 |
|
|
(QI "arm_reg_or_extendqisi_mem_op")])
|
| 412 |
|
|
(define_mode_attr qhs_extenddi_cstr [(SI "r") (HI "rm") (QI "rUq")])
|
| 413 |
|
|
(define_mode_attr qhs_zextenddi_cstr [(SI "r") (HI "rm") (QI "rm")])
|
| 414 |
|
|
|
| 415 |
|
|
;; Mode attributes used for fixed-point support.
|
| 416 |
|
|
(define_mode_attr qaddsub_suf [(V4UQQ "8") (V2UHQ "16") (UQQ "8") (UHQ "16")
|
| 417 |
|
|
(V2UHA "16") (UHA "16")
|
| 418 |
|
|
(V4QQ "8") (V2HQ "16") (QQ "8") (HQ "16")
|
| 419 |
|
|
(V2HA "16") (HA "16") (SQ "") (SA "")])
|
| 420 |
|
|
|
| 421 |
|
|
;; Mode attribute for vshll.
|
| 422 |
|
|
(define_mode_attr V_innermode [(V8QI "QI") (V4HI "HI") (V2SI "SI")])
|
| 423 |
|
|
|
| 424 |
|
|
;;----------------------------------------------------------------------------
|
| 425 |
|
|
;; Code attributes
|
| 426 |
|
|
;;----------------------------------------------------------------------------
|
| 427 |
|
|
|
| 428 |
|
|
;; Assembler mnemonics for vqh_ops and vqhs_ops iterators.
|
| 429 |
|
|
(define_code_attr VQH_mnem [(plus "vadd") (smin "vmin") (smax "vmax")
|
| 430 |
|
|
(umin "vmin") (umax "vmax")])
|
| 431 |
|
|
|
| 432 |
|
|
;; Signs of above, where relevant.
|
| 433 |
|
|
(define_code_attr VQH_sign [(plus "i") (smin "s") (smax "s") (umin "u")
|
| 434 |
|
|
(umax "u")])
|
| 435 |
|
|
|
| 436 |
|
|
(define_code_attr cnb [(ltu "CC_C") (geu "CC")])
|
| 437 |
|
|
(define_code_attr optab [(ltu "ltu") (geu "geu")])
|
| 438 |
|
|
|
| 439 |
|
|
;; Assembler mnemonics for signedness of widening operations.
|
| 440 |
|
|
(define_code_attr US [(sign_extend "s") (zero_extend "u")])
|
