OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [config/] [arm/] [iwmmxt.md] - Blame information for rev 720

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 709 jeremybenn 
;; ??? This file needs auditing for thumb2
2 
;; Patterns for the Intel Wireless MMX technology architecture.
3 
;; Copyright (C) 2003, 2004, 2005, 2007, 2008, 2010
4 
;; Free Software Foundation, Inc.
5 
;; Contributed by Red Hat.
6 
 
7 
;; This file is part of GCC.
8 
 
9 
;; GCC is free software; you can redistribute it and/or modify it under
10 
;; the terms of the GNU General Public License as published by the Free
11 
;; Software Foundation; either version 3, or (at your option) any later
12 
;; version.
13 
 
14 
;; GCC is distributed in the hope that it will be useful, but WITHOUT
15 
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 
;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
17 
;; License for more details.
18 
 
19 
;; You should have received a copy of the GNU General Public License
20 
;; along with GCC; see the file COPYING3.  If not see
21 
;; .
22 
 
23 
 
24 
(define_insn "iwmmxt_iordi3"
25 
  [(set (match_operand:DI         0 "register_operand" "=y,?&r,?&r")
26 
        (ior:DI (match_operand:DI 1 "register_operand" "%y,0,r")
27 
                (match_operand:DI 2 "register_operand"  "y,r,r")))]
28 
  "TARGET_REALLY_IWMMXT"
29 
  "@
30 
   wor%?\\t%0, %1, %2
31 
   #
32 
   #"
33 
  [(set_attr "predicable" "yes")
34 
   (set_attr "length" "4,8,8")])
35 
 
36 
(define_insn "iwmmxt_xordi3"
37 
  [(set (match_operand:DI         0 "register_operand" "=y,?&r,?&r")
38 
        (xor:DI (match_operand:DI 1 "register_operand" "%y,0,r")
39 
                (match_operand:DI 2 "register_operand"  "y,r,r")))]
40 
  "TARGET_REALLY_IWMMXT"
41 
  "@
42 
   wxor%?\\t%0, %1, %2
43 
   #
44 
   #"
45 
  [(set_attr "predicable" "yes")
46 
   (set_attr "length" "4,8,8")])
47 
 
48 
(define_insn "iwmmxt_anddi3"
49 
  [(set (match_operand:DI         0 "register_operand" "=y,?&r,?&r")
50 
        (and:DI (match_operand:DI 1 "register_operand" "%y,0,r")
51 
                (match_operand:DI 2 "register_operand"  "y,r,r")))]
52 
  "TARGET_REALLY_IWMMXT"
53 
  "@
54 
   wand%?\\t%0, %1, %2
55 
   #
56 
   #"
57 
  [(set_attr "predicable" "yes")
58 
   (set_attr "length" "4,8,8")])
59 
 
60 
(define_insn "iwmmxt_nanddi3"
61 
  [(set (match_operand:DI                 0 "register_operand" "=y")
62 
        (and:DI (match_operand:DI         1 "register_operand"  "y")
63 
                (not:DI (match_operand:DI 2 "register_operand"  "y"))))]
64 
  "TARGET_REALLY_IWMMXT"
65 
  "wandn%?\\t%0, %1, %2"
66 
  [(set_attr "predicable" "yes")])
67 
 
68 
(define_insn "*iwmmxt_arm_movdi"
69 
  [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, m,y,y,yr,y,yrUy")
70 
        (match_operand:DI 1 "di_operand"              "rIK,mi,r,y,yr,y,yrUy,y"))]
71 
  "TARGET_REALLY_IWMMXT
72 
   && (   register_operand (operands[0], DImode)
73 
       || register_operand (operands[1], DImode))"
74 
  "*
75 
{
76 
  switch (which_alternative)
77 
    {
78 
    default:
79 
      return output_move_double (operands, true, NULL);
80 
    case 0:
81 
      return \"#\";
82 
    case 3:
83 
      return \"wmov%?\\t%0,%1\";
84 
    case 4:
85 
      return \"tmcrr%?\\t%0,%Q1,%R1\";
86 
    case 5:
87 
      return \"tmrrc%?\\t%Q0,%R0,%1\";
88 
    case 6:
89 
      return \"wldrd%?\\t%0,%1\";
90 
    case 7:
91 
      return \"wstrd%?\\t%1,%0\";
92 
    }
93 
}"
94 
  [(set_attr "length"         "8,8,8,4,4,4,4,4")
95 
   (set_attr "type"           "*,load1,store2,*,*,*,*,*")
96 
   (set_attr "pool_range"     "*,1020,*,*,*,*,*,*")
97 
   (set_attr "neg_pool_range" "*,1012,*,*,*,*,*,*")]
98 
)
99 
 
100 
(define_insn "*iwmmxt_movsi_insn"
101 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,rk, m,z,r,?z,Uy,z")
102 
        (match_operand:SI 1 "general_operand"      "rk, I,K,mi,rk,r,z,Uy,z, z"))]
103 
  "TARGET_REALLY_IWMMXT
104 
   && (   register_operand (operands[0], SImode)
105 
       || register_operand (operands[1], SImode))"
106 
  "*
107 
   switch (which_alternative)
108 
   {
109 
   case 0: return \"mov\\t%0, %1\";
110 
   case 1: return \"mov\\t%0, %1\";
111 
   case 2: return \"mvn\\t%0, #%B1\";
112 
   case 3: return \"ldr\\t%0, %1\";
113 
   case 4: return \"str\\t%1, %0\";
114 
   case 5: return \"tmcr\\t%0, %1\";
115 
   case 6: return \"tmrc\\t%0, %1\";
116 
   case 7: return arm_output_load_gr (operands);
117 
   case 8: return \"wstrw\\t%1, %0\";
118 
   default:return \"wstrw\\t%1, [sp, #-4]!\;wldrw\\t%0, [sp], #4\\t@move CG reg\";
119 
  }"
120 
  [(set_attr "type"           "*,*,*,load1,store1,*,*,load1,store1,*")
121 
   (set_attr "length"         "*,*,*,*,        *,*,*,  16,     *,8")
122 
   (set_attr "pool_range"     "*,*,*,4096,     *,*,*,1024,     *,*")
123 
   (set_attr "neg_pool_range" "*,*,*,4084,     *,*,*,   *,  1012,*")
124 
   ;; Note - the "predicable" attribute is not allowed to have alternatives.
125 
   ;; Since the wSTRw wCx instruction is not predicable, we cannot support
126 
   ;; predicating any of the alternatives in this template.  Instead,
127 
   ;; we do the predication ourselves, in cond_iwmmxt_movsi_insn.
128 
   (set_attr "predicable"     "no")
129 
   ;; Also - we have to pretend that these insns clobber the condition code
130 
   ;; bits as otherwise arm_final_prescan_insn() will try to conditionalize
131 
   ;; them.
132 
   (set_attr "conds" "clob")]
133 
)
134 
 
135 
;; Because iwmmxt_movsi_insn is not predicable, we provide the
136 
;; cond_exec version explicitly, with appropriate constraints.
137 
 
138 
(define_insn "*cond_iwmmxt_movsi_insn"
139 
  [(cond_exec
140 
     (match_operator 2 "arm_comparison_operator"
141 
      [(match_operand 3 "cc_register" "")
142 
      (const_int 0)])
143 
     (set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r, m,z,r")
144 
          (match_operand:SI 1 "general_operand"      "rI,K,mi,r,r,z")))]
145 
  "TARGET_REALLY_IWMMXT
146 
   && (   register_operand (operands[0], SImode)
147 
       || register_operand (operands[1], SImode))"
148 
  "*
149 
   switch (which_alternative)
150 
   {
151 
   case 0: return \"mov%?\\t%0, %1\";
152 
   case 1: return \"mvn%?\\t%0, #%B1\";
153 
   case 2: return \"ldr%?\\t%0, %1\";
154 
   case 3: return \"str%?\\t%1, %0\";
155 
   case 4: return \"tmcr%?\\t%0, %1\";
156 
   default: return \"tmrc%?\\t%0, %1\";
157 
  }"
158 
  [(set_attr "type"           "*,*,load1,store1,*,*")
159 
   (set_attr "pool_range"     "*,*,4096,     *,*,*")
160 
   (set_attr "neg_pool_range" "*,*,4084,     *,*,*")]
161 
)
162 
 
163 
(define_insn "mov_internal"
164 
  [(set (match_operand:VMMX 0 "nonimmediate_operand" "=y,m,y,?r,?y,?r,?r,?m")
165 
        (match_operand:VMMX 1 "general_operand"       "y,y,mi,y,r,r,mi,r"))]
166 
  "TARGET_REALLY_IWMMXT"
167 
  "*
168 
   switch (which_alternative)
169 
   {
170 
   case 0: return \"wmov%?\\t%0, %1\";
171 
   case 1: return \"wstrd%?\\t%1, %0\";
172 
   case 2: return \"wldrd%?\\t%0, %1\";
173 
   case 3: return \"tmrrc%?\\t%Q0, %R0, %1\";
174 
   case 4: return \"tmcrr%?\\t%0, %Q1, %R1\";
175 
   case 5: return \"#\";
176 
   default: return output_move_double (operands, true, NULL);
177 
   }"
178 
  [(set_attr "predicable" "yes")
179 
   (set_attr "length"         "4,     4,   4,4,4,8,   8,8")
180 
   (set_attr "type"           "*,store1,load1,*,*,*,load1,store1")
181 
   (set_attr "pool_range"     "*,     *, 256,*,*,*, 256,*")
182 
   (set_attr "neg_pool_range" "*,     *, 244,*,*,*, 244,*")])
183 
 
184 
;; Vector add/subtract
185 
 
186 
(define_insn "*add3_iwmmxt"
187 
  [(set (match_operand:VMMX            0 "register_operand" "=y")
188 
        (plus:VMMX (match_operand:VMMX 1 "register_operand"  "y")
189 
                   (match_operand:VMMX 2 "register_operand"  "y")))]
190 
  "TARGET_REALLY_IWMMXT"
191 
  "wadd%?\\t%0, %1, %2"
192 
  [(set_attr "predicable" "yes")])
193 
 
194 
(define_insn "ssaddv8qi3"
195 
  [(set (match_operand:V8QI               0 "register_operand" "=y")
196 
        (ss_plus:V8QI (match_operand:V8QI 1 "register_operand"  "y")
197 
                      (match_operand:V8QI 2 "register_operand"  "y")))]
198 
  "TARGET_REALLY_IWMMXT"
199 
  "waddbss%?\\t%0, %1, %2"
200 
  [(set_attr "predicable" "yes")])
201 
 
202 
(define_insn "ssaddv4hi3"
203 
  [(set (match_operand:V4HI               0 "register_operand" "=y")
204 
        (ss_plus:V4HI (match_operand:V4HI 1 "register_operand"  "y")
205 
                      (match_operand:V4HI 2 "register_operand"  "y")))]
206 
  "TARGET_REALLY_IWMMXT"
207 
  "waddhss%?\\t%0, %1, %2"
208 
  [(set_attr "predicable" "yes")])
209 
 
210 
(define_insn "ssaddv2si3"
211 
  [(set (match_operand:V2SI               0 "register_operand" "=y")
212 
        (ss_plus:V2SI (match_operand:V2SI 1 "register_operand"  "y")
213 
                      (match_operand:V2SI 2 "register_operand"  "y")))]
214 
  "TARGET_REALLY_IWMMXT"
215 
  "waddwss%?\\t%0, %1, %2"
216 
  [(set_attr "predicable" "yes")])
217 
 
218 
(define_insn "usaddv8qi3"
219 
  [(set (match_operand:V8QI               0 "register_operand" "=y")
220 
        (us_plus:V8QI (match_operand:V8QI 1 "register_operand"  "y")
221 
                      (match_operand:V8QI 2 "register_operand"  "y")))]
222 
  "TARGET_REALLY_IWMMXT"
223 
  "waddbus%?\\t%0, %1, %2"
224 
  [(set_attr "predicable" "yes")])
225 
 
226 
(define_insn "usaddv4hi3"
227 
  [(set (match_operand:V4HI               0 "register_operand" "=y")
228 
        (us_plus:V4HI (match_operand:V4HI 1 "register_operand"  "y")
229 
                      (match_operand:V4HI 2 "register_operand"  "y")))]
230 
  "TARGET_REALLY_IWMMXT"
231 
  "waddhus%?\\t%0, %1, %2"
232 
  [(set_attr "predicable" "yes")])
233 
 
234 
(define_insn "usaddv2si3"
235 
  [(set (match_operand:V2SI               0 "register_operand" "=y")
236 
        (us_plus:V2SI (match_operand:V2SI 1 "register_operand"  "y")
237 
                      (match_operand:V2SI 2 "register_operand"  "y")))]
238 
  "TARGET_REALLY_IWMMXT"
239 
  "waddwus%?\\t%0, %1, %2"
240 
  [(set_attr "predicable" "yes")])
241 
 
242 
(define_insn "*sub3_iwmmxt"
243 
  [(set (match_operand:VMMX             0 "register_operand" "=y")
244 
        (minus:VMMX (match_operand:VMMX 1 "register_operand"  "y")
245 
                    (match_operand:VMMX 2 "register_operand"  "y")))]
246 
  "TARGET_REALLY_IWMMXT"
247 
  "wsub%?\\t%0, %1, %2"
248 
  [(set_attr "predicable" "yes")])
249 
 
250 
(define_insn "sssubv8qi3"
251 
  [(set (match_operand:V8QI                0 "register_operand" "=y")
252 
        (ss_minus:V8QI (match_operand:V8QI 1 "register_operand"  "y")
253 
                       (match_operand:V8QI 2 "register_operand"  "y")))]
254 
  "TARGET_REALLY_IWMMXT"
255 
  "wsubbss%?\\t%0, %1, %2"
256 
  [(set_attr "predicable" "yes")])
257 
 
258 
(define_insn "sssubv4hi3"
259 
  [(set (match_operand:V4HI                0 "register_operand" "=y")
260 
        (ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "y")
261 
                       (match_operand:V4HI 2 "register_operand" "y")))]
262 
  "TARGET_REALLY_IWMMXT"
263 
  "wsubhss%?\\t%0, %1, %2"
264 
  [(set_attr "predicable" "yes")])
265 
 
266 
(define_insn "sssubv2si3"
267 
  [(set (match_operand:V2SI                0 "register_operand" "=y")
268 
        (ss_minus:V2SI (match_operand:V2SI 1 "register_operand" "y")
269 
                       (match_operand:V2SI 2 "register_operand" "y")))]
270 
  "TARGET_REALLY_IWMMXT"
271 
  "wsubwss%?\\t%0, %1, %2"
272 
  [(set_attr "predicable" "yes")])
273 
 
274 
(define_insn "ussubv8qi3"
275 
  [(set (match_operand:V8QI                0 "register_operand" "=y")
276 
        (us_minus:V8QI (match_operand:V8QI 1 "register_operand" "y")
277 
                       (match_operand:V8QI 2 "register_operand" "y")))]
278 
  "TARGET_REALLY_IWMMXT"
279 
  "wsubbus%?\\t%0, %1, %2"
280 
  [(set_attr "predicable" "yes")])
281 
 
282 
(define_insn "ussubv4hi3"
283 
  [(set (match_operand:V4HI                0 "register_operand" "=y")
284 
        (us_minus:V4HI (match_operand:V4HI 1 "register_operand" "y")
285 
                       (match_operand:V4HI 2 "register_operand" "y")))]
286 
  "TARGET_REALLY_IWMMXT"
287 
  "wsubhus%?\\t%0, %1, %2"
288 
  [(set_attr "predicable" "yes")])
289 
 
290 
(define_insn "ussubv2si3"
291 
  [(set (match_operand:V2SI                0 "register_operand" "=y")
292 
        (us_minus:V2SI (match_operand:V2SI 1 "register_operand" "y")
293 
                       (match_operand:V2SI 2 "register_operand" "y")))]
294 
  "TARGET_REALLY_IWMMXT"
295 
  "wsubwus%?\\t%0, %1, %2"
296 
  [(set_attr "predicable" "yes")])
297 
 
298 
(define_insn "*mulv4hi3_iwmmxt"
299 
  [(set (match_operand:V4HI            0 "register_operand" "=y")
300 
        (mult:V4HI (match_operand:V4HI 1 "register_operand" "y")
301 
                   (match_operand:V4HI 2 "register_operand" "y")))]
302 
  "TARGET_REALLY_IWMMXT"
303 
  "wmulul%?\\t%0, %1, %2"
304 
  [(set_attr "predicable" "yes")])
305 
 
306 
(define_insn "smulv4hi3_highpart"
307 
  [(set (match_operand:V4HI                                0 "register_operand" "=y")
308 
        (truncate:V4HI
309 
         (lshiftrt:V4SI
310 
          (mult:V4SI (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
311 
                     (sign_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")))
312 
          (const_int 16))))]
313 
  "TARGET_REALLY_IWMMXT"
314 
  "wmulsm%?\\t%0, %1, %2"
315 
  [(set_attr "predicable" "yes")])
316 
 
317 
(define_insn "umulv4hi3_highpart"
318 
  [(set (match_operand:V4HI                                0 "register_operand" "=y")
319 
        (truncate:V4HI
320 
         (lshiftrt:V4SI
321 
          (mult:V4SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
322 
                     (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")))
323 
          (const_int 16))))]
324 
  "TARGET_REALLY_IWMMXT"
325 
  "wmulum%?\\t%0, %1, %2"
326 
  [(set_attr "predicable" "yes")])
327 
 
328 
(define_insn "iwmmxt_wmacs"
329 
  [(set (match_operand:DI               0 "register_operand" "=y")
330 
        (unspec:DI [(match_operand:DI   1 "register_operand" "0")
331 
                    (match_operand:V4HI 2 "register_operand" "y")
332 
                    (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WMACS))]
333 
  "TARGET_REALLY_IWMMXT"
334 
  "wmacs%?\\t%0, %2, %3"
335 
  [(set_attr "predicable" "yes")])
336 
 
337 
(define_insn "iwmmxt_wmacsz"
338 
  [(set (match_operand:DI               0 "register_operand" "=y")
339 
        (unspec:DI [(match_operand:V4HI 1 "register_operand" "y")
340 
                    (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMACSZ))]
341 
  "TARGET_REALLY_IWMMXT"
342 
  "wmacsz%?\\t%0, %1, %2"
343 
  [(set_attr "predicable" "yes")])
344 
 
345 
(define_insn "iwmmxt_wmacu"
346 
  [(set (match_operand:DI               0 "register_operand" "=y")
347 
        (unspec:DI [(match_operand:DI   1 "register_operand" "0")
348 
                    (match_operand:V4HI 2 "register_operand" "y")
349 
                    (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WMACU))]
350 
  "TARGET_REALLY_IWMMXT"
351 
  "wmacu%?\\t%0, %2, %3"
352 
  [(set_attr "predicable" "yes")])
353 
 
354 
(define_insn "iwmmxt_wmacuz"
355 
  [(set (match_operand:DI               0 "register_operand" "=y")
356 
        (unspec:DI [(match_operand:V4HI 1 "register_operand" "y")
357 
                    (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMACUZ))]
358 
  "TARGET_REALLY_IWMMXT"
359 
  "wmacuz%?\\t%0, %1, %2"
360 
  [(set_attr "predicable" "yes")])
361 
 
362 
;; Same as xordi3, but don't show input operands so that we don't think
363 
;; they are live.
364 
(define_insn "iwmmxt_clrdi"
365 
  [(set (match_operand:DI 0 "register_operand" "=y")
366 
        (unspec:DI [(const_int 0)] UNSPEC_CLRDI))]
367 
  "TARGET_REALLY_IWMMXT"
368 
  "wxor%?\\t%0, %0, %0"
369 
  [(set_attr "predicable" "yes")])
370 
 
371 
;; Seems like cse likes to generate these, so we have to support them.
372 
 
373 
(define_insn "*iwmmxt_clrv8qi"
374 
  [(set (match_operand:V8QI 0 "register_operand" "=y")
375 
        (const_vector:V8QI [(const_int 0) (const_int 0)
376 
                            (const_int 0) (const_int 0)
377 
                            (const_int 0) (const_int 0)
378 
                            (const_int 0) (const_int 0)]))]
379 
  "TARGET_REALLY_IWMMXT"
380 
  "wxor%?\\t%0, %0, %0"
381 
  [(set_attr "predicable" "yes")])
382 
 
383 
(define_insn "*iwmmxt_clrv4hi"
384 
  [(set (match_operand:V4HI 0 "register_operand" "=y")
385 
        (const_vector:V4HI [(const_int 0) (const_int 0)
386 
                            (const_int 0) (const_int 0)]))]
387 
  "TARGET_REALLY_IWMMXT"
388 
  "wxor%?\\t%0, %0, %0"
389 
  [(set_attr "predicable" "yes")])
390 
 
391 
(define_insn "*iwmmxt_clrv2si"
392 
  [(set (match_operand:V2SI 0 "register_operand" "=y")
393 
        (const_vector:V2SI [(const_int 0) (const_int 0)]))]
394 
  "TARGET_REALLY_IWMMXT"
395 
  "wxor%?\\t%0, %0, %0"
396 
  [(set_attr "predicable" "yes")])
397 
 
398 
;; Unsigned averages/sum of absolute differences
399 
 
400 
(define_insn "iwmmxt_uavgrndv8qi3"
401 
  [(set (match_operand:V8QI              0 "register_operand" "=y")
402 
        (ashiftrt:V8QI
403 
         (plus:V8QI (plus:V8QI
404 
                     (match_operand:V8QI 1 "register_operand" "y")
405 
                     (match_operand:V8QI 2 "register_operand" "y"))
406 
                    (const_vector:V8QI [(const_int 1)
407 
                                        (const_int 1)
408 
                                        (const_int 1)
409 
                                        (const_int 1)
410 
                                        (const_int 1)
411 
                                        (const_int 1)
412 
                                        (const_int 1)
413 
                                        (const_int 1)]))
414 
         (const_int 1)))]
415 
  "TARGET_REALLY_IWMMXT"
416 
  "wavg2br%?\\t%0, %1, %2"
417 
  [(set_attr "predicable" "yes")])
418 
 
419 
(define_insn "iwmmxt_uavgrndv4hi3"
420 
  [(set (match_operand:V4HI              0 "register_operand" "=y")
421 
        (ashiftrt:V4HI
422 
         (plus:V4HI (plus:V4HI
423 
                     (match_operand:V4HI 1 "register_operand" "y")
424 
                     (match_operand:V4HI 2 "register_operand" "y"))
425 
                    (const_vector:V4HI [(const_int 1)
426 
                                        (const_int 1)
427 
                                        (const_int 1)
428 
                                        (const_int 1)]))
429 
         (const_int 1)))]
430 
  "TARGET_REALLY_IWMMXT"
431 
  "wavg2hr%?\\t%0, %1, %2"
432 
  [(set_attr "predicable" "yes")])
433 
 
434 
 
435 
(define_insn "iwmmxt_uavgv8qi3"
436 
  [(set (match_operand:V8QI                 0 "register_operand" "=y")
437 
        (ashiftrt:V8QI (plus:V8QI
438 
                        (match_operand:V8QI 1 "register_operand" "y")
439 
                        (match_operand:V8QI 2 "register_operand" "y"))
440 
                       (const_int 1)))]
441 
  "TARGET_REALLY_IWMMXT"
442 
  "wavg2b%?\\t%0, %1, %2"
443 
  [(set_attr "predicable" "yes")])
444 
 
445 
(define_insn "iwmmxt_uavgv4hi3"
446 
  [(set (match_operand:V4HI                 0 "register_operand" "=y")
447 
        (ashiftrt:V4HI (plus:V4HI
448 
                        (match_operand:V4HI 1 "register_operand" "y")
449 
                        (match_operand:V4HI 2 "register_operand" "y"))
450 
                       (const_int 1)))]
451 
  "TARGET_REALLY_IWMMXT"
452 
  "wavg2h%?\\t%0, %1, %2"
453 
  [(set_attr "predicable" "yes")])
454 
 
455 
(define_insn "iwmmxt_psadbw"
456 
  [(set (match_operand:V8QI                       0 "register_operand" "=y")
457 
        (abs:V8QI (minus:V8QI (match_operand:V8QI 1 "register_operand" "y")
458 
                              (match_operand:V8QI 2 "register_operand" "y"))))]
459 
  "TARGET_REALLY_IWMMXT"
460 
  "psadbw%?\\t%0, %1, %2"
461 
  [(set_attr "predicable" "yes")])
462 
 
463 
 
464 
;; Insert/extract/shuffle
465 
 
466 
(define_insn "iwmmxt_tinsrb"
467 
  [(set (match_operand:V8QI                             0 "register_operand"    "=y")
468 
        (vec_merge:V8QI (match_operand:V8QI             1 "register_operand"     "0")
469 
                        (vec_duplicate:V8QI
470 
                         (truncate:QI (match_operand:SI 2 "nonimmediate_operand" "r")))
471 
                        (match_operand:SI               3 "immediate_operand"    "i")))]
472 
  "TARGET_REALLY_IWMMXT"
473 
  "tinsrb%?\\t%0, %2, %3"
474 
  [(set_attr "predicable" "yes")])
475 
 
476 
(define_insn "iwmmxt_tinsrh"
477 
  [(set (match_operand:V4HI                             0 "register_operand"    "=y")
478 
        (vec_merge:V4HI (match_operand:V4HI             1 "register_operand"     "0")
479 
                        (vec_duplicate:V4HI
480 
                         (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "r")))
481 
                        (match_operand:SI               3 "immediate_operand"    "i")))]
482 
  "TARGET_REALLY_IWMMXT"
483 
  "tinsrh%?\\t%0, %2, %3"
484 
  [(set_attr "predicable" "yes")])
485 
 
486 
(define_insn "iwmmxt_tinsrw"
487 
  [(set (match_operand:V2SI                 0 "register_operand"    "=y")
488 
        (vec_merge:V2SI (match_operand:V2SI 1 "register_operand"     "0")
489 
                        (vec_duplicate:V2SI
490 
                         (match_operand:SI  2 "nonimmediate_operand" "r"))
491 
                        (match_operand:SI   3 "immediate_operand"    "i")))]
492 
  "TARGET_REALLY_IWMMXT"
493 
  "tinsrw%?\\t%0, %2, %3"
494 
  [(set_attr "predicable" "yes")])
495 
 
496 
(define_insn "iwmmxt_textrmub"
497 
  [(set (match_operand:SI                                  0 "register_operand" "=r")
498 
        (zero_extend:SI (vec_select:QI (match_operand:V8QI 1 "register_operand" "y")
499 
                                       (parallel
500 
                                        [(match_operand:SI 2 "immediate_operand" "i")]))))]
501 
  "TARGET_REALLY_IWMMXT"
502 
  "textrmub%?\\t%0, %1, %2"
503 
  [(set_attr "predicable" "yes")])
504 
 
505 
(define_insn "iwmmxt_textrmsb"
506 
  [(set (match_operand:SI                                  0 "register_operand" "=r")
507 
        (sign_extend:SI (vec_select:QI (match_operand:V8QI 1 "register_operand" "y")
508 
                                       (parallel
509 
                                        [(match_operand:SI 2 "immediate_operand" "i")]))))]
510 
  "TARGET_REALLY_IWMMXT"
511 
  "textrmsb%?\\t%0, %1, %2"
512 
  [(set_attr "predicable" "yes")])
513 
 
514 
(define_insn "iwmmxt_textrmuh"
515 
  [(set (match_operand:SI                                  0 "register_operand" "=r")
516 
        (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
517 
                                       (parallel
518 
                                        [(match_operand:SI 2 "immediate_operand" "i")]))))]
519 
  "TARGET_REALLY_IWMMXT"
520 
  "textrmuh%?\\t%0, %1, %2"
521 
  [(set_attr "predicable" "yes")])
522 
 
523 
(define_insn "iwmmxt_textrmsh"
524 
  [(set (match_operand:SI                                  0 "register_operand" "=r")
525 
        (sign_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
526 
                                       (parallel
527 
                                        [(match_operand:SI 2 "immediate_operand" "i")]))))]
528 
  "TARGET_REALLY_IWMMXT"
529 
  "textrmsh%?\\t%0, %1, %2"
530 
  [(set_attr "predicable" "yes")])
531 
 
532 
;; There are signed/unsigned variants of this instruction, but they are
533 
;; pointless.
534 
(define_insn "iwmmxt_textrmw"
535 
  [(set (match_operand:SI                           0 "register_operand" "=r")
536 
        (vec_select:SI (match_operand:V2SI          1 "register_operand" "y")
537 
                       (parallel [(match_operand:SI 2 "immediate_operand" "i")])))]
538 
  "TARGET_REALLY_IWMMXT"
539 
  "textrmsw%?\\t%0, %1, %2"
540 
  [(set_attr "predicable" "yes")])
541 
 
542 
(define_insn "iwmmxt_wshufh"
543 
  [(set (match_operand:V4HI               0 "register_operand" "=y")
544 
        (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
545 
                      (match_operand:SI   2 "immediate_operand" "i")] UNSPEC_WSHUFH))]
546 
  "TARGET_REALLY_IWMMXT"
547 
  "wshufh%?\\t%0, %1, %2"
548 
  [(set_attr "predicable" "yes")])
549 
 
550 
;; Mask-generating comparisons
551 
;;
552 
;; Note - you cannot use patterns like these here:
553 
;;
554 
;;   (set (match:) (: (match:) (match:)))
555 
;;
556 
;; Because GCC will assume that the truth value (1 or 0) is installed
557 
;; into the entire destination vector, (with the '1' going into the least
558 
;; significant element of the vector).  This is not how these instructions
559 
;; behave.
560 
;;
561 
;; Unfortunately the current patterns are illegal.  They are SET insns
562 
;; without a SET in them.  They work in most cases for ordinary code
563 
;; generation, but there are circumstances where they can cause gcc to fail.
564 
;; XXX - FIXME.
565 
 
566 
(define_insn "eqv8qi3"
567 
  [(unspec_volatile [(match_operand:V8QI 0 "register_operand" "=y")
568 
                     (match_operand:V8QI 1 "register_operand"  "y")
569 
                     (match_operand:V8QI 2 "register_operand"  "y")]
570 
                    VUNSPEC_WCMP_EQ)]
571 
  "TARGET_REALLY_IWMMXT"
572 
  "wcmpeqb%?\\t%0, %1, %2"
573 
  [(set_attr "predicable" "yes")])
574 
 
575 
(define_insn "eqv4hi3"
576 
  [(unspec_volatile [(match_operand:V4HI 0 "register_operand" "=y")
577 
                     (match_operand:V4HI 1 "register_operand"  "y")
578 
                     (match_operand:V4HI 2 "register_operand"  "y")]
579 
                    VUNSPEC_WCMP_EQ)]
580 
  "TARGET_REALLY_IWMMXT"
581 
  "wcmpeqh%?\\t%0, %1, %2"
582 
  [(set_attr "predicable" "yes")])
583 
 
584 
(define_insn "eqv2si3"
585 
  [(unspec_volatile:V2SI [(match_operand:V2SI 0 "register_operand" "=y")
586 
                          (match_operand:V2SI 1 "register_operand"  "y")
587 
                          (match_operand:V2SI 2 "register_operand"  "y")]
588 
                         VUNSPEC_WCMP_EQ)]
589 
  "TARGET_REALLY_IWMMXT"
590 
  "wcmpeqw%?\\t%0, %1, %2"
591 
  [(set_attr "predicable" "yes")])
592 
 
593 
(define_insn "gtuv8qi3"
594 
  [(unspec_volatile [(match_operand:V8QI 0 "register_operand" "=y")
595 
                     (match_operand:V8QI 1 "register_operand"  "y")
596 
                     (match_operand:V8QI 2 "register_operand"  "y")]
597 
                    VUNSPEC_WCMP_GTU)]
598 
  "TARGET_REALLY_IWMMXT"
599 
  "wcmpgtub%?\\t%0, %1, %2"
600 
  [(set_attr "predicable" "yes")])
601 
 
602 
(define_insn "gtuv4hi3"
603 
  [(unspec_volatile [(match_operand:V4HI 0 "register_operand" "=y")
604 
                     (match_operand:V4HI 1 "register_operand"  "y")
605 
                     (match_operand:V4HI 2 "register_operand"  "y")]
606 
                    VUNSPEC_WCMP_GTU)]
607 
  "TARGET_REALLY_IWMMXT"
608 
  "wcmpgtuh%?\\t%0, %1, %2"
609 
  [(set_attr "predicable" "yes")])
610 
 
611 
(define_insn "gtuv2si3"
612 
  [(unspec_volatile [(match_operand:V2SI 0 "register_operand" "=y")
613 
                     (match_operand:V2SI 1 "register_operand"  "y")
614 
                     (match_operand:V2SI 2 "register_operand"  "y")]
615 
                    VUNSPEC_WCMP_GTU)]
616 
  "TARGET_REALLY_IWMMXT"
617 
  "wcmpgtuw%?\\t%0, %1, %2"
618 
  [(set_attr "predicable" "yes")])
619 
 
620 
(define_insn "gtv8qi3"
621 
  [(unspec_volatile [(match_operand:V8QI 0 "register_operand" "=y")
622 
                     (match_operand:V8QI 1 "register_operand"  "y")
623 
                     (match_operand:V8QI 2 "register_operand"  "y")]
624 
                    VUNSPEC_WCMP_GT)]
625 
  "TARGET_REALLY_IWMMXT"
626 
  "wcmpgtsb%?\\t%0, %1, %2"
627 
  [(set_attr "predicable" "yes")])
628 
 
629 
(define_insn "gtv4hi3"
630 
  [(unspec_volatile [(match_operand:V4HI 0 "register_operand" "=y")
631 
                     (match_operand:V4HI 1 "register_operand"  "y")
632 
                     (match_operand:V4HI 2 "register_operand"  "y")]
633 
                    VUNSPEC_WCMP_GT)]
634 
  "TARGET_REALLY_IWMMXT"
635 
  "wcmpgtsh%?\\t%0, %1, %2"
636 
  [(set_attr "predicable" "yes")])
637 
 
638 
(define_insn "gtv2si3"
639 
  [(unspec_volatile [(match_operand:V2SI 0 "register_operand" "=y")
640 
                     (match_operand:V2SI 1 "register_operand"  "y")
641 
                     (match_operand:V2SI 2 "register_operand"  "y")]
642 
                    VUNSPEC_WCMP_GT)]
643 
  "TARGET_REALLY_IWMMXT"
644 
  "wcmpgtsw%?\\t%0, %1, %2"
645 
  [(set_attr "predicable" "yes")])
646 
 
647 
;; Max/min insns
648 
 
649 
(define_insn "*smax3_iwmmxt"
650 
  [(set (match_operand:VMMX            0 "register_operand" "=y")
651 
        (smax:VMMX (match_operand:VMMX 1 "register_operand" "y")
652 
                   (match_operand:VMMX 2 "register_operand" "y")))]
653 
  "TARGET_REALLY_IWMMXT"
654 
  "wmaxs%?\\t%0, %1, %2"
655 
  [(set_attr "predicable" "yes")])
656 
 
657 
(define_insn "*umax3_iwmmxt"
658 
  [(set (match_operand:VMMX            0 "register_operand" "=y")
659 
        (umax:VMMX (match_operand:VMMX 1 "register_operand" "y")
660 
                   (match_operand:VMMX 2 "register_operand" "y")))]
661 
  "TARGET_REALLY_IWMMXT"
662 
  "wmaxu%?\\t%0, %1, %2"
663 
  [(set_attr "predicable" "yes")])
664 
 
665 
(define_insn "*smin3_iwmmxt"
666 
  [(set (match_operand:VMMX            0 "register_operand" "=y")
667 
        (smin:VMMX (match_operand:VMMX 1 "register_operand" "y")
668 
                   (match_operand:VMMX 2 "register_operand" "y")))]
669 
  "TARGET_REALLY_IWMMXT"
670 
  "wmins%?\\t%0, %1, %2"
671 
  [(set_attr "predicable" "yes")])
672 
 
673 
(define_insn "*umin3_iwmmxt"
674 
  [(set (match_operand:VMMX            0 "register_operand" "=y")
675 
        (umin:VMMX (match_operand:VMMX 1 "register_operand" "y")
676 
                   (match_operand:VMMX 2 "register_operand" "y")))]
677 
  "TARGET_REALLY_IWMMXT"
678 
  "wminu%?\\t%0, %1, %2"
679 
  [(set_attr "predicable" "yes")])
680 
 
681 
;; Pack/unpack insns.
682 
 
683 
(define_insn "iwmmxt_wpackhss"
684 
  [(set (match_operand:V8QI                    0 "register_operand" "=y")
685 
        (vec_concat:V8QI
686 
         (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "y"))
687 
         (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
688 
  "TARGET_REALLY_IWMMXT"
689 
  "wpackhss%?\\t%0, %1, %2"
690 
  [(set_attr "predicable" "yes")])
691 
 
692 
(define_insn "iwmmxt_wpackwss"
693 
  [(set (match_operand:V4HI                    0 "register_operand" "=y")
694 
        (vec_concat:V4HI
695 
         (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "y"))
696 
         (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
697 
  "TARGET_REALLY_IWMMXT"
698 
  "wpackwss%?\\t%0, %1, %2"
699 
  [(set_attr "predicable" "yes")])
700 
 
701 
(define_insn "iwmmxt_wpackdss"
702 
  [(set (match_operand:V2SI                0 "register_operand" "=y")
703 
        (vec_concat:V2SI
704 
         (ss_truncate:SI (match_operand:DI 1 "register_operand" "y"))
705 
         (ss_truncate:SI (match_operand:DI 2 "register_operand" "y"))))]
706 
  "TARGET_REALLY_IWMMXT"
707 
  "wpackdss%?\\t%0, %1, %2"
708 
  [(set_attr "predicable" "yes")])
709 
 
710 
(define_insn "iwmmxt_wpackhus"
711 
  [(set (match_operand:V8QI                    0 "register_operand" "=y")
712 
        (vec_concat:V8QI
713 
         (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "y"))
714 
         (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
715 
  "TARGET_REALLY_IWMMXT"
716 
  "wpackhus%?\\t%0, %1, %2"
717 
  [(set_attr "predicable" "yes")])
718 
 
719 
(define_insn "iwmmxt_wpackwus"
720 
  [(set (match_operand:V4HI                    0 "register_operand" "=y")
721 
        (vec_concat:V4HI
722 
         (us_truncate:V2HI (match_operand:V2SI 1 "register_operand" "y"))
723 
         (us_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
724 
  "TARGET_REALLY_IWMMXT"
725 
  "wpackwus%?\\t%0, %1, %2"
726 
  [(set_attr "predicable" "yes")])
727 
 
728 
(define_insn "iwmmxt_wpackdus"
729 
  [(set (match_operand:V2SI                0 "register_operand" "=y")
730 
        (vec_concat:V2SI
731 
         (us_truncate:SI (match_operand:DI 1 "register_operand" "y"))
732 
         (us_truncate:SI (match_operand:DI 2 "register_operand" "y"))))]
733 
  "TARGET_REALLY_IWMMXT"
734 
  "wpackdus%?\\t%0, %1, %2"
735 
  [(set_attr "predicable" "yes")])
736 
 
737 
 
738 
(define_insn "iwmmxt_wunpckihb"
739 
  [(set (match_operand:V8QI                   0 "register_operand" "=y")
740 
        (vec_merge:V8QI
741 
         (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "y")
742 
                          (parallel [(const_int 4)
743 
                                     (const_int 0)
744 
                                     (const_int 5)
745 
                                     (const_int 1)
746 
                                     (const_int 6)
747 
                                     (const_int 2)
748 
                                     (const_int 7)
749 
                                     (const_int 3)]))
750 
         (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
751 
                          (parallel [(const_int 0)
752 
                                     (const_int 4)
753 
                                     (const_int 1)
754 
                                     (const_int 5)
755 
                                     (const_int 2)
756 
                                     (const_int 6)
757 
                                     (const_int 3)
758 
                                     (const_int 7)]))
759 
         (const_int 85)))]
760 
  "TARGET_REALLY_IWMMXT"
761 
  "wunpckihb%?\\t%0, %1, %2"
762 
  [(set_attr "predicable" "yes")])
763 
 
764 
(define_insn "iwmmxt_wunpckihh"
765 
  [(set (match_operand:V4HI                   0 "register_operand" "=y")
766 
        (vec_merge:V4HI
767 
         (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "y")
768 
                          (parallel [(const_int 0)
769 
                                     (const_int 2)
770 
                                     (const_int 1)
771 
                                     (const_int 3)]))
772 
         (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
773 
                          (parallel [(const_int 2)
774 
                                     (const_int 0)
775 
                                     (const_int 3)
776 
                                     (const_int 1)]))
777 
         (const_int 5)))]
778 
  "TARGET_REALLY_IWMMXT"
779 
  "wunpckihh%?\\t%0, %1, %2"
780 
  [(set_attr "predicable" "yes")])
781 
 
782 
(define_insn "iwmmxt_wunpckihw"
783 
  [(set (match_operand:V2SI                   0 "register_operand" "=y")
784 
        (vec_merge:V2SI
785 
         (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "y")
786 
                          (parallel [(const_int 0)
787 
                                     (const_int 1)]))
788 
         (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
789 
                          (parallel [(const_int 1)
790 
                                     (const_int 0)]))
791 
         (const_int 1)))]
792 
  "TARGET_REALLY_IWMMXT"
793 
  "wunpckihw%?\\t%0, %1, %2"
794 
  [(set_attr "predicable" "yes")])
795 
 
796 
(define_insn "iwmmxt_wunpckilb"
797 
  [(set (match_operand:V8QI                   0 "register_operand" "=y")
798 
        (vec_merge:V8QI
799 
         (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "y")
800 
                          (parallel [(const_int 0)
801 
                                     (const_int 4)
802 
                                     (const_int 1)
803 
                                     (const_int 5)
804 
                                     (const_int 2)
805 
                                     (const_int 6)
806 
                                     (const_int 3)
807 
                                     (const_int 7)]))
808 
         (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
809 
                          (parallel [(const_int 4)
810 
                                     (const_int 0)
811 
                                     (const_int 5)
812 
                                     (const_int 1)
813 
                                     (const_int 6)
814 
                                     (const_int 2)
815 
                                     (const_int 7)
816 
                                     (const_int 3)]))
817 
         (const_int 85)))]
818 
  "TARGET_REALLY_IWMMXT"
819 
  "wunpckilb%?\\t%0, %1, %2"
820 
  [(set_attr "predicable" "yes")])
821 
 
822 
(define_insn "iwmmxt_wunpckilh"
823 
  [(set (match_operand:V4HI                   0 "register_operand" "=y")
824 
        (vec_merge:V4HI
825 
         (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "y")
826 
                          (parallel [(const_int 2)
827 
                                     (const_int 0)
828 
                                     (const_int 3)
829 
                                     (const_int 1)]))
830 
         (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
831 
                          (parallel [(const_int 0)
832 
                                     (const_int 2)
833 
                                     (const_int 1)
834 
                                     (const_int 3)]))
835 
         (const_int 5)))]
836 
  "TARGET_REALLY_IWMMXT"
837 
  "wunpckilh%?\\t%0, %1, %2"
838 
  [(set_attr "predicable" "yes")])
839 
 
840 
(define_insn "iwmmxt_wunpckilw"
841 
  [(set (match_operand:V2SI                   0 "register_operand" "=y")
842 
        (vec_merge:V2SI
843 
         (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "y")
844 
                           (parallel [(const_int 1)
845 
                                      (const_int 0)]))
846 
         (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
847 
                          (parallel [(const_int 0)
848 
                                     (const_int 1)]))
849 
         (const_int 1)))]
850 
  "TARGET_REALLY_IWMMXT"
851 
  "wunpckilw%?\\t%0, %1, %2"
852 
  [(set_attr "predicable" "yes")])
853 
 
854 
(define_insn "iwmmxt_wunpckehub"
855 
  [(set (match_operand:V4HI                   0 "register_operand" "=y")
856 
        (zero_extend:V4HI
857 
         (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y")
858 
                          (parallel [(const_int 4) (const_int 5)
859 
                                     (const_int 6) (const_int 7)]))))]
860 
  "TARGET_REALLY_IWMMXT"
861 
  "wunpckehub%?\\t%0, %1"
862 
  [(set_attr "predicable" "yes")])
863 
 
864 
(define_insn "iwmmxt_wunpckehuh"
865 
  [(set (match_operand:V2SI                   0 "register_operand" "=y")
866 
        (zero_extend:V2SI
867 
         (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y")
868 
                          (parallel [(const_int 2) (const_int 3)]))))]
869 
  "TARGET_REALLY_IWMMXT"
870 
  "wunpckehuh%?\\t%0, %1"
871 
  [(set_attr "predicable" "yes")])
872 
 
873 
(define_insn "iwmmxt_wunpckehuw"
874 
  [(set (match_operand:DI                   0 "register_operand" "=y")
875 
        (zero_extend:DI
876 
         (vec_select:SI (match_operand:V2SI 1 "register_operand" "y")
877 
                        (parallel [(const_int 1)]))))]
878 
  "TARGET_REALLY_IWMMXT"
879 
  "wunpckehuw%?\\t%0, %1"
880 
  [(set_attr "predicable" "yes")])
881 
 
882 
(define_insn "iwmmxt_wunpckehsb"
883 
  [(set (match_operand:V4HI                   0 "register_operand" "=y")
884 
        (sign_extend:V4HI
885 
         (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y")
886 
                          (parallel [(const_int 4) (const_int 5)
887 
                                     (const_int 6) (const_int 7)]))))]
888 
  "TARGET_REALLY_IWMMXT"
889 
  "wunpckehsb%?\\t%0, %1"
890 
  [(set_attr "predicable" "yes")])
891 
 
892 
(define_insn "iwmmxt_wunpckehsh"
893 
  [(set (match_operand:V2SI                   0 "register_operand" "=y")
894 
        (sign_extend:V2SI
895 
         (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y")
896 
                          (parallel [(const_int 2) (const_int 3)]))))]
897 
  "TARGET_REALLY_IWMMXT"
898 
  "wunpckehsh%?\\t%0, %1"
899 
  [(set_attr "predicable" "yes")])
900 
 
901 
(define_insn "iwmmxt_wunpckehsw"
902 
  [(set (match_operand:DI                   0 "register_operand" "=y")
903 
        (sign_extend:DI
904 
         (vec_select:SI (match_operand:V2SI 1 "register_operand" "y")
905 
                        (parallel [(const_int 1)]))))]
906 
  "TARGET_REALLY_IWMMXT"
907 
  "wunpckehsw%?\\t%0, %1"
908 
  [(set_attr "predicable" "yes")])
909 
 
910 
(define_insn "iwmmxt_wunpckelub"
911 
  [(set (match_operand:V4HI                   0 "register_operand" "=y")
912 
        (zero_extend:V4HI
913 
         (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y")
914 
                          (parallel [(const_int 0) (const_int 1)
915 
                                     (const_int 2) (const_int 3)]))))]
916 
  "TARGET_REALLY_IWMMXT"
917 
  "wunpckelub%?\\t%0, %1"
918 
  [(set_attr "predicable" "yes")])
919 
 
920 
(define_insn "iwmmxt_wunpckeluh"
921 
  [(set (match_operand:V2SI                   0 "register_operand" "=y")
922 
        (zero_extend:V2SI
923 
         (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y")
924 
                          (parallel [(const_int 0) (const_int 1)]))))]
925 
  "TARGET_REALLY_IWMMXT"
926 
  "wunpckeluh%?\\t%0, %1"
927 
  [(set_attr "predicable" "yes")])
928 
 
929 
(define_insn "iwmmxt_wunpckeluw"
930 
  [(set (match_operand:DI                   0 "register_operand" "=y")
931 
        (zero_extend:DI
932 
         (vec_select:SI (match_operand:V2SI 1 "register_operand" "y")
933 
                        (parallel [(const_int 0)]))))]
934 
  "TARGET_REALLY_IWMMXT"
935 
  "wunpckeluw%?\\t%0, %1"
936 
  [(set_attr "predicable" "yes")])
937 
 
938 
(define_insn "iwmmxt_wunpckelsb"
939 
  [(set (match_operand:V4HI                   0 "register_operand" "=y")
940 
        (sign_extend:V4HI
941 
         (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y")
942 
                          (parallel [(const_int 0) (const_int 1)
943 
                                     (const_int 2) (const_int 3)]))))]
944 
  "TARGET_REALLY_IWMMXT"
945 
  "wunpckelsb%?\\t%0, %1"
946 
  [(set_attr "predicable" "yes")])
947 
 
948 
(define_insn "iwmmxt_wunpckelsh"
949 
  [(set (match_operand:V2SI                   0 "register_operand" "=y")
950 
        (sign_extend:V2SI
951 
         (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y")
952 
                          (parallel [(const_int 0) (const_int 1)]))))]
953 
  "TARGET_REALLY_IWMMXT"
954 
  "wunpckelsh%?\\t%0, %1"
955 
  [(set_attr "predicable" "yes")])
956 
 
957 
(define_insn "iwmmxt_wunpckelsw"
958 
  [(set (match_operand:DI                   0 "register_operand" "=y")
959 
        (sign_extend:DI
960 
         (vec_select:SI (match_operand:V2SI 1 "register_operand" "y")
961 
                        (parallel [(const_int 0)]))))]
962 
  "TARGET_REALLY_IWMMXT"
963 
  "wunpckelsw%?\\t%0, %1"
964 
  [(set_attr "predicable" "yes")])
965 
 
966 
;; Shifts
967 
 
968 
(define_insn "rorv4hi3"
969 
  [(set (match_operand:V4HI                0 "register_operand" "=y")
970 
        (rotatert:V4HI (match_operand:V4HI 1 "register_operand" "y")
971 
                       (match_operand:SI   2 "register_operand" "z")))]
972 
  "TARGET_REALLY_IWMMXT"
973 
  "wrorhg%?\\t%0, %1, %2"
974 
  [(set_attr "predicable" "yes")])
975 
 
976 
(define_insn "rorv2si3"
977 
  [(set (match_operand:V2SI                0 "register_operand" "=y")
978 
        (rotatert:V2SI (match_operand:V2SI 1 "register_operand" "y")
979 
                       (match_operand:SI   2 "register_operand" "z")))]
980 
  "TARGET_REALLY_IWMMXT"
981 
  "wrorwg%?\\t%0, %1, %2"
982 
  [(set_attr "predicable" "yes")])
983 
 
984 
(define_insn "rordi3"
985 
  [(set (match_operand:DI              0 "register_operand" "=y")
986 
        (rotatert:DI (match_operand:DI 1 "register_operand" "y")
987 
                   (match_operand:SI   2 "register_operand" "z")))]
988 
  "TARGET_REALLY_IWMMXT"
989 
  "wrordg%?\\t%0, %1, %2"
990 
  [(set_attr "predicable" "yes")])
991 
 
992 
(define_insn "ashr3_iwmmxt"
993 
  [(set (match_operand:VSHFT                 0 "register_operand" "=y")
994 
        (ashiftrt:VSHFT (match_operand:VSHFT 1 "register_operand" "y")
995 
                        (match_operand:SI    2 "register_operand" "z")))]
996 
  "TARGET_REALLY_IWMMXT"
997 
  "wsrag%?\\t%0, %1, %2"
998 
  [(set_attr "predicable" "yes")])
999 
 
1000 
(define_insn "lshr3_iwmmxt"
1001 
  [(set (match_operand:VSHFT                 0 "register_operand" "=y")
1002 
        (lshiftrt:VSHFT (match_operand:VSHFT 1 "register_operand" "y")
1003 
                        (match_operand:SI    2 "register_operand" "z")))]
1004 
  "TARGET_REALLY_IWMMXT"
1005 
  "wsrlg%?\\t%0, %1, %2"
1006 
  [(set_attr "predicable" "yes")])
1007 
 
1008 
(define_insn "ashl3_iwmmxt"
1009 
  [(set (match_operand:VSHFT               0 "register_operand" "=y")
1010 
        (ashift:VSHFT (match_operand:VSHFT 1 "register_operand" "y")
1011 
                      (match_operand:SI    2 "register_operand" "z")))]
1012 
  "TARGET_REALLY_IWMMXT"
1013 
  "wsllg%?\\t%0, %1, %2"
1014 
  [(set_attr "predicable" "yes")])
1015 
 
1016 
(define_insn "rorv4hi3_di"
1017 
  [(set (match_operand:V4HI                0 "register_operand" "=y")
1018 
        (rotatert:V4HI (match_operand:V4HI 1 "register_operand" "y")
1019 
                       (match_operand:DI   2 "register_operand" "y")))]
1020 
  "TARGET_REALLY_IWMMXT"
1021 
  "wrorh%?\\t%0, %1, %2"
1022 
  [(set_attr "predicable" "yes")])
1023 
 
1024 
(define_insn "rorv2si3_di"
1025 
  [(set (match_operand:V2SI                0 "register_operand" "=y")
1026 
        (rotatert:V2SI (match_operand:V2SI 1 "register_operand" "y")
1027 
                       (match_operand:DI   2 "register_operand" "y")))]
1028 
  "TARGET_REALLY_IWMMXT"
1029 
  "wrorw%?\\t%0, %1, %2"
1030 
  [(set_attr "predicable" "yes")])
1031 
 
1032 
(define_insn "rordi3_di"
1033 
  [(set (match_operand:DI              0 "register_operand" "=y")
1034 
        (rotatert:DI (match_operand:DI 1 "register_operand" "y")
1035 
                   (match_operand:DI   2 "register_operand" "y")))]
1036 
  "TARGET_REALLY_IWMMXT"
1037 
  "wrord%?\\t%0, %1, %2"
1038 
  [(set_attr "predicable" "yes")])
1039 
 
1040 
(define_insn "ashrv4hi3_di"
1041 
  [(set (match_operand:V4HI                0 "register_operand" "=y")
1042 
        (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "y")
1043 
                       (match_operand:DI   2 "register_operand" "y")))]
1044 
  "TARGET_REALLY_IWMMXT"
1045 
  "wsrah%?\\t%0, %1, %2"
1046 
  [(set_attr "predicable" "yes")])
1047 
 
1048 
(define_insn "ashrv2si3_di"
1049 
  [(set (match_operand:V2SI                0 "register_operand" "=y")
1050 
        (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "y")
1051 
                       (match_operand:DI   2 "register_operand" "y")))]
1052 
  "TARGET_REALLY_IWMMXT"
1053 
  "wsraw%?\\t%0, %1, %2"
1054 
  [(set_attr "predicable" "yes")])
1055 
 
1056 
(define_insn "ashrdi3_di"
1057 
  [(set (match_operand:DI              0 "register_operand" "=y")
1058 
        (ashiftrt:DI (match_operand:DI 1 "register_operand" "y")
1059 
                   (match_operand:DI   2 "register_operand" "y")))]
1060 
  "TARGET_REALLY_IWMMXT"
1061 
  "wsrad%?\\t%0, %1, %2"
1062 
  [(set_attr "predicable" "yes")])
1063 
 
1064 
(define_insn "lshrv4hi3_di"
1065 
  [(set (match_operand:V4HI                0 "register_operand" "=y")
1066 
        (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "y")
1067 
                       (match_operand:DI   2 "register_operand" "y")))]
1068 
  "TARGET_REALLY_IWMMXT"
1069 
  "wsrlh%?\\t%0, %1, %2"
1070 
  [(set_attr "predicable" "yes")])
1071 
 
1072 
(define_insn "lshrv2si3_di"
1073 
  [(set (match_operand:V2SI                0 "register_operand" "=y")
1074 
        (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "y")
1075 
                       (match_operand:DI   2 "register_operand" "y")))]
1076 
  "TARGET_REALLY_IWMMXT"
1077 
  "wsrlw%?\\t%0, %1, %2"
1078 
  [(set_attr "predicable" "yes")])
1079 
 
1080 
(define_insn "lshrdi3_di"
1081 
  [(set (match_operand:DI              0 "register_operand" "=y")
1082 
        (lshiftrt:DI (match_operand:DI 1 "register_operand" "y")
1083 
                     (match_operand:DI 2 "register_operand" "y")))]
1084 
  "TARGET_REALLY_IWMMXT"
1085 
  "wsrld%?\\t%0, %1, %2"
1086 
  [(set_attr "predicable" "yes")])
1087 
 
1088 
(define_insn "ashlv4hi3_di"
1089 
  [(set (match_operand:V4HI              0 "register_operand" "=y")
1090 
        (ashift:V4HI (match_operand:V4HI 1 "register_operand" "y")
1091 
                     (match_operand:DI   2 "register_operand" "y")))]
1092 
  "TARGET_REALLY_IWMMXT"
1093 
  "wsllh%?\\t%0, %1, %2"
1094 
  [(set_attr "predicable" "yes")])
1095 
 
1096 
(define_insn "ashlv2si3_di"
1097 
  [(set (match_operand:V2SI              0 "register_operand" "=y")
1098 
        (ashift:V2SI (match_operand:V2SI 1 "register_operand" "y")
1099 
                       (match_operand:DI 2 "register_operand" "y")))]
1100 
  "TARGET_REALLY_IWMMXT"
1101 
  "wsllw%?\\t%0, %1, %2"
1102 
  [(set_attr "predicable" "yes")])
1103 
 
1104 
(define_insn "ashldi3_di"
1105 
  [(set (match_operand:DI            0 "register_operand" "=y")
1106 
        (ashift:DI (match_operand:DI 1 "register_operand" "y")
1107 
                   (match_operand:DI 2 "register_operand" "y")))]
1108 
  "TARGET_REALLY_IWMMXT"
1109 
  "wslld%?\\t%0, %1, %2"
1110 
  [(set_attr "predicable" "yes")])
1111 
 
1112 
(define_insn "iwmmxt_wmadds"
1113 
  [(set (match_operand:V4HI               0 "register_operand" "=y")
1114 
        (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
1115 
                      (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMADDS))]
1116 
  "TARGET_REALLY_IWMMXT"
1117 
  "wmadds%?\\t%0, %1, %2"
1118 
  [(set_attr "predicable" "yes")])
1119 
 
1120 
(define_insn "iwmmxt_wmaddu"
1121 
  [(set (match_operand:V4HI               0 "register_operand" "=y")
1122 
        (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
1123 
                      (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMADDU))]
1124 
  "TARGET_REALLY_IWMMXT"
1125 
  "wmaddu%?\\t%0, %1, %2"
1126 
  [(set_attr "predicable" "yes")])
1127 
 
1128 
(define_insn "iwmmxt_tmia"
1129 
  [(set (match_operand:DI                    0 "register_operand" "=y")
1130 
        (plus:DI (match_operand:DI           1 "register_operand" "0")
1131 
                 (mult:DI (sign_extend:DI
1132 
                           (match_operand:SI 2 "register_operand" "r"))
1133 
                          (sign_extend:DI
1134 
                           (match_operand:SI 3 "register_operand" "r")))))]
1135 
  "TARGET_REALLY_IWMMXT"
1136 
  "tmia%?\\t%0, %2, %3"
1137 
  [(set_attr "predicable" "yes")])
1138 
 
1139 
(define_insn "iwmmxt_tmiaph"
1140 
  [(set (match_operand:DI          0 "register_operand" "=y")
1141 
        (plus:DI (match_operand:DI 1 "register_operand" "0")
1142 
                 (plus:DI
1143 
                  (mult:DI (sign_extend:DI
1144 
                            (truncate:HI (match_operand:SI 2 "register_operand" "r")))
1145 
                           (sign_extend:DI
1146 
                            (truncate:HI (match_operand:SI 3 "register_operand" "r"))))
1147 
                  (mult:DI (sign_extend:DI
1148 
                            (truncate:HI (ashiftrt:SI (match_dup 2) (const_int 16))))
1149 
                           (sign_extend:DI
1150 
                            (truncate:HI (ashiftrt:SI (match_dup 3) (const_int 16))))))))]
1151 
  "TARGET_REALLY_IWMMXT"
1152 
  "tmiaph%?\\t%0, %2, %3"
1153 
  [(set_attr "predicable" "yes")])
1154 
 
1155 
(define_insn "iwmmxt_tmiabb"
1156 
  [(set (match_operand:DI          0 "register_operand" "=y")
1157 
        (plus:DI (match_operand:DI 1 "register_operand" "0")
1158 
                 (mult:DI (sign_extend:DI
1159 
                           (truncate:HI (match_operand:SI 2 "register_operand" "r")))
1160 
                          (sign_extend:DI
1161 
                           (truncate:HI (match_operand:SI 3 "register_operand" "r"))))))]
1162 
  "TARGET_REALLY_IWMMXT"
1163 
  "tmiabb%?\\t%0, %2, %3"
1164 
  [(set_attr "predicable" "yes")])
1165 
 
1166 
(define_insn "iwmmxt_tmiatb"
1167 
  [(set (match_operand:DI          0 "register_operand" "=y")
1168 
        (plus:DI (match_operand:DI 1 "register_operand" "0")
1169 
                 (mult:DI (sign_extend:DI
1170 
                           (truncate:HI (ashiftrt:SI
1171 
                                         (match_operand:SI 2 "register_operand" "r")
1172 
                                         (const_int 16))))
1173 
                          (sign_extend:DI
1174 
                           (truncate:HI (match_operand:SI 3 "register_operand" "r"))))))]
1175 
  "TARGET_REALLY_IWMMXT"
1176 
  "tmiatb%?\\t%0, %2, %3"
1177 
  [(set_attr "predicable" "yes")])
1178 
 
1179 
(define_insn "iwmmxt_tmiabt"
1180 
  [(set (match_operand:DI          0 "register_operand" "=y")
1181 
        (plus:DI (match_operand:DI 1 "register_operand" "0")
1182 
                 (mult:DI (sign_extend:DI
1183 
                           (truncate:HI (match_operand:SI 2 "register_operand" "r")))
1184 
                          (sign_extend:DI
1185 
                           (truncate:HI (ashiftrt:SI
1186 
                                         (match_operand:SI 3 "register_operand" "r")
1187 
                                         (const_int 16)))))))]
1188 
  "TARGET_REALLY_IWMMXT"
1189 
  "tmiabt%?\\t%0, %2, %3"
1190 
  [(set_attr "predicable" "yes")])
1191 
 
1192 
(define_insn "iwmmxt_tmiatt"
1193 
  [(set (match_operand:DI          0 "register_operand" "=y")
1194 
        (plus:DI (match_operand:DI 1 "register_operand" "0")
1195 
                 (mult:DI (sign_extend:DI
1196 
                           (truncate:HI (ashiftrt:SI
1197 
                                         (match_operand:SI 2 "register_operand" "r")
1198 
                                         (const_int 16))))
1199 
                          (sign_extend:DI
1200 
                           (truncate:HI (ashiftrt:SI
1201 
                                         (match_operand:SI 3 "register_operand" "r")
1202 
                                         (const_int 16)))))))]
1203 
  "TARGET_REALLY_IWMMXT"
1204 
  "tmiatt%?\\t%0, %2, %3"
1205 
  [(set_attr "predicable" "yes")])
1206 
 
1207 
(define_insn "iwmmxt_tbcstqi"
1208 
  [(set (match_operand:V8QI                   0 "register_operand" "=y")
1209 
        (vec_duplicate:V8QI (match_operand:QI 1 "register_operand" "r")))]
1210 
  "TARGET_REALLY_IWMMXT"
1211 
  "tbcstb%?\\t%0, %1"
1212 
  [(set_attr "predicable" "yes")])
1213 
 
1214 
(define_insn "iwmmxt_tbcsthi"
1215 
  [(set (match_operand:V4HI                   0 "register_operand" "=y")
1216 
        (vec_duplicate:V4HI (match_operand:HI 1 "register_operand" "r")))]
1217 
  "TARGET_REALLY_IWMMXT"
1218 
  "tbcsth%?\\t%0, %1"
1219 
  [(set_attr "predicable" "yes")])
1220 
 
1221 
(define_insn "iwmmxt_tbcstsi"
1222 
  [(set (match_operand:V2SI                   0 "register_operand" "=y")
1223 
        (vec_duplicate:V2SI (match_operand:SI 1 "register_operand" "r")))]
1224 
  "TARGET_REALLY_IWMMXT"
1225 
  "tbcstw%?\\t%0, %1"
1226 
  [(set_attr "predicable" "yes")])
1227 
 
1228 
(define_insn "iwmmxt_tmovmskb"
1229 
  [(set (match_operand:SI               0 "register_operand" "=r")
1230 
        (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")] UNSPEC_TMOVMSK))]
1231 
  "TARGET_REALLY_IWMMXT"
1232 
  "tmovmskb%?\\t%0, %1"
1233 
  [(set_attr "predicable" "yes")])
1234 
 
1235 
(define_insn "iwmmxt_tmovmskh"
1236 
  [(set (match_operand:SI               0 "register_operand" "=r")
1237 
        (unspec:SI [(match_operand:V4HI 1 "register_operand" "y")] UNSPEC_TMOVMSK))]
1238 
  "TARGET_REALLY_IWMMXT"
1239 
  "tmovmskh%?\\t%0, %1"
1240 
  [(set_attr "predicable" "yes")])
1241 
 
1242 
(define_insn "iwmmxt_tmovmskw"
1243 
  [(set (match_operand:SI               0 "register_operand" "=r")
1244 
        (unspec:SI [(match_operand:V2SI 1 "register_operand" "y")] UNSPEC_TMOVMSK))]
1245 
  "TARGET_REALLY_IWMMXT"
1246 
  "tmovmskw%?\\t%0, %1"
1247 
  [(set_attr "predicable" "yes")])
1248 
 
1249 
(define_insn "iwmmxt_waccb"
1250 
  [(set (match_operand:DI               0 "register_operand" "=y")
1251 
        (unspec:DI [(match_operand:V8QI 1 "register_operand" "y")] UNSPEC_WACC))]
1252 
  "TARGET_REALLY_IWMMXT"
1253 
  "waccb%?\\t%0, %1"
1254 
  [(set_attr "predicable" "yes")])
1255 
 
1256 
(define_insn "iwmmxt_wacch"
1257 
  [(set (match_operand:DI               0 "register_operand" "=y")
1258 
        (unspec:DI [(match_operand:V4HI 1 "register_operand" "y")] UNSPEC_WACC))]
1259 
  "TARGET_REALLY_IWMMXT"
1260 
  "wacch%?\\t%0, %1"
1261 
  [(set_attr "predicable" "yes")])
1262 
 
1263 
(define_insn "iwmmxt_waccw"
1264 
  [(set (match_operand:DI               0 "register_operand" "=y")
1265 
        (unspec:DI [(match_operand:V2SI 1 "register_operand" "y")] UNSPEC_WACC))]
1266 
  "TARGET_REALLY_IWMMXT"
1267 
  "waccw%?\\t%0, %1"
1268 
  [(set_attr "predicable" "yes")])
1269 
 
1270 
(define_insn "iwmmxt_walign"
1271 
  [(set (match_operand:V8QI                           0 "register_operand" "=y,y")
1272 
        (subreg:V8QI (ashiftrt:TI
1273 
                      (subreg:TI (vec_concat:V16QI
1274 
                                  (match_operand:V8QI 1 "register_operand" "y,y")
1275 
                                  (match_operand:V8QI 2 "register_operand" "y,y")) 0)
1276 
                      (mult:SI
1277 
                       (match_operand:SI              3 "nonmemory_operand" "i,z")
1278 
                       (const_int 8))) 0))]
1279 
  "TARGET_REALLY_IWMMXT"
1280 
  "@
1281 
   waligni%?\\t%0, %1, %2, %3
1282 
   walignr%U3%?\\t%0, %1, %2"
1283 
  [(set_attr "predicable" "yes")])
1284 
 
1285 
(define_insn "iwmmxt_tmrc"
1286 
  [(set (match_operand:SI                      0 "register_operand" "=r")
1287 
        (unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "i")]
1288 
                            VUNSPEC_TMRC))]
1289 
  "TARGET_REALLY_IWMMXT"
1290 
  "tmrc%?\\t%0, %w1"
1291 
  [(set_attr "predicable" "yes")])
1292 
 
1293 
(define_insn "iwmmxt_tmcr"
1294 
  [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i")
1295 
                        (match_operand:SI 1 "register_operand"  "r")]
1296 
                       VUNSPEC_TMCR)]
1297 
  "TARGET_REALLY_IWMMXT"
1298 
  "tmcr%?\\t%w0, %1"
1299 
  [(set_attr "predicable" "yes")])
1300 
 
1301 
(define_insn "iwmmxt_wsadb"
1302 
  [(set (match_operand:V8QI               0 "register_operand" "=y")
1303 
        (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
1304 
                      (match_operand:V8QI 2 "register_operand" "y")] UNSPEC_WSAD))]
1305 
  "TARGET_REALLY_IWMMXT"
1306 
  "wsadb%?\\t%0, %1, %2"
1307 
  [(set_attr "predicable" "yes")])
1308 
 
1309 
(define_insn "iwmmxt_wsadh"
1310 
  [(set (match_operand:V4HI               0 "register_operand" "=y")
1311 
        (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
1312 
                      (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WSAD))]
1313 
  "TARGET_REALLY_IWMMXT"
1314 
  "wsadh%?\\t%0, %1, %2"
1315 
  [(set_attr "predicable" "yes")])
1316 
 
1317 
(define_insn "iwmmxt_wsadbz"
1318 
  [(set (match_operand:V8QI               0 "register_operand" "=y")
1319 
        (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
1320 
                      (match_operand:V8QI 2 "register_operand" "y")] UNSPEC_WSADZ))]
1321 
  "TARGET_REALLY_IWMMXT"
1322 
  "wsadbz%?\\t%0, %1, %2"
1323 
  [(set_attr "predicable" "yes")])
1324 
 
1325 
(define_insn "iwmmxt_wsadhz"
1326 
  [(set (match_operand:V4HI               0 "register_operand" "=y")
1327 
        (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
1328 
                      (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WSADZ))]
1329 
  "TARGET_REALLY_IWMMXT"
1330 
  "wsadhz%?\\t%0, %1, %2"
1331 
  [(set_attr "predicable" "yes")])
1332 
 

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.