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1 709 jeremybenn
;; Predicate definitions for ARM and Thumb
2
;; Copyright (C) 2004, 2007, 2008, 2010 Free Software Foundation, Inc.
3
;; Contributed by ARM Ltd.
4
 
5
;; This file is part of GCC.
6
 
7
;; GCC is free software; you can redistribute it and/or modify it
8
;; under the terms of the GNU General Public License as published
9
;; by the Free Software Foundation; either version 3, or (at your
10
;; option) any later version.
11
 
12
;; GCC is distributed in the hope that it will be useful, but WITHOUT
13
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14
;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
15
;; License for more details.
16
 
17
;; You should have received a copy of the GNU General Public License
18
;; along with GCC; see the file COPYING3.  If not see
19
;; .
20
 
21
(define_predicate "s_register_operand"
22
  (match_code "reg,subreg")
23
{
24
  if (GET_CODE (op) == SUBREG)
25
    op = SUBREG_REG (op);
26
  /* We don't consider registers whose class is NO_REGS
27
     to be a register operand.  */
28
  /* XXX might have to check for lo regs only for thumb ??? */
29
  return (GET_CODE (op) == REG
30
          && (REGNO (op) >= FIRST_PSEUDO_REGISTER
31
              || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
32
})
33
 
34
;; Any hard register.
35
(define_predicate "arm_hard_register_operand"
36
  (match_code "reg")
37
{
38
  return REGNO (op) < FIRST_PSEUDO_REGISTER;
39
})
40
 
41
;; A low register.
42
(define_predicate "low_register_operand"
43
  (and (match_code "reg")
44
       (match_test "REGNO (op) <= LAST_LO_REGNUM")))
45
 
46
;; A low register or const_int.
47
(define_predicate "low_reg_or_int_operand"
48
  (ior (match_code "const_int")
49
       (match_operand 0 "low_register_operand")))
50
 
51
;; Any core register, or any pseudo.  */
52
(define_predicate "arm_general_register_operand"
53
  (match_code "reg,subreg")
54
{
55
  if (GET_CODE (op) == SUBREG)
56
    op = SUBREG_REG (op);
57
 
58
  return (GET_CODE (op) == REG
59
          && (REGNO (op) <= LAST_ARM_REGNUM
60
              || REGNO (op) >= FIRST_PSEUDO_REGISTER));
61
})
62
 
63
(define_predicate "f_register_operand"
64
  (match_code "reg,subreg")
65
{
66
  if (GET_CODE (op) == SUBREG)
67
    op = SUBREG_REG (op);
68
 
69
  /* We don't consider registers whose class is NO_REGS
70
     to be a register operand.  */
71
  return (GET_CODE (op) == REG
72
          && (REGNO (op) >= FIRST_PSEUDO_REGISTER
73
              || REGNO_REG_CLASS (REGNO (op)) == FPA_REGS));
74
})
75
 
76
(define_predicate "vfp_register_operand"
77
  (match_code "reg,subreg")
78
{
79
  if (GET_CODE (op) == SUBREG)
80
    op = SUBREG_REG (op);
81
 
82
  /* We don't consider registers whose class is NO_REGS
83
     to be a register operand.  */
84
  return (GET_CODE (op) == REG
85
          && (REGNO (op) >= FIRST_PSEUDO_REGISTER
86
              || REGNO_REG_CLASS (REGNO (op)) == VFP_D0_D7_REGS
87
              || REGNO_REG_CLASS (REGNO (op)) == VFP_LO_REGS
88
              || (TARGET_VFPD32
89
                  && REGNO_REG_CLASS (REGNO (op)) == VFP_REGS)));
90
})
91
 
92
(define_special_predicate "subreg_lowpart_operator"
93
  (and (match_code "subreg")
94
       (match_test "subreg_lowpart_p (op)")))
95
 
96
;; Reg, subreg(reg) or const_int.
97
(define_predicate "reg_or_int_operand"
98
  (ior (match_code "const_int")
99
       (match_operand 0 "s_register_operand")))
100
 
101
(define_predicate "arm_immediate_operand"
102
  (and (match_code "const_int")
103
       (match_test "const_ok_for_arm (INTVAL (op))")))
104
 
105
;; A constant value which fits into two instructions, each taking
106
;; an arithmetic constant operand for one of the words.
107
(define_predicate "arm_immediate_di_operand"
108
  (and (match_code "const_int,const_double")
109
       (match_test "arm_const_double_by_immediates (op)")))
110
 
111
(define_predicate "arm_neg_immediate_operand"
112
  (and (match_code "const_int")
113
       (match_test "const_ok_for_arm (-INTVAL (op))")))
114
 
115
(define_predicate "arm_not_immediate_operand"
116
  (and (match_code "const_int")
117
       (match_test "const_ok_for_arm (~INTVAL (op))")))
118
 
119
(define_predicate "const0_operand"
120
  (and (match_code "const_int")
121
       (match_test "INTVAL (op) == 0")))
122
 
123
;; Something valid on the RHS of an ARM data-processing instruction
124
(define_predicate "arm_rhs_operand"
125
  (ior (match_operand 0 "s_register_operand")
126
       (match_operand 0 "arm_immediate_operand")))
127
 
128
(define_predicate "arm_rhsm_operand"
129
  (ior (match_operand 0 "arm_rhs_operand")
130
       (match_operand 0 "memory_operand")))
131
 
132
;; This doesn't have to do much because the constant is already checked
133
;; in the shift_operator predicate.
134
(define_predicate "shift_amount_operand"
135
  (ior (and (match_test "TARGET_ARM")
136
            (match_operand 0 "s_register_operand"))
137
       (match_operand 0 "const_int_operand")))
138
 
139
(define_predicate "const_neon_scalar_shift_amount_operand"
140
  (and (match_code "const_int")
141
       (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) <= GET_MODE_BITSIZE (mode)
142
        && ((unsigned HOST_WIDE_INT) INTVAL (op)) > 0")))
143
 
144
(define_predicate "arm_add_operand"
145
  (ior (match_operand 0 "arm_rhs_operand")
146
       (match_operand 0 "arm_neg_immediate_operand")))
147
 
148
(define_predicate "arm_addimm_operand"
149
  (ior (match_operand 0 "arm_immediate_operand")
150
       (match_operand 0 "arm_neg_immediate_operand")))
151
 
152
(define_predicate "arm_not_operand"
153
  (ior (match_operand 0 "arm_rhs_operand")
154
       (match_operand 0 "arm_not_immediate_operand")))
155
 
156
(define_predicate "arm_di_operand"
157
  (ior (match_operand 0 "s_register_operand")
158
       (match_operand 0 "arm_immediate_di_operand")))
159
 
160
;; True if the operand is a memory reference which contains an
161
;; offsettable address.
162
(define_predicate "offsettable_memory_operand"
163
  (and (match_code "mem")
164
       (match_test
165
        "offsettable_address_p (reload_completed | reload_in_progress,
166
                                mode, XEXP (op, 0))")))
167
 
168
;; True if the operand is a memory operand that does not have an
169
;; automodified base register (and thus will not generate output reloads).
170
(define_predicate "call_memory_operand"
171
  (and (match_code "mem")
172
       (and (match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0)))
173
                         != RTX_AUTOINC")
174
            (match_operand 0 "memory_operand"))))
175
 
176
(define_predicate "arm_reload_memory_operand"
177
  (and (match_code "mem,reg,subreg")
178
       (match_test "(!CONSTANT_P (op)
179
                     && (true_regnum(op) == -1
180
                         || (GET_CODE (op) == REG
181
                             && REGNO (op) >= FIRST_PSEUDO_REGISTER)))")))
182
 
183
;; True for valid operands for the rhs of an floating point insns.
184
;;   Allows regs or certain consts on FPA, just regs for everything else.
185
(define_predicate "arm_float_rhs_operand"
186
  (ior (match_operand 0 "s_register_operand")
187
       (and (match_code "const_double")
188
            (match_test "TARGET_FPA && arm_const_double_rtx (op)"))))
189
 
190
(define_predicate "arm_float_add_operand"
191
  (ior (match_operand 0 "arm_float_rhs_operand")
192
       (and (match_code "const_double")
193
            (match_test "TARGET_FPA && neg_const_double_rtx_ok_for_fpa (op)"))))
194
 
195
(define_predicate "vfp_compare_operand"
196
  (ior (match_operand 0 "s_register_operand")
197
       (and (match_code "const_double")
198
            (match_test "arm_const_double_rtx (op)"))))
199
 
200
(define_predicate "arm_float_compare_operand"
201
  (if_then_else (match_test "TARGET_VFP")
202
                (match_operand 0 "vfp_compare_operand")
203
                (match_operand 0 "arm_float_rhs_operand")))
204
 
205
;; True for valid index operands.
206
(define_predicate "index_operand"
207
  (ior (match_operand 0 "s_register_operand")
208
       (and (match_operand 0 "immediate_operand")
209
            (match_test "(GET_CODE (op) != CONST_INT
210
                          || (INTVAL (op) < 4096 && INTVAL (op) > -4096))"))))
211
 
212
;; True for operators that can be combined with a shift in ARM state.
213
(define_special_predicate "shiftable_operator"
214
  (and (match_code "plus,minus,ior,xor,and")
215
       (match_test "mode == GET_MODE (op)")))
216
 
217
;; True for logical binary operators.
218
(define_special_predicate "logical_binary_operator"
219
  (and (match_code "ior,xor,and")
220
       (match_test "mode == GET_MODE (op)")))
221
 
222
;; True for commutative operators
223
(define_special_predicate "commutative_binary_operator"
224
  (and (match_code "ior,xor,and,plus")
225
       (match_test "mode == GET_MODE (op)")))
226
 
227
;; True for shift operators.
228
;; Notes:
229
;;  * mult is only permitted with a constant shift amount
230
;;  * patterns that permit register shift amounts only in ARM mode use
231
;;    shift_amount_operand, patterns that always allow registers do not,
232
;;    so we don't have to worry about that sort of thing here.
233
(define_special_predicate "shift_operator"
234
  (and (ior (ior (and (match_code "mult")
235
                      (match_test "power_of_two_operand (XEXP (op, 1), mode)"))
236
                 (and (match_code "rotate")
237
                      (match_test "GET_CODE (XEXP (op, 1)) == CONST_INT
238
                                   && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
239
            (and (match_code "ashift,ashiftrt,lshiftrt,rotatert")
240
                 (match_test "GET_CODE (XEXP (op, 1)) != CONST_INT
241
                              || ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
242
       (match_test "mode == GET_MODE (op)")))
243
 
244
;; True for shift operators which can be used with saturation instructions.
245
(define_special_predicate "sat_shift_operator"
246
  (and (match_code "ashift,ashiftrt")
247
       (match_test "GET_CODE (XEXP (op, 1)) == CONST_INT
248
                    && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1)) <= 32)")
249
       (match_test "mode == GET_MODE (op)")))
250
 
251
;; True for MULT, to identify which variant of shift_operator is in use.
252
(define_special_predicate "mult_operator"
253
  (match_code "mult"))
254
 
255
;; True for operators that have 16-bit thumb variants.  */
256
(define_special_predicate "thumb_16bit_operator"
257
  (match_code "plus,minus,and,ior,xor"))
258
 
259
;; True for EQ & NE
260
(define_special_predicate "equality_operator"
261
  (match_code "eq,ne"))
262
 
263
;; True for integer comparisons and, if FP is active, for comparisons
264
;; other than LTGT or UNEQ.
265
(define_special_predicate "expandable_comparison_operator"
266
  (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,
267
               unordered,ordered,unlt,unle,unge,ungt"))
268
 
269
;; Likewise, but only accept comparisons that are directly supported
270
;; by ARM condition codes.
271
(define_special_predicate "arm_comparison_operator"
272
  (and (match_operand 0 "expandable_comparison_operator")
273
       (match_test "maybe_get_arm_condition_code (op) != ARM_NV")))
274
 
275
(define_special_predicate "lt_ge_comparison_operator"
276
  (match_code "lt,ge"))
277
 
278
(define_special_predicate "noov_comparison_operator"
279
  (match_code "lt,ge,eq,ne"))
280
 
281
(define_special_predicate "minmax_operator"
282
  (and (match_code "smin,smax,umin,umax")
283
       (match_test "mode == GET_MODE (op)")))
284
 
285
(define_special_predicate "cc_register"
286
  (and (match_code "reg")
287
       (and (match_test "REGNO (op) == CC_REGNUM")
288
            (ior (match_test "mode == GET_MODE (op)")
289
                 (match_test "mode == VOIDmode && GET_MODE_CLASS (GET_MODE (op)) == MODE_CC")))))
290
 
291
(define_special_predicate "dominant_cc_register"
292
  (match_code "reg")
293
{
294
  if (mode == VOIDmode)
295
    {
296
      mode = GET_MODE (op);
297
 
298
      if (GET_MODE_CLASS (mode) != MODE_CC)
299
        return false;
300
    }
301
 
302
  return (cc_register (op, mode)
303
          && (mode == CC_DNEmode
304
             || mode == CC_DEQmode
305
             || mode == CC_DLEmode
306
             || mode == CC_DLTmode
307
             || mode == CC_DGEmode
308
             || mode == CC_DGTmode
309
             || mode == CC_DLEUmode
310
             || mode == CC_DLTUmode
311
             || mode == CC_DGEUmode
312
             || mode == CC_DGTUmode));
313
})
314
 
315
(define_special_predicate "arm_extendqisi_mem_op"
316
  (and (match_operand 0 "memory_operand")
317
       (match_test "TARGET_ARM ? arm_legitimate_address_outer_p (mode,
318
                                                                 XEXP (op, 0),
319
                                                                 SIGN_EXTEND,
320
                                                                 0)
321
                               : memory_address_p (QImode, XEXP (op, 0))")))
322
 
323
(define_special_predicate "arm_reg_or_extendqisi_mem_op"
324
  (ior (match_operand 0 "arm_extendqisi_mem_op")
325
       (match_operand 0 "s_register_operand")))
326
 
327
(define_predicate "power_of_two_operand"
328
  (match_code "const_int")
329
{
330
  unsigned HOST_WIDE_INT value = INTVAL (op) & 0xffffffff;
331
 
332
  return value != 0 && (value & (value - 1)) == 0;
333
})
334
 
335
(define_predicate "nonimmediate_di_operand"
336
  (match_code "reg,subreg,mem")
337
{
338
   if (s_register_operand (op, mode))
339
     return true;
340
 
341
   if (GET_CODE (op) == SUBREG)
342
     op = SUBREG_REG (op);
343
 
344
   return GET_CODE (op) == MEM && memory_address_p (DImode, XEXP (op, 0));
345
})
346
 
347
(define_predicate "di_operand"
348
  (ior (match_code "const_int,const_double")
349
       (and (match_code "reg,subreg,mem")
350
            (match_operand 0 "nonimmediate_di_operand"))))
351
 
352
(define_predicate "nonimmediate_soft_df_operand"
353
  (match_code "reg,subreg,mem")
354
{
355
  if (s_register_operand (op, mode))
356
    return true;
357
 
358
  if (GET_CODE (op) == SUBREG)
359
    op = SUBREG_REG (op);
360
 
361
  return GET_CODE (op) == MEM && memory_address_p (DFmode, XEXP (op, 0));
362
})
363
 
364
(define_predicate "soft_df_operand"
365
  (ior (match_code "const_double")
366
       (and (match_code "reg,subreg,mem")
367
            (match_operand 0 "nonimmediate_soft_df_operand"))))
368
 
369
(define_special_predicate "load_multiple_operation"
370
  (match_code "parallel")
371
{
372
  HOST_WIDE_INT count = XVECLEN (op, 0);
373
  unsigned dest_regno;
374
  rtx src_addr;
375
  HOST_WIDE_INT i = 1, base = 0;
376
  HOST_WIDE_INT offset = 0;
377
  rtx elt;
378
  bool addr_reg_loaded = false;
379
  bool update = false;
380
 
381
  if (count <= 1
382
      || GET_CODE (XVECEXP (op, 0, 0)) != SET
383
      || !REG_P (SET_DEST (XVECEXP (op, 0, 0))))
384
    return false;
385
 
386
  /* Check to see if this might be a write-back.  */
387
  if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
388
    {
389
      i++;
390
      base = 1;
391
      update = true;
392
 
393
      /* Now check it more carefully.  */
394
      if (GET_CODE (SET_DEST (elt)) != REG
395
          || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
396
          || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
397
          || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
398
        return false;
399
    }
400
 
401
  /* Perform a quick check so we don't blow up below.  */
402
  if (count <= i
403
      || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
404
      || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG
405
      || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM)
406
    return false;
407
 
408
  dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1)));
409
  src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0);
410
  if (GET_CODE (src_addr) == PLUS)
411
    {
412
      if (GET_CODE (XEXP (src_addr, 1)) != CONST_INT)
413
        return false;
414
      offset = INTVAL (XEXP (src_addr, 1));
415
      src_addr = XEXP (src_addr, 0);
416
    }
417
  if (!REG_P (src_addr))
418
    return false;
419
 
420
  for (; i < count; i++)
421
    {
422
      elt = XVECEXP (op, 0, i);
423
 
424
      if (GET_CODE (elt) != SET
425
          || GET_CODE (SET_DEST (elt)) != REG
426
          || GET_MODE (SET_DEST (elt)) != SImode
427
          || REGNO (SET_DEST (elt)) <= dest_regno
428
          || GET_CODE (SET_SRC (elt)) != MEM
429
          || GET_MODE (SET_SRC (elt)) != SImode
430
          || ((GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
431
               || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
432
               || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
433
               || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != offset + (i - base) * 4)
434
              && (!REG_P (XEXP (SET_SRC (elt), 0))
435
                  || offset + (i - base) * 4 != 0)))
436
        return false;
437
      dest_regno = REGNO (SET_DEST (elt));
438
      if (dest_regno == REGNO (src_addr))
439
        addr_reg_loaded = true;
440
    }
441
  /* For Thumb, we only have updating instructions.  If the pattern does
442
     not describe an update, it must be because the address register is
443
     in the list of loaded registers - on the hardware, this has the effect
444
     of overriding the update.  */
445
  if (update && addr_reg_loaded)
446
    return false;
447
  if (TARGET_THUMB1)
448
    return update || addr_reg_loaded;
449
  return true;
450
})
451
 
452
(define_special_predicate "store_multiple_operation"
453
  (match_code "parallel")
454
{
455
  HOST_WIDE_INT count = XVECLEN (op, 0);
456
  unsigned src_regno;
457
  rtx dest_addr;
458
  HOST_WIDE_INT i = 1, base = 0, offset = 0;
459
  rtx elt;
460
 
461
  if (count <= 1
462
      || GET_CODE (XVECEXP (op, 0, 0)) != SET)
463
    return false;
464
 
465
  /* Check to see if this might be a write-back.  */
466
  if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
467
    {
468
      i++;
469
      base = 1;
470
 
471
      /* Now check it more carefully.  */
472
      if (GET_CODE (SET_DEST (elt)) != REG
473
          || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
474
          || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
475
          || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
476
        return false;
477
    }
478
 
479
  /* Perform a quick check so we don't blow up below.  */
480
  if (count <= i
481
      || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
482
      || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM
483
      || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG)
484
    return false;
485
 
486
  src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1)));
487
  dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0);
488
 
489
  if (GET_CODE (dest_addr) == PLUS)
490
    {
491
      if (GET_CODE (XEXP (dest_addr, 1)) != CONST_INT)
492
        return false;
493
      offset = INTVAL (XEXP (dest_addr, 1));
494
      dest_addr = XEXP (dest_addr, 0);
495
    }
496
  if (!REG_P (dest_addr))
497
    return false;
498
 
499
  for (; i < count; i++)
500
    {
501
      elt = XVECEXP (op, 0, i);
502
 
503
      if (GET_CODE (elt) != SET
504
          || GET_CODE (SET_SRC (elt)) != REG
505
          || GET_MODE (SET_SRC (elt)) != SImode
506
          || REGNO (SET_SRC (elt)) <= src_regno
507
          || GET_CODE (SET_DEST (elt)) != MEM
508
          || GET_MODE (SET_DEST (elt)) != SImode
509
          || ((GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
510
               || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
511
               || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
512
               || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != offset + (i - base) * 4)
513
              && (!REG_P (XEXP (SET_DEST (elt), 0))
514
                  || offset + (i - base) * 4 != 0)))
515
        return false;
516
      src_regno = REGNO (SET_SRC (elt));
517
    }
518
 
519
  return true;
520
})
521
 
522
(define_special_predicate "multi_register_push"
523
  (match_code "parallel")
524
{
525
  if ((GET_CODE (XVECEXP (op, 0, 0)) != SET)
526
      || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
527
      || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT))
528
    return false;
529
 
530
  return true;
531
})
532
 
533
(define_predicate "push_mult_memory_operand"
534
  (match_code "mem")
535
{
536
  /* ??? Given how PUSH_MULT is generated in the prologues, is there
537
     any point in testing for thumb1 specially?  All of the variants
538
     use the same form.  */
539
  if (TARGET_THUMB1)
540
    {
541
      /* ??? No attempt is made to represent STMIA, or validate that
542
         the stack adjustment matches the register count.  This is
543
         true of the ARM/Thumb2 path as well.  */
544
      rtx x = XEXP (op, 0);
545
      if (GET_CODE (x) != PRE_MODIFY)
546
        return false;
547
      if (XEXP (x, 0) != stack_pointer_rtx)
548
        return false;
549
      x = XEXP (x, 1);
550
      if (GET_CODE (x) != PLUS)
551
        return false;
552
      if (XEXP (x, 0) != stack_pointer_rtx)
553
        return false;
554
      return CONST_INT_P (XEXP (x, 1));
555
    }
556
 
557
  /* ARM and Thumb2 handle pre-modify in their legitimate_address.  */
558
  return memory_operand (op, mode);
559
})
560
 
561
;;-------------------------------------------------------------------------
562
;;
563
;; Thumb predicates
564
;;
565
 
566
(define_predicate "thumb1_cmp_operand"
567
  (ior (and (match_code "reg,subreg")
568
            (match_operand 0 "s_register_operand"))
569
       (and (match_code "const_int")
570
            (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 256"))))
571
 
572
(define_predicate "thumb1_cmpneg_operand"
573
  (and (match_code "const_int")
574
       (match_test "INTVAL (op) < 0 && INTVAL (op) > -256")))
575
 
576
;; Return TRUE if a result can be stored in OP without clobbering the
577
;; condition code register.  Prior to reload we only accept a
578
;; register.  After reload we have to be able to handle memory as
579
;; well, since a pseudo may not get a hard reg and reload cannot
580
;; handle output-reloads on jump insns.
581
 
582
;; We could possibly handle mem before reload as well, but that might
583
;; complicate things with the need to handle increment
584
;; side-effects.
585
(define_predicate "thumb_cbrch_target_operand"
586
  (and (match_code "reg,subreg,mem")
587
       (ior (match_operand 0 "s_register_operand")
588
            (and (match_test "reload_in_progress || reload_completed")
589
                 (match_operand 0 "memory_operand")))))
590
 
591
;;-------------------------------------------------------------------------
592
;;
593
;; MAVERICK predicates
594
;;
595
 
596
(define_predicate "cirrus_register_operand"
597
  (match_code "reg,subreg")
598
{
599
  if (GET_CODE (op) == SUBREG)
600
    op = SUBREG_REG (op);
601
 
602
  return (GET_CODE (op) == REG
603
          && (REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS
604
              || REGNO_REG_CLASS (REGNO (op)) == GENERAL_REGS));
605
})
606
 
607
(define_predicate "cirrus_fp_register"
608
  (match_code "reg,subreg")
609
{
610
  if (GET_CODE (op) == SUBREG)
611
    op = SUBREG_REG (op);
612
 
613
  return (GET_CODE (op) == REG
614
          && (REGNO (op) >= FIRST_PSEUDO_REGISTER
615
              || REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS));
616
})
617
 
618
(define_predicate "cirrus_shift_const"
619
  (and (match_code "const_int")
620
       (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 64")))
621
 
622
 
623
;; Neon predicates
624
 
625
(define_predicate "const_multiple_of_8_operand"
626
  (match_code "const_int")
627
{
628
  unsigned HOST_WIDE_INT val = INTVAL (op);
629
  return (val & 7) == 0;
630
})
631
 
632
(define_predicate "imm_for_neon_mov_operand"
633
  (match_code "const_vector")
634
{
635
  return neon_immediate_valid_for_move (op, mode, NULL, NULL);
636
})
637
 
638
(define_predicate "imm_for_neon_lshift_operand"
639
  (match_code "const_vector")
640
{
641
  return neon_immediate_valid_for_shift (op, mode, NULL, NULL, true);
642
})
643
 
644
(define_predicate "imm_for_neon_rshift_operand"
645
  (match_code "const_vector")
646
{
647
  return neon_immediate_valid_for_shift (op, mode, NULL, NULL, false);
648
})
649
 
650
(define_predicate "imm_lshift_or_reg_neon"
651
  (ior (match_operand 0 "s_register_operand")
652
       (match_operand 0 "imm_for_neon_lshift_operand")))
653
 
654
(define_predicate "imm_rshift_or_reg_neon"
655
  (ior (match_operand 0 "s_register_operand")
656
       (match_operand 0 "imm_for_neon_rshift_operand")))
657
 
658
(define_predicate "imm_for_neon_logic_operand"
659
  (match_code "const_vector")
660
{
661
  return (TARGET_NEON
662
          && neon_immediate_valid_for_logic (op, mode, 0, NULL, NULL));
663
})
664
 
665
(define_predicate "imm_for_neon_inv_logic_operand"
666
  (match_code "const_vector")
667
{
668
  return (TARGET_NEON
669
          && neon_immediate_valid_for_logic (op, mode, 1, NULL, NULL));
670
})
671
 
672
(define_predicate "neon_logic_op2"
673
  (ior (match_operand 0 "imm_for_neon_logic_operand")
674
       (match_operand 0 "s_register_operand")))
675
 
676
(define_predicate "neon_inv_logic_op2"
677
  (ior (match_operand 0 "imm_for_neon_inv_logic_operand")
678
       (match_operand 0 "s_register_operand")))
679
 
680
;; TODO: We could check lane numbers more precisely based on the mode.
681
(define_predicate "neon_lane_number"
682
  (and (match_code "const_int")
683
       (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 15")))
684
;; Predicates for named expanders that overlap multiple ISAs.
685
 
686
(define_predicate "cmpdi_operand"
687
  (if_then_else (match_test "TARGET_HARD_FLOAT && TARGET_MAVERICK")
688
                (and (match_test "TARGET_ARM")
689
                     (match_operand 0 "cirrus_fp_register"))
690
                (and (match_test "TARGET_32BIT")
691
                     (match_operand 0 "arm_di_operand"))))
692
 
693
;; True if the operand is memory reference suitable for a ldrex/strex.
694
(define_predicate "arm_sync_memory_operand"
695
  (and (match_operand 0 "memory_operand")
696
       (match_code "reg" "0")))
697
 
698
;; Predicates for parallel expanders based on mode.
699
(define_special_predicate "vect_par_constant_high"
700
  (match_code "parallel")
701
{
702
  HOST_WIDE_INT count = XVECLEN (op, 0);
703
  int i;
704
  int base = GET_MODE_NUNITS (mode);
705
 
706
  if ((count < 1)
707
      || (count != base/2))
708
    return false;
709
 
710
  if (!VECTOR_MODE_P (mode))
711
    return false;
712
 
713
  for (i = 0; i < count; i++)
714
   {
715
     rtx elt = XVECEXP (op, 0, i);
716
     int val;
717
 
718
     if (GET_CODE (elt) != CONST_INT)
719
       return false;
720
 
721
     val = INTVAL (elt);
722
     if (val != (base/2) + i)
723
       return false;
724
   }
725
  return true;
726
})
727
 
728
(define_special_predicate "vect_par_constant_low"
729
  (match_code "parallel")
730
{
731
  HOST_WIDE_INT count = XVECLEN (op, 0);
732
  int i;
733
  int base = GET_MODE_NUNITS (mode);
734
 
735
  if ((count < 1)
736
      || (count != base/2))
737
    return false;
738
 
739
  if (!VECTOR_MODE_P (mode))
740
    return false;
741
 
742
  for (i = 0; i < count; i++)
743
   {
744
     rtx elt = XVECEXP (op, 0, i);
745
     int val;
746
 
747
     if (GET_CODE (elt) != CONST_INT)
748
       return false;
749
 
750
     val = INTVAL (elt);
751
     if (val != i)
752
       return false;
753
   }
754
  return true;
755
})
756
 
757
(define_predicate "const_double_vcvt_power_of_two_reciprocal"
758
  (and (match_code "const_double")
759
       (match_test "TARGET_32BIT && TARGET_VFP
760
                   && vfp3_const_double_for_fract_bits (op)")))
761
 
762
(define_predicate "neon_struct_operand"
763
  (and (match_code "mem")
764
       (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2)")))
765
 
766
(define_predicate "neon_struct_or_register_operand"
767
  (ior (match_operand 0 "neon_struct_operand")
768
       (match_operand 0 "s_register_operand")))
769
 
770
(define_special_predicate "add_operator"
771
  (match_code "plus"))
772
 
773
(define_predicate "mem_noofs_operand"
774
  (and (match_code "mem")
775
       (match_code "reg" "0")))

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