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jeremybenn |
;; Machine Description for shared bits common to IWMMXT and Neon.
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;; Copyright (C) 2006, 2007, 2010, 2012 Free Software Foundation, Inc.
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;; Written by CodeSourcery.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful, but
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;; WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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;; General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; .
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;; Vector Moves
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(define_expand "mov"
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[(set (match_operand:VALL 0 "nonimmediate_operand" "")
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(match_operand:VALL 1 "general_operand" ""))]
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"TARGET_NEON
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|| (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))"
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{
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if (can_create_pseudo_p ())
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{
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if (GET_CODE (operands[0]) != REG)
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operands[1] = force_reg (mode, operands[1]);
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else if (TARGET_NEON && CONSTANT_P (operands[1]))
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{
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operands[1] = neon_make_constant (operands[1]);
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gcc_assert (operands[1] != NULL_RTX);
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}
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}
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})
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;; Vector arithmetic. Expanders are blank, then unnamed insns implement
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;; patterns separately for IWMMXT and Neon.
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(define_expand "add3"
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[(set (match_operand:VALL 0 "s_register_operand" "")
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(plus:VALL (match_operand:VALL 1 "s_register_operand" "")
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(match_operand:VALL 2 "s_register_operand" "")))]
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"(TARGET_NEON && ((mode != V2SFmode && mode != V4SFmode)
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|| flag_unsafe_math_optimizations))
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|| (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))"
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{
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})
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(define_expand "sub3"
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[(set (match_operand:VALL 0 "s_register_operand" "")
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(minus:VALL (match_operand:VALL 1 "s_register_operand" "")
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(match_operand:VALL 2 "s_register_operand" "")))]
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"(TARGET_NEON && ((mode != V2SFmode && mode != V4SFmode)
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|| flag_unsafe_math_optimizations))
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|| (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))"
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{
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})
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(define_expand "mul3"
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[(set (match_operand:VALLW 0 "s_register_operand" "")
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(mult:VALLW (match_operand:VALLW 1 "s_register_operand" "")
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(match_operand:VALLW 2 "s_register_operand" "")))]
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"(TARGET_NEON && ((mode != V2SFmode && mode != V4SFmode)
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|| flag_unsafe_math_optimizations))
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|| (mode == V4HImode && TARGET_REALLY_IWMMXT)"
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{
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})
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(define_expand "smin3"
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[(set (match_operand:VALLW 0 "s_register_operand" "")
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(smin:VALLW (match_operand:VALLW 1 "s_register_operand" "")
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(match_operand:VALLW 2 "s_register_operand" "")))]
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"(TARGET_NEON && ((mode != V2SFmode && mode != V4SFmode)
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|| flag_unsafe_math_optimizations))
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|| (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))"
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{
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})
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(define_expand "umin3"
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[(set (match_operand:VINTW 0 "s_register_operand" "")
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(umin:VINTW (match_operand:VINTW 1 "s_register_operand" "")
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(match_operand:VINTW 2 "s_register_operand" "")))]
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"TARGET_NEON
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|| (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))"
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{
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})
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(define_expand "smax3"
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[(set (match_operand:VALLW 0 "s_register_operand" "")
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(smax:VALLW (match_operand:VALLW 1 "s_register_operand" "")
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(match_operand:VALLW 2 "s_register_operand" "")))]
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"(TARGET_NEON && ((mode != V2SFmode && mode != V4SFmode)
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|| flag_unsafe_math_optimizations))
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|| (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))"
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{
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})
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(define_expand "umax3"
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[(set (match_operand:VINTW 0 "s_register_operand" "")
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(umax:VINTW (match_operand:VINTW 1 "s_register_operand" "")
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(match_operand:VINTW 2 "s_register_operand" "")))]
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"TARGET_NEON
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|| (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))"
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{
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})
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(define_expand "vec_perm_const"
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[(match_operand:VALL 0 "s_register_operand" "")
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(match_operand:VALL 1 "s_register_operand" "")
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(match_operand:VALL 2 "s_register_operand" "")
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(match_operand: 3 "" "")]
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"TARGET_NEON
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|| (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))"
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{
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if (arm_expand_vec_perm_const (operands[0], operands[1],
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operands[2], operands[3]))
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DONE;
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else
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FAIL;
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})
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(define_expand "vec_perm"
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[(match_operand:VE 0 "s_register_operand" "")
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(match_operand:VE 1 "s_register_operand" "")
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(match_operand:VE 2 "s_register_operand" "")
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(match_operand:VE 3 "s_register_operand" "")]
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"TARGET_NEON && !BYTES_BIG_ENDIAN"
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{
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arm_expand_vec_perm (operands[0], operands[1], operands[2], operands[3]);
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DONE;
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})
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