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jeremybenn |
;; ARM VFP11 pipeline description
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;; Copyright (C) 2003, 2005, 2007, 2008 Free Software Foundation, Inc.
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;; Written by CodeSourcery.
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;;
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;; This file is part of GCC.
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; .
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(define_automaton "vfp11")
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;; There are 3 pipelines in the VFP11 unit.
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;;
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;; - A 8-stage FMAC pipeline (7 execute + writeback) with forward from
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;; fourth stage for simple operations.
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;;
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;; - A 5-stage DS pipeline (4 execute + writeback) for divide/sqrt insns.
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;; These insns also uses first execute stage of FMAC pipeline.
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;;
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;; - A 4-stage LS pipeline (execute + 2 memory + writeback) with forward from
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;; second memory stage for loads.
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;; We do not model Write-After-Read hazards.
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;; We do not do write scheduling with the arm core, so it is only necessary
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;; to model the first stage of each pipeline
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;; ??? Need to model LS pipeline properly for load/store multiple?
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;; We do not model fmstat properly. This could be done by modeling pipelines
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;; properly and defining an absence set between a dummy fmstat unit and all
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;; other vfp units.
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(define_cpu_unit "fmac" "vfp11")
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(define_cpu_unit "ds" "vfp11")
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(define_cpu_unit "vfp_ls" "vfp11")
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(define_cpu_unit "fmstat" "vfp11")
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(exclusion_set "fmac,ds" "fmstat")
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(define_insn_reservation "vfp_ffarith" 4
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(and (eq_attr "generic_vfp" "yes")
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(eq_attr "type" "fcpys,ffariths,ffarithd,fcmps,fcmpd"))
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"fmac")
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(define_insn_reservation "vfp_farith" 8
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(and (eq_attr "generic_vfp" "yes")
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(eq_attr "type" "fadds,faddd,fconsts,fconstd,f_cvt,fmuls,fmacs"))
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"fmac")
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(define_insn_reservation "vfp_fmul" 9
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(and (eq_attr "generic_vfp" "yes")
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(eq_attr "type" "fmuld,fmacd"))
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"fmac*2")
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(define_insn_reservation "vfp_fdivs" 19
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(and (eq_attr "generic_vfp" "yes")
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(eq_attr "type" "fdivs"))
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"ds*15")
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(define_insn_reservation "vfp_fdivd" 33
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(and (eq_attr "generic_vfp" "yes")
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(eq_attr "type" "fdivd"))
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"fmac+ds*29")
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;; Moves to/from arm regs also use the load/store pipeline.
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(define_insn_reservation "vfp_fload" 4
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(and (eq_attr "generic_vfp" "yes")
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(eq_attr "type" "f_loads,f_loadd,r_2_f"))
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"vfp_ls")
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(define_insn_reservation "vfp_fstore" 4
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(and (eq_attr "generic_vfp" "yes")
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(eq_attr "type" "f_stores,f_stored,f_2_r"))
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"vfp_ls")
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(define_insn_reservation "vfp_to_cpsr" 4
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(and (eq_attr "generic_vfp" "yes")
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(eq_attr "type" "f_flag"))
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"fmstat,vfp_ls*3")
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