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[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [config/] [avr/] [avr-dimode.md] - Blame information for rev 709

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1 709 jeremybenn
;;   Machine description for GNU compiler,
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;;   for Atmel AVR micro controllers.
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;;   Copyright (C) 1998 - 2011
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;;   Free Software Foundation, Inc.
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;;   Contributed by Georg Lay (avr@gjlay.de)
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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;; GNU General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3.  If not see
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;; .
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; The purpose of this file is to provide a light-weight DImode
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;; implementation for AVR.  The trouble with DImode is that tree -> RTL
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;; lowering leads to really unpleasant code for operations that don't
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;; work byte-wise like NEG, PLUS, MINUS, etc.  Defining optabs entries for
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;; them won't help because the optab machinery assumes these operations
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;; are cheap and does not check if a libgcc implementation is available.
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;;
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;; The DImode insns are all straight forward -- except movdi.  The approach
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;; of this implementation is to provide DImode insns without the burden of
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;; introducing movdi.
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;;
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;; The caveat is that if there are insns for some mode, there must also be a
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;; respective move insn that describes reloads.  Therefore, this
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;; implementation uses an accumulator-based model with two hard-coded,
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;; accumulator-like registers
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;;
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;;    A[] = reg:DI 18
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;;    B[] = reg:DI 10
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;;
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;; so that no DImode insn contains pseudos or needs reloading.
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(define_constants
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  [(ACC_A       18)
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   (ACC_B       10)])
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Addition
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(define_expand "adddi3"
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  [(parallel [(match_operand:DI 0 "general_operand" "")
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              (match_operand:DI 1 "general_operand" "")
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              (match_operand:DI 2 "general_operand" "")])]
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  "avr_have_dimode"
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  {
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    rtx acc_a = gen_rtx_REG (DImode, ACC_A);
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62
    emit_move_insn (acc_a, operands[1]);
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    if (s8_operand (operands[2], VOIDmode))
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      {
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        emit_move_insn (gen_rtx_REG (QImode, REG_X), operands[2]);
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        emit_insn (gen_adddi3_const8_insn ());
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      }
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    else if (CONST_INT_P (operands[2])
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             || CONST_DOUBLE_P (operands[2]))
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      {
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        emit_insn (gen_adddi3_const_insn (operands[2]));
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      }
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    else
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      {
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        emit_move_insn (gen_rtx_REG (DImode, ACC_B), operands[2]);
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        emit_insn (gen_adddi3_insn ());
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      }
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    emit_move_insn (operands[0], acc_a);
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    DONE;
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  })
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(define_insn "adddi3_insn"
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  [(set (reg:DI ACC_A)
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        (plus:DI (reg:DI ACC_A)
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                 (reg:DI ACC_B)))]
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  "avr_have_dimode"
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  "%~call __adddi3"
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  [(set_attr "adjust_len" "call")
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   (set_attr "cc" "clobber")])
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(define_insn "adddi3_const8_insn"
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  [(set (reg:DI ACC_A)
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        (plus:DI (reg:DI ACC_A)
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                 (sign_extend:DI (reg:QI REG_X))))]
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  "avr_have_dimode"
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  "%~call __adddi3_s8"
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  [(set_attr "adjust_len" "call")
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   (set_attr "cc" "clobber")])
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(define_insn "adddi3_const_insn"
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  [(set (reg:DI ACC_A)
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        (plus:DI (reg:DI ACC_A)
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                 (match_operand:DI 0 "const_double_operand" "n")))]
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  "avr_have_dimode
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   && !s8_operand (operands[0], VOIDmode)"
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  {
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    return avr_out_plus64 (operands[0], NULL);
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  }
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  [(set_attr "adjust_len" "plus64")
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   (set_attr "cc" "clobber")])
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114
 
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Subtraction
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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119
(define_expand "subdi3"
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  [(parallel [(match_operand:DI 0 "general_operand" "")
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              (match_operand:DI 1 "general_operand" "")
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              (match_operand:DI 2 "general_operand" "")])]
123
  "avr_have_dimode"
124
  {
125
    rtx acc_a = gen_rtx_REG (DImode, ACC_A);
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127
    emit_move_insn (acc_a, operands[1]);
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    emit_move_insn (gen_rtx_REG (DImode, ACC_B), operands[2]);
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    emit_insn (gen_subdi3_insn ());
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    emit_move_insn (operands[0], acc_a);
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    DONE;
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  })
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(define_insn "subdi3_insn"
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  [(set (reg:DI ACC_A)
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        (minus:DI (reg:DI ACC_A)
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                  (reg:DI ACC_B)))]
138
  "avr_have_dimode"
139
  "%~call __subdi3"
140
  [(set_attr "adjust_len" "call")
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   (set_attr "cc" "set_czn")])
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143
 
144
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Negation
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
147
 
148
(define_expand "negdi2"
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  [(parallel [(match_operand:DI 0 "general_operand" "")
150
              (match_operand:DI 1 "general_operand" "")])]
151
  "avr_have_dimode"
152
  {
153
    rtx acc_a = gen_rtx_REG (DImode, ACC_A);
154
 
155
    emit_move_insn (acc_a, operands[1]);
156
    emit_insn (gen_negdi2_insn ());
157
    emit_move_insn (operands[0], acc_a);
158
    DONE;
159
  })
160
 
161
(define_insn "negdi2_insn"
162
  [(set (reg:DI ACC_A)
163
        (neg:DI (reg:DI ACC_A)))]
164
  "avr_have_dimode"
165
  "%~call __negdi2"
166
  [(set_attr "adjust_len" "call")
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   (set_attr "cc" "clobber")])
168
 
169
 
170
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Comparison
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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174
(define_expand "conditional_jump"
175
  [(set (pc)
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        (if_then_else
177
         (match_operator 0 "ordered_comparison_operator" [(cc0)
178
                                                          (const_int 0)])
179
         (label_ref (match_operand 1 "" ""))
180
         (pc)))]
181
  "avr_have_dimode")
182
 
183
(define_expand "cbranchdi4"
184
  [(parallel [(match_operand:DI 1 "register_operand" "")
185
              (match_operand:DI 2 "nonmemory_operand" "")
186
              (match_operator 0 "ordered_comparison_operator" [(cc0)
187
                                                               (const_int 0)])
188
              (label_ref (match_operand 3 "" ""))])]
189
  "avr_have_dimode"
190
  {
191
    rtx acc_a = gen_rtx_REG (DImode, ACC_A);
192
 
193
    emit_move_insn (acc_a, operands[1]);
194
 
195
    if (s8_operand (operands[2], VOIDmode))
196
      {
197
        emit_move_insn (gen_rtx_REG (QImode, REG_X), operands[2]);
198
        emit_insn (gen_compare_const8_di2 ());
199
      }
200
    else if (CONST_INT_P (operands[2])
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             || CONST_DOUBLE_P (operands[2]))
202
      {
203
        emit_insn (gen_compare_const_di2 (operands[2]));
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      }
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    else
206
      {
207
        emit_move_insn (gen_rtx_REG (DImode, ACC_B), operands[2]);
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        emit_insn (gen_compare_di2 ());
209
      }
210
 
211
    emit_jump_insn (gen_conditional_jump (operands[0], operands[3]));
212
    DONE;
213
  })
214
 
215
(define_insn "compare_di2"
216
  [(set (cc0)
217
        (compare (reg:DI ACC_A)
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                 (reg:DI ACC_B)))]
219
  "avr_have_dimode"
220
  "%~call __cmpdi2"
221
  [(set_attr "adjust_len" "call")
222
   (set_attr "cc" "compare")])
223
 
224
(define_insn "compare_const8_di2"
225
  [(set (cc0)
226
        (compare (reg:DI ACC_A)
227
                 (sign_extend:DI (reg:QI REG_X))))]
228
  "avr_have_dimode"
229
  "%~call __cmpdi2_s8"
230
  [(set_attr "adjust_len" "call")
231
   (set_attr "cc" "compare")])
232
 
233
(define_insn "compare_const_di2"
234
  [(set (cc0)
235
        (compare (reg:DI ACC_A)
236
                 (match_operand:DI 0 "const_double_operand" "n")))
237
   (clobber (match_scratch:QI 1 "=&d"))]
238
  "avr_have_dimode
239
   && !s8_operand (operands[0], VOIDmode)"
240
  {
241
    return avr_out_compare64 (insn, operands, NULL);
242
  }
243
  [(set_attr "adjust_len" "compare64")
244
   (set_attr "cc" "compare")])
245
 
246
 
247
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
248
;; Shifts and Rotate
249
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
250
 
251
(define_code_iterator di_shifts
252
  [ashift ashiftrt lshiftrt rotate])
253
 
254
;; Shift functions from libgcc are called without defining these insns,
255
;; but with them we can describe their reduced register footprint.
256
 
257
;; "ashldi3"
258
;; "ashrdi3"
259
;; "lshrdi3"
260
;; "rotldi3"
261
(define_expand "di3"
262
  [(parallel [(match_operand:DI 0 "general_operand" "")
263
              (di_shifts:DI (match_operand:DI 1 "general_operand" "")
264
                            (match_operand:QI 2 "general_operand" ""))])]
265
  "avr_have_dimode"
266
  {
267
    rtx acc_a = gen_rtx_REG (DImode, ACC_A);
268
 
269
    emit_move_insn (acc_a, operands[1]);
270
    emit_move_insn (gen_rtx_REG (QImode, 16), operands[2]);
271
    emit_insn (gen_di3_insn ());
272
    emit_move_insn (operands[0], acc_a);
273
    DONE;
274
  })
275
 
276
(define_insn "di3_insn"
277
  [(set (reg:DI ACC_A)
278
        (di_shifts:DI (reg:DI ACC_A)
279
                      (reg:QI 16)))]
280
  "avr_have_dimode"
281
  "%~call __di3"
282
  [(set_attr "adjust_len" "call")
283
   (set_attr "cc" "clobber")])

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