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;;   Machine description for GNU compiler,

;;   for ATMEL AVR micro controllers.

;;   Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2007, 2008,

;;   2009, 2010, 2011 Free Software Foundation, Inc.

;;   Contributed by Denis Chertykov (chertykov@gmail.com)

;; This file is part of GCC.

;; GCC is free software; you can redistribute it and/or modify

;; it under the terms of the GNU General Public License as published by

;; the Free Software Foundation; either version 3, or (at your option)

;; any later version.

;; GCC is distributed in the hope that it will be useful,

;; but WITHOUT ANY WARRANTY; without even the implied warranty of

;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

;; GNU General Public License for more details.

;; You should have received a copy of the GNU General Public License

;; along with GCC; see the file COPYING3.  If not see

;; .

;; Special characters after '%':

;;  A  No effect (add 0).

;;  B  Add 1 to REG number, MEM address or CONST_INT.

;;  C  Add 2.

;;  D  Add 3.

;;  j  Branch condition.

;;  k  Reverse branch condition.

;;..m..Constant Direct Data memory address.

;;  i  Print the SFR address quivalent of a CONST_INT or a CONST_INT

;;     RAM address.  The resulting addres is suitable to be used in IN/OUT.

;;  o  Displacement for (mem (plus (reg) (const_int))) operands.

;;  p  POST_INC or PRE_DEC address as a pointer (X, Y, Z)

;;  r  POST_INC or PRE_DEC address as a register (r26, r28, r30)

;; T/T Print operand suitable for BLD/BST instruction, i.e. register and

;;     bit number.  This gets 2 operands: The first %T gets a REG_P and

;;     just cashes the operand for the next %T.  The second %T gets

;;     a CONST_INT that represents a bit position.

;;     Example: With %0 = (reg:HI 18)  and  %1 = (const_int 13)

;;              "%T0%T1" it will print "r19,5".

;;     Notice that you must not write a comma between %T0 and %T1.

;; T/t Similar to above, but don't print the comma and the bit number.

;;     Example: With %0 = (reg:HI 18)  and  %1 = (const_int 13)

;;              "%T0%t1" it will print "r19".

;;..x..Constant Direct Program memory address.

;;  ~  Output 'r' if not AVR_HAVE_JMP_CALL.

;;  !  Output 'e' if AVR_HAVE_EIJMP_EICALL.

(define_constants

  [(REG_X       26)

   (REG_Y       28)

   (REG_Z       30)

   (REG_W       24)

   (REG_SP      32)

   (LPM_REGNO   0)      ; implicit target register of LPM

   (TMP_REGNO   0)      ; temporary register r0

   (ZERO_REGNO  1)      ; zero register r1

   ])

(define_c_enum "unspec"

  [UNSPEC_STRLEN

   UNSPEC_MOVMEM

   UNSPEC_INDEX_JMP

   UNSPEC_FMUL

   UNSPEC_FMULS

   UNSPEC_FMULSU

   UNSPEC_COPYSIGN

   UNSPEC_IDENTITY

   UNSPEC_INSERT_BITS

   ])

(define_c_enum "unspecv"

  [UNSPECV_PROLOGUE_SAVES

   UNSPECV_EPILOGUE_RESTORES

   UNSPECV_WRITE_SP

   UNSPECV_GOTO_RECEIVER

   UNSPECV_ENABLE_IRQS

   UNSPECV_NOP

   UNSPECV_SLEEP

   UNSPECV_WDR

   UNSPECV_DELAY_CYCLES

   ])

(include "predicates.md")

(include "constraints.md")

;; Condition code settings.

(define_attr "cc" "none,set_czn,set_zn,set_n,compare,clobber,

                   out_plus, out_plus_noclobber,ldi"

  (const_string "none"))

(define_attr "type" "branch,branch1,arith,xcall"

  (const_string "arith"))

;; The size of instructions in bytes.

;; XXX may depend from "cc"

(define_attr "length" ""

  (cond [(eq_attr "type" "branch")

         (if_then_else (and (ge (minus (pc) (match_dup 0))

                                (const_int -63))

                            (le (minus (pc) (match_dup 0))

                                (const_int 62)))

                       (const_int 1)

                       (if_then_else (and (ge (minus (pc) (match_dup 0))

                                              (const_int -2045))

                                          (le (minus (pc) (match_dup 0))

                                              (const_int 2045)))

                                     (const_int 2)

                                     (const_int 3)))

         (eq_attr "type" "branch1")

         (if_then_else (and (ge (minus (pc) (match_dup 0))

                                (const_int -62))

                            (le (minus (pc) (match_dup 0))

                                (const_int 61)))

                       (const_int 2)

                       (if_then_else (and (ge (minus (pc) (match_dup 0))

                                              (const_int -2044))

                                          (le (minus (pc) (match_dup 0))

                                              (const_int 2043)))

                                     (const_int 3)

                                     (const_int 4)))

         (eq_attr "type" "xcall")

         (if_then_else (match_test "!AVR_HAVE_JMP_CALL")

                       (const_int 1)

                       (const_int 2))]

        (const_int 2)))

;; Lengths of several insns are adjusted in avr.c:adjust_insn_length().

;; Following insn attribute tells if and how the adjustment has to be

;; done:

;;     no     No adjustment needed; attribute "length" is fine.

;; Otherwise do special processing depending on the attribute.

(define_attr "adjust_len"

  "out_bitop, out_plus, out_plus_noclobber, plus64, addto_sp,

   tsthi, tstpsi, tstsi, compare, compare64, call,

   mov8, mov16, mov24, mov32, reload_in16, reload_in24, reload_in32,

   xload, movmem,

   ashlqi, ashrqi, lshrqi,

   ashlhi, ashrhi, lshrhi,

   ashlsi, ashrsi, lshrsi,

   ashlpsi, ashrpsi, lshrpsi,

   insert_bits,

   no"

  (const_string "no"))

;; Flavours of instruction set architecture (ISA), used in enabled attribute

;; mov  : ISA has no MOVW                movw  : ISA has MOVW

;; rjmp : ISA has no CALL/JMP            jmp   : ISA has CALL/JMP

;; ijmp : ISA has no EICALL/EIJMP        eijmp : ISA has EICALL/EIJMP

;; lpm  : ISA has no LPMX                lpmx  : ISA has LPMX

;; elpm : ISA has ELPM but no ELPMX      elpmx : ISA has ELPMX

;; no_xmega: non-XMEGA core              xmega : XMEGA core

(define_attr "isa"

  "mov,movw, rjmp,jmp, ijmp,eijmp, lpm,lpmx, elpm,elpmx, no_xmega,xmega,

   standard"

  (const_string "standard"))

(define_attr "enabled" ""

  (cond [(eq_attr "isa" "standard")

         (const_int 1)

         (and (eq_attr "isa" "mov")

              (match_test "!AVR_HAVE_MOVW"))

         (const_int 1)

         (and (eq_attr "isa" "movw")

              (match_test "AVR_HAVE_MOVW"))

         (const_int 1)

         (and (eq_attr "isa" "rjmp")

              (match_test "!AVR_HAVE_JMP_CALL"))

         (const_int 1)

         (and (eq_attr "isa" "jmp")

              (match_test "AVR_HAVE_JMP_CALL"))

         (const_int 1)

         (and (eq_attr "isa" "ijmp")

              (match_test "!AVR_HAVE_EIJMP_EICALL"))

         (const_int 1)

         (and (eq_attr "isa" "eijmp")

              (match_test "AVR_HAVE_EIJMP_EICALL"))

         (const_int 1)

         (and (eq_attr "isa" "lpm")

              (match_test "!AVR_HAVE_LPMX"))

         (const_int 1)

         (and (eq_attr "isa" "lpmx")

              (match_test "AVR_HAVE_LPMX"))

         (const_int 1)

         (and (eq_attr "isa" "elpm")

              (match_test "AVR_HAVE_ELPM && !AVR_HAVE_ELPMX"))

         (const_int 1)

         (and (eq_attr "isa" "elpmx")

              (match_test "AVR_HAVE_ELPMX"))

         (const_int 1)

         (and (eq_attr "isa" "xmega")

              (match_test "AVR_XMEGA"))

         (const_int 1)

         (and (eq_attr "isa" "no_xmega")

              (match_test "!AVR_XMEGA"))

         (const_int 1)

         ] (const_int 0)))

;; Define mode iterators

(define_mode_iterator QIHI  [(QI "") (HI "")])

(define_mode_iterator QIHI2 [(QI "") (HI "")])

(define_mode_iterator QISI [(QI "") (HI "") (PSI "") (SI "")])

(define_mode_iterator QIDI [(QI "") (HI "") (PSI "") (SI "") (DI "")])

(define_mode_iterator HISI [(HI "") (PSI "") (SI "")])

;; All supported move-modes

(define_mode_iterator MOVMODE [(QI "") (HI "") (SI "") (SF "") (PSI "")])

;; Define code iterators

;; Define two incarnations so that we can build the cross product.

(define_code_iterator any_extend  [sign_extend zero_extend])

(define_code_iterator any_extend2 [sign_extend zero_extend])

(define_code_iterator xior [xor ior])

(define_code_iterator eqne [eq ne])

;; Define code attributes

(define_code_attr extend_su

  [(sign_extend "s")

   (zero_extend "u")])

(define_code_attr extend_u

  [(sign_extend "")

   (zero_extend "u")])

(define_code_attr extend_s

  [(sign_extend "s")

   (zero_extend "")])

;; Constrain input operand of widening multiply, i.e. MUL resp. MULS.

(define_code_attr mul_r_d

  [(zero_extend "r")

   (sign_extend "d")])

;; Map RTX code to its standard insn name

(define_code_attr code_stdname

  [(ashift   "ashl")

   (ashiftrt "ashr")

   (lshiftrt "lshr")

   (ior      "ior")

   (xor      "xor")

   (rotate   "rotl")])

;;========================================================================

;; The following is used by nonlocal_goto and setjmp.

;; The receiver pattern will create no instructions since internally

;; virtual_stack_vars = hard_frame_pointer + 1 so the RTL become R28=R28

;; This avoids creating add/sub offsets in frame_pointer save/resore.

;; The 'null' receiver also avoids  problems with optimisation

;; not recognising incoming jmp and removing code that resets frame_pointer.

;; The code derived from builtins.c.

(define_expand "nonlocal_goto_receiver"

  [(set (reg:HI REG_Y)

        (unspec_volatile:HI [(const_int 0)] UNSPECV_GOTO_RECEIVER))]

  ""

  {

    emit_move_insn (virtual_stack_vars_rtx,

                    gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx,

                                  gen_int_mode (STARTING_FRAME_OFFSET,

                                                Pmode)));

  /* This might change the hard frame pointer in ways that aren't

    apparent to early optimization passes, so force a clobber.  */

    emit_clobber (hard_frame_pointer_rtx);

    DONE;

  })

;; Defining nonlocal_goto_receiver means we must also define this.

;; even though its function is identical to that in builtins.c

(define_expand "nonlocal_goto"

  [(use (match_operand 0 "general_operand"))

   (use (match_operand 1 "general_operand"))

   (use (match_operand 2 "general_operand"))

   (use (match_operand 3 "general_operand"))]

  ""

{

  rtx r_label = copy_to_reg (operands[1]);

  rtx r_fp = operands[3];

  rtx r_sp = operands[2];

  emit_clobber (gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode)));

  emit_clobber (gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx));

  emit_move_insn (hard_frame_pointer_rtx, r_fp);

  emit_stack_restore (SAVE_NONLOCAL, r_sp);

  emit_use (hard_frame_pointer_rtx);

  emit_use (stack_pointer_rtx);

  emit_indirect_jump (r_label);

  DONE;

})

(define_insn "pushqi1"

  [(set (mem:QI (post_dec:HI (reg:HI REG_SP)))

        (match_operand:QI 0 "reg_or_0_operand" "r,L"))]

  ""

  "@

        push %0

        push __zero_reg__"

  [(set_attr "length" "1,1")])

;; All modes for a multi-byte push.  We must include complex modes here too,

;; lest emit_single_push_insn "helpfully " create the auto-inc itself.

(define_mode_iterator MPUSH

  [(CQI "")

   (HI "") (CHI "")

   (PSI "")

   (SI "") (CSI "")

   (DI "") (CDI "")

   (SF "") (SC "")])

(define_expand "push1"

  [(match_operand:MPUSH 0 "" "")]

  ""

{

  int i;

  for (i = GET_MODE_SIZE (mode) - 1; i >= 0; --i)

    {

      rtx part = simplify_gen_subreg (QImode, operands[0], mode, i);

      if (part != const0_rtx)

        part = force_reg (QImode, part);

      emit_insn (gen_pushqi1 (part));

    }

  DONE;

})

;; Notice a special-case when adding N to SP where N results in a

;; zero REG_ARGS_SIZE.  This is equivalent to a move from FP.

(define_split

  [(set (reg:HI REG_SP) (match_operand:HI 0 "register_operand" ""))]

  "reload_completed

   && frame_pointer_needed

   && !cfun->calls_alloca

   && find_reg_note (insn, REG_ARGS_SIZE, const0_rtx)"

  [(set (reg:HI REG_SP) (reg:HI REG_Y))]

  "")

;;========================================================================

;; Move stuff around

(define_expand "load_libgcc"

  [(set (match_dup 3)

        (match_dup 2))

   (set (reg:MOVMODE 22)

        (match_operand:MOVMODE 1 "memory_operand" ""))

   (set (match_operand:MOVMODE 0 "register_operand" "")

        (reg:MOVMODE 22))]

  "avr_load_libgcc_p (operands[1])"

  {

    operands[3] = gen_rtx_REG (HImode, REG_Z);

    operands[2] = force_operand (XEXP (operands[1], 0), NULL_RTX);

    operands[1] = replace_equiv_address (operands[1], operands[3]);

    set_mem_addr_space (operands[1], ADDR_SPACE_FLASH);

  })

(define_insn "load__libgcc"

  [(set (reg:MOVMODE 22)

        (match_operand:MOVMODE 0 "memory_operand" "m,m"))]

  "avr_load_libgcc_p (operands[0])

   && REG_P (XEXP (operands[0], 0))

   && REG_Z == REGNO (XEXP (operands[0], 0))"

  {

    operands[0] = GEN_INT (GET_MODE_SIZE (mode));

    return "%~call __load_%0";

  }

  [(set_attr "length" "1,2")

   (set_attr "isa" "rjmp,jmp")

   (set_attr "cc" "clobber")])

(define_insn_and_split "xload8_A"

  [(set (match_operand:QI 0 "register_operand" "=r")

        (match_operand:QI 1 "memory_operand"    "m"))

   (clobber (reg:HI REG_Z))]

  "can_create_pseudo_p()

   && !avr_xload_libgcc_p (QImode)

   && avr_mem_memx_p (operands[1])

   && REG_P (XEXP (operands[1], 0))"

  { gcc_unreachable(); }

  "&& 1"

  [(clobber (const_int 0))]

  {

    rtx insn, addr = XEXP (operands[1], 0);

    rtx hi8 = gen_reg_rtx (QImode);

    rtx reg_z = gen_rtx_REG (HImode, REG_Z);

    emit_move_insn (reg_z, simplify_gen_subreg (HImode, addr, PSImode, 0));

    emit_move_insn (hi8, simplify_gen_subreg (QImode, addr, PSImode, 2));

    insn = emit_insn (gen_xload_8 (operands[0], hi8));

    set_mem_addr_space (SET_SRC (single_set (insn)),

                                 MEM_ADDR_SPACE (operands[1]));

    DONE;

  })

(define_insn_and_split "xload_A"

  [(set (match_operand:MOVMODE 0 "register_operand" "=r")

        (match_operand:MOVMODE 1 "memory_operand"    "m"))

   (clobber (reg:QI 21))

   (clobber (reg:HI REG_Z))]

  "can_create_pseudo_p()

   && avr_mem_memx_p (operands[1])

   && REG_P (XEXP (operands[1], 0))"

  { gcc_unreachable(); }

  "&& 1"

  [(clobber (const_int 0))]

  {

    rtx addr = XEXP (operands[1], 0);

    rtx reg_z = gen_rtx_REG (HImode, REG_Z);

    rtx addr_hi8 = simplify_gen_subreg (QImode, addr, PSImode, 2);

    addr_space_t as = MEM_ADDR_SPACE (operands[1]);

    rtx insn;

    /* Split the address to R21:Z */

    emit_move_insn (reg_z, simplify_gen_subreg (HImode, addr, PSImode, 0));

    emit_move_insn (gen_rtx_REG (QImode, 21), addr_hi8);

    /* Load with code from libgcc */

    insn = emit_insn (gen_xload__libgcc ());

    set_mem_addr_space (SET_SRC (single_set (insn)), as);

    /* Move to destination */

    emit_move_insn (operands[0], gen_rtx_REG (mode, 22));

    DONE;

  })

;; Move value from address space memx to a register

;; These insns must be prior to respective generic move insn.

(define_insn "xload_8"

  [(set (match_operand:QI 0 "register_operand"                   "=&r,r")

        (mem:QI (lo_sum:PSI (match_operand:QI 1 "register_operand" "r,r")

                            (reg:HI REG_Z))))]

  "!avr_xload_libgcc_p (QImode)"

  {

    return avr_out_xload (insn, operands, NULL);

  }

  [(set_attr "length" "3,4")

   (set_attr "adjust_len" "*,xload")

   (set_attr "isa" "lpmx,lpm")

   (set_attr "cc" "none")])

;; R21:Z : 24-bit source address

;; R22   : 1-4 byte output

;; "xload_qi_libgcc"

;; "xload_hi_libgcc"

;; "xload_psi_libgcc"

;; "xload_si_libgcc"

;; "xload_sf_libgcc"

(define_insn "xload__libgcc"

  [(set (reg:MOVMODE 22)

        (mem:MOVMODE (lo_sum:PSI (reg:QI 21)

                                 (reg:HI REG_Z))))

   (clobber (reg:QI 21))

   (clobber (reg:HI REG_Z))]

  "avr_xload_libgcc_p (mode)"

  {

    rtx x_bytes = GEN_INT (GET_MODE_SIZE (mode));

    output_asm_insn ("%~call __xload_%0", &x_bytes);

    return "";

  }

  [(set_attr "type" "xcall")

   (set_attr "cc" "clobber")])

;; General move expanders

;; "movqi"

;; "movhi"

;; "movsi"

;; "movsf"

;; "movpsi"

(define_expand "mov"

  [(set (match_operand:MOVMODE 0 "nonimmediate_operand" "")

        (match_operand:MOVMODE 1 "general_operand" ""))]

  ""

  {

    rtx dest = operands[0];

    rtx src  = operands[1];

    if (avr_mem_flash_p (dest))

      DONE;

    /* One of the operands has to be in a register.  */

    if (!register_operand (dest, mode)

        && !(register_operand (src, mode)

             || src == CONST0_RTX (mode)))

      {

        operands[1] = src = copy_to_mode_reg (mode, src);

      }

  if (avr_mem_memx_p (src))

    {

      rtx addr = XEXP (src, 0);

      if (!REG_P (addr))

        src = replace_equiv_address (src, copy_to_mode_reg (PSImode, addr));

      if (!avr_xload_libgcc_p (mode))

        emit_insn (gen_xload8_A (dest, src));

      else

        emit_insn (gen_xload_A (dest, src));

      DONE;

    }

    if (avr_load_libgcc_p (src))

      {

        /* For the small devices, do loads per libgcc call.  */

        emit_insn (gen_load_libgcc (dest, src));

        DONE;

      }

  })

;;========================================================================

;; move byte

;; The last alternative (any immediate constant to any register) is

;; very expensive.  It should be optimized by peephole2 if a scratch

;; register is available, but then that register could just as well be

;; allocated for the variable we are loading.  But, most of NO_LD_REGS

;; are call-saved registers, and most of LD_REGS are call-used registers,

;; so this may still be a win for registers live across function calls.

(define_insn "movqi_insn"

  [(set (match_operand:QI 0 "nonimmediate_operand" "=r ,d,Qm,r ,q,r,*r")

        (match_operand:QI 1 "nox_general_operand"   "rL,i,rL,Qm,r,q,i"))]

  "register_operand (operands[0], QImode)

   || register_operand (operands[1], QImode)

   || const0_rtx == operands[1]"

  {

    return output_movqi (insn, operands, NULL);

  }

  [(set_attr "length" "1,1,5,5,1,1,4")

   (set_attr "adjust_len" "mov8")

   (set_attr "cc" "ldi,none,clobber,clobber,none,none,clobber")])

;; This is used in peephole2 to optimize loading immediate constants

;; if a scratch register from LD_REGS happens to be available.

(define_insn "*reload_inqi"

  [(set (match_operand:QI 0 "register_operand" "=l")

        (match_operand:QI 1 "immediate_operand" "i"))

   (clobber (match_operand:QI 2 "register_operand" "=&d"))]

  "reload_completed"

  "ldi %2,lo8(%1)

        mov %0,%2"

  [(set_attr "length" "2")

   (set_attr "cc" "none")])

(define_peephole2

  [(match_scratch:QI 2 "d")

   (set (match_operand:QI 0 "l_register_operand" "")

        (match_operand:QI 1 "immediate_operand" ""))]

  "(operands[1] != const0_rtx

    && operands[1] != const1_rtx

    && operands[1] != constm1_rtx)"

  [(parallel [(set (match_dup 0) (match_dup 1))

              (clobber (match_dup 2))])]

  "")

;;============================================================================

;; move word (16 bit)

;; Move register $1 to the Stack Pointer register SP.

;; This insn is emit during function prologue/epilogue generation.

;;    $2 =  0: We know that IRQs are off

;;    $2 =  1: We know that IRQs are on

;;    $2 =  2: SP has 8 bits only, IRQ state does not matter

;;    $2 = -1: We don't know anything about IRQ on/off

;; Always write SP via unspec, see PR50063

(define_insn "movhi_sp_r"

  [(set (match_operand:HI 0 "stack_register_operand"                "=q,q,q,q,q")

        (unspec_volatile:HI [(match_operand:HI 1 "register_operand"  "r,r,r,r,r")

                             (match_operand:HI 2 "const_int_operand" "L,P,N,K,LPN")]

                            UNSPECV_WRITE_SP))]

  ""

  "@

        out %B0,%B1\;out %A0,%A1

        cli\;out %B0,%B1\;sei\;out %A0,%A1

        in __tmp_reg__,__SREG__\;cli\;out %B0,%B1\;out __SREG__,__tmp_reg__\;out %A0,%A1

        out %A0,%A1

        out %A0,%A1\;out %B0,%B1"

  [(set_attr "length" "2,4,5,1,2")

   (set_attr "isa" "no_xmega,no_xmega,no_xmega,*,xmega")

   (set_attr "cc" "none")])

(define_peephole2

  [(match_scratch:QI 2 "d")

   (set (match_operand:HI 0 "l_register_operand" "")

        (match_operand:HI 1 "immediate_operand" ""))]

  "(operands[1] != const0_rtx

    && operands[1] != constm1_rtx)"

  [(parallel [(set (match_dup 0) (match_dup 1))

              (clobber (match_dup 2))])]

  "")

;; '*' because it is not used in rtl generation, only in above peephole

(define_insn "*reload_inhi"

  [(set (match_operand:HI 0 "register_operand" "=r")

        (match_operand:HI 1 "immediate_operand" "i"))

   (clobber (match_operand:QI 2 "register_operand" "=&d"))]

  "reload_completed"

  {

    return output_reload_inhi (operands, operands[2], NULL);

  }

  [(set_attr "length" "4")

   (set_attr "adjust_len" "reload_in16")

   (set_attr "cc" "none")])

(define_insn "*movhi"

  [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m ,d,*r,q,r")

        (match_operand:HI 1 "nox_general_operand"   "r,L,m,rL,i,i ,r,q"))]

  "register_operand (operands[0], HImode)

   || register_operand (operands[1], HImode)

   || const0_rtx == operands[1]"

  {

    return output_movhi (insn, operands, NULL);

  }

  [(set_attr "length" "2,2,6,7,2,6,5,2")

   (set_attr "adjust_len" "mov16")

   (set_attr "cc" "none,none,clobber,clobber,none,clobber,none,none")])

(define_peephole2 ; movw

  [(set (match_operand:QI 0 "even_register_operand" "")

        (match_operand:QI 1 "even_register_operand" ""))

   (set (match_operand:QI 2 "odd_register_operand" "")

        (match_operand:QI 3 "odd_register_operand" ""))]

  "(AVR_HAVE_MOVW

    && REGNO (operands[0]) == REGNO (operands[2]) - 1

    && REGNO (operands[1]) == REGNO (operands[3]) - 1)"

  [(set (match_dup 4) (match_dup 5))]

  {

    operands[4] = gen_rtx_REG (HImode, REGNO (operands[0]));

    operands[5] = gen_rtx_REG (HImode, REGNO (operands[1]));

  })

(define_peephole2 ; movw_r

  [(set (match_operand:QI 0 "odd_register_operand" "")

        (match_operand:QI 1 "odd_register_operand" ""))

   (set (match_operand:QI 2 "even_register_operand" "")

        (match_operand:QI 3 "even_register_operand" ""))]

  "(AVR_HAVE_MOVW

    && REGNO (operands[2]) == REGNO (operands[0]) - 1

    && REGNO (operands[3]) == REGNO (operands[1]) - 1)"

  [(set (match_dup 4) (match_dup 5))]

  {

    operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));

    operands[5] = gen_rtx_REG (HImode, REGNO (operands[3]));

  })

;; For LPM loads from AS1 we split

;;    R = *Z

;; to

;;    R = *Z++

;;    Z = Z - sizeof (R)

;;

;; so that the second instruction can be optimized out.

(define_split ; "split-lpmx"

  [(set (match_operand:HISI 0 "register_operand" "")

        (match_operand:HISI 1 "memory_operand" ""))]

  "reload_completed

   && AVR_HAVE_LPMX"

  [(set (match_dup 0)

        (match_dup 2))

   (set (match_dup 3)

        (plus:HI (match_dup 3)

                 (match_dup 4)))]

  {

     rtx addr = XEXP (operands[1], 0);

     if (!avr_mem_flash_p (operands[1])

         || !REG_P (addr)

         || reg_overlap_mentioned_p (addr, operands[0]))

       {

         FAIL;

       }

    operands[2] = replace_equiv_address (operands[1],

                                         gen_rtx_POST_INC (Pmode, addr));

    operands[3] = addr;

    operands[4] = gen_int_mode (-GET_MODE_SIZE (mode), HImode);

  })

;;==========================================================================

;; xpointer move (24 bit)

(define_peephole2 ; *reload_inpsi

  [(match_scratch:QI 2 "d")

   (set (match_operand:PSI 0 "l_register_operand" "")

        (match_operand:PSI 1 "immediate_operand" ""))

   (match_dup 2)]

  "operands[1] != const0_rtx

   && operands[1] != constm1_rtx"

  [(parallel [(set (match_dup 0)

                   (match_dup 1))

              (clobber (match_dup 2))])]

  "")

;; '*' because it is not used in rtl generation.

(define_insn "*reload_inpsi"

  [(set (match_operand:PSI 0 "register_operand" "=r")

        (match_operand:PSI 1 "immediate_operand" "i"))

   (clobber (match_operand:QI 2 "register_operand" "=&d"))]

  "reload_completed"

  {

    return avr_out_reload_inpsi (operands, operands[2], NULL);

  }

  [(set_attr "length" "6")

   (set_attr "adjust_len" "reload_in24")

   (set_attr "cc" "clobber")])

(define_insn "*movpsi"

  [(set (match_operand:PSI 0 "nonimmediate_operand" "=r,r,r ,Qm,!d,r")

        (match_operand:PSI 1 "nox_general_operand"   "r,L,Qm,rL,i ,i"))]

  "register_operand (operands[0], PSImode)

   || register_operand (operands[1], PSImode)

   || const0_rtx == operands[1]"

  {

    return avr_out_movpsi (insn, operands, NULL);

  }

  [(set_attr "length" "3,3,8,9,4,10")

   (set_attr "adjust_len" "mov24")

   (set_attr "cc" "none,none,clobber,clobber,none,clobber")])

;;==========================================================================

;; move double word (32 bit)

(define_peephole2 ; *reload_insi

  [(match_scratch:QI 2 "d")

   (set (match_operand:SI 0 "l_register_operand" "")

        (match_operand:SI 1 "const_int_operand" ""))

   (match_dup 2)]

  "(operands[1] != const0_rtx

    && operands[1] != constm1_rtx)"

  [(parallel [(set (match_dup 0) (match_dup 1))

              (clobber (match_dup 2))])]

  "")

;; '*' because it is not used in rtl generation.

(define_insn "*reload_insi"

  [(set (match_operand:SI 0 "register_operand" "=r")

        (match_operand:SI 1 "const_int_operand" "n"))

   (clobber (match_operand:QI 2 "register_operand" "=&d"))]

  "reload_completed"

  {

    return output_reload_insisf (operands, operands[2], NULL);

  }

  [(set_attr "length" "8")

   (set_attr "adjust_len" "reload_in32")

   (set_attr "cc" "clobber")])

(define_insn "*movsi"

  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r ,Qm,!d,r")

        (match_operand:SI 1 "nox_general_operand"   "r,L,Qm,rL,i ,i"))]

  "register_operand (operands[0], SImode)

   || register_operand (operands[1], SImode)

   || const0_rtx == operands[1]"

  {

    return output_movsisf (insn, operands, NULL);

  }

  [(set_attr "length" "4,4,8,9,4,10")

   (set_attr "adjust_len" "mov32")

   (set_attr "cc" "none,none,clobber,clobber,none,clobber")])

;; fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff

;; move floating point numbers (32 bit)

(define_insn "*movsf"

  [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,r ,Qm,!d,r")

        (match_operand:SF 1 "nox_general_operand"   "r,G,Qm,rG,F ,F"))]

  "register_operand (operands[0], SFmode)

   || register_operand (operands[1], SFmode)

   || operands[1] == CONST0_RTX (SFmode)"

  {

    return output_movsisf (insn, operands, NULL);

  }

  [(set_attr "length" "4,4,8,9,4,10")

   (set_attr "adjust_len" "mov32")

   (set_attr "cc" "none,none,clobber,clobber,none,clobber")])

(define_peephole2 ; *reload_insf

  [(match_scratch:QI 2 "d")

   (set (match_operand:SF 0 "l_register_operand" "")

        (match_operand:SF 1 "const_double_operand" ""))

   (match_dup 2)]

  "operands[1] != CONST0_RTX (SFmode)"

  [(parallel [(set (match_dup 0)

                   (match_dup 1))

              (clobber (match_dup 2))])]

  "")

;; '*' because it is not used in rtl generation.

(define_insn "*reload_insf"

  [(set (match_operand:SF 0 "register_operand" "=r")

        (match_operand:SF 1 "const_double_operand" "F"))

   (clobber (match_operand:QI 2 "register_operand" "=&d"))]

  "reload_completed"

  {

    return output_reload_insisf (operands, operands[2], NULL);

  }

  [(set_attr "length" "8")

   (set_attr "adjust_len" "reload_in32")

   (set_attr "cc" "clobber")])

;;=========================================================================

;; move string (like memcpy)

(define_expand "movmemhi"

  [(parallel [(set (match_operand:BLK 0 "memory_operand" "")

                   (match_operand:BLK 1 "memory_operand" ""))

              (use (match_operand:HI 2 "const_int_operand" ""))

              (use (match_operand:HI 3 "const_int_operand" ""))])]

  ""

  {

    if (avr_emit_movmemhi (operands))

      DONE;

    FAIL;

  })

(define_mode_attr MOVMEM_r_d [(QI "r")

                              (HI "wd")])

;; $0     : Address Space

;; $1, $2 : Loop register

;; R30    : source address

;; R26    : destination address

;; "movmem_qi"

;; "movmem_hi"

(define_insn "movmem_"

  [(set (mem:BLK (reg:HI REG_X))

        (mem:BLK (reg:HI REG_Z)))

   (unspec [(match_operand:QI 0 "const_int_operand" "n")]

           UNSPEC_MOVMEM)

   (use (match_operand:QIHI 1 "register_operand" ""))

   (clobber (reg:HI REG_X))

   (clobber (reg:HI REG_Z))

   (clobber (reg:QI LPM_REGNO))

   (clobber (match_operand:QIHI 2 "register_operand" "=1"))]

  ""

  {

    return avr_out_movmem (insn, operands, NULL);

  }

  [(set_attr "adjust_len" "movmem")

   (set_attr "cc" "clobber")])

;; $0    : Address Space

;; $1    : RAMPZ RAM address

;; R24   : #bytes and loop register

;; R23:Z : 24-bit source address

;; R26   : 16-bit destination address

;; "movmemx_qi"

;; "movmemx_hi"

(define_insn "movmemx_"

  [(set (mem:BLK (reg:HI REG_X))

        (mem:BLK (lo_sum:PSI (reg:QI 23)

                             (reg:HI REG_Z))))

   (unspec [(match_operand:QI 0 "const_int_operand" "n")]

           UNSPEC_MOVMEM)

   (use (reg:QIHI 24))

   (clobber (reg:HI REG_X))

   (clobber (reg:HI REG_Z))

   (clobber (reg:QI LPM_REGNO))

   (clobber (reg:HI 24))

   (clobber (reg:QI 23))

   (clobber (mem:QI (match_operand:QI 1 "io_address_operand" "n")))]

  ""

  "%~call __movmemx_"

  [(set_attr "type" "xcall")

   (set_attr "cc" "clobber")])

;; =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2

;; memset (%0, %2, %1)

(define_expand "setmemhi"

  [(parallel [(set (match_operand:BLK 0 "memory_operand" "")

                   (match_operand 2 "const_int_operand" ""))

              (use (match_operand:HI 1 "const_int_operand" ""))

              (use (match_operand:HI 3 "const_int_operand" ""))

              (clobber (match_scratch:HI 4 ""))

              (clobber (match_dup 5))])]

  ""

  {

    rtx addr0;

    enum machine_mode mode;

    /* If value to set is not zero, use the library routine.  */

    if (operands[2] != const0_rtx)

      FAIL;

    if (!CONST_INT_P (operands[1]))

      FAIL;

    mode = u8_operand (operands[1], VOIDmode) ? QImode : HImode;

    operands[5] = gen_rtx_SCRATCH (mode);

    operands[1] = copy_to_mode_reg (mode,

                                    gen_int_mode (INTVAL (operands[1]), mode));

    addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));

    operands[0] = gen_rtx_MEM (BLKmode, addr0);

  })