OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [config/] [bfin/] [bfin-modes.def] - Blame information for rev 801

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 709 jeremybenn
/* Definitions of target machine for GNU compiler, for Blackfin.
2
   Copyright (C) 2005, 2007 Free Software Foundation, Inc.
3
   Contributed by Analog Devices.
4
 
5
   This file is part of GCC.
6
 
7
   GCC is free software; you can redistribute it and/or modify it
8
   under the terms of the GNU General Public License as published
9
   by the Free Software Foundation; either version 3, or (at your
10
   option) any later version.
11
 
12
   GCC is distributed in the hope that it will be useful, but WITHOUT
13
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
15
   License for more details.
16
 
17
   You should have received a copy of the GNU General Public License
18
   along with GCC; see the file COPYING3.  If not see
19
   .  */
20
 
21
/* PDImode for the 40-bit accumulators.  */
22
PARTIAL_INT_MODE (DI);
23
 
24
/* Two of those - covering both accumulators for vector multiplications.  */
25
VECTOR_MODE (INT, PDI, 2);
26
 
27
VECTOR_MODE (INT, HI, 2); /* V2HI */
28
VECTOR_MODE (INT, SI, 2); /* V2SI - occasionally used.  */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.