OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [config/] [bfin/] [elf.h] - Blame information for rev 801

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 709 jeremybenn
/* Copyright (C) 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
2
 
3
This file is part of GCC.
4
 
5
GCC is free software; you can redistribute it and/or modify it under
6
the terms of the GNU General Public License as published by the Free
7
Software Foundation; either version 3, or (at your option) any later
8
version.
9
 
10
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
11
WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
13
for more details.
14
 
15
Under Section 7 of GPL version 3, you are granted additional
16
permissions described in the GCC Runtime Library Exception, version
17
3.1, as published by the Free Software Foundation.
18
 
19
You should have received a copy of the GNU General Public License and
20
a copy of the GCC Runtime Library Exception along with this program;
21
see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
22
<http://www.gnu.org/licenses/>.  */
23
 
24
#undef  STARTFILE_SPEC
25
#define STARTFILE_SPEC "\
26
%{msim:%{!shared:crt0%O%s}} \
27
%{!msim:%{!mcpu=bf561*:%{!msdram:basiccrt%O%s} %{msdram:basiccrts%O%s};: \
28
                       %{!msdram:basiccrt561%O%s} %{msdram:basiccrt561s%O%s}} \
29
        %{mcpu=bf561*:%{mmulticore:%{!mcorea:%{!mcoreb:basiccrt561b%O%s}}}}} \
30
crti%O%s crtbegin%O%s crtlibid%O%s"
31
 
32
#undef  ENDFILE_SPEC
33
#define ENDFILE_SPEC    "crtend%O%s crtn%O%s"
34
 
35
#undef  LIB_SPEC
36
#define LIB_SPEC "--start-group -lc %{msim:-lsim}%{!msim:-lnosys} --end-group \
37
%{!T*:%{!msim:%{!msdram: \
38
              %{mcpu=bf512*:-T bf512.ld%s}%{mcpu=bf514*:-T bf514.ld%s} \
39
              %{mcpu=bf516*:-T bf516.ld%s}%{mcpu=bf518*:-T bf518.ld%s} \
40
              %{mcpu=bf522*:-T bf522.ld%s}%{mcpu=bf523*:-T bf523.ld%s} \
41
              %{mcpu=bf524*:-T bf524.ld%s}%{mcpu=bf525*:-T bf525.ld%s} \
42
              %{mcpu=bf526*:-T bf526.ld%s}%{mcpu=bf527*:-T bf527.ld%s} \
43
              %{mcpu=bf531*:-T bf531.ld%s}%{mcpu=bf532*:-T bf532.ld%s} \
44
              %{mcpu=bf533*:-T bf533.ld%s}%{mcpu=bf534*:-T bf534.ld%s} \
45
              %{mcpu=bf536*:-T bf536.ld%s}%{mcpu=bf537*:-T bf537.ld%s} \
46
              %{mcpu=bf538*:-T bf538.ld%s}%{mcpu=bf539*:-T bf539.ld%s} \
47
              %{mcpu=bf542*:-T bf542.ld%s}%{mcpu=bf544*:-T bf544.ld%s} \
48
              %{mcpu=bf547*:-T bf547.ld%s}%{mcpu=bf548*:-T bf548.ld%s} \
49
              %{mcpu=bf549*:-T bf549.ld%s} \
50
              %{mcpu=bf561*:%{!mmulticore:-T bf561.ld%s} \
51
                            %{mmulticore:%{mcorea:-T bf561a.ld%s}} \
52
                            %{mmulticore:%{mcoreb:-T bf561b.ld%s}} \
53
                            %{mmulticore:%{!mcorea:%{!mcoreb:-T bf561m.ld%s}}}} \
54
              %{mcpu=bf592*:-T bf592.ld%s} \
55
              %{!mcpu=*:%eno processor type specified for linking} \
56
              %{!mcpu=bf561*:-T bfin-common-sc.ld%s} \
57
              %{mcpu=bf561*:%{!mmulticore:-T bfin-common-sc.ld%s} \
58
                           %{mmulticore:-T bfin-common-mc.ld%s}}}}}"
59
 
60
#undef USER_LABEL_PREFIX
61
#define USER_LABEL_PREFIX "_"
62
 
63
#ifdef __BFIN_FDPIC__
64
#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC)      \
65
asm (SECTION_OP); \
66
asm ("P3 = [SP + 20];\n\tcall " USER_LABEL_PREFIX #FUNC ";"); \
67
asm (TEXT_SECTION_ASM_OP);
68
#endif
69
 
70
#undef SUBTARGET_DRIVER_SELF_SPECS
71
#define SUBTARGET_DRIVER_SELF_SPECS \
72
     "%{mfdpic:-msim} %{mid-shared-library:-msim}"
73
 
74
#define NO_IMPLICIT_EXTERN_C

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.