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1 709 jeremybenn
;; Predicates of machine description for CR16.
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;; Copyright (C) 2012 Free Software Foundation, Inc.
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;; Contributed by KPIT Cummins Infosystems Limited.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;;
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
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;; License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3.  If not see
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;; .
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;;  Predicates
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;; Predicates for sbit/cbit instructions
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;; bit operand used for the generation of bit insn generation
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(define_predicate "bit_operand"
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  (match_code "mem")
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{
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  return ((GET_CODE (op) == MEM && OK_FOR_Z (op)));
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})
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;; Unsigned 4-bits constant int or double value.
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(define_predicate "u4bits_operand"
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  (match_code "const_int,const_double")
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{
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  if (GET_CODE (op) == CONST_DOUBLE)
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    return cr16_const_double_ok (op);
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    return (UNSIGNED_INT_FITS_N_BITS(INTVAL (op), 4)) ? 1 : 0;
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})
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;; Operand is a constant integer where
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;; only one bit is set to 1.
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(define_predicate "one_bit_operand"
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  (match_code "const_int")
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{
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  unsigned int val;
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  val = INTVAL (op);
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  if (mode == QImode)
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    val &= 0xff;
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  else if (mode == HImode)
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    val &= 0xffff;
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  else
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    gcc_unreachable();
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  if (val != 0)
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    return (val & (val - 1)) == 0; /* true if only one bit is set.  */
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  else
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    return 0;
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})
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;; Operand is a constant integer where
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;; only one bit is set to 0.
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(define_predicate "rev_one_bit_operand"
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  (match_code "const_int")
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{
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  unsigned int val;
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  val = ~INTVAL (op); /* Invert and use.  */
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  if (mode == QImode)
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    val &= 0xff;
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  else if (mode == HImode)
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    val &= 0xffff;
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  else
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    gcc_unreachable();
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  if (val != 0)
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    return (val & (val - 1)) == 0; /* true if only one bit is set.  */
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  else
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    return 0;
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})
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;; Predicates for shift instructions
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;; Immediate operand predicate for count in shift operations.
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;; Immediate shall be 3-bits in case operand to be operated on
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;; is a qi mode operand.
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(define_predicate "shift_qi_imm_operand"
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  (match_code "const_int")
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{
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  return (UNSIGNED_INT_FITS_N_BITS(INTVAL (op), 3)) ? 1 : 0;
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})
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;; Immediate shall be 4-bits in case operand to be operated on
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;; is a hi mode operand.
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(define_predicate "shift_hi_imm_operand"
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  (match_code "const_int")
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{
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  return (UNSIGNED_INT_FITS_N_BITS(INTVAL (op), 4)) ? 1 : 0;
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})
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;; Immediate shall be 3-bits in case operand to be operated on
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;; is a si mode operand.
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(define_predicate "shift_si_imm_operand"
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  (match_code "const_int")
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{
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  return (UNSIGNED_INT_FITS_N_BITS(INTVAL (op), 5)) ? 1 : 0;
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})
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;; Predicates for jump/call instructions
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;; Jump immediate cannot be more than 24-bits
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(define_predicate "jump_imm_operand"
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  (match_code "const_int")
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{
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  return (UNSIGNED_INT_FITS_N_BITS(INTVAL (op), 24)) ? 1 : 0;
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})
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;; Call immediate cannot be more than 24-bits
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(define_predicate "call_imm_operand"
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  (match_operand 0 "immediate_operand")
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{
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  if (GET_CODE (op) != CONST_INT) return 1;
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    return (UNSIGNED_INT_FITS_N_BITS(INTVAL (op), 24)) ? 1 : 0;
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})
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;; Operand is register or 4-bit immediate operand
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(define_predicate "reg_or_u4bits_operand"
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  (ior (match_operand 0 "u4bits_operand")
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       (match_operand 0 "register_operand")))
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;; Operand is a register or symbol reference
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(define_predicate "reg_or_sym_operand"
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  (ior (match_code "symbol_ref")
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       (match_operand 0 "register_operand")))
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;; Operand is a non stack pointer register
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(define_predicate "nosp_reg_operand"
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  (and (match_operand 0 "register_operand")
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       (match_test "REGNO (op) != SP_REGNUM")))
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(define_predicate "hard_reg_operand"
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  (and (match_operand 0 "register_operand")
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       (match_test "REGNO (op) <= 15")))
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;; Operand is a memory reference and
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;; not a push operand.
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(define_predicate "store_operand"
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  (and (match_operand 0 "memory_operand")
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       (not (match_operand 0 "push_operand"))))
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;; Helper predicate
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(define_predicate "reg_or_int_operand"
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  (ior (match_code "const_int")
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       (match_operand 0 "register_operand")))
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;;
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;;
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;; Atithmetic/logical predicates
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;; QI Helper
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(define_predicate "arith_qi_operand"
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   (match_code "const_int")
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{
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        return (IN_RAN(INTVAL (op), 0, 15) && ((INTVAL (op) != 9)
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                || (INTVAL (op) != 11))) ? 1 : 0 ;
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})
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;;QI Reg, subreg(reg) or const_int.
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(define_predicate "reg_qi_int_operand"
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  (ior (match_operand 0 "arith_qi_operand")
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       (match_operand 0 "register_operand")))
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;; HI Helper
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(define_predicate "arith_hi_operand"
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   (match_code "const_int")
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{
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        return (IN_RAN(INTVAL (op), -32768, 32768) ) ? 1 : 0 ;
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})
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;;HI Reg, subreg(reg) or const_int.
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(define_predicate "reg_hi_int_operand"
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  (ior (match_operand 0 "arith_hi_operand")
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       (match_operand 0 "register_operand")))
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;;SI Reg, subreg(reg) or const_int.
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(define_predicate "reg_si_int_operand"
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  (ior (match_operand 0 "const_int_operand")
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       (match_operand 0 "register_operand")))
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;;
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;; Shift predicates
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;; QI Helper
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(define_predicate "shift_qi_operand"
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   (match_code "const_int")
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{
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        return (IN_RAN(INTVAL (op), 0, 7) ) ? 1 : 0;
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})
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;;QI Reg, subreg(reg) or const_int.
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(define_predicate "shift_reg_qi_int_operand"
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  (ior (match_operand 0 "shift_qi_operand")
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       (match_operand 0 "register_operand")))
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;; HI Helper
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(define_predicate "shift_hi_operand"
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   (match_code "const_int")
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{
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        return (IN_RAN(INTVAL (op), 0, 15) ) ? 1 : 0 ;
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})
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;;HI Reg, subreg(reg) or const_int.
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(define_predicate "shift_reg_hi_int_operand"
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  (ior (match_operand 0 "shift_hi_operand")
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       (match_operand 0 "register_operand")))
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;; SI Helper
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(define_predicate "shift_si_operand"
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   (match_code "const_int")
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{
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        return (IN_RAN(INTVAL (op), 0, 31) ) ? 1 : 0;
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})
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;;SI Reg, subreg(reg) or const_int.
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(define_predicate "shift_reg_si_int_operand"
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  (ior (match_operand 0 "shift_si_operand")
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       (match_operand 0 "register_operand")))

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