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1 709 jeremybenn
;; DFA scheduling description for EPIPHANY
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;; Copyright (C) 2004, 2006, 2007, 2009 Free Software Foundation, Inc.
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;; Contributed by Embecosm on behalf of Adapteva, Inc.
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;; This file is part of GCC.
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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;; GNU General Public License for more details.
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3.  If not see
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;; .
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;; Two automata are defined to reduce number of states
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;; which a single large automaton will have. (Factoring)
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(define_automaton "inst_pipeline,fpu_pipe")
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;; This unit is basically the decode unit of the processor.
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;; Since epiphany is a dual issue machine, it is as if there are two
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;; units so that any insn can be processed by either one
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;; of the decoding unit.
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(define_cpu_unit "pipe_01,pipe_02" "inst_pipeline")
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;; The fixed point arithmetic unit.
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(define_cpu_unit  "int" "inst_pipeline")
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;; The floating point unit.
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(define_cpu_unit "F0" "fpu_pipe")
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;; ----------------------------------------------------
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;; This reservation is to simplify the dual issue description.
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(define_reservation  "issue"  "pipe_01|pipe_02")
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;; This is to express instructions that cannot be paired.
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(define_reservation  "d_lock" "pipe_01+pipe_02")
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;; We don't model all pipeline stages; we model the issue stage
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;; inasmuch as we allow only two instructions to issue simultaneously,
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;; and flow instructions prevent any simultaneous issue of another instruction.
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;; (This uses pipe_01 and pipe_02).
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;; Double issue of 'other' insns is prevented by using the int unit in the
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;; E1 stage.
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;; Double issue of float instructions is prevented by using F0 in the E1 stage.
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(define_insn_reservation "simple_arith" 2
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  (and (eq_attr "pipe_model" "epiphany")
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       (eq_attr "type" "move,cmove,compare,shift,misc,mul")
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       (eq_attr "length" "4"))
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  "issue,int")
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; anything but fp / fp_int has a bypass
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(define_bypass 1 "simple_arith" "simple_arith,simple_arith_2,simple_arith_4,load,store,branch,call,flow")
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(define_insn_reservation "simple_arith_2" 2
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  (and (eq_attr "pipe_model" "epiphany")
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       (eq_attr "type" "move,cmove,compare,shift,misc,mul")
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       (eq_attr "length" "8"))
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  "issue,issue+int,int")
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(define_insn_reservation "simple_arith_4" 4
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  (and (eq_attr "pipe_model" "epiphany")
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       (eq_attr "type" "move,compare,shift,misc,mul")
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       (eq_attr "length" "12,16,20,24"))
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  "issue,issue+int,issue+int,issue+int,int")
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;; Loads have a latency of two.
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;; Note that we fix up the latency of post_modify in epiphany.c:epiphany_adjust_cost
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(define_insn_reservation "load" 3
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  (and (eq_attr "pipe_model" "epiphany")
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       (eq_attr "type" "load"))
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  "issue,int")
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; anything but fp / fp_int has a bypass
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(define_bypass 2 "load" "simple_arith,simple_arith_2,simple_arith_4,load,store,branch,call,flow")
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(define_insn_reservation "store" 1
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  (and (eq_attr "pipe_model" "epiphany")
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       (eq_attr "type" "store"))
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  "issue,int")
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;; Branch
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;; Latency when taken:  3
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;; Issue Rate:  1
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;; The latency is 1 when the branch is not taken.
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;; We can't really do much with the latency, even if we could express it,
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;; but the pairing restrictions are useful to take into account.
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(define_insn_reservation "branch"  1
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  (and (eq_attr "pipe_model" "epiphany")
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       (eq_attr "type" "branch,uncond_branch"))
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  "d_lock")
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;; calls introduce a longisch delay that is likely to flush the pipelines
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;; of the caller's instructions.  Both the call instruction itself and
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;; the rts at the end of the call / sfunc incurs a three cycle penalty,
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;; thus also isolating the scheduling of caller and callee.
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(define_insn_reservation "call" 8
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  (and (eq_attr "pipe_model" "epiphany")
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       (eq_attr "type" "call,sfunc,fp_sfunc"))
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  "d_lock*8")
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(define_insn_reservation "flow" 1
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  (and (eq_attr "pipe_model" "epiphany")
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       (eq_attr "type" "flow"))
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  "d_lock")
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(define_insn_reservation "fp_arith_trunc"  3
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  (and (eq_attr "pipe_model" "epiphany")
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       (and (eq_attr "type" "fp,fp_int")
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            (eq_attr "rounding" "trunc")))
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  "issue,F0")
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(define_insn_reservation "fp_arith_nearest"  5
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  (and (eq_attr "pipe_model" "epiphany")
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       (and (eq_attr "type" "fp,fp_int")
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            (eq_attr "rounding" "nearest")))
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  "issue,F0")
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(define_bypass 2 "fp_arith_trunc" "store")
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(define_bypass 4 "fp_arith_nearest" "store")

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