OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [config/] [frv/] [frv.c] - Blame information for rev 713

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 709 jeremybenn
/* Copyright (C) 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2005, 2006, 2007,
2
   2008, 2009, 2010, 2011  Free Software Foundation, Inc.
3
   Contributed by Red Hat, Inc.
4
 
5
This file is part of GCC.
6
 
7
GCC is free software; you can redistribute it and/or modify
8
it under the terms of the GNU General Public License as published by
9
the Free Software Foundation; either version 3, or (at your option)
10
any later version.
11
 
12
GCC is distributed in the hope that it will be useful,
13
but WITHOUT ANY WARRANTY; without even the implied warranty of
14
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15
GNU General Public License for more details.
16
 
17
You should have received a copy of the GNU General Public License
18
along with GCC; see the file COPYING3.  If not see
19
<http://www.gnu.org/licenses/>.  */
20
 
21
#include "config.h"
22
#include "system.h"
23
#include "coretypes.h"
24
#include "tm.h"
25
#include "rtl.h"
26
#include "tree.h"
27
#include "regs.h"
28
#include "hard-reg-set.h"
29
#include "insn-config.h"
30
#include "conditions.h"
31
#include "insn-flags.h"
32
#include "output.h"
33
#include "insn-attr.h"
34
#include "flags.h"
35
#include "recog.h"
36
#include "reload.h"
37
#include "expr.h"
38
#include "obstack.h"
39
#include "except.h"
40
#include "function.h"
41
#include "optabs.h"
42
#include "diagnostic-core.h"
43
#include "basic-block.h"
44
#include "tm_p.h"
45
#include "ggc.h"
46
#include "target.h"
47
#include "target-def.h"
48
#include "targhooks.h"
49
#include "integrate.h"
50
#include "langhooks.h"
51
#include "df.h"
52
 
53
#ifndef FRV_INLINE
54
#define FRV_INLINE inline
55
#endif
56
 
57
/* The maximum number of distinct NOP patterns.  There are three:
58
   nop, fnop and mnop.  */
59
#define NUM_NOP_PATTERNS 3
60
 
61
/* Classification of instructions and units: integer, floating-point/media,
62
   branch and control.  */
63
enum frv_insn_group { GROUP_I, GROUP_FM, GROUP_B, GROUP_C, NUM_GROUPS };
64
 
65
/* The DFA names of the units, in packet order.  */
66
static const char *const frv_unit_names[] =
67
{
68
  "c",
69
  "i0", "f0",
70
  "i1", "f1",
71
  "i2", "f2",
72
  "i3", "f3",
73
  "b0", "b1"
74
};
75
 
76
/* The classification of each unit in frv_unit_names[].  */
77
static const enum frv_insn_group frv_unit_groups[ARRAY_SIZE (frv_unit_names)] =
78
{
79
  GROUP_C,
80
  GROUP_I, GROUP_FM,
81
  GROUP_I, GROUP_FM,
82
  GROUP_I, GROUP_FM,
83
  GROUP_I, GROUP_FM,
84
  GROUP_B, GROUP_B
85
};
86
 
87
/* Return the DFA unit code associated with the Nth unit of integer
88
   or floating-point group GROUP,  */
89
#define NTH_UNIT(GROUP, N) frv_unit_codes[(GROUP) + (N) * 2 + 1]
90
 
91
/* Return the number of integer or floating-point unit UNIT
92
   (1 for I1, 2 for F2, etc.).  */
93
#define UNIT_NUMBER(UNIT) (((UNIT) - 1) / 2)
94
 
95
/* The DFA unit number for each unit in frv_unit_names[].  */
96
static int frv_unit_codes[ARRAY_SIZE (frv_unit_names)];
97
 
98
/* FRV_TYPE_TO_UNIT[T] is the last unit in frv_unit_names[] that can issue
99
   an instruction of type T.  The value is ARRAY_SIZE (frv_unit_names) if
100
   no instruction of type T has been seen.  */
101
static unsigned int frv_type_to_unit[TYPE_UNKNOWN + 1];
102
 
103
/* An array of dummy nop INSNs, one for each type of nop that the
104
   target supports.  */
105
static GTY(()) rtx frv_nops[NUM_NOP_PATTERNS];
106
 
107
/* The number of nop instructions in frv_nops[].  */
108
static unsigned int frv_num_nops;
109
 
110
  /* The type of access.  FRV_IO_UNKNOWN means the access can be either
111
     a read or a write.  */
112
enum frv_io_type { FRV_IO_UNKNOWN, FRV_IO_READ, FRV_IO_WRITE };
113
 
114
/* Information about one __builtin_read or __builtin_write access, or
115
   the combination of several such accesses.  The most general value
116
   is all-zeros (an unknown access to an unknown address).  */
117
struct frv_io {
118
  enum frv_io_type type;
119
 
120
  /* The constant address being accessed, or zero if not known.  */
121
  HOST_WIDE_INT const_address;
122
 
123
  /* The run-time address, as used in operand 0 of the membar pattern.  */
124
  rtx var_address;
125
};
126
 
127
/* Return true if instruction INSN should be packed with the following
128
   instruction.  */
129
#define PACKING_FLAG_P(INSN) (GET_MODE (INSN) == TImode)
130
 
131
/* Set the value of PACKING_FLAG_P(INSN).  */
132
#define SET_PACKING_FLAG(INSN) PUT_MODE (INSN, TImode)
133
#define CLEAR_PACKING_FLAG(INSN) PUT_MODE (INSN, VOIDmode)
134
 
135
/* Loop with REG set to each hard register in rtx X.  */
136
#define FOR_EACH_REGNO(REG, X)                                          \
137
  for (REG = REGNO (X);                                                 \
138
       REG < REGNO (X) + HARD_REGNO_NREGS (REGNO (X), GET_MODE (X));    \
139
       REG++)
140
 
141
/* This structure contains machine specific function data.  */
142
struct GTY(()) machine_function
143
{
144
  /* True if we have created an rtx that relies on the stack frame.  */
145
  int frame_needed;
146
 
147
  /* True if this function contains at least one __builtin_{read,write}*.  */
148
  bool has_membar_p;
149
};
150
 
151
/* Temporary register allocation support structure.  */
152
typedef struct frv_tmp_reg_struct
153
  {
154
    HARD_REG_SET regs;          /* possible registers to allocate */
155
    int next_reg[N_REG_CLASSES];        /* next register to allocate per class */
156
  }
157
frv_tmp_reg_t;
158
 
159
/* Register state information for VLIW re-packing phase.  */
160
#define REGSTATE_CC_MASK        0x07    /* Mask to isolate CCn for cond exec */
161
#define REGSTATE_MODIFIED       0x08    /* reg modified in current VLIW insn */
162
#define REGSTATE_IF_TRUE        0x10    /* reg modified in cond exec true */
163
#define REGSTATE_IF_FALSE       0x20    /* reg modified in cond exec false */
164
 
165
#define REGSTATE_IF_EITHER      (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE)
166
 
167
typedef unsigned char regstate_t;
168
 
169
/* Used in frv_frame_accessor_t to indicate the direction of a register-to-
170
   memory move.  */
171
enum frv_stack_op
172
{
173
  FRV_LOAD,
174
  FRV_STORE
175
};
176
 
177
/* Information required by frv_frame_access.  */
178
typedef struct
179
{
180
  /* This field is FRV_LOAD if registers are to be loaded from the stack and
181
     FRV_STORE if they should be stored onto the stack.  FRV_STORE implies
182
     the move is being done by the prologue code while FRV_LOAD implies it
183
     is being done by the epilogue.  */
184
  enum frv_stack_op op;
185
 
186
  /* The base register to use when accessing the stack.  This may be the
187
     frame pointer, stack pointer, or a temporary.  The choice of register
188
     depends on which part of the frame is being accessed and how big the
189
     frame is.  */
190
  rtx base;
191
 
192
  /* The offset of BASE from the bottom of the current frame, in bytes.  */
193
  int base_offset;
194
} frv_frame_accessor_t;
195
 
196
/* Conditional execution support gathered together in one structure.  */
197
typedef struct
198
  {
199
    /* Linked list of insns to add if the conditional execution conversion was
200
       successful.  Each link points to an EXPR_LIST which points to the pattern
201
       of the insn to add, and the insn to be inserted before.  */
202
    rtx added_insns_list;
203
 
204
    /* Identify which registers are safe to allocate for if conversions to
205
       conditional execution.  We keep the last allocated register in the
206
       register classes between COND_EXEC statements.  This will mean we allocate
207
       different registers for each different COND_EXEC group if we can.  This
208
       might allow the scheduler to intermix two different COND_EXEC sections.  */
209
    frv_tmp_reg_t tmp_reg;
210
 
211
    /* For nested IFs, identify which CC registers are used outside of setting
212
       via a compare isnsn, and using via a check insn.  This will allow us to
213
       know if we can rewrite the register to use a different register that will
214
       be paired with the CR register controlling the nested IF-THEN blocks.  */
215
    HARD_REG_SET nested_cc_ok_rewrite;
216
 
217
    /* Temporary registers allocated to hold constants during conditional
218
       execution.  */
219
    rtx scratch_regs[FIRST_PSEUDO_REGISTER];
220
 
221
    /* Current number of temp registers available.  */
222
    int cur_scratch_regs;
223
 
224
    /* Number of nested conditional execution blocks.  */
225
    int num_nested_cond_exec;
226
 
227
    /* Map of insns that set up constants in scratch registers.  */
228
    bitmap scratch_insns_bitmap;
229
 
230
    /* Conditional execution test register (CC0..CC7).  */
231
    rtx cr_reg;
232
 
233
    /* Conditional execution compare register that is paired with cr_reg, so that
234
       nested compares can be done.  The csubcc and caddcc instructions don't
235
       have enough bits to specify both a CC register to be set and a CR register
236
       to do the test on, so the same bit number is used for both.  Needless to
237
       say, this is rather inconvenient for GCC.  */
238
    rtx nested_cc_reg;
239
 
240
    /* Extra CR registers used for &&, ||.  */
241
    rtx extra_int_cr;
242
    rtx extra_fp_cr;
243
 
244
    /* Previous CR used in nested if, to make sure we are dealing with the same
245
       nested if as the previous statement.  */
246
    rtx last_nested_if_cr;
247
  }
248
frv_ifcvt_t;
249
 
250
static /* GTY(()) */ frv_ifcvt_t frv_ifcvt;
251
 
252
/* Map register number to smallest register class.  */
253
enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
254
 
255
/* Cached value of frv_stack_info.  */
256
static frv_stack_t *frv_stack_cache = (frv_stack_t *)0;
257
 
258
/* Forward references */
259
 
260
static void frv_option_override                 (void);
261
static bool frv_legitimate_address_p            (enum machine_mode, rtx, bool);
262
static int frv_default_flags_for_cpu            (void);
263
static int frv_string_begins_with               (const_tree, const char *);
264
static FRV_INLINE bool frv_small_data_reloc_p   (rtx, int);
265
static void frv_print_operand                   (FILE *, rtx, int);
266
static void frv_print_operand_address           (FILE *, rtx);
267
static bool frv_print_operand_punct_valid_p     (unsigned char code);
268
static void frv_print_operand_memory_reference_reg
269
                                                (FILE *, rtx);
270
static void frv_print_operand_memory_reference  (FILE *, rtx, int);
271
static int frv_print_operand_jump_hint          (rtx);
272
static const char *comparison_string            (enum rtx_code, rtx);
273
static rtx frv_function_value                   (const_tree, const_tree,
274
                                                 bool);
275
static rtx frv_libcall_value                    (enum machine_mode,
276
                                                 const_rtx);
277
static FRV_INLINE int frv_regno_ok_for_base_p   (int, int);
278
static rtx single_set_pattern                   (rtx);
279
static int frv_function_contains_far_jump       (void);
280
static rtx frv_alloc_temp_reg                   (frv_tmp_reg_t *,
281
                                                 enum reg_class,
282
                                                 enum machine_mode,
283
                                                 int, int);
284
static rtx frv_frame_offset_rtx                 (int);
285
static rtx frv_frame_mem                        (enum machine_mode, rtx, int);
286
static rtx frv_dwarf_store                      (rtx, int);
287
static void frv_frame_insn                      (rtx, rtx);
288
static void frv_frame_access                    (frv_frame_accessor_t*,
289
                                                 rtx, int);
290
static void frv_frame_access_multi              (frv_frame_accessor_t*,
291
                                                 frv_stack_t *, int);
292
static void frv_frame_access_standard_regs      (enum frv_stack_op,
293
                                                 frv_stack_t *);
294
static struct machine_function *frv_init_machine_status         (void);
295
static rtx frv_int_to_acc                       (enum insn_code, int, rtx);
296
static enum machine_mode frv_matching_accg_mode (enum machine_mode);
297
static rtx frv_read_argument                    (tree, unsigned int);
298
static rtx frv_read_iacc_argument               (enum machine_mode, tree, unsigned int);
299
static int frv_check_constant_argument          (enum insn_code, int, rtx);
300
static rtx frv_legitimize_target                (enum insn_code, rtx);
301
static rtx frv_legitimize_argument              (enum insn_code, int, rtx);
302
static rtx frv_legitimize_tls_address           (rtx, enum tls_model);
303
static rtx frv_legitimize_address               (rtx, rtx, enum machine_mode);
304
static rtx frv_expand_set_builtin               (enum insn_code, tree, rtx);
305
static rtx frv_expand_unop_builtin              (enum insn_code, tree, rtx);
306
static rtx frv_expand_binop_builtin             (enum insn_code, tree, rtx);
307
static rtx frv_expand_cut_builtin               (enum insn_code, tree, rtx);
308
static rtx frv_expand_binopimm_builtin          (enum insn_code, tree, rtx);
309
static rtx frv_expand_voidbinop_builtin         (enum insn_code, tree);
310
static rtx frv_expand_int_void2arg              (enum insn_code, tree);
311
static rtx frv_expand_prefetches                (enum insn_code, tree);
312
static rtx frv_expand_voidtriop_builtin         (enum insn_code, tree);
313
static rtx frv_expand_voidaccop_builtin         (enum insn_code, tree);
314
static rtx frv_expand_mclracc_builtin           (tree);
315
static rtx frv_expand_mrdacc_builtin            (enum insn_code, tree);
316
static rtx frv_expand_mwtacc_builtin            (enum insn_code, tree);
317
static rtx frv_expand_noargs_builtin            (enum insn_code);
318
static void frv_split_iacc_move                 (rtx, rtx);
319
static rtx frv_emit_comparison                  (enum rtx_code, rtx, rtx);
320
static int frv_clear_registers_used             (rtx *, void *);
321
static void frv_ifcvt_add_insn                  (rtx, rtx, int);
322
static rtx frv_ifcvt_rewrite_mem                (rtx, enum machine_mode, rtx);
323
static rtx frv_ifcvt_load_value                 (rtx, rtx);
324
static int frv_acc_group_1                      (rtx *, void *);
325
static unsigned int frv_insn_unit               (rtx);
326
static bool frv_issues_to_branch_unit_p         (rtx);
327
static int frv_cond_flags                       (rtx);
328
static bool frv_regstate_conflict_p             (regstate_t, regstate_t);
329
static int frv_registers_conflict_p_1           (rtx *, void *);
330
static bool frv_registers_conflict_p            (rtx);
331
static void frv_registers_update_1              (rtx, const_rtx, void *);
332
static void frv_registers_update                (rtx);
333
static void frv_start_packet                    (void);
334
static void frv_start_packet_block              (void);
335
static void frv_finish_packet                   (void (*) (void));
336
static bool frv_pack_insn_p                     (rtx);
337
static void frv_add_insn_to_packet              (rtx);
338
static void frv_insert_nop_in_packet            (rtx);
339
static bool frv_for_each_packet                 (void (*) (void));
340
static bool frv_sort_insn_group_1               (enum frv_insn_group,
341
                                                 unsigned int, unsigned int,
342
                                                 unsigned int, unsigned int,
343
                                                 state_t);
344
static int frv_compare_insns                    (const void *, const void *);
345
static void frv_sort_insn_group                 (enum frv_insn_group);
346
static void frv_reorder_packet                  (void);
347
static void frv_fill_unused_units               (enum frv_insn_group);
348
static void frv_align_label                     (void);
349
static void frv_reorg_packet                    (void);
350
static void frv_register_nop                    (rtx);
351
static void frv_reorg                           (void);
352
static void frv_pack_insns                      (void);
353
static void frv_function_prologue               (FILE *, HOST_WIDE_INT);
354
static void frv_function_epilogue               (FILE *, HOST_WIDE_INT);
355
static bool frv_assemble_integer                (rtx, unsigned, int);
356
static void frv_init_builtins                   (void);
357
static rtx frv_expand_builtin                   (tree, rtx, rtx, enum machine_mode, int);
358
static void frv_init_libfuncs                   (void);
359
static bool frv_in_small_data_p                 (const_tree);
360
static void frv_asm_output_mi_thunk
361
  (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
362
static void frv_setup_incoming_varargs          (cumulative_args_t,
363
                                                 enum machine_mode,
364
                                                 tree, int *, int);
365
static rtx frv_expand_builtin_saveregs          (void);
366
static void frv_expand_builtin_va_start         (tree, rtx);
367
static bool frv_rtx_costs                       (rtx, int, int, int, int*,
368
                                                 bool);
369
static int frv_register_move_cost               (enum machine_mode,
370
                                                 reg_class_t, reg_class_t);
371
static int frv_memory_move_cost                 (enum machine_mode,
372
                                                 reg_class_t, bool);
373
static void frv_asm_out_constructor             (rtx, int);
374
static void frv_asm_out_destructor              (rtx, int);
375
static bool frv_function_symbol_referenced_p    (rtx);
376
static bool frv_legitimate_constant_p           (enum machine_mode, rtx);
377
static bool frv_cannot_force_const_mem          (enum machine_mode, rtx);
378
static const char *unspec_got_name              (int);
379
static void frv_output_const_unspec             (FILE *,
380
                                                 const struct frv_unspec *);
381
static bool frv_function_ok_for_sibcall         (tree, tree);
382
static rtx frv_struct_value_rtx                 (tree, int);
383
static bool frv_must_pass_in_stack (enum machine_mode mode, const_tree type);
384
static int frv_arg_partial_bytes (cumulative_args_t, enum machine_mode,
385
                                  tree, bool);
386
static rtx frv_function_arg (cumulative_args_t, enum machine_mode,
387
                             const_tree, bool);
388
static rtx frv_function_incoming_arg (cumulative_args_t, enum machine_mode,
389
                                      const_tree, bool);
390
static void frv_function_arg_advance (cumulative_args_t, enum machine_mode,
391
                                       const_tree, bool);
392
static unsigned int frv_function_arg_boundary   (enum machine_mode,
393
                                                 const_tree);
394
static void frv_output_dwarf_dtprel             (FILE *, int, rtx)
395
  ATTRIBUTE_UNUSED;
396
static reg_class_t frv_secondary_reload         (bool, rtx, reg_class_t,
397
                                                 enum machine_mode,
398
                                                 secondary_reload_info *);
399
static bool frv_frame_pointer_required          (void);
400
static bool frv_can_eliminate                   (const int, const int);
401
static void frv_conditional_register_usage      (void);
402
static void frv_trampoline_init                 (rtx, tree, rtx);
403
static bool frv_class_likely_spilled_p          (reg_class_t);
404
 
405
/* Initialize the GCC target structure.  */
406
#undef TARGET_PRINT_OPERAND
407
#define TARGET_PRINT_OPERAND frv_print_operand
408
#undef TARGET_PRINT_OPERAND_ADDRESS
409
#define TARGET_PRINT_OPERAND_ADDRESS frv_print_operand_address
410
#undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
411
#define TARGET_PRINT_OPERAND_PUNCT_VALID_P frv_print_operand_punct_valid_p
412
#undef  TARGET_ASM_FUNCTION_PROLOGUE
413
#define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue
414
#undef  TARGET_ASM_FUNCTION_EPILOGUE
415
#define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue
416
#undef  TARGET_ASM_INTEGER
417
#define TARGET_ASM_INTEGER frv_assemble_integer
418
#undef TARGET_OPTION_OVERRIDE
419
#define TARGET_OPTION_OVERRIDE frv_option_override
420
#undef TARGET_INIT_BUILTINS
421
#define TARGET_INIT_BUILTINS frv_init_builtins
422
#undef TARGET_EXPAND_BUILTIN
423
#define TARGET_EXPAND_BUILTIN frv_expand_builtin
424
#undef TARGET_INIT_LIBFUNCS
425
#define TARGET_INIT_LIBFUNCS frv_init_libfuncs
426
#undef TARGET_IN_SMALL_DATA_P
427
#define TARGET_IN_SMALL_DATA_P frv_in_small_data_p
428
#undef TARGET_REGISTER_MOVE_COST
429
#define TARGET_REGISTER_MOVE_COST frv_register_move_cost
430
#undef TARGET_MEMORY_MOVE_COST
431
#define TARGET_MEMORY_MOVE_COST frv_memory_move_cost
432
#undef TARGET_RTX_COSTS
433
#define TARGET_RTX_COSTS frv_rtx_costs
434
#undef TARGET_ASM_CONSTRUCTOR
435
#define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor
436
#undef TARGET_ASM_DESTRUCTOR
437
#define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor
438
 
439
#undef TARGET_ASM_OUTPUT_MI_THUNK
440
#define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk
441
#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
442
#define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
443
 
444
#undef  TARGET_SCHED_ISSUE_RATE
445
#define TARGET_SCHED_ISSUE_RATE frv_issue_rate
446
 
447
#undef TARGET_LEGITIMIZE_ADDRESS
448
#define TARGET_LEGITIMIZE_ADDRESS frv_legitimize_address
449
 
450
#undef TARGET_FUNCTION_OK_FOR_SIBCALL
451
#define TARGET_FUNCTION_OK_FOR_SIBCALL frv_function_ok_for_sibcall
452
#undef TARGET_LEGITIMATE_CONSTANT_P
453
#define TARGET_LEGITIMATE_CONSTANT_P frv_legitimate_constant_p
454
#undef TARGET_CANNOT_FORCE_CONST_MEM
455
#define TARGET_CANNOT_FORCE_CONST_MEM frv_cannot_force_const_mem
456
 
457
#undef TARGET_HAVE_TLS
458
#define TARGET_HAVE_TLS HAVE_AS_TLS
459
 
460
#undef TARGET_STRUCT_VALUE_RTX
461
#define TARGET_STRUCT_VALUE_RTX frv_struct_value_rtx
462
#undef TARGET_MUST_PASS_IN_STACK
463
#define TARGET_MUST_PASS_IN_STACK frv_must_pass_in_stack
464
#undef TARGET_PASS_BY_REFERENCE
465
#define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack
466
#undef TARGET_ARG_PARTIAL_BYTES
467
#define TARGET_ARG_PARTIAL_BYTES frv_arg_partial_bytes
468
#undef TARGET_FUNCTION_ARG
469
#define TARGET_FUNCTION_ARG frv_function_arg
470
#undef TARGET_FUNCTION_INCOMING_ARG
471
#define TARGET_FUNCTION_INCOMING_ARG frv_function_incoming_arg
472
#undef TARGET_FUNCTION_ARG_ADVANCE
473
#define TARGET_FUNCTION_ARG_ADVANCE frv_function_arg_advance
474
#undef TARGET_FUNCTION_ARG_BOUNDARY
475
#define TARGET_FUNCTION_ARG_BOUNDARY frv_function_arg_boundary
476
 
477
#undef TARGET_EXPAND_BUILTIN_SAVEREGS
478
#define TARGET_EXPAND_BUILTIN_SAVEREGS frv_expand_builtin_saveregs
479
#undef TARGET_SETUP_INCOMING_VARARGS
480
#define TARGET_SETUP_INCOMING_VARARGS frv_setup_incoming_varargs
481
#undef TARGET_MACHINE_DEPENDENT_REORG
482
#define TARGET_MACHINE_DEPENDENT_REORG frv_reorg
483
 
484
#undef TARGET_EXPAND_BUILTIN_VA_START
485
#define TARGET_EXPAND_BUILTIN_VA_START frv_expand_builtin_va_start
486
 
487
#if HAVE_AS_TLS
488
#undef TARGET_ASM_OUTPUT_DWARF_DTPREL
489
#define TARGET_ASM_OUTPUT_DWARF_DTPREL frv_output_dwarf_dtprel
490
#endif
491
 
492
#undef TARGET_CLASS_LIKELY_SPILLED_P
493
#define TARGET_CLASS_LIKELY_SPILLED_P frv_class_likely_spilled_p
494
 
495
#undef  TARGET_SECONDARY_RELOAD
496
#define TARGET_SECONDARY_RELOAD frv_secondary_reload
497
 
498
#undef TARGET_LEGITIMATE_ADDRESS_P
499
#define TARGET_LEGITIMATE_ADDRESS_P frv_legitimate_address_p
500
 
501
#undef TARGET_FRAME_POINTER_REQUIRED
502
#define TARGET_FRAME_POINTER_REQUIRED frv_frame_pointer_required
503
 
504
#undef TARGET_CAN_ELIMINATE
505
#define TARGET_CAN_ELIMINATE frv_can_eliminate
506
 
507
#undef TARGET_CONDITIONAL_REGISTER_USAGE
508
#define TARGET_CONDITIONAL_REGISTER_USAGE frv_conditional_register_usage
509
 
510
#undef TARGET_TRAMPOLINE_INIT
511
#define TARGET_TRAMPOLINE_INIT frv_trampoline_init
512
 
513
#undef TARGET_FUNCTION_VALUE
514
#define TARGET_FUNCTION_VALUE frv_function_value
515
#undef TARGET_LIBCALL_VALUE
516
#define TARGET_LIBCALL_VALUE frv_libcall_value
517
 
518
struct gcc_target targetm = TARGET_INITIALIZER;
519
 
520
#define FRV_SYMBOL_REF_TLS_P(RTX) \
521
  (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
522
 
523
 
524
/* Any function call that satisfies the machine-independent
525
   requirements is eligible on FR-V.  */
526
 
527
static bool
528
frv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
529
                             tree exp ATTRIBUTE_UNUSED)
530
{
531
  return true;
532
}
533
 
534
/* Return true if SYMBOL is a small data symbol and relocation RELOC
535
   can be used to access it directly in a load or store.  */
536
 
537
static FRV_INLINE bool
538
frv_small_data_reloc_p (rtx symbol, int reloc)
539
{
540
  return (GET_CODE (symbol) == SYMBOL_REF
541
          && SYMBOL_REF_SMALL_P (symbol)
542
          && (!TARGET_FDPIC || flag_pic == 1)
543
          && (reloc == R_FRV_GOTOFF12 || reloc == R_FRV_GPREL12));
544
}
545
 
546
/* Return true if X is a valid relocation unspec.  If it is, fill in UNSPEC
547
   appropriately.  */
548
 
549
bool
550
frv_const_unspec_p (rtx x, struct frv_unspec *unspec)
551
{
552
  if (GET_CODE (x) == CONST)
553
    {
554
      unspec->offset = 0;
555
      x = XEXP (x, 0);
556
      if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
557
        {
558
          unspec->offset += INTVAL (XEXP (x, 1));
559
          x = XEXP (x, 0);
560
        }
561
      if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_GOT)
562
        {
563
          unspec->symbol = XVECEXP (x, 0, 0);
564
          unspec->reloc = INTVAL (XVECEXP (x, 0, 1));
565
 
566
          if (unspec->offset == 0)
567
            return true;
568
 
569
          if (frv_small_data_reloc_p (unspec->symbol, unspec->reloc)
570
              && unspec->offset > 0
571
              && unspec->offset < g_switch_value)
572
            return true;
573
        }
574
    }
575
  return false;
576
}
577
 
578
/* Decide whether we can force certain constants to memory.  If we
579
   decide we can't, the caller should be able to cope with it in
580
   another way.
581
 
582
   We never allow constants to be forced into memory for TARGET_FDPIC.
583
   This is necessary for several reasons:
584
 
585
   1. Since frv_legitimate_constant_p rejects constant pool addresses, the
586
      target-independent code will try to force them into the constant
587
      pool, thus leading to infinite recursion.
588
 
589
   2. We can never introduce new constant pool references during reload.
590
      Any such reference would require use of the pseudo FDPIC register.
591
 
592
   3. We can't represent a constant added to a function pointer (which is
593
      not the same as a pointer to a function+constant).
594
 
595
   4. In many cases, it's more efficient to calculate the constant in-line.  */
596
 
597
static bool
598
frv_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED,
599
                            rtx x ATTRIBUTE_UNUSED)
600
{
601
  return TARGET_FDPIC;
602
}
603
 
604
static int
605
frv_default_flags_for_cpu (void)
606
{
607
  switch (frv_cpu_type)
608
    {
609
    case FRV_CPU_GENERIC:
610
      return MASK_DEFAULT_FRV;
611
 
612
    case FRV_CPU_FR550:
613
      return MASK_DEFAULT_FR550;
614
 
615
    case FRV_CPU_FR500:
616
    case FRV_CPU_TOMCAT:
617
      return MASK_DEFAULT_FR500;
618
 
619
    case FRV_CPU_FR450:
620
      return MASK_DEFAULT_FR450;
621
 
622
    case FRV_CPU_FR405:
623
    case FRV_CPU_FR400:
624
      return MASK_DEFAULT_FR400;
625
 
626
    case FRV_CPU_FR300:
627
    case FRV_CPU_SIMPLE:
628
      return MASK_DEFAULT_SIMPLE;
629
 
630
    default:
631
      gcc_unreachable ();
632
    }
633
}
634
 
635
/* Implement TARGET_OPTION_OVERRIDE.  */
636
 
637
static void
638
frv_option_override (void)
639
{
640
  int regno;
641
  unsigned int i;
642
 
643
  target_flags |= (frv_default_flags_for_cpu () & ~target_flags_explicit);
644
 
645
  /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the
646
     linker about linking pic and non-pic code.  */
647
  if (TARGET_LIBPIC)
648
    {
649
      if (!flag_pic)            /* -fPIC */
650
        flag_pic = 2;
651
 
652
      if (!global_options_set.x_g_switch_value) /* -G0 */
653
        {
654
          g_switch_value = 0;
655
        }
656
    }
657
 
658
  /* A C expression whose value is a register class containing hard
659
     register REGNO.  In general there is more than one such class;
660
     choose a class which is "minimal", meaning that no smaller class
661
     also contains the register.  */
662
 
663
  for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
664
    {
665
      enum reg_class rclass;
666
 
667
      if (GPR_P (regno))
668
        {
669
          int gpr_reg = regno - GPR_FIRST;
670
 
671
          if (gpr_reg == GR8_REG)
672
            rclass = GR8_REGS;
673
 
674
          else if (gpr_reg == GR9_REG)
675
            rclass = GR9_REGS;
676
 
677
          else if (gpr_reg == GR14_REG)
678
            rclass = FDPIC_FPTR_REGS;
679
 
680
          else if (gpr_reg == FDPIC_REGNO)
681
            rclass = FDPIC_REGS;
682
 
683
          else if ((gpr_reg & 3) == 0)
684
            rclass = QUAD_REGS;
685
 
686
          else if ((gpr_reg & 1) == 0)
687
            rclass = EVEN_REGS;
688
 
689
          else
690
            rclass = GPR_REGS;
691
        }
692
 
693
      else if (FPR_P (regno))
694
        {
695
          int fpr_reg = regno - GPR_FIRST;
696
          if ((fpr_reg & 3) == 0)
697
            rclass = QUAD_FPR_REGS;
698
 
699
          else if ((fpr_reg & 1) == 0)
700
            rclass = FEVEN_REGS;
701
 
702
          else
703
            rclass = FPR_REGS;
704
        }
705
 
706
      else if (regno == LR_REGNO)
707
        rclass = LR_REG;
708
 
709
      else if (regno == LCR_REGNO)
710
        rclass = LCR_REG;
711
 
712
      else if (ICC_P (regno))
713
        rclass = ICC_REGS;
714
 
715
      else if (FCC_P (regno))
716
        rclass = FCC_REGS;
717
 
718
      else if (ICR_P (regno))
719
        rclass = ICR_REGS;
720
 
721
      else if (FCR_P (regno))
722
        rclass = FCR_REGS;
723
 
724
      else if (ACC_P (regno))
725
        {
726
          int r = regno - ACC_FIRST;
727
          if ((r & 3) == 0)
728
            rclass = QUAD_ACC_REGS;
729
          else if ((r & 1) == 0)
730
            rclass = EVEN_ACC_REGS;
731
          else
732
            rclass = ACC_REGS;
733
        }
734
 
735
      else if (ACCG_P (regno))
736
        rclass = ACCG_REGS;
737
 
738
      else
739
        rclass = NO_REGS;
740
 
741
      regno_reg_class[regno] = rclass;
742
    }
743
 
744
  /* Check for small data option */
745
  if (!global_options_set.x_g_switch_value && !TARGET_LIBPIC)
746
    g_switch_value = SDATA_DEFAULT_SIZE;
747
 
748
  /* There is no single unaligned SI op for PIC code.  Sometimes we
749
     need to use ".4byte" and sometimes we need to use ".picptr".
750
     See frv_assemble_integer for details.  */
751
  if (flag_pic || TARGET_FDPIC)
752
    targetm.asm_out.unaligned_op.si = 0;
753
 
754
  if ((target_flags_explicit & MASK_LINKED_FP) == 0)
755
    target_flags |= MASK_LINKED_FP;
756
 
757
  if ((target_flags_explicit & MASK_OPTIMIZE_MEMBAR) == 0)
758
    target_flags |= MASK_OPTIMIZE_MEMBAR;
759
 
760
  for (i = 0; i < ARRAY_SIZE (frv_unit_names); i++)
761
    frv_unit_codes[i] = get_cpu_unit_code (frv_unit_names[i]);
762
 
763
  for (i = 0; i < ARRAY_SIZE (frv_type_to_unit); i++)
764
    frv_type_to_unit[i] = ARRAY_SIZE (frv_unit_codes);
765
 
766
  init_machine_status = frv_init_machine_status;
767
}
768
 
769
 
770
/* Return true if NAME (a STRING_CST node) begins with PREFIX.  */
771
 
772
static int
773
frv_string_begins_with (const_tree name, const char *prefix)
774
{
775
  const int prefix_len = strlen (prefix);
776
 
777
  /* Remember: NAME's length includes the null terminator.  */
778
  return (TREE_STRING_LENGTH (name) > prefix_len
779
          && strncmp (TREE_STRING_POINTER (name), prefix, prefix_len) == 0);
780
}
781
 
782
/* Zero or more C statements that may conditionally modify two variables
783
   `fixed_regs' and `call_used_regs' (both of type `char []') after they have
784
   been initialized from the two preceding macros.
785
 
786
   This is necessary in case the fixed or call-clobbered registers depend on
787
   target flags.
788
 
789
   You need not define this macro if it has no work to do.
790
 
791
   If the usage of an entire class of registers depends on the target flags,
792
   you may indicate this to GCC by using this macro to modify `fixed_regs' and
793
   `call_used_regs' to 1 for each of the registers in the classes which should
794
   not be used by GCC.  Also define the macro `REG_CLASS_FROM_LETTER' to return
795
   `NO_REGS' if it is called with a letter for a class that shouldn't be used.
796
 
797
   (However, if this class is not included in `GENERAL_REGS' and all of the
798
   insn patterns whose constraints permit this class are controlled by target
799
   switches, then GCC will automatically avoid using these registers when the
800
   target switches are opposed to them.)  */
801
 
802
static void
803
frv_conditional_register_usage (void)
804
{
805
  int i;
806
 
807
  for (i = GPR_FIRST + NUM_GPRS; i <= GPR_LAST; i++)
808
    fixed_regs[i] = call_used_regs[i] = 1;
809
 
810
  for (i = FPR_FIRST + NUM_FPRS; i <= FPR_LAST; i++)
811
    fixed_regs[i] = call_used_regs[i] = 1;
812
 
813
  /* Reserve the registers used for conditional execution.  At present, we need
814
     1 ICC and 1 ICR register.  */
815
  fixed_regs[ICC_TEMP] = call_used_regs[ICC_TEMP] = 1;
816
  fixed_regs[ICR_TEMP] = call_used_regs[ICR_TEMP] = 1;
817
 
818
  if (TARGET_FIXED_CC)
819
    {
820
      fixed_regs[ICC_FIRST] = call_used_regs[ICC_FIRST] = 1;
821
      fixed_regs[FCC_FIRST] = call_used_regs[FCC_FIRST] = 1;
822
      fixed_regs[ICR_FIRST] = call_used_regs[ICR_FIRST] = 1;
823
      fixed_regs[FCR_FIRST] = call_used_regs[FCR_FIRST] = 1;
824
    }
825
 
826
  if (TARGET_FDPIC)
827
    fixed_regs[GPR_FIRST + 16] = fixed_regs[GPR_FIRST + 17] =
828
      call_used_regs[GPR_FIRST + 16] = call_used_regs[GPR_FIRST + 17] = 0;
829
 
830
#if 0
831
  /* If -fpic, SDA_BASE_REG is the PIC register.  */
832
  if (g_switch_value == 0 && !flag_pic)
833
    fixed_regs[SDA_BASE_REG] = call_used_regs[SDA_BASE_REG] = 0;
834
 
835
  if (!flag_pic)
836
    fixed_regs[PIC_REGNO] = call_used_regs[PIC_REGNO] = 0;
837
#endif
838
}
839
 
840
 
841
/*
842
 * Compute the stack frame layout
843
 *
844
 * Register setup:
845
 * +---------------+-----------------------+-----------------------+
846
 * |Register       |type                   |caller-save/callee-save|
847
 * +---------------+-----------------------+-----------------------+
848
 * |GR0            |Zero register          |        -              |
849
 * |GR1            |Stack pointer(SP)      |        -              |
850
 * |GR2            |Frame pointer(FP)      |        -              |
851
 * |GR3            |Hidden parameter       |        caller save    |
852
 * |GR4-GR7        |        -              |        caller save    |
853
 * |GR8-GR13       |Argument register      |        caller save    |
854
 * |GR14-GR15      |        -              |        caller save    |
855
 * |GR16-GR31      |        -              |        callee save    |
856
 * |GR32-GR47      |        -              |        caller save    |
857
 * |GR48-GR63      |        -              |        callee save    |
858
 * |FR0-FR15       |        -              |        caller save    |
859
 * |FR16-FR31      |        -              |        callee save    |
860
 * |FR32-FR47      |        -              |        caller save    |
861
 * |FR48-FR63      |        -              |        callee save    |
862
 * +---------------+-----------------------+-----------------------+
863
 *
864
 * Stack frame setup:
865
 * Low
866
 *     SP-> |-----------------------------------|
867
 *          |         Argument area             |
868
 *          |-----------------------------------|
869
 *          |    Register save area             |
870
 *          |-----------------------------------|
871
 *          |   Local variable save area        |
872
 *     FP-> |-----------------------------------|
873
 *          |       Old FP                      |
874
 *          |-----------------------------------|
875
 *          |    Hidden parameter save area     |
876
 *          |-----------------------------------|
877
 *          | Return address(LR) storage area   |
878
 *          |-----------------------------------|
879
 *          |     Padding for alignment         |
880
 *          |-----------------------------------|
881
 *          |     Register argument area        |
882
 * OLD SP-> |-----------------------------------|
883
 *          |       Parameter area              |
884
 *          |-----------------------------------|
885
 * High
886
 *
887
 * Argument area/Parameter area:
888
 *
889
 * When a function is called, this area is used for argument transfer.  When
890
 * the argument is set up by the caller function, this area is referred to as
891
 * the argument area.  When the argument is referenced by the callee function,
892
 * this area is referred to as the parameter area.  The area is allocated when
893
 * all arguments cannot be placed on the argument register at the time of
894
 * argument transfer.
895
 *
896
 * Register save area:
897
 *
898
 * This is a register save area that must be guaranteed for the caller
899
 * function.  This area is not secured when the register save operation is not
900
 * needed.
901
 *
902
 * Local variable save area:
903
 *
904
 * This is the area for local variables and temporary variables.
905
 *
906
 * Old FP:
907
 *
908
 * This area stores the FP value of the caller function.
909
 *
910
 * Hidden parameter save area:
911
 *
912
 * This area stores the start address of the return value storage
913
 * area for a struct/union return function.
914
 * When a struct/union is used as the return value, the caller
915
 * function stores the return value storage area start address in
916
 * register GR3 and passes it to the caller function.
917
 * The callee function interprets the address stored in the GR3
918
 * as the return value storage area start address.
919
 * When register GR3 needs to be saved into memory, the callee
920
 * function saves it in the hidden parameter save area.  This
921
 * area is not secured when the save operation is not needed.
922
 *
923
 * Return address(LR) storage area:
924
 *
925
 * This area saves the LR.  The LR stores the address of a return to the caller
926
 * function for the purpose of function calling.
927
 *
928
 * Argument register area:
929
 *
930
 * This area saves the argument register.  This area is not secured when the
931
 * save operation is not needed.
932
 *
933
 * Argument:
934
 *
935
 * Arguments, the count of which equals the count of argument registers (6
936
 * words), are positioned in registers GR8 to GR13 and delivered to the callee
937
 * function.  When a struct/union return function is called, the return value
938
 * area address is stored in register GR3.  Arguments not placed in the
939
 * argument registers will be stored in the stack argument area for transfer
940
 * purposes.  When an 8-byte type argument is to be delivered using registers,
941
 * it is divided into two and placed in two registers for transfer.  When
942
 * argument registers must be saved to memory, the callee function secures an
943
 * argument register save area in the stack.  In this case, a continuous
944
 * argument register save area must be established in the parameter area.  The
945
 * argument register save area must be allocated as needed to cover the size of
946
 * the argument register to be saved.  If the function has a variable count of
947
 * arguments, it saves all argument registers in the argument register save
948
 * area.
949
 *
950
 * Argument Extension Format:
951
 *
952
 * When an argument is to be stored in the stack, its type is converted to an
953
 * extended type in accordance with the individual argument type.  The argument
954
 * is freed by the caller function after the return from the callee function is
955
 * made.
956
 *
957
 * +-----------------------+---------------+------------------------+
958
 * |    Argument Type      |Extended Type  |Stack Storage Size(byte)|
959
 * +-----------------------+---------------+------------------------+
960
 * |char                   |int            |        4               |
961
 * |signed char            |int            |        4               |
962
 * |unsigned char          |int            |        4               |
963
 * |[signed] short int     |int            |        4               |
964
 * |unsigned short int     |int            |        4               |
965
 * |[signed] int           |No extension   |        4               |
966
 * |unsigned int           |No extension   |        4               |
967
 * |[signed] long int      |No extension   |        4               |
968
 * |unsigned long int      |No extension   |        4               |
969
 * |[signed] long long int |No extension   |        8               |
970
 * |unsigned long long int |No extension   |        8               |
971
 * |float                  |double         |        8               |
972
 * |double                 |No extension   |        8               |
973
 * |long double            |No extension   |        8               |
974
 * |pointer                |No extension   |        4               |
975
 * |struct/union           |-              |        4 (*1)          |
976
 * +-----------------------+---------------+------------------------+
977
 *
978
 * When a struct/union is to be delivered as an argument, the caller copies it
979
 * to the local variable area and delivers the address of that area.
980
 *
981
 * Return Value:
982
 *
983
 * +-------------------------------+----------------------+
984
 * |Return Value Type              |Return Value Interface|
985
 * +-------------------------------+----------------------+
986
 * |void                           |None                  |
987
 * |[signed|unsigned] char         |GR8                   |
988
 * |[signed|unsigned] short int    |GR8                   |
989
 * |[signed|unsigned] int          |GR8                   |
990
 * |[signed|unsigned] long int     |GR8                   |
991
 * |pointer                        |GR8                   |
992
 * |[signed|unsigned] long long int|GR8 & GR9             |
993
 * |float                          |GR8                   |
994
 * |double                         |GR8 & GR9             |
995
 * |long double                    |GR8 & GR9             |
996
 * |struct/union                   |(*1)                  |
997
 * +-------------------------------+----------------------+
998
 *
999
 * When a struct/union is used as the return value, the caller function stores
1000
 * the start address of the return value storage area into GR3 and then passes
1001
 * it to the callee function.  The callee function interprets GR3 as the start
1002
 * address of the return value storage area.  When this address needs to be
1003
 * saved in memory, the callee function secures the hidden parameter save area
1004
 * and saves the address in that area.
1005
 */
1006
 
1007
frv_stack_t *
1008
frv_stack_info (void)
1009
{
1010
  static frv_stack_t info, zero_info;
1011
  frv_stack_t *info_ptr = &info;
1012
  tree fndecl           = current_function_decl;
1013
  int varargs_p         = 0;
1014
  tree cur_arg;
1015
  tree next_arg;
1016
  int range;
1017
  int alignment;
1018
  int offset;
1019
 
1020
  /* If we've already calculated the values and reload is complete,
1021
     just return now.  */
1022
  if (frv_stack_cache)
1023
    return frv_stack_cache;
1024
 
1025
  /* Zero all fields.  */
1026
  info = zero_info;
1027
 
1028
  /* Set up the register range information.  */
1029
  info_ptr->regs[STACK_REGS_GPR].name         = "gpr";
1030
  info_ptr->regs[STACK_REGS_GPR].first        = LAST_ARG_REGNUM + 1;
1031
  info_ptr->regs[STACK_REGS_GPR].last         = GPR_LAST;
1032
  info_ptr->regs[STACK_REGS_GPR].dword_p      = TRUE;
1033
 
1034
  info_ptr->regs[STACK_REGS_FPR].name         = "fpr";
1035
  info_ptr->regs[STACK_REGS_FPR].first        = FPR_FIRST;
1036
  info_ptr->regs[STACK_REGS_FPR].last         = FPR_LAST;
1037
  info_ptr->regs[STACK_REGS_FPR].dword_p      = TRUE;
1038
 
1039
  info_ptr->regs[STACK_REGS_LR].name          = "lr";
1040
  info_ptr->regs[STACK_REGS_LR].first         = LR_REGNO;
1041
  info_ptr->regs[STACK_REGS_LR].last          = LR_REGNO;
1042
  info_ptr->regs[STACK_REGS_LR].special_p     = 1;
1043
 
1044
  info_ptr->regs[STACK_REGS_CC].name          = "cc";
1045
  info_ptr->regs[STACK_REGS_CC].first         = CC_FIRST;
1046
  info_ptr->regs[STACK_REGS_CC].last          = CC_LAST;
1047
  info_ptr->regs[STACK_REGS_CC].field_p       = TRUE;
1048
 
1049
  info_ptr->regs[STACK_REGS_LCR].name         = "lcr";
1050
  info_ptr->regs[STACK_REGS_LCR].first        = LCR_REGNO;
1051
  info_ptr->regs[STACK_REGS_LCR].last         = LCR_REGNO;
1052
 
1053
  info_ptr->regs[STACK_REGS_STDARG].name      = "stdarg";
1054
  info_ptr->regs[STACK_REGS_STDARG].first     = FIRST_ARG_REGNUM;
1055
  info_ptr->regs[STACK_REGS_STDARG].last      = LAST_ARG_REGNUM;
1056
  info_ptr->regs[STACK_REGS_STDARG].dword_p   = 1;
1057
  info_ptr->regs[STACK_REGS_STDARG].special_p = 1;
1058
 
1059
  info_ptr->regs[STACK_REGS_STRUCT].name      = "struct";
1060
  info_ptr->regs[STACK_REGS_STRUCT].first     = FRV_STRUCT_VALUE_REGNUM;
1061
  info_ptr->regs[STACK_REGS_STRUCT].last      = FRV_STRUCT_VALUE_REGNUM;
1062
  info_ptr->regs[STACK_REGS_STRUCT].special_p = 1;
1063
 
1064
  info_ptr->regs[STACK_REGS_FP].name          = "fp";
1065
  info_ptr->regs[STACK_REGS_FP].first         = FRAME_POINTER_REGNUM;
1066
  info_ptr->regs[STACK_REGS_FP].last          = FRAME_POINTER_REGNUM;
1067
  info_ptr->regs[STACK_REGS_FP].special_p     = 1;
1068
 
1069
  /* Determine if this is a stdarg function.  If so, allocate space to store
1070
     the 6 arguments.  */
1071
  if (cfun->stdarg)
1072
    varargs_p = 1;
1073
 
1074
  else
1075
    {
1076
      /* Find the last argument, and see if it is __builtin_va_alist.  */
1077
      for (cur_arg = DECL_ARGUMENTS (fndecl); cur_arg != (tree)0; cur_arg = next_arg)
1078
        {
1079
          next_arg = DECL_CHAIN (cur_arg);
1080
          if (next_arg == (tree)0)
1081
            {
1082
              if (DECL_NAME (cur_arg)
1083
                  && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)), "__builtin_va_alist"))
1084
                varargs_p = 1;
1085
 
1086
              break;
1087
            }
1088
        }
1089
    }
1090
 
1091
  /* Iterate over all of the register ranges.  */
1092
  for (range = 0; range < STACK_REGS_MAX; range++)
1093
    {
1094
      frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1095
      int first = reg_ptr->first;
1096
      int last = reg_ptr->last;
1097
      int size_1word = 0;
1098
      int size_2words = 0;
1099
      int regno;
1100
 
1101
      /* Calculate which registers need to be saved & save area size.  */
1102
      switch (range)
1103
        {
1104
        default:
1105
          for (regno = first; regno <= last; regno++)
1106
            {
1107
              if ((df_regs_ever_live_p (regno) && !call_used_regs[regno])
1108
                  || (crtl->calls_eh_return
1109
                      && (regno >= FIRST_EH_REGNUM && regno <= LAST_EH_REGNUM))
1110
                  || (!TARGET_FDPIC && flag_pic
1111
                      && crtl->uses_pic_offset_table && regno == PIC_REGNO))
1112
                {
1113
                  info_ptr->save_p[regno] = REG_SAVE_1WORD;
1114
                  size_1word += UNITS_PER_WORD;
1115
                }
1116
            }
1117
          break;
1118
 
1119
          /* Calculate whether we need to create a frame after everything else
1120
             has been processed.  */
1121
        case STACK_REGS_FP:
1122
          break;
1123
 
1124
        case STACK_REGS_LR:
1125
          if (df_regs_ever_live_p (LR_REGNO)
1126
              || profile_flag
1127
              /* This is set for __builtin_return_address, etc.  */
1128
              || cfun->machine->frame_needed
1129
              || (TARGET_LINKED_FP && frame_pointer_needed)
1130
              || (!TARGET_FDPIC && flag_pic
1131
                  && crtl->uses_pic_offset_table))
1132
            {
1133
              info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1134
              size_1word += UNITS_PER_WORD;
1135
            }
1136
          break;
1137
 
1138
        case STACK_REGS_STDARG:
1139
          if (varargs_p)
1140
            {
1141
              /* If this is a stdarg function with a non varardic
1142
                 argument split between registers and the stack,
1143
                 adjust the saved registers downward.  */
1144
              last -= (ADDR_ALIGN (crtl->args.pretend_args_size, UNITS_PER_WORD)
1145
                       / UNITS_PER_WORD);
1146
 
1147
              for (regno = first; regno <= last; regno++)
1148
                {
1149
                  info_ptr->save_p[regno] = REG_SAVE_1WORD;
1150
                  size_1word += UNITS_PER_WORD;
1151
                }
1152
 
1153
              info_ptr->stdarg_size = size_1word;
1154
            }
1155
          break;
1156
 
1157
        case STACK_REGS_STRUCT:
1158
          if (cfun->returns_struct)
1159
            {
1160
              info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1161
              size_1word += UNITS_PER_WORD;
1162
            }
1163
          break;
1164
        }
1165
 
1166
 
1167
      if (size_1word)
1168
        {
1169
          /* If this is a field, it only takes one word.  */
1170
          if (reg_ptr->field_p)
1171
            size_1word = UNITS_PER_WORD;
1172
 
1173
          /* Determine which register pairs can be saved together.  */
1174
          else if (reg_ptr->dword_p && TARGET_DWORD)
1175
            {
1176
              for (regno = first; regno < last; regno += 2)
1177
                {
1178
                  if (info_ptr->save_p[regno] && info_ptr->save_p[regno+1])
1179
                    {
1180
                      size_2words += 2 * UNITS_PER_WORD;
1181
                      size_1word -= 2 * UNITS_PER_WORD;
1182
                      info_ptr->save_p[regno] = REG_SAVE_2WORDS;
1183
                      info_ptr->save_p[regno+1] = REG_SAVE_NO_SAVE;
1184
                    }
1185
                }
1186
            }
1187
 
1188
          reg_ptr->size_1word = size_1word;
1189
          reg_ptr->size_2words = size_2words;
1190
 
1191
          if (! reg_ptr->special_p)
1192
            {
1193
              info_ptr->regs_size_1word += size_1word;
1194
              info_ptr->regs_size_2words += size_2words;
1195
            }
1196
        }
1197
    }
1198
 
1199
  /* Set up the sizes of each each field in the frame body, making the sizes
1200
     of each be divisible by the size of a dword if dword operations might
1201
     be used, or the size of a word otherwise.  */
1202
  alignment = (TARGET_DWORD? 2 * UNITS_PER_WORD : UNITS_PER_WORD);
1203
 
1204
  info_ptr->parameter_size = ADDR_ALIGN (crtl->outgoing_args_size, alignment);
1205
  info_ptr->regs_size = ADDR_ALIGN (info_ptr->regs_size_2words
1206
                                    + info_ptr->regs_size_1word,
1207
                                    alignment);
1208
  info_ptr->vars_size = ADDR_ALIGN (get_frame_size (), alignment);
1209
 
1210
  info_ptr->pretend_size = crtl->args.pretend_args_size;
1211
 
1212
  /* Work out the size of the frame, excluding the header.  Both the frame
1213
     body and register parameter area will be dword-aligned.  */
1214
  info_ptr->total_size
1215
    = (ADDR_ALIGN (info_ptr->parameter_size
1216
                   + info_ptr->regs_size
1217
                   + info_ptr->vars_size,
1218
                   2 * UNITS_PER_WORD)
1219
       + ADDR_ALIGN (info_ptr->pretend_size
1220
                     + info_ptr->stdarg_size,
1221
                     2 * UNITS_PER_WORD));
1222
 
1223
  /* See if we need to create a frame at all, if so add header area.  */
1224
  if (info_ptr->total_size  > 0
1225
      || frame_pointer_needed
1226
      || info_ptr->regs[STACK_REGS_LR].size_1word > 0
1227
      || info_ptr->regs[STACK_REGS_STRUCT].size_1word > 0)
1228
    {
1229
      offset = info_ptr->parameter_size;
1230
      info_ptr->header_size = 4 * UNITS_PER_WORD;
1231
      info_ptr->total_size += 4 * UNITS_PER_WORD;
1232
 
1233
      /* Calculate the offsets to save normal register pairs.  */
1234
      for (range = 0; range < STACK_REGS_MAX; range++)
1235
        {
1236
          frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1237
          if (! reg_ptr->special_p)
1238
            {
1239
              int first = reg_ptr->first;
1240
              int last = reg_ptr->last;
1241
              int regno;
1242
 
1243
              for (regno = first; regno <= last; regno++)
1244
                if (info_ptr->save_p[regno] == REG_SAVE_2WORDS
1245
                    && regno != FRAME_POINTER_REGNUM
1246
                    && (regno < FIRST_ARG_REGNUM
1247
                        || regno > LAST_ARG_REGNUM))
1248
                  {
1249
                    info_ptr->reg_offset[regno] = offset;
1250
                    offset += 2 * UNITS_PER_WORD;
1251
                  }
1252
            }
1253
        }
1254
 
1255
      /* Calculate the offsets to save normal single registers.  */
1256
      for (range = 0; range < STACK_REGS_MAX; range++)
1257
        {
1258
          frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1259
          if (! reg_ptr->special_p)
1260
            {
1261
              int first = reg_ptr->first;
1262
              int last = reg_ptr->last;
1263
              int regno;
1264
 
1265
              for (regno = first; regno <= last; regno++)
1266
                if (info_ptr->save_p[regno] == REG_SAVE_1WORD
1267
                    && regno != FRAME_POINTER_REGNUM
1268
                    && (regno < FIRST_ARG_REGNUM
1269
                        || regno > LAST_ARG_REGNUM))
1270
                  {
1271
                    info_ptr->reg_offset[regno] = offset;
1272
                    offset += UNITS_PER_WORD;
1273
                  }
1274
            }
1275
        }
1276
 
1277
      /* Calculate the offset to save the local variables at.  */
1278
      offset = ADDR_ALIGN (offset, alignment);
1279
      if (info_ptr->vars_size)
1280
        {
1281
          info_ptr->vars_offset = offset;
1282
          offset += info_ptr->vars_size;
1283
        }
1284
 
1285
      /* Align header to a dword-boundary.  */
1286
      offset = ADDR_ALIGN (offset, 2 * UNITS_PER_WORD);
1287
 
1288
      /* Calculate the offsets in the fixed frame.  */
1289
      info_ptr->save_p[FRAME_POINTER_REGNUM] = REG_SAVE_1WORD;
1290
      info_ptr->reg_offset[FRAME_POINTER_REGNUM] = offset;
1291
      info_ptr->regs[STACK_REGS_FP].size_1word = UNITS_PER_WORD;
1292
 
1293
      info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1294
      info_ptr->reg_offset[LR_REGNO] = offset + 2*UNITS_PER_WORD;
1295
      info_ptr->regs[STACK_REGS_LR].size_1word = UNITS_PER_WORD;
1296
 
1297
      if (cfun->returns_struct)
1298
        {
1299
          info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1300
          info_ptr->reg_offset[FRV_STRUCT_VALUE_REGNUM] = offset + UNITS_PER_WORD;
1301
          info_ptr->regs[STACK_REGS_STRUCT].size_1word = UNITS_PER_WORD;
1302
        }
1303
 
1304
      /* Calculate the offsets to store the arguments passed in registers
1305
         for stdarg functions.  The register pairs are first and the single
1306
         register if any is last.  The register save area starts on a
1307
         dword-boundary.  */
1308
      if (info_ptr->stdarg_size)
1309
        {
1310
          int first = info_ptr->regs[STACK_REGS_STDARG].first;
1311
          int last  = info_ptr->regs[STACK_REGS_STDARG].last;
1312
          int regno;
1313
 
1314
          /* Skip the header.  */
1315
          offset += 4 * UNITS_PER_WORD;
1316
          for (regno = first; regno <= last; regno++)
1317
            {
1318
              if (info_ptr->save_p[regno] == REG_SAVE_2WORDS)
1319
                {
1320
                  info_ptr->reg_offset[regno] = offset;
1321
                  offset += 2 * UNITS_PER_WORD;
1322
                }
1323
              else if (info_ptr->save_p[regno] == REG_SAVE_1WORD)
1324
                {
1325
                  info_ptr->reg_offset[regno] = offset;
1326
                  offset += UNITS_PER_WORD;
1327
                }
1328
            }
1329
        }
1330
    }
1331
 
1332
  if (reload_completed)
1333
    frv_stack_cache = info_ptr;
1334
 
1335
  return info_ptr;
1336
}
1337
 
1338
 
1339
/* Print the information about the frv stack offsets, etc. when debugging.  */
1340
 
1341
void
1342
frv_debug_stack (frv_stack_t *info)
1343
{
1344
  int range;
1345
 
1346
  if (!info)
1347
    info = frv_stack_info ();
1348
 
1349
  fprintf (stderr, "\nStack information for function %s:\n",
1350
           ((current_function_decl && DECL_NAME (current_function_decl))
1351
            ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
1352
            : "<unknown>"));
1353
 
1354
  fprintf (stderr, "\ttotal_size\t= %6d\n", info->total_size);
1355
  fprintf (stderr, "\tvars_size\t= %6d\n", info->vars_size);
1356
  fprintf (stderr, "\tparam_size\t= %6d\n", info->parameter_size);
1357
  fprintf (stderr, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n",
1358
           info->regs_size, info->regs_size_1word, info->regs_size_2words);
1359
 
1360
  fprintf (stderr, "\theader_size\t= %6d\n", info->header_size);
1361
  fprintf (stderr, "\tpretend_size\t= %6d\n", info->pretend_size);
1362
  fprintf (stderr, "\tvars_offset\t= %6d\n", info->vars_offset);
1363
  fprintf (stderr, "\tregs_offset\t= %6d\n", info->regs_offset);
1364
 
1365
  for (range = 0; range < STACK_REGS_MAX; range++)
1366
    {
1367
      frv_stack_regs_t *regs = &(info->regs[range]);
1368
      if ((regs->size_1word + regs->size_2words) > 0)
1369
        {
1370
          int first = regs->first;
1371
          int last  = regs->last;
1372
          int regno;
1373
 
1374
          fprintf (stderr, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =",
1375
                   regs->name, regs->size_1word + regs->size_2words,
1376
                   regs->size_1word, regs->size_2words);
1377
 
1378
          for (regno = first; regno <= last; regno++)
1379
            {
1380
              if (info->save_p[regno] == REG_SAVE_1WORD)
1381
                fprintf (stderr, " %s (%d)", reg_names[regno],
1382
                         info->reg_offset[regno]);
1383
 
1384
              else if (info->save_p[regno] == REG_SAVE_2WORDS)
1385
                fprintf (stderr, " %s-%s (%d)", reg_names[regno],
1386
                         reg_names[regno+1], info->reg_offset[regno]);
1387
            }
1388
 
1389
          fputc ('\n', stderr);
1390
        }
1391
    }
1392
 
1393
  fflush (stderr);
1394
}
1395
 
1396
 
1397
 
1398
 
1399
/* Used during final to control the packing of insns.  The value is
1400
   1 if the current instruction should be packed with the next one,
1401
 
1402
 
1403
static int frv_insn_packing_flag;
1404
 
1405
/* True if the current function contains a far jump.  */
1406
 
1407
static int
1408
frv_function_contains_far_jump (void)
1409
{
1410
  rtx insn = get_insns ();
1411
  while (insn != NULL
1412
         && !(GET_CODE (insn) == JUMP_INSN
1413
              /* Ignore tablejump patterns.  */
1414
              && GET_CODE (PATTERN (insn)) != ADDR_VEC
1415
              && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
1416
              && get_attr_far_jump (insn) == FAR_JUMP_YES))
1417
    insn = NEXT_INSN (insn);
1418
  return (insn != NULL);
1419
}
1420
 
1421
/* For the FRV, this function makes sure that a function with far jumps
1422
   will return correctly.  It also does the VLIW packing.  */
1423
 
1424
static void
1425
frv_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1426
{
1427
  rtx insn, next, last_call;
1428
 
1429
  /* If no frame was created, check whether the function uses a call
1430
     instruction to implement a far jump.  If so, save the link in gr3 and
1431
     replace all returns to LR with returns to GR3.  GR3 is used because it
1432
     is call-clobbered, because is not available to the register allocator,
1433
     and because all functions that take a hidden argument pointer will have
1434
     a stack frame.  */
1435
  if (frv_stack_info ()->total_size == 0 && frv_function_contains_far_jump ())
1436
    {
1437
      rtx insn;
1438
 
1439
      /* Just to check that the above comment is true.  */
1440
      gcc_assert (!df_regs_ever_live_p (GPR_FIRST + 3));
1441
 
1442
      /* Generate the instruction that saves the link register.  */
1443
      fprintf (file, "\tmovsg lr,gr3\n");
1444
 
1445
      /* Replace the LR with GR3 in *return_internal patterns.  The insn
1446
         will now return using jmpl @(gr3,0) rather than bralr.  We cannot
1447
         simply emit a different assembly directive because bralr and jmpl
1448
         execute in different units.  */
1449
      for (insn = get_insns(); insn != NULL; insn = NEXT_INSN (insn))
1450
        if (GET_CODE (insn) == JUMP_INSN)
1451
          {
1452
            rtx pattern = PATTERN (insn);
1453
            if (GET_CODE (pattern) == PARALLEL
1454
                && XVECLEN (pattern, 0) >= 2
1455
                && GET_CODE (XVECEXP (pattern, 0, 0)) == RETURN
1456
                && GET_CODE (XVECEXP (pattern, 0, 1)) == USE)
1457
              {
1458
                rtx address = XEXP (XVECEXP (pattern, 0, 1), 0);
1459
                if (GET_CODE (address) == REG && REGNO (address) == LR_REGNO)
1460
                  SET_REGNO (address, GPR_FIRST + 3);
1461
              }
1462
          }
1463
    }
1464
 
1465
  frv_pack_insns ();
1466
 
1467
  /* Allow the garbage collector to free the nops created by frv_reorg.  */
1468
  memset (frv_nops, 0, sizeof (frv_nops));
1469
 
1470
  /* Locate CALL_ARG_LOCATION notes that have been misplaced
1471
     and move them back to where they should be located.  */
1472
  last_call = NULL_RTX;
1473
  for (insn = get_insns (); insn; insn = next)
1474
    {
1475
      next = NEXT_INSN (insn);
1476
      if (CALL_P (insn)
1477
          || (INSN_P (insn) && GET_CODE (PATTERN (insn)) == SEQUENCE
1478
              && CALL_P (XVECEXP (PATTERN (insn), 0, 0))))
1479
        last_call = insn;
1480
 
1481
      if (!NOTE_P (insn) || NOTE_KIND (insn) != NOTE_INSN_CALL_ARG_LOCATION)
1482
        continue;
1483
 
1484
      if (NEXT_INSN (last_call) == insn)
1485
        continue;
1486
 
1487
      NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
1488
      PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
1489
      PREV_INSN (insn) = last_call;
1490
      NEXT_INSN (insn) = NEXT_INSN (last_call);
1491
      PREV_INSN (NEXT_INSN (insn)) = insn;
1492
      NEXT_INSN (PREV_INSN (insn)) = insn;
1493
      last_call = insn;
1494
    }
1495
}
1496
 
1497
 
1498
/* Return the next available temporary register in a given class.  */
1499
 
1500
static rtx
1501
frv_alloc_temp_reg (
1502
     frv_tmp_reg_t *info,       /* which registers are available */
1503
     enum reg_class rclass,     /* register class desired */
1504
     enum machine_mode mode,    /* mode to allocate register with */
1505
     int mark_as_used,          /* register not available after allocation */
1506
     int no_abort)              /* return NULL instead of aborting */
1507
{
1508
  int regno = info->next_reg[ (int)rclass ];
1509
  int orig_regno = regno;
1510
  HARD_REG_SET *reg_in_class = &reg_class_contents[ (int)rclass ];
1511
  int i, nr;
1512
 
1513
  for (;;)
1514
    {
1515
      if (TEST_HARD_REG_BIT (*reg_in_class, regno)
1516
          && TEST_HARD_REG_BIT (info->regs, regno))
1517
          break;
1518
 
1519
      if (++regno >= FIRST_PSEUDO_REGISTER)
1520
        regno = 0;
1521
      if (regno == orig_regno)
1522
        {
1523
          gcc_assert (no_abort);
1524
          return NULL_RTX;
1525
        }
1526
    }
1527
 
1528
  nr = HARD_REGNO_NREGS (regno, mode);
1529
  info->next_reg[ (int)rclass ] = regno + nr;
1530
 
1531
  if (mark_as_used)
1532
    for (i = 0; i < nr; i++)
1533
      CLEAR_HARD_REG_BIT (info->regs, regno+i);
1534
 
1535
  return gen_rtx_REG (mode, regno);
1536
}
1537
 
1538
 
1539
/* Return an rtx with the value OFFSET, which will either be a register or a
1540
   signed 12-bit integer.  It can be used as the second operand in an "add"
1541
   instruction, or as the index in a load or store.
1542
 
1543
   The function returns a constant rtx if OFFSET is small enough, otherwise
1544
   it loads the constant into register OFFSET_REGNO and returns that.  */
1545
static rtx
1546
frv_frame_offset_rtx (int offset)
1547
{
1548
  rtx offset_rtx = GEN_INT (offset);
1549
  if (IN_RANGE (offset, -2048, 2047))
1550
    return offset_rtx;
1551
  else
1552
    {
1553
      rtx reg_rtx = gen_rtx_REG (SImode, OFFSET_REGNO);
1554
      if (IN_RANGE (offset, -32768, 32767))
1555
        emit_insn (gen_movsi (reg_rtx, offset_rtx));
1556
      else
1557
        {
1558
          emit_insn (gen_movsi_high (reg_rtx, offset_rtx));
1559
          emit_insn (gen_movsi_lo_sum (reg_rtx, offset_rtx));
1560
        }
1561
      return reg_rtx;
1562
    }
1563
}
1564
 
1565
/* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))).  The
1566
   prologue and epilogue uses such expressions to access the stack.  */
1567
static rtx
1568
frv_frame_mem (enum machine_mode mode, rtx base, int offset)
1569
{
1570
  return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode,
1571
                                          base,
1572
                                          frv_frame_offset_rtx (offset)));
1573
}
1574
 
1575
/* Generate a frame-related expression:
1576
 
1577
        (set REG (mem (plus (sp) (const_int OFFSET)))).
1578
 
1579
   Such expressions are used in FRAME_RELATED_EXPR notes for more complex
1580
   instructions.  Marking the expressions as frame-related is superfluous if
1581
   the note contains just a single set.  But if the note contains a PARALLEL
1582
   or SEQUENCE that has several sets, each set must be individually marked
1583
   as frame-related.  */
1584
static rtx
1585
frv_dwarf_store (rtx reg, int offset)
1586
{
1587
  rtx set = gen_rtx_SET (VOIDmode,
1588
                         gen_rtx_MEM (GET_MODE (reg),
1589
                                      plus_constant (stack_pointer_rtx,
1590
                                                     offset)),
1591
                         reg);
1592
  RTX_FRAME_RELATED_P (set) = 1;
1593
  return set;
1594
}
1595
 
1596
/* Emit a frame-related instruction whose pattern is PATTERN.  The
1597
   instruction is the last in a sequence that cumulatively performs the
1598
   operation described by DWARF_PATTERN.  The instruction is marked as
1599
   frame-related and has a REG_FRAME_RELATED_EXPR note containing
1600
   DWARF_PATTERN.  */
1601
static void
1602
frv_frame_insn (rtx pattern, rtx dwarf_pattern)
1603
{
1604
  rtx insn = emit_insn (pattern);
1605
  RTX_FRAME_RELATED_P (insn) = 1;
1606
  REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
1607
                                      dwarf_pattern,
1608
                                      REG_NOTES (insn));
1609
}
1610
 
1611
/* Emit instructions that transfer REG to or from the memory location (sp +
1612
   STACK_OFFSET).  The register is stored in memory if ACCESSOR->OP is
1613
   FRV_STORE and loaded if it is FRV_LOAD.  Only the prologue uses this
1614
   function to store registers and only the epilogue uses it to load them.
1615
 
1616
   The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET).
1617
   The generated instruction will use BASE as its base register.  BASE may
1618
   simply be the stack pointer, but if several accesses are being made to a
1619
   region far away from the stack pointer, it may be more efficient to set
1620
   up a temporary instead.
1621
 
1622
   Store instructions will be frame-related and will be annotated with the
1623
   overall effect of the store.  Load instructions will be followed by a
1624
   (use) to prevent later optimizations from zapping them.
1625
 
1626
   The function takes care of the moves to and from SPRs, using TEMP_REGNO
1627
   as a temporary in such cases.  */
1628
static void
1629
frv_frame_access (frv_frame_accessor_t *accessor, rtx reg, int stack_offset)
1630
{
1631
  enum machine_mode mode = GET_MODE (reg);
1632
  rtx mem = frv_frame_mem (mode,
1633
                           accessor->base,
1634
                           stack_offset - accessor->base_offset);
1635
 
1636
  if (accessor->op == FRV_LOAD)
1637
    {
1638
      if (SPR_P (REGNO (reg)))
1639
        {
1640
          rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1641
          emit_insn (gen_rtx_SET (VOIDmode, temp, mem));
1642
          emit_insn (gen_rtx_SET (VOIDmode, reg, temp));
1643
        }
1644
      else
1645
        {
1646
          /* We cannot use reg+reg addressing for DImode access.  */
1647
          if (mode == DImode
1648
              && GET_CODE (XEXP (mem, 0)) == PLUS
1649
              && GET_CODE (XEXP (XEXP (mem, 0), 0)) == REG
1650
              && GET_CODE (XEXP (XEXP (mem, 0), 1)) == REG)
1651
            {
1652
              rtx temp = gen_rtx_REG (SImode, TEMP_REGNO);
1653
 
1654
              emit_move_insn (temp,
1655
                              gen_rtx_PLUS (SImode, XEXP (XEXP (mem, 0), 0),
1656
                                            XEXP (XEXP (mem, 0), 1)));
1657
              mem = gen_rtx_MEM (DImode, temp);
1658
            }
1659
          emit_insn (gen_rtx_SET (VOIDmode, reg, mem));
1660
        }
1661
      emit_use (reg);
1662
    }
1663
  else
1664
    {
1665
      if (SPR_P (REGNO (reg)))
1666
        {
1667
          rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1668
          emit_insn (gen_rtx_SET (VOIDmode, temp, reg));
1669
          frv_frame_insn (gen_rtx_SET (Pmode, mem, temp),
1670
                          frv_dwarf_store (reg, stack_offset));
1671
        }
1672
      else if (mode == DImode)
1673
        {
1674
          /* For DImode saves, the dwarf2 version needs to be a SEQUENCE
1675
             with a separate save for each register.  */
1676
          rtx reg1 = gen_rtx_REG (SImode, REGNO (reg));
1677
          rtx reg2 = gen_rtx_REG (SImode, REGNO (reg) + 1);
1678
          rtx set1 = frv_dwarf_store (reg1, stack_offset);
1679
          rtx set2 = frv_dwarf_store (reg2, stack_offset + 4);
1680
 
1681
          /* Also we cannot use reg+reg addressing.  */
1682
          if (GET_CODE (XEXP (mem, 0)) == PLUS
1683
              && GET_CODE (XEXP (XEXP (mem, 0), 0)) == REG
1684
              && GET_CODE (XEXP (XEXP (mem, 0), 1)) == REG)
1685
            {
1686
              rtx temp = gen_rtx_REG (SImode, TEMP_REGNO);
1687
              emit_move_insn (temp,
1688
                              gen_rtx_PLUS (SImode, XEXP (XEXP (mem, 0), 0),
1689
                                            XEXP (XEXP (mem, 0), 1)));
1690
              mem = gen_rtx_MEM (DImode, temp);
1691
            }
1692
 
1693
          frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1694
                          gen_rtx_PARALLEL (VOIDmode,
1695
                                            gen_rtvec (2, set1, set2)));
1696
        }
1697
      else
1698
        frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1699
                        frv_dwarf_store (reg, stack_offset));
1700
    }
1701
}
1702
 
1703
/* A function that uses frv_frame_access to transfer a group of registers to
1704
   or from the stack.  ACCESSOR is passed directly to frv_frame_access, INFO
1705
   is the stack information generated by frv_stack_info, and REG_SET is the
1706
   number of the register set to transfer.  */
1707
static void
1708
frv_frame_access_multi (frv_frame_accessor_t *accessor,
1709
                        frv_stack_t *info,
1710
                        int reg_set)
1711
{
1712
  frv_stack_regs_t *regs_info;
1713
  int regno;
1714
 
1715
  regs_info = &info->regs[reg_set];
1716
  for (regno = regs_info->first; regno <= regs_info->last; regno++)
1717
    if (info->save_p[regno])
1718
      frv_frame_access (accessor,
1719
                        info->save_p[regno] == REG_SAVE_2WORDS
1720
                        ? gen_rtx_REG (DImode, regno)
1721
                        : gen_rtx_REG (SImode, regno),
1722
                        info->reg_offset[regno]);
1723
}
1724
 
1725
/* Save or restore callee-saved registers that are kept outside the frame
1726
   header.  The function saves the registers if OP is FRV_STORE and restores
1727
   them if OP is FRV_LOAD.  INFO is the stack information generated by
1728
   frv_stack_info.  */
1729
static void
1730
frv_frame_access_standard_regs (enum frv_stack_op op, frv_stack_t *info)
1731
{
1732
  frv_frame_accessor_t accessor;
1733
 
1734
  accessor.op = op;
1735
  accessor.base = stack_pointer_rtx;
1736
  accessor.base_offset = 0;
1737
  frv_frame_access_multi (&accessor, info, STACK_REGS_GPR);
1738
  frv_frame_access_multi (&accessor, info, STACK_REGS_FPR);
1739
  frv_frame_access_multi (&accessor, info, STACK_REGS_LCR);
1740
}
1741
 
1742
 
1743
/* Called after register allocation to add any instructions needed for the
1744
   prologue.  Using a prologue insn is favored compared to putting all of the
1745
   instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1746
   it allows the scheduler to intermix instructions with the saves of
1747
   the caller saved registers.  In some cases, it might be necessary
1748
   to emit a barrier instruction as the last insn to prevent such
1749
   scheduling.
1750
 
1751
   Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
1752
   so that the debug info generation code can handle them properly.  */
1753
void
1754
frv_expand_prologue (void)
1755
{
1756
  frv_stack_t *info = frv_stack_info ();
1757
  rtx sp = stack_pointer_rtx;
1758
  rtx fp = frame_pointer_rtx;
1759
  frv_frame_accessor_t accessor;
1760
 
1761
  if (TARGET_DEBUG_STACK)
1762
    frv_debug_stack (info);
1763
 
1764
  if (info->total_size == 0)
1765
    return;
1766
 
1767
  /* We're interested in three areas of the frame here:
1768
 
1769
         A: the register save area
1770
         B: the old FP
1771
         C: the header after B
1772
 
1773
     If the frame pointer isn't used, we'll have to set up A, B and C
1774
     using the stack pointer.  If the frame pointer is used, we'll access
1775
     them as follows:
1776
 
1777
         A: set up using sp
1778
         B: set up using sp or a temporary (see below)
1779
         C: set up using fp
1780
 
1781
     We set up B using the stack pointer if the frame is small enough.
1782
     Otherwise, it's more efficient to copy the old stack pointer into a
1783
     temporary and use that.
1784
 
1785
     Note that it's important to make sure the prologue and epilogue use the
1786
     same registers to access A and C, since doing otherwise will confuse
1787
     the aliasing code.  */
1788
 
1789
  /* Set up ACCESSOR for accessing region B above.  If the frame pointer
1790
     isn't used, the same method will serve for C.  */
1791
  accessor.op = FRV_STORE;
1792
  if (frame_pointer_needed && info->total_size > 2048)
1793
    {
1794
      accessor.base = gen_rtx_REG (Pmode, OLD_SP_REGNO);
1795
      accessor.base_offset = info->total_size;
1796
      emit_insn (gen_movsi (accessor.base, sp));
1797
    }
1798
  else
1799
    {
1800
      accessor.base = stack_pointer_rtx;
1801
      accessor.base_offset = 0;
1802
    }
1803
 
1804
  /* Allocate the stack space.  */
1805
  {
1806
    rtx asm_offset = frv_frame_offset_rtx (-info->total_size);
1807
    rtx dwarf_offset = GEN_INT (-info->total_size);
1808
 
1809
    frv_frame_insn (gen_stack_adjust (sp, sp, asm_offset),
1810
                    gen_rtx_SET (Pmode,
1811
                                 sp,
1812
                                 gen_rtx_PLUS (Pmode, sp, dwarf_offset)));
1813
  }
1814
 
1815
  /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET)
1816
     and point the new one to that location.  */
1817
  if (frame_pointer_needed)
1818
    {
1819
      int fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1820
 
1821
      /* ASM_SRC and DWARF_SRC both point to the frame header.  ASM_SRC is
1822
         based on ACCESSOR.BASE but DWARF_SRC is always based on the stack
1823
         pointer.  */
1824
      rtx asm_src = plus_constant (accessor.base,
1825
                                   fp_offset - accessor.base_offset);
1826
      rtx dwarf_src = plus_constant (sp, fp_offset);
1827
 
1828
      /* Store the old frame pointer at (sp + FP_OFFSET).  */
1829
      frv_frame_access (&accessor, fp, fp_offset);
1830
 
1831
      /* Set up the new frame pointer.  */
1832
      frv_frame_insn (gen_rtx_SET (VOIDmode, fp, asm_src),
1833
                      gen_rtx_SET (VOIDmode, fp, dwarf_src));
1834
 
1835
      /* Access region C from the frame pointer.  */
1836
      accessor.base = fp;
1837
      accessor.base_offset = fp_offset;
1838
    }
1839
 
1840
  /* Set up region C.  */
1841
  frv_frame_access_multi (&accessor, info, STACK_REGS_STRUCT);
1842
  frv_frame_access_multi (&accessor, info, STACK_REGS_LR);
1843
  frv_frame_access_multi (&accessor, info, STACK_REGS_STDARG);
1844
 
1845
  /* Set up region A.  */
1846
  frv_frame_access_standard_regs (FRV_STORE, info);
1847
 
1848
  /* If this is a varargs/stdarg function, issue a blockage to prevent the
1849
     scheduler from moving loads before the stores saving the registers.  */
1850
  if (info->stdarg_size > 0)
1851
    emit_insn (gen_blockage ());
1852
 
1853
  /* Set up pic register/small data register for this function.  */
1854
  if (!TARGET_FDPIC && flag_pic && crtl->uses_pic_offset_table)
1855
    emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode, PIC_REGNO),
1856
                                 gen_rtx_REG (Pmode, LR_REGNO),
1857
                                 gen_rtx_REG (SImode, OFFSET_REGNO)));
1858
}
1859
 
1860
 
1861
/* Under frv, all of the work is done via frv_expand_epilogue, but
1862
   this function provides a convenient place to do cleanup.  */
1863
 
1864
static void
1865
frv_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
1866
                       HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1867
{
1868
  frv_stack_cache = (frv_stack_t *)0;
1869
 
1870
  /* Zap last used registers for conditional execution.  */
1871
  memset (&frv_ifcvt.tmp_reg, 0, sizeof (frv_ifcvt.tmp_reg));
1872
 
1873
  /* Release the bitmap of created insns.  */
1874
  BITMAP_FREE (frv_ifcvt.scratch_insns_bitmap);
1875
}
1876
 
1877
 
1878
/* Called after register allocation to add any instructions needed for the
1879
   epilogue.  Using an epilogue insn is favored compared to putting all of the
1880
   instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1881
   it allows the scheduler to intermix instructions with the saves of
1882
   the caller saved registers.  In some cases, it might be necessary
1883
   to emit a barrier instruction as the last insn to prevent such
1884
   scheduling.  */
1885
 
1886
void
1887
frv_expand_epilogue (bool emit_return)
1888
{
1889
  frv_stack_t *info = frv_stack_info ();
1890
  rtx fp = frame_pointer_rtx;
1891
  rtx sp = stack_pointer_rtx;
1892
  rtx return_addr;
1893
  int fp_offset;
1894
 
1895
  fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1896
 
1897
  /* Restore the stack pointer to its original value if alloca or the like
1898
     is used.  */
1899
  if (! current_function_sp_is_unchanging)
1900
    emit_insn (gen_addsi3 (sp, fp, frv_frame_offset_rtx (-fp_offset)));
1901
 
1902
  /* Restore the callee-saved registers that were used in this function.  */
1903
  frv_frame_access_standard_regs (FRV_LOAD, info);
1904
 
1905
  /* Set RETURN_ADDR to the address we should return to.  Set it to NULL if
1906
     no return instruction should be emitted.  */
1907
  if (info->save_p[LR_REGNO])
1908
    {
1909
      int lr_offset;
1910
      rtx mem;
1911
 
1912
      /* Use the same method to access the link register's slot as we did in
1913
         the prologue.  In other words, use the frame pointer if available,
1914
         otherwise use the stack pointer.
1915
 
1916
         LR_OFFSET is the offset of the link register's slot from the start
1917
         of the frame and MEM is a memory rtx for it.  */
1918
      lr_offset = info->reg_offset[LR_REGNO];
1919
      if (frame_pointer_needed)
1920
        mem = frv_frame_mem (Pmode, fp, lr_offset - fp_offset);
1921
      else
1922
        mem = frv_frame_mem (Pmode, sp, lr_offset);
1923
 
1924
      /* Load the old link register into a GPR.  */
1925
      return_addr = gen_rtx_REG (Pmode, TEMP_REGNO);
1926
      emit_insn (gen_rtx_SET (VOIDmode, return_addr, mem));
1927
    }
1928
  else
1929
    return_addr = gen_rtx_REG (Pmode, LR_REGNO);
1930
 
1931
  /* Restore the old frame pointer.  Emit a USE afterwards to make sure
1932
     the load is preserved.  */
1933
  if (frame_pointer_needed)
1934
    {
1935
      emit_insn (gen_rtx_SET (VOIDmode, fp, gen_rtx_MEM (Pmode, fp)));
1936
      emit_use (fp);
1937
    }
1938
 
1939
  /* Deallocate the stack frame.  */
1940
  if (info->total_size != 0)
1941
    {
1942
      rtx offset = frv_frame_offset_rtx (info->total_size);
1943
      emit_insn (gen_stack_adjust (sp, sp, offset));
1944
    }
1945
 
1946
  /* If this function uses eh_return, add the final stack adjustment now.  */
1947
  if (crtl->calls_eh_return)
1948
    emit_insn (gen_stack_adjust (sp, sp, EH_RETURN_STACKADJ_RTX));
1949
 
1950
  if (emit_return)
1951
    emit_jump_insn (gen_epilogue_return (return_addr));
1952
  else
1953
    {
1954
      rtx lr = return_addr;
1955
 
1956
      if (REGNO (return_addr) != LR_REGNO)
1957
        {
1958
          lr = gen_rtx_REG (Pmode, LR_REGNO);
1959
          emit_move_insn (lr, return_addr);
1960
        }
1961
 
1962
      emit_use (lr);
1963
    }
1964
}
1965
 
1966
 
1967
/* Worker function for TARGET_ASM_OUTPUT_MI_THUNK.  */
1968
 
1969
static void
1970
frv_asm_output_mi_thunk (FILE *file,
1971
                         tree thunk_fndecl ATTRIBUTE_UNUSED,
1972
                         HOST_WIDE_INT delta,
1973
                         HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
1974
                         tree function)
1975
{
1976
  const char *name_func = XSTR (XEXP (DECL_RTL (function), 0), 0);
1977
  const char *name_arg0 = reg_names[FIRST_ARG_REGNUM];
1978
  const char *name_jmp = reg_names[JUMP_REGNO];
1979
  const char *parallel = (frv_issue_rate () > 1 ? ".p" : "");
1980
 
1981
  /* Do the add using an addi if possible.  */
1982
  if (IN_RANGE (delta, -2048, 2047))
1983
    fprintf (file, "\taddi %s,#%d,%s\n", name_arg0, (int) delta, name_arg0);
1984
  else
1985
    {
1986
      const char *const name_add = reg_names[TEMP_REGNO];
1987
      fprintf (file, "\tsethi%s #hi(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
1988
               parallel, delta, name_add);
1989
      fprintf (file, "\tsetlo #lo(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
1990
               delta, name_add);
1991
      fprintf (file, "\tadd %s,%s,%s\n", name_add, name_arg0, name_arg0);
1992
    }
1993
 
1994
  if (TARGET_FDPIC)
1995
    {
1996
      const char *name_pic = reg_names[FDPIC_REGNO];
1997
      name_jmp = reg_names[FDPIC_FPTR_REGNO];
1998
 
1999
      if (flag_pic != 1)
2000
        {
2001
          fprintf (file, "\tsethi%s #gotofffuncdeschi(", parallel);
2002
          assemble_name (file, name_func);
2003
          fprintf (file, "),%s\n", name_jmp);
2004
 
2005
          fprintf (file, "\tsetlo #gotofffuncdesclo(");
2006
          assemble_name (file, name_func);
2007
          fprintf (file, "),%s\n", name_jmp);
2008
 
2009
          fprintf (file, "\tldd @(%s,%s), %s\n", name_jmp, name_pic, name_jmp);
2010
        }
2011
      else
2012
        {
2013
          fprintf (file, "\tlddo @(%s,#gotofffuncdesc12(", name_pic);
2014
          assemble_name (file, name_func);
2015
          fprintf (file, "\t)), %s\n", name_jmp);
2016
        }
2017
    }
2018
  else if (!flag_pic)
2019
    {
2020
      fprintf (file, "\tsethi%s #hi(", parallel);
2021
      assemble_name (file, name_func);
2022
      fprintf (file, "),%s\n", name_jmp);
2023
 
2024
      fprintf (file, "\tsetlo #lo(");
2025
      assemble_name (file, name_func);
2026
      fprintf (file, "),%s\n", name_jmp);
2027
    }
2028
  else
2029
    {
2030
      /* Use JUMP_REGNO as a temporary PIC register.  */
2031
      const char *name_lr = reg_names[LR_REGNO];
2032
      const char *name_gppic = name_jmp;
2033
      const char *name_tmp = reg_names[TEMP_REGNO];
2034
 
2035
      fprintf (file, "\tmovsg %s,%s\n", name_lr, name_tmp);
2036
      fprintf (file, "\tcall 1f\n");
2037
      fprintf (file, "1:\tmovsg %s,%s\n", name_lr, name_gppic);
2038
      fprintf (file, "\tmovgs %s,%s\n", name_tmp, name_lr);
2039
      fprintf (file, "\tsethi%s #gprelhi(1b),%s\n", parallel, name_tmp);
2040
      fprintf (file, "\tsetlo #gprello(1b),%s\n", name_tmp);
2041
      fprintf (file, "\tsub %s,%s,%s\n", name_gppic, name_tmp, name_gppic);
2042
 
2043
      fprintf (file, "\tsethi%s #gprelhi(", parallel);
2044
      assemble_name (file, name_func);
2045
      fprintf (file, "),%s\n", name_tmp);
2046
 
2047
      fprintf (file, "\tsetlo #gprello(");
2048
      assemble_name (file, name_func);
2049
      fprintf (file, "),%s\n", name_tmp);
2050
 
2051
      fprintf (file, "\tadd %s,%s,%s\n", name_gppic, name_tmp, name_jmp);
2052
    }
2053
 
2054
  /* Jump to the function address.  */
2055
  fprintf (file, "\tjmpl @(%s,%s)\n", name_jmp, reg_names[GPR_FIRST+0]);
2056
}
2057
 
2058
 
2059
 
2060
/* On frv, create a frame whenever we need to create stack.  */
2061
 
2062
static bool
2063
frv_frame_pointer_required (void)
2064
{
2065
  /* If we forgoing the usual linkage requirements, we only need
2066
     a frame pointer if the stack pointer might change.  */
2067
  if (!TARGET_LINKED_FP)
2068
    return !current_function_sp_is_unchanging;
2069
 
2070
  if (! current_function_is_leaf)
2071
    return true;
2072
 
2073
  if (get_frame_size () != 0)
2074
    return true;
2075
 
2076
  if (cfun->stdarg)
2077
    return true;
2078
 
2079
  if (!current_function_sp_is_unchanging)
2080
    return true;
2081
 
2082
  if (!TARGET_FDPIC && flag_pic && crtl->uses_pic_offset_table)
2083
    return true;
2084
 
2085
  if (profile_flag)
2086
    return true;
2087
 
2088
  if (cfun->machine->frame_needed)
2089
    return true;
2090
 
2091
  return false;
2092
}
2093
 
2094
 
2095
/* Worker function for TARGET_CAN_ELIMINATE.  */
2096
 
2097
bool
2098
frv_can_eliminate (const int from, const int to)
2099
{
2100
  return (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM
2101
          ? ! frame_pointer_needed
2102
          : true);
2103
}
2104
 
2105
/* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'.  It specifies the
2106
   initial difference between the specified pair of registers.  This macro must
2107
   be defined if `ELIMINABLE_REGS' is defined.  */
2108
 
2109
/* See frv_stack_info for more details on the frv stack frame.  */
2110
 
2111
int
2112
frv_initial_elimination_offset (int from, int to)
2113
{
2114
  frv_stack_t *info = frv_stack_info ();
2115
  int ret = 0;
2116
 
2117
  if (to == STACK_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2118
    ret = info->total_size - info->pretend_size;
2119
 
2120
  else if (to == STACK_POINTER_REGNUM && from == FRAME_POINTER_REGNUM)
2121
    ret = info->reg_offset[FRAME_POINTER_REGNUM];
2122
 
2123
  else if (to == FRAME_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2124
    ret = (info->total_size
2125
           - info->reg_offset[FRAME_POINTER_REGNUM]
2126
           - info->pretend_size);
2127
 
2128
  else
2129
    gcc_unreachable ();
2130
 
2131
  if (TARGET_DEBUG_STACK)
2132
    fprintf (stderr, "Eliminate %s to %s by adding %d\n",
2133
             reg_names [from], reg_names[to], ret);
2134
 
2135
  return ret;
2136
}
2137
 
2138
 
2139
/* Worker function for TARGET_SETUP_INCOMING_VARARGS.  */
2140
 
2141
static void
2142
frv_setup_incoming_varargs (cumulative_args_t cum_v,
2143
                            enum machine_mode mode,
2144
                            tree type ATTRIBUTE_UNUSED,
2145
                            int *pretend_size,
2146
                            int second_time)
2147
{
2148
  CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
2149
 
2150
  if (TARGET_DEBUG_ARG)
2151
    fprintf (stderr,
2152
             "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n",
2153
             *cum, GET_MODE_NAME (mode), *pretend_size, second_time);
2154
}
2155
 
2156
 
2157
/* Worker function for TARGET_EXPAND_BUILTIN_SAVEREGS.  */
2158
 
2159
static rtx
2160
frv_expand_builtin_saveregs (void)
2161
{
2162
  int offset = UNITS_PER_WORD * FRV_NUM_ARG_REGS;
2163
 
2164
  if (TARGET_DEBUG_ARG)
2165
    fprintf (stderr, "expand_builtin_saveregs: offset from ap = %d\n",
2166
             offset);
2167
 
2168
  return gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx, GEN_INT (- offset));
2169
}
2170
 
2171
 
2172
/* Expand __builtin_va_start to do the va_start macro.  */
2173
 
2174
static void
2175
frv_expand_builtin_va_start (tree valist, rtx nextarg)
2176
{
2177
  tree t;
2178
  int num = crtl->args.info - FIRST_ARG_REGNUM - FRV_NUM_ARG_REGS;
2179
 
2180
  nextarg = gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx,
2181
                          GEN_INT (UNITS_PER_WORD * num));
2182
 
2183
  if (TARGET_DEBUG_ARG)
2184
    {
2185
      fprintf (stderr, "va_start: args_info = %d, num = %d\n",
2186
               crtl->args.info, num);
2187
 
2188
      debug_rtx (nextarg);
2189
    }
2190
 
2191
  t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist,
2192
              fold_convert (TREE_TYPE (valist),
2193
                            make_tree (sizetype, nextarg)));
2194
  TREE_SIDE_EFFECTS (t) = 1;
2195
 
2196
  expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2197
}
2198
 
2199
 
2200
/* Expand a block move operation, and return 1 if successful.  Return 0
2201
   if we should let the compiler generate normal code.
2202
 
2203
   operands[0] is the destination
2204
   operands[1] is the source
2205
   operands[2] is the length
2206
   operands[3] is the alignment */
2207
 
2208
/* Maximum number of loads to do before doing the stores */
2209
#ifndef MAX_MOVE_REG
2210
#define MAX_MOVE_REG 4
2211
#endif
2212
 
2213
/* Maximum number of total loads to do.  */
2214
#ifndef TOTAL_MOVE_REG
2215
#define TOTAL_MOVE_REG 8
2216
#endif
2217
 
2218
int
2219
frv_expand_block_move (rtx operands[])
2220
{
2221
  rtx orig_dest = operands[0];
2222
  rtx orig_src  = operands[1];
2223
  rtx bytes_rtx = operands[2];
2224
  rtx align_rtx = operands[3];
2225
  int constp    = (GET_CODE (bytes_rtx) == CONST_INT);
2226
  int align;
2227
  int bytes;
2228
  int offset;
2229
  int num_reg;
2230
  int i;
2231
  rtx src_reg;
2232
  rtx dest_reg;
2233
  rtx src_addr;
2234
  rtx dest_addr;
2235
  rtx src_mem;
2236
  rtx dest_mem;
2237
  rtx tmp_reg;
2238
  rtx stores[MAX_MOVE_REG];
2239
  int move_bytes;
2240
  enum machine_mode mode;
2241
 
2242
  /* If this is not a fixed size move, just call memcpy.  */
2243
  if (! constp)
2244
    return FALSE;
2245
 
2246
  /* This should be a fixed size alignment.  */
2247
  gcc_assert (GET_CODE (align_rtx) == CONST_INT);
2248
 
2249
  align = INTVAL (align_rtx);
2250
 
2251
  /* Anything to move? */
2252
  bytes = INTVAL (bytes_rtx);
2253
  if (bytes <= 0)
2254
    return TRUE;
2255
 
2256
  /* Don't support real large moves.  */
2257
  if (bytes > TOTAL_MOVE_REG*align)
2258
    return FALSE;
2259
 
2260
  /* Move the address into scratch registers.  */
2261
  dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2262
  src_reg  = copy_addr_to_reg (XEXP (orig_src,  0));
2263
 
2264
  num_reg = offset = 0;
2265
  for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes))
2266
    {
2267
      /* Calculate the correct offset for src/dest.  */
2268
      if (offset == 0)
2269
        {
2270
          src_addr  = src_reg;
2271
          dest_addr = dest_reg;
2272
        }
2273
      else
2274
        {
2275
          src_addr = plus_constant (src_reg, offset);
2276
          dest_addr = plus_constant (dest_reg, offset);
2277
        }
2278
 
2279
      /* Generate the appropriate load and store, saving the stores
2280
         for later.  */
2281
      if (bytes >= 4 && align >= 4)
2282
        mode = SImode;
2283
      else if (bytes >= 2 && align >= 2)
2284
        mode = HImode;
2285
      else
2286
        mode = QImode;
2287
 
2288
      move_bytes = GET_MODE_SIZE (mode);
2289
      tmp_reg = gen_reg_rtx (mode);
2290
      src_mem = change_address (orig_src, mode, src_addr);
2291
      dest_mem = change_address (orig_dest, mode, dest_addr);
2292
      emit_insn (gen_rtx_SET (VOIDmode, tmp_reg, src_mem));
2293
      stores[num_reg++] = gen_rtx_SET (VOIDmode, dest_mem, tmp_reg);
2294
 
2295
      if (num_reg >= MAX_MOVE_REG)
2296
        {
2297
          for (i = 0; i < num_reg; i++)
2298
            emit_insn (stores[i]);
2299
          num_reg = 0;
2300
        }
2301
    }
2302
 
2303
  for (i = 0; i < num_reg; i++)
2304
    emit_insn (stores[i]);
2305
 
2306
  return TRUE;
2307
}
2308
 
2309
 
2310
/* Expand a block clear operation, and return 1 if successful.  Return 0
2311
   if we should let the compiler generate normal code.
2312
 
2313
   operands[0] is the destination
2314
   operands[1] is the length
2315
   operands[3] is the alignment */
2316
 
2317
int
2318
frv_expand_block_clear (rtx operands[])
2319
{
2320
  rtx orig_dest = operands[0];
2321
  rtx bytes_rtx = operands[1];
2322
  rtx align_rtx = operands[3];
2323
  int constp    = (GET_CODE (bytes_rtx) == CONST_INT);
2324
  int align;
2325
  int bytes;
2326
  int offset;
2327
  rtx dest_reg;
2328
  rtx dest_addr;
2329
  rtx dest_mem;
2330
  int clear_bytes;
2331
  enum machine_mode mode;
2332
 
2333
  /* If this is not a fixed size move, just call memcpy.  */
2334
  if (! constp)
2335
    return FALSE;
2336
 
2337
  /* This should be a fixed size alignment.  */
2338
  gcc_assert (GET_CODE (align_rtx) == CONST_INT);
2339
 
2340
  align = INTVAL (align_rtx);
2341
 
2342
  /* Anything to move? */
2343
  bytes = INTVAL (bytes_rtx);
2344
  if (bytes <= 0)
2345
    return TRUE;
2346
 
2347
  /* Don't support real large clears.  */
2348
  if (bytes > TOTAL_MOVE_REG*align)
2349
    return FALSE;
2350
 
2351
  /* Move the address into a scratch register.  */
2352
  dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2353
 
2354
  offset = 0;
2355
  for ( ; bytes > 0; (bytes -= clear_bytes), (offset += clear_bytes))
2356
    {
2357
      /* Calculate the correct offset for src/dest.  */
2358
      dest_addr = ((offset == 0)
2359
                   ? dest_reg
2360
                   : plus_constant (dest_reg, offset));
2361
 
2362
      /* Generate the appropriate store of gr0.  */
2363
      if (bytes >= 4 && align >= 4)
2364
        mode = SImode;
2365
      else if (bytes >= 2 && align >= 2)
2366
        mode = HImode;
2367
      else
2368
        mode = QImode;
2369
 
2370
      clear_bytes = GET_MODE_SIZE (mode);
2371
      dest_mem = change_address (orig_dest, mode, dest_addr);
2372
      emit_insn (gen_rtx_SET (VOIDmode, dest_mem, const0_rtx));
2373
    }
2374
 
2375
  return TRUE;
2376
}
2377
 
2378
 
2379
/* The following variable is used to output modifiers of assembler
2380
   code of the current output insn.  */
2381
 
2382
static rtx *frv_insn_operands;
2383
 
2384
/* The following function is used to add assembler insn code suffix .p
2385
   if it is necessary.  */
2386
 
2387
const char *
2388
frv_asm_output_opcode (FILE *f, const char *ptr)
2389
{
2390
  int c;
2391
 
2392
  if (frv_insn_packing_flag <= 0)
2393
    return ptr;
2394
 
2395
  for (; *ptr && *ptr != ' ' && *ptr != '\t';)
2396
    {
2397
      c = *ptr++;
2398
      if (c == '%' && ((*ptr >= 'a' && *ptr <= 'z')
2399
                       || (*ptr >= 'A' && *ptr <= 'Z')))
2400
        {
2401
          int letter = *ptr++;
2402
 
2403
          c = atoi (ptr);
2404
          frv_print_operand (f, frv_insn_operands [c], letter);
2405
          while ((c = *ptr) >= '0' && c <= '9')
2406
            ptr++;
2407
        }
2408
      else
2409
        fputc (c, f);
2410
    }
2411
 
2412
  fprintf (f, ".p");
2413
 
2414
  return ptr;
2415
}
2416
 
2417
/* Set up the packing bit for the current output insn.  Note that this
2418
   function is not called for asm insns.  */
2419
 
2420
void
2421
frv_final_prescan_insn (rtx insn, rtx *opvec,
2422
                        int noperands ATTRIBUTE_UNUSED)
2423
{
2424
  if (INSN_P (insn))
2425
    {
2426
      if (frv_insn_packing_flag >= 0)
2427
        {
2428
          frv_insn_operands = opvec;
2429
          frv_insn_packing_flag = PACKING_FLAG_P (insn);
2430
        }
2431
      else if (recog_memoized (insn) >= 0
2432
               && get_attr_acc_group (insn) == ACC_GROUP_ODD)
2433
        /* Packing optimizations have been disabled, but INSN can only
2434
           be issued in M1.  Insert an mnop in M0.  */
2435
        fprintf (asm_out_file, "\tmnop.p\n");
2436
    }
2437
}
2438
 
2439
 
2440
 
2441
/* A C expression whose value is RTL representing the address in a stack frame
2442
   where the pointer to the caller's frame is stored.  Assume that FRAMEADDR is
2443
   an RTL expression for the address of the stack frame itself.
2444
 
2445
   If you don't define this macro, the default is to return the value of
2446
   FRAMEADDR--that is, the stack frame address is also the address of the stack
2447
   word that points to the previous frame.  */
2448
 
2449
/* The default is correct, but we need to make sure the frame gets created.  */
2450
rtx
2451
frv_dynamic_chain_address (rtx frame)
2452
{
2453
  cfun->machine->frame_needed = 1;
2454
  return frame;
2455
}
2456
 
2457
 
2458
/* A C expression whose value is RTL representing the value of the return
2459
   address for the frame COUNT steps up from the current frame, after the
2460
   prologue.  FRAMEADDR is the frame pointer of the COUNT frame, or the frame
2461
   pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
2462
   defined.
2463
 
2464
   The value of the expression must always be the correct address when COUNT is
2465
   zero, but may be `NULL_RTX' if there is not way to determine the return
2466
   address of other frames.  */
2467
 
2468
rtx
2469
frv_return_addr_rtx (int count, rtx frame)
2470
{
2471
  if (count != 0)
2472
    return const0_rtx;
2473
  cfun->machine->frame_needed = 1;
2474
  return gen_rtx_MEM (Pmode, plus_constant (frame, 8));
2475
}
2476
 
2477
/* Given a memory reference MEMREF, interpret the referenced memory as
2478
   an array of MODE values, and return a reference to the element
2479
   specified by INDEX.  Assume that any pre-modification implicit in
2480
   MEMREF has already happened.
2481
 
2482
   MEMREF must be a legitimate operand for modes larger than SImode.
2483
   frv_legitimate_address_p forbids register+register addresses, which
2484
   this function cannot handle.  */
2485
rtx
2486
frv_index_memory (rtx memref, enum machine_mode mode, int index)
2487
{
2488
  rtx base = XEXP (memref, 0);
2489
  if (GET_CODE (base) == PRE_MODIFY)
2490
    base = XEXP (base, 0);
2491
  return change_address (memref, mode,
2492
                         plus_constant (base, index * GET_MODE_SIZE (mode)));
2493
}
2494
 
2495
 
2496
/* Print a memory address as an operand to reference that memory location.  */
2497
static void
2498
frv_print_operand_address (FILE * stream, rtx x)
2499
{
2500
  if (GET_CODE (x) == MEM)
2501
    x = XEXP (x, 0);
2502
 
2503
  switch (GET_CODE (x))
2504
    {
2505
    case REG:
2506
      fputs (reg_names [ REGNO (x)], stream);
2507
      return;
2508
 
2509
    case CONST_INT:
2510
      fprintf (stream, "%ld", (long) INTVAL (x));
2511
      return;
2512
 
2513
    case SYMBOL_REF:
2514
      assemble_name (stream, XSTR (x, 0));
2515
      return;
2516
 
2517
    case LABEL_REF:
2518
    case CONST:
2519
      output_addr_const (stream, x);
2520
      return;
2521
 
2522
    case PLUS:
2523
      /* Poorly constructed asm statements can trigger this alternative.
2524
         See gcc/testsuite/gcc.dg/asm-4.c for an example.  */
2525
      frv_print_operand_memory_reference (stream, x, 0);
2526
      return;
2527
 
2528
    default:
2529
      break;
2530
    }
2531
 
2532
  fatal_insn ("bad insn to frv_print_operand_address:", x);
2533
}
2534
 
2535
 
2536
static void
2537
frv_print_operand_memory_reference_reg (FILE * stream, rtx x)
2538
{
2539
  int regno = true_regnum (x);
2540
  if (GPR_P (regno))
2541
    fputs (reg_names[regno], stream);
2542
  else
2543
    fatal_insn ("bad register to frv_print_operand_memory_reference_reg:", x);
2544
}
2545
 
2546
/* Print a memory reference suitable for the ld/st instructions.  */
2547
 
2548
static void
2549
frv_print_operand_memory_reference (FILE * stream, rtx x, int addr_offset)
2550
{
2551
  struct frv_unspec unspec;
2552
  rtx x0 = NULL_RTX;
2553
  rtx x1 = NULL_RTX;
2554
 
2555
  switch (GET_CODE (x))
2556
    {
2557
    case SUBREG:
2558
    case REG:
2559
      x0 = x;
2560
      break;
2561
 
2562
    case PRE_MODIFY:            /* (pre_modify (reg) (plus (reg) (reg))) */
2563
      x0 = XEXP (x, 0);
2564
      x1 = XEXP (XEXP (x, 1), 1);
2565
      break;
2566
 
2567
    case CONST_INT:
2568
      x1 = x;
2569
      break;
2570
 
2571
    case PLUS:
2572
      x0 = XEXP (x, 0);
2573
      x1 = XEXP (x, 1);
2574
      if (GET_CODE (x0) == CONST_INT)
2575
        {
2576
          x0 = XEXP (x, 1);
2577
          x1 = XEXP (x, 0);
2578
        }
2579
      break;
2580
 
2581
    default:
2582
      fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2583
      break;
2584
 
2585
    }
2586
 
2587
  if (addr_offset)
2588
    {
2589
      if (!x1)
2590
        x1 = const0_rtx;
2591
      else if (GET_CODE (x1) != CONST_INT)
2592
        fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2593
    }
2594
 
2595
  fputs ("@(", stream);
2596
  if (!x0)
2597
    fputs (reg_names[GPR_R0], stream);
2598
  else if (GET_CODE (x0) == REG || GET_CODE (x0) == SUBREG)
2599
    frv_print_operand_memory_reference_reg (stream, x0);
2600
  else
2601
    fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2602
 
2603
  fputs (",", stream);
2604
  if (!x1)
2605
    fputs (reg_names [GPR_R0], stream);
2606
 
2607
  else
2608
    {
2609
      switch (GET_CODE (x1))
2610
        {
2611
        case SUBREG:
2612
        case REG:
2613
          frv_print_operand_memory_reference_reg (stream, x1);
2614
          break;
2615
 
2616
        case CONST_INT:
2617
          fprintf (stream, "%ld", (long) (INTVAL (x1) + addr_offset));
2618
          break;
2619
 
2620
        case CONST:
2621
          if (!frv_const_unspec_p (x1, &unspec))
2622
            fatal_insn ("bad insn to frv_print_operand_memory_reference:", x1);
2623
          frv_output_const_unspec (stream, &unspec);
2624
          break;
2625
 
2626
        default:
2627
          fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2628
        }
2629
    }
2630
 
2631
  fputs (")", stream);
2632
}
2633
 
2634
 
2635
/* Return 2 for likely branches and 0 for non-likely branches  */
2636
 
2637
#define FRV_JUMP_LIKELY 2
2638
#define FRV_JUMP_NOT_LIKELY 0
2639
 
2640
static int
2641
frv_print_operand_jump_hint (rtx insn)
2642
{
2643
  rtx note;
2644
  rtx labelref;
2645
  int ret;
2646
  HOST_WIDE_INT prob = -1;
2647
  enum { UNKNOWN, BACKWARD, FORWARD } jump_type = UNKNOWN;
2648
 
2649
  gcc_assert (GET_CODE (insn) == JUMP_INSN);
2650
 
2651
  /* Assume any non-conditional jump is likely.  */
2652
  if (! any_condjump_p (insn))
2653
    ret = FRV_JUMP_LIKELY;
2654
 
2655
  else
2656
    {
2657
      labelref = condjump_label (insn);
2658
      if (labelref)
2659
        {
2660
          rtx label = XEXP (labelref, 0);
2661
          jump_type = (insn_current_address > INSN_ADDRESSES (INSN_UID (label))
2662
                       ? BACKWARD
2663
                       : FORWARD);
2664
        }
2665
 
2666
      note = find_reg_note (insn, REG_BR_PROB, 0);
2667
      if (!note)
2668
        ret = ((jump_type == BACKWARD) ? FRV_JUMP_LIKELY : FRV_JUMP_NOT_LIKELY);
2669
 
2670
      else
2671
        {
2672
          prob = INTVAL (XEXP (note, 0));
2673
          ret = ((prob >= (REG_BR_PROB_BASE / 2))
2674
                 ? FRV_JUMP_LIKELY
2675
                 : FRV_JUMP_NOT_LIKELY);
2676
        }
2677
    }
2678
 
2679
#if 0
2680
  if (TARGET_DEBUG)
2681
    {
2682
      char *direction;
2683
 
2684
      switch (jump_type)
2685
        {
2686
        default:
2687
        case UNKNOWN:   direction = "unknown jump direction";   break;
2688
        case BACKWARD:  direction = "jump backward";            break;
2689
        case FORWARD:   direction = "jump forward";             break;
2690
        }
2691
 
2692
      fprintf (stderr,
2693
               "%s: uid %ld, %s, probability = %ld, max prob. = %ld, hint = %d\n",
2694
               IDENTIFIER_POINTER (DECL_NAME (current_function_decl)),
2695
               (long)INSN_UID (insn), direction, (long)prob,
2696
               (long)REG_BR_PROB_BASE, ret);
2697
    }
2698
#endif
2699
 
2700
  return ret;
2701
}
2702
 
2703
 
2704
/* Return the comparison operator to use for CODE given that the ICC
2705
   register is OP0.  */
2706
 
2707
static const char *
2708
comparison_string (enum rtx_code code, rtx op0)
2709
{
2710
  bool is_nz_p = GET_MODE (op0) == CC_NZmode;
2711
  switch (code)
2712
    {
2713
    default:  output_operand_lossage ("bad condition code");
2714
    case EQ:  return "eq";
2715
    case NE:  return "ne";
2716
    case LT:  return is_nz_p ? "n" : "lt";
2717
    case LE:  return "le";
2718
    case GT:  return "gt";
2719
    case GE:  return is_nz_p ? "p" : "ge";
2720
    case LTU: return is_nz_p ? "no" : "c";
2721
    case LEU: return is_nz_p ? "eq" : "ls";
2722
    case GTU: return is_nz_p ? "ne" : "hi";
2723
    case GEU: return is_nz_p ? "ra" : "nc";
2724
    }
2725
}
2726
 
2727
/* Print an operand to an assembler instruction.
2728
 
2729
   `%' followed by a letter and a digit says to output an operand in an
2730
   alternate fashion.  Four letters have standard, built-in meanings
2731
   described below.  The hook `TARGET_PRINT_OPERAND' can define
2732
   additional letters with nonstandard meanings.
2733
 
2734
   `%cDIGIT' can be used to substitute an operand that is a constant value
2735
   without the syntax that normally indicates an immediate operand.
2736
 
2737
   `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated
2738
   before printing.
2739
 
2740
   `%aDIGIT' can be used to substitute an operand as if it were a memory
2741
   reference, with the actual operand treated as the address.  This may be
2742
   useful when outputting a "load address" instruction, because often the
2743
   assembler syntax for such an instruction requires you to write the operand
2744
   as if it were a memory reference.
2745
 
2746
   `%lDIGIT' is used to substitute a `label_ref' into a jump instruction.
2747
 
2748
   `%=' outputs a number which is unique to each instruction in the entire
2749
   compilation.  This is useful for making local labels to be referred to more
2750
   than once in a single template that generates multiple assembler
2751
   instructions.
2752
 
2753
   `%' followed by a punctuation character specifies a substitution that
2754
   does not use an operand.  Only one case is standard: `%%' outputs a
2755
   `%' into the assembler code.  Other nonstandard cases can be defined
2756
   in the `TARGET_PRINT_OPERAND' hook.  You must also define which
2757
   punctuation characters are valid with the
2758
   `TARGET_PRINT_OPERAND_PUNCT_VALID_P' hook.  */
2759
 
2760
static void
2761
frv_print_operand (FILE * file, rtx x, int code)
2762
{
2763
  struct frv_unspec unspec;
2764
  HOST_WIDE_INT value;
2765
  int offset;
2766
 
2767
  if (code != 0 && !ISALPHA (code))
2768
    value = 0;
2769
 
2770
  else if (GET_CODE (x) == CONST_INT)
2771
    value = INTVAL (x);
2772
 
2773
  else if (GET_CODE (x) == CONST_DOUBLE)
2774
    {
2775
      if (GET_MODE (x) == SFmode)
2776
        {
2777
          REAL_VALUE_TYPE rv;
2778
          long l;
2779
 
2780
          REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
2781
          REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2782
          value = l;
2783
        }
2784
 
2785
      else if (GET_MODE (x) == VOIDmode)
2786
        value = CONST_DOUBLE_LOW (x);
2787
 
2788
      else
2789
        fatal_insn ("bad insn in frv_print_operand, bad const_double", x);
2790
    }
2791
 
2792
  else
2793
    value = 0;
2794
 
2795
  switch (code)
2796
    {
2797
 
2798
    case '.':
2799
      /* Output r0.  */
2800
      fputs (reg_names[GPR_R0], file);
2801
      break;
2802
 
2803
    case '#':
2804
      fprintf (file, "%d", frv_print_operand_jump_hint (current_output_insn));
2805
      break;
2806
 
2807
    case '@':
2808
      /* Output small data area base register (gr16).  */
2809
      fputs (reg_names[SDA_BASE_REG], file);
2810
      break;
2811
 
2812
    case '~':
2813
      /* Output pic register (gr17).  */
2814
      fputs (reg_names[PIC_REGNO], file);
2815
      break;
2816
 
2817
    case '*':
2818
      /* Output the temporary integer CCR register.  */
2819
      fputs (reg_names[ICR_TEMP], file);
2820
      break;
2821
 
2822
    case '&':
2823
      /* Output the temporary integer CC register.  */
2824
      fputs (reg_names[ICC_TEMP], file);
2825
      break;
2826
 
2827
    /* case 'a': print an address.  */
2828
 
2829
    case 'C':
2830
      /* Print appropriate test for integer branch false operation.  */
2831
      fputs (comparison_string (reverse_condition (GET_CODE (x)),
2832
                                XEXP (x, 0)), file);
2833
      break;
2834
 
2835
    case 'c':
2836
      /* Print appropriate test for integer branch true operation.  */
2837
      fputs (comparison_string (GET_CODE (x), XEXP (x, 0)), file);
2838
      break;
2839
 
2840
    case 'e':
2841
      /* Print 1 for a NE and 0 for an EQ to give the final argument
2842
         for a conditional instruction.  */
2843
      if (GET_CODE (x) == NE)
2844
        fputs ("1", file);
2845
 
2846
      else if (GET_CODE (x) == EQ)
2847
        fputs ("0", file);
2848
 
2849
      else
2850
        fatal_insn ("bad insn to frv_print_operand, 'e' modifier:", x);
2851
      break;
2852
 
2853
    case 'F':
2854
      /* Print appropriate test for floating point branch false operation.  */
2855
      switch (GET_CODE (x))
2856
        {
2857
        default:
2858
          fatal_insn ("bad insn to frv_print_operand, 'F' modifier:", x);
2859
 
2860
        case EQ:  fputs ("ne",  file); break;
2861
        case NE:  fputs ("eq",  file); break;
2862
        case LT:  fputs ("uge", file); break;
2863
        case LE:  fputs ("ug",  file); break;
2864
        case GT:  fputs ("ule", file); break;
2865
        case GE:  fputs ("ul",  file); break;
2866
        }
2867
      break;
2868
 
2869
    case 'f':
2870
      /* Print appropriate test for floating point branch true operation.  */
2871
      switch (GET_CODE (x))
2872
        {
2873
        default:
2874
          fatal_insn ("bad insn to frv_print_operand, 'f' modifier:", x);
2875
 
2876
        case EQ:  fputs ("eq",  file); break;
2877
        case NE:  fputs ("ne",  file); break;
2878
        case LT:  fputs ("lt",  file); break;
2879
        case LE:  fputs ("le",  file); break;
2880
        case GT:  fputs ("gt",  file); break;
2881
        case GE:  fputs ("ge",  file); break;
2882
        }
2883
      break;
2884
 
2885
    case 'g':
2886
      /* Print appropriate GOT function.  */
2887
      if (GET_CODE (x) != CONST_INT)
2888
        fatal_insn ("bad insn to frv_print_operand, 'g' modifier:", x);
2889
      fputs (unspec_got_name (INTVAL (x)), file);
2890
      break;
2891
 
2892
    case 'I':
2893
      /* Print 'i' if the operand is a constant, or is a memory reference that
2894
         adds a constant.  */
2895
      if (GET_CODE (x) == MEM)
2896
        x = ((GET_CODE (XEXP (x, 0)) == PLUS)
2897
             ? XEXP (XEXP (x, 0), 1)
2898
             : XEXP (x, 0));
2899
      else if (GET_CODE (x) == PLUS)
2900
        x = XEXP (x, 1);
2901
 
2902
      switch (GET_CODE (x))
2903
        {
2904
        default:
2905
          break;
2906
 
2907
        case CONST_INT:
2908
        case SYMBOL_REF:
2909
        case CONST:
2910
          fputs ("i", file);
2911
          break;
2912
        }
2913
      break;
2914
 
2915
    case 'i':
2916
      /* For jump instructions, print 'i' if the operand is a constant or
2917
         is an expression that adds a constant.  */
2918
      if (GET_CODE (x) == CONST_INT)
2919
        fputs ("i", file);
2920
 
2921
      else
2922
        {
2923
          if (GET_CODE (x) == CONST_INT
2924
              || (GET_CODE (x) == PLUS
2925
                  && (GET_CODE (XEXP (x, 1)) == CONST_INT
2926
                      || GET_CODE (XEXP (x, 0)) == CONST_INT)))
2927
            fputs ("i", file);
2928
        }
2929
      break;
2930
 
2931
    case 'L':
2932
      /* Print the lower register of a double word register pair */
2933
      if (GET_CODE (x) == REG)
2934
        fputs (reg_names[ REGNO (x)+1 ], file);
2935
      else
2936
        fatal_insn ("bad insn to frv_print_operand, 'L' modifier:", x);
2937
      break;
2938
 
2939
    /* case 'l': print a LABEL_REF.  */
2940
 
2941
    case 'M':
2942
    case 'N':
2943
      /* Print a memory reference for ld/st/jmp, %N prints a memory reference
2944
         for the second word of double memory operations.  */
2945
      offset = (code == 'M') ? 0 : UNITS_PER_WORD;
2946
      switch (GET_CODE (x))
2947
        {
2948
        default:
2949
          fatal_insn ("bad insn to frv_print_operand, 'M/N' modifier:", x);
2950
 
2951
        case MEM:
2952
          frv_print_operand_memory_reference (file, XEXP (x, 0), offset);
2953
          break;
2954
 
2955
        case REG:
2956
        case SUBREG:
2957
        case CONST_INT:
2958
        case PLUS:
2959
        case SYMBOL_REF:
2960
          frv_print_operand_memory_reference (file, x, offset);
2961
          break;
2962
        }
2963
      break;
2964
 
2965
    case 'O':
2966
      /* Print the opcode of a command.  */
2967
      switch (GET_CODE (x))
2968
        {
2969
        default:
2970
          fatal_insn ("bad insn to frv_print_operand, 'O' modifier:", x);
2971
 
2972
        case PLUS:     fputs ("add", file); break;
2973
        case MINUS:    fputs ("sub", file); break;
2974
        case AND:      fputs ("and", file); break;
2975
        case IOR:      fputs ("or",  file); break;
2976
        case XOR:      fputs ("xor", file); break;
2977
        case ASHIFT:   fputs ("sll", file); break;
2978
        case ASHIFTRT: fputs ("sra", file); break;
2979
        case LSHIFTRT: fputs ("srl", file); break;
2980
        }
2981
      break;
2982
 
2983
    /* case 'n': negate and print a constant int.  */
2984
 
2985
    case 'P':
2986
      /* Print PIC label using operand as the number.  */
2987
      if (GET_CODE (x) != CONST_INT)
2988
        fatal_insn ("bad insn to frv_print_operand, P modifier:", x);
2989
 
2990
      fprintf (file, ".LCF%ld", (long)INTVAL (x));
2991
      break;
2992
 
2993
    case 'U':
2994
      /* Print 'u' if the operand is a update load/store.  */
2995
      if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
2996
        fputs ("u", file);
2997
      break;
2998
 
2999
    case 'z':
3000
      /* If value is 0, print gr0, otherwise it must be a register.  */
3001
      if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0)
3002
        fputs (reg_names[GPR_R0], file);
3003
 
3004
      else if (GET_CODE (x) == REG)
3005
        fputs (reg_names [REGNO (x)], file);
3006
 
3007
      else
3008
        fatal_insn ("bad insn in frv_print_operand, z case", x);
3009
      break;
3010
 
3011
    case 'x':
3012
      /* Print constant in hex.  */
3013
      if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
3014
        {
3015
          fprintf (file, "%s0x%.4lx", IMMEDIATE_PREFIX, (long) value);
3016
          break;
3017
        }
3018
 
3019
      /* Fall through.  */
3020
 
3021
    case '\0':
3022
      if (GET_CODE (x) == REG)
3023
        fputs (reg_names [REGNO (x)], file);
3024
 
3025
      else if (GET_CODE (x) == CONST_INT
3026
              || GET_CODE (x) == CONST_DOUBLE)
3027
        fprintf (file, "%s%ld", IMMEDIATE_PREFIX, (long) value);
3028
 
3029
      else if (frv_const_unspec_p (x, &unspec))
3030
        frv_output_const_unspec (file, &unspec);
3031
 
3032
      else if (GET_CODE (x) == MEM)
3033
        frv_print_operand_address (file, XEXP (x, 0));
3034
 
3035
      else if (CONSTANT_ADDRESS_P (x))
3036
        frv_print_operand_address (file, x);
3037
 
3038
      else
3039
        fatal_insn ("bad insn in frv_print_operand, 0 case", x);
3040
 
3041
      break;
3042
 
3043
    default:
3044
      fatal_insn ("frv_print_operand: unknown code", x);
3045
      break;
3046
    }
3047
 
3048
  return;
3049
}
3050
 
3051
static bool
3052
frv_print_operand_punct_valid_p (unsigned char code)
3053
{
3054
  return (code == '.' || code == '#' || code == '@' || code == '~'
3055
          || code == '*' || code == '&');
3056
}
3057
 
3058
 
3059
/* A C statement (sans semicolon) for initializing the variable CUM for the
3060
   state at the beginning of the argument list.  The variable has type
3061
   `CUMULATIVE_ARGS'.  The value of FNTYPE is the tree node for the data type
3062
   of the function which will receive the args, or 0 if the args are to a
3063
   compiler support library function.  The value of INDIRECT is nonzero when
3064
   processing an indirect call, for example a call through a function pointer.
3065
   The value of INDIRECT is zero for a call to an explicitly named function, a
3066
   library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
3067
   arguments for the function being compiled.
3068
 
3069
   When processing a call to a compiler support library function, LIBNAME
3070
   identifies which one.  It is a `symbol_ref' rtx which contains the name of
3071
   the function, as a string.  LIBNAME is 0 when an ordinary C function call is
3072
   being processed.  Thus, each time this macro is called, either LIBNAME or
3073
   FNTYPE is nonzero, but never both of them at once.  */
3074
 
3075
void
3076
frv_init_cumulative_args (CUMULATIVE_ARGS *cum,
3077
                          tree fntype,
3078
                          rtx libname,
3079
                          tree fndecl,
3080
                          int incoming)
3081
{
3082
  *cum = FIRST_ARG_REGNUM;
3083
 
3084
  if (TARGET_DEBUG_ARG)
3085
    {
3086
      fprintf (stderr, "\ninit_cumulative_args:");
3087
      if (!fndecl && fntype)
3088
        fputs (" indirect", stderr);
3089
 
3090
      if (incoming)
3091
        fputs (" incoming", stderr);
3092
 
3093
      if (fntype)
3094
        {
3095
          tree ret_type = TREE_TYPE (fntype);
3096
          fprintf (stderr, " return=%s,",
3097
                   tree_code_name[ (int)TREE_CODE (ret_type) ]);
3098
        }
3099
 
3100
      if (libname && GET_CODE (libname) == SYMBOL_REF)
3101
        fprintf (stderr, " libname=%s", XSTR (libname, 0));
3102
 
3103
      if (cfun->returns_struct)
3104
        fprintf (stderr, " return-struct");
3105
 
3106
      putc ('\n', stderr);
3107
    }
3108
}
3109
 
3110
 
3111
/* Return true if we should pass an argument on the stack rather than
3112
   in registers.  */
3113
 
3114
static bool
3115
frv_must_pass_in_stack (enum machine_mode mode, const_tree type)
3116
{
3117
  if (mode == BLKmode)
3118
    return true;
3119
  if (type == NULL)
3120
    return false;
3121
  return AGGREGATE_TYPE_P (type);
3122
}
3123
 
3124
/* If defined, a C expression that gives the alignment boundary, in bits, of an
3125
   argument with the specified mode and type.  If it is not defined,
3126
   `PARM_BOUNDARY' is used for all arguments.  */
3127
 
3128
static unsigned int
3129
frv_function_arg_boundary (enum machine_mode mode ATTRIBUTE_UNUSED,
3130
                           const_tree type ATTRIBUTE_UNUSED)
3131
{
3132
  return BITS_PER_WORD;
3133
}
3134
 
3135
static rtx
3136
frv_function_arg_1 (cumulative_args_t cum_v, enum machine_mode mode,
3137
                    const_tree type ATTRIBUTE_UNUSED, bool named,
3138
                    bool incoming ATTRIBUTE_UNUSED)
3139
{
3140
  const CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
3141
 
3142
  enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3143
  int arg_num = *cum;
3144
  rtx ret;
3145
  const char *debstr;
3146
 
3147
  /* Return a marker for use in the call instruction.  */
3148
  if (xmode == VOIDmode)
3149
    {
3150
      ret = const0_rtx;
3151
      debstr = "<0>";
3152
    }
3153
 
3154
  else if (arg_num <= LAST_ARG_REGNUM)
3155
    {
3156
      ret = gen_rtx_REG (xmode, arg_num);
3157
      debstr = reg_names[arg_num];
3158
    }
3159
 
3160
  else
3161
    {
3162
      ret = NULL_RTX;
3163
      debstr = "memory";
3164
    }
3165
 
3166
  if (TARGET_DEBUG_ARG)
3167
    fprintf (stderr,
3168
             "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n",
3169
             arg_num, GET_MODE_NAME (mode), named, GET_MODE_SIZE (mode), debstr);
3170
 
3171
  return ret;
3172
}
3173
 
3174
static rtx
3175
frv_function_arg (cumulative_args_t cum, enum machine_mode mode,
3176
                  const_tree type, bool named)
3177
{
3178
  return frv_function_arg_1 (cum, mode, type, named, false);
3179
}
3180
 
3181
static rtx
3182
frv_function_incoming_arg (cumulative_args_t cum, enum machine_mode mode,
3183
                           const_tree type, bool named)
3184
{
3185
  return frv_function_arg_1 (cum, mode, type, named, true);
3186
}
3187
 
3188
 
3189
/* A C statement (sans semicolon) to update the summarizer variable CUM to
3190
   advance past an argument in the argument list.  The values MODE, TYPE and
3191
   NAMED describe that argument.  Once this is done, the variable CUM is
3192
   suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
3193
 
3194
   This macro need not do anything if the argument in question was passed on
3195
   the stack.  The compiler knows how to track the amount of stack space used
3196
   for arguments without any special help.  */
3197
 
3198
static void
3199
frv_function_arg_advance (cumulative_args_t cum_v,
3200
                          enum machine_mode mode,
3201
                          const_tree type ATTRIBUTE_UNUSED,
3202
                          bool named)
3203
{
3204
  CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
3205
 
3206
  enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3207
  int bytes = GET_MODE_SIZE (xmode);
3208
  int words = (bytes + UNITS_PER_WORD  - 1) / UNITS_PER_WORD;
3209
  int arg_num = *cum;
3210
 
3211
  *cum = arg_num + words;
3212
 
3213
  if (TARGET_DEBUG_ARG)
3214
    fprintf (stderr,
3215
             "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n",
3216
             arg_num, GET_MODE_NAME (mode), named, words * UNITS_PER_WORD);
3217
}
3218
 
3219
 
3220
/* A C expression for the number of words, at the beginning of an argument,
3221
   must be put in registers.  The value must be zero for arguments that are
3222
   passed entirely in registers or that are entirely pushed on the stack.
3223
 
3224
   On some machines, certain arguments must be passed partially in registers
3225
   and partially in memory.  On these machines, typically the first N words of
3226
   arguments are passed in registers, and the rest on the stack.  If a
3227
   multi-word argument (a `double' or a structure) crosses that boundary, its
3228
   first few words must be passed in registers and the rest must be pushed.
3229
   This macro tells the compiler when this occurs, and how many of the words
3230
   should go in registers.
3231
 
3232
   `FUNCTION_ARG' for these arguments should return the first register to be
3233
   used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
3234
   the called function.  */
3235
 
3236
static int
3237
frv_arg_partial_bytes (cumulative_args_t cum, enum machine_mode mode,
3238
                       tree type ATTRIBUTE_UNUSED, bool named ATTRIBUTE_UNUSED)
3239
{
3240
 
3241
  enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3242
  int bytes = GET_MODE_SIZE (xmode);
3243
  int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3244
  int arg_num = *get_cumulative_args (cum);
3245
  int ret;
3246
 
3247
  ret = ((arg_num <= LAST_ARG_REGNUM && arg_num + words > LAST_ARG_REGNUM+1)
3248
         ? LAST_ARG_REGNUM - arg_num + 1
3249
         : 0);
3250
  ret *= UNITS_PER_WORD;
3251
 
3252
  if (TARGET_DEBUG_ARG && ret)
3253
    fprintf (stderr, "frv_arg_partial_bytes: %d\n", ret);
3254
 
3255
  return ret;
3256
}
3257
 
3258
 
3259
/* Implements TARGET_FUNCTION_VALUE.  */
3260
 
3261
static rtx
3262
frv_function_value (const_tree valtype,
3263
                    const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
3264
                    bool outgoing ATTRIBUTE_UNUSED)
3265
{
3266
  return gen_rtx_REG (TYPE_MODE (valtype), RETURN_VALUE_REGNUM);
3267
}
3268
 
3269
 
3270
/* Implements TARGET_LIBCALL_VALUE.  */
3271
 
3272
static rtx
3273
frv_libcall_value (enum machine_mode mode,
3274
                   const_rtx fun ATTRIBUTE_UNUSED)
3275
{
3276
  return gen_rtx_REG (mode, RETURN_VALUE_REGNUM);
3277
}
3278
 
3279
 
3280
/* Implements FUNCTION_VALUE_REGNO_P.  */
3281
 
3282
bool
3283
frv_function_value_regno_p (const unsigned int regno)
3284
{
3285
  return (regno == RETURN_VALUE_REGNUM);
3286
}
3287
 
3288
/* Return true if a register is ok to use as a base or index register.  */
3289
 
3290
static FRV_INLINE int
3291
frv_regno_ok_for_base_p (int regno, int strict_p)
3292
{
3293
  if (GPR_P (regno))
3294
    return TRUE;
3295
 
3296
  if (strict_p)
3297
    return (reg_renumber[regno] >= 0 && GPR_P (reg_renumber[regno]));
3298
 
3299
  if (regno == ARG_POINTER_REGNUM)
3300
    return TRUE;
3301
 
3302
  return (regno >= FIRST_PSEUDO_REGISTER);
3303
}
3304
 
3305
 
3306
/* A C compound statement with a conditional `goto LABEL;' executed if X (an
3307
   RTX) is a legitimate memory address on the target machine for a memory
3308
   operand of mode MODE.
3309
 
3310
   It usually pays to define several simpler macros to serve as subroutines for
3311
   this one.  Otherwise it may be too complicated to understand.
3312
 
3313
   This macro must exist in two variants: a strict variant and a non-strict
3314
   one.  The strict variant is used in the reload pass.  It must be defined so
3315
   that any pseudo-register that has not been allocated a hard register is
3316
   considered a memory reference.  In contexts where some kind of register is
3317
   required, a pseudo-register with no hard register must be rejected.
3318
 
3319
   The non-strict variant is used in other passes.  It must be defined to
3320
   accept all pseudo-registers in every context where some kind of register is
3321
   required.
3322
 
3323
   Compiler source files that want to use the strict variant of this macro
3324
   define the macro `REG_OK_STRICT'.  You should use an `#ifdef REG_OK_STRICT'
3325
   conditional to define the strict variant in that case and the non-strict
3326
   variant otherwise.
3327
 
3328
   Normally, constant addresses which are the sum of a `symbol_ref' and an
3329
   integer are stored inside a `const' RTX to mark them as constant.
3330
   Therefore, there is no need to recognize such sums specifically as
3331
   legitimate addresses.  Normally you would simply recognize any `const' as
3332
   legitimate.
3333
 
3334
   Usually `TARGET_PRINT_OPERAND_ADDRESS' is not prepared to handle
3335
   constant sums that are not marked with `const'.  It assumes that a
3336
   naked `plus' indicates indexing.  If so, then you *must* reject such
3337
   naked constant sums as illegitimate addresses, so that none of them
3338
   will be given to `TARGET_PRINT_OPERAND_ADDRESS'.  */
3339
 
3340
int
3341
frv_legitimate_address_p_1 (enum machine_mode mode,
3342
                            rtx x,
3343
                            int strict_p,
3344
                            int condexec_p,
3345
                            int allow_double_reg_p)
3346
{
3347
  rtx x0, x1;
3348
  int ret = 0;
3349
  HOST_WIDE_INT value;
3350
  unsigned regno0;
3351
 
3352
  if (FRV_SYMBOL_REF_TLS_P (x))
3353
    return 0;
3354
 
3355
  switch (GET_CODE (x))
3356
    {
3357
    default:
3358
      break;
3359
 
3360
    case SUBREG:
3361
      x = SUBREG_REG (x);
3362
      if (GET_CODE (x) != REG)
3363
        break;
3364
 
3365
      /* Fall through.  */
3366
 
3367
    case REG:
3368
      ret = frv_regno_ok_for_base_p (REGNO (x), strict_p);
3369
      break;
3370
 
3371
    case PRE_MODIFY:
3372
      x0 = XEXP (x, 0);
3373
      x1 = XEXP (x, 1);
3374
      if (GET_CODE (x0) != REG
3375
          || ! frv_regno_ok_for_base_p (REGNO (x0), strict_p)
3376
          || GET_CODE (x1) != PLUS
3377
          || ! rtx_equal_p (x0, XEXP (x1, 0))
3378
          || GET_CODE (XEXP (x1, 1)) != REG
3379
          || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1, 1)), strict_p))
3380
        break;
3381
 
3382
      ret = 1;
3383
      break;
3384
 
3385
    case CONST_INT:
3386
      /* 12-bit immediate */
3387
      if (condexec_p)
3388
        ret = FALSE;
3389
      else
3390
        {
3391
          ret = IN_RANGE (INTVAL (x), -2048, 2047);
3392
 
3393
          /* If we can't use load/store double operations, make sure we can
3394
             address the second word.  */
3395
          if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3396
            ret = IN_RANGE (INTVAL (x) + GET_MODE_SIZE (mode) - 1,
3397
                            -2048, 2047);
3398
        }
3399
      break;
3400
 
3401
    case PLUS:
3402
      x0 = XEXP (x, 0);
3403
      x1 = XEXP (x, 1);
3404
 
3405
      if (GET_CODE (x0) == SUBREG)
3406
        x0 = SUBREG_REG (x0);
3407
 
3408
      if (GET_CODE (x0) != REG)
3409
        break;
3410
 
3411
      regno0 = REGNO (x0);
3412
      if (!frv_regno_ok_for_base_p (regno0, strict_p))
3413
        break;
3414
 
3415
      switch (GET_CODE (x1))
3416
        {
3417
        default:
3418
          break;
3419
 
3420
        case SUBREG:
3421
          x1 = SUBREG_REG (x1);
3422
          if (GET_CODE (x1) != REG)
3423
            break;
3424
 
3425
          /* Fall through.  */
3426
 
3427
        case REG:
3428
          /* Do not allow reg+reg addressing for modes > 1 word if we
3429
             can't depend on having move double instructions.  */
3430
          if (!allow_double_reg_p && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3431
            ret = FALSE;
3432
          else
3433
            ret = frv_regno_ok_for_base_p (REGNO (x1), strict_p);
3434
          break;
3435
 
3436
        case CONST_INT:
3437
          /* 12-bit immediate */
3438
          if (condexec_p)
3439
            ret = FALSE;
3440
          else
3441
            {
3442
              value = INTVAL (x1);
3443
              ret = IN_RANGE (value, -2048, 2047);
3444
 
3445
              /* If we can't use load/store double operations, make sure we can
3446
                 address the second word.  */
3447
              if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3448
                ret = IN_RANGE (value + GET_MODE_SIZE (mode) - 1, -2048, 2047);
3449
            }
3450
          break;
3451
 
3452
        case CONST:
3453
          if (!condexec_p && got12_operand (x1, VOIDmode))
3454
            ret = TRUE;
3455
          break;
3456
 
3457
        }
3458
      break;
3459
    }
3460
 
3461
  if (TARGET_DEBUG_ADDR)
3462
    {
3463
      fprintf (stderr, "\n========== legitimate_address_p, mode = %s, result = %d, addresses are %sstrict%s\n",
3464
               GET_MODE_NAME (mode), ret, (strict_p) ? "" : "not ",
3465
               (condexec_p) ? ", inside conditional code" : "");
3466
      debug_rtx (x);
3467
    }
3468
 
3469
  return ret;
3470
}
3471
 
3472
bool
3473
frv_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
3474
{
3475
  return frv_legitimate_address_p_1 (mode, x, strict_p, FALSE, FALSE);
3476
}
3477
 
3478
/* Given an ADDR, generate code to inline the PLT.  */
3479
static rtx
3480
gen_inlined_tls_plt (rtx addr)
3481
{
3482
  rtx retval, dest;
3483
  rtx picreg = get_hard_reg_initial_val (Pmode, FDPIC_REG);
3484
 
3485
 
3486
  dest = gen_reg_rtx (DImode);
3487
 
3488
  if (flag_pic == 1)
3489
    {
3490
      /*
3491
        -fpic version:
3492
 
3493
        lddi.p  @(gr15, #gottlsdesc12(ADDR)), gr8
3494
        calll    #gettlsoff(ADDR)@(gr8, gr0)
3495
      */
3496
      emit_insn (gen_tls_lddi (dest, addr, picreg));
3497
    }
3498
  else
3499
    {
3500
      /*
3501
        -fPIC version:
3502
 
3503
        sethi.p #gottlsdeschi(ADDR), gr8
3504
        setlo   #gottlsdesclo(ADDR), gr8
3505
        ldd     #tlsdesc(ADDR)@(gr15, gr8), gr8
3506
        calll   #gettlsoff(ADDR)@(gr8, gr0)
3507
      */
3508
      rtx reguse = gen_reg_rtx (Pmode);
3509
      emit_insn (gen_tlsoff_hilo (reguse, addr, GEN_INT (R_FRV_GOTTLSDESCHI)));
3510
      emit_insn (gen_tls_tlsdesc_ldd (dest, picreg, reguse, addr));
3511
    }
3512
 
3513
  retval = gen_reg_rtx (Pmode);
3514
  emit_insn (gen_tls_indirect_call (retval, addr, dest, picreg));
3515
  return retval;
3516
}
3517
 
3518
/* Emit a TLSMOFF or TLSMOFF12 offset, depending on -mTLS.  Returns
3519
   the destination address.  */
3520
static rtx
3521
gen_tlsmoff (rtx addr, rtx reg)
3522
{
3523
  rtx dest = gen_reg_rtx (Pmode);
3524
 
3525
  if (TARGET_BIG_TLS)
3526
    {
3527
      /* sethi.p #tlsmoffhi(x), grA
3528
         setlo   #tlsmofflo(x), grA
3529
      */
3530
      dest = gen_reg_rtx (Pmode);
3531
      emit_insn (gen_tlsoff_hilo (dest, addr,
3532
                                  GEN_INT (R_FRV_TLSMOFFHI)));
3533
      dest = gen_rtx_PLUS (Pmode, dest, reg);
3534
    }
3535
  else
3536
    {
3537
      /* addi grB, #tlsmoff12(x), grC
3538
           -or-
3539
         ld/st @(grB, #tlsmoff12(x)), grC
3540
      */
3541
      dest = gen_reg_rtx (Pmode);
3542
      emit_insn (gen_symGOTOFF2reg_i (dest, addr, reg,
3543
                                      GEN_INT (R_FRV_TLSMOFF12)));
3544
    }
3545
  return dest;
3546
}
3547
 
3548
/* Generate code for a TLS address.  */
3549
static rtx
3550
frv_legitimize_tls_address (rtx addr, enum tls_model model)
3551
{
3552
  rtx dest, tp = gen_rtx_REG (Pmode, 29);
3553
  rtx picreg = get_hard_reg_initial_val (Pmode, 15);
3554
 
3555
  switch (model)
3556
    {
3557
    case TLS_MODEL_INITIAL_EXEC:
3558
      if (flag_pic == 1)
3559
        {
3560
          /* -fpic version.
3561
             ldi @(gr15, #gottlsoff12(x)), gr5
3562
           */
3563
          dest = gen_reg_rtx (Pmode);
3564
          emit_insn (gen_tls_load_gottlsoff12 (dest, addr, picreg));
3565
          dest = gen_rtx_PLUS (Pmode, tp, dest);
3566
        }
3567
      else
3568
        {
3569
          /* -fPIC or anything else.
3570
 
3571
            sethi.p #gottlsoffhi(x), gr14
3572
            setlo   #gottlsofflo(x), gr14
3573
            ld      #tlsoff(x)@(gr15, gr14), gr9
3574
          */
3575
          rtx tmp = gen_reg_rtx (Pmode);
3576
          dest = gen_reg_rtx (Pmode);
3577
          emit_insn (gen_tlsoff_hilo (tmp, addr,
3578
                                      GEN_INT (R_FRV_GOTTLSOFF_HI)));
3579
 
3580
          emit_insn (gen_tls_tlsoff_ld (dest, picreg, tmp, addr));
3581
          dest = gen_rtx_PLUS (Pmode, tp, dest);
3582
        }
3583
      break;
3584
    case TLS_MODEL_LOCAL_DYNAMIC:
3585
      {
3586
        rtx reg, retval;
3587
 
3588
        if (TARGET_INLINE_PLT)
3589
          retval = gen_inlined_tls_plt (GEN_INT (0));
3590
        else
3591
          {
3592
            /* call #gettlsoff(0) */
3593
            retval = gen_reg_rtx (Pmode);
3594
            emit_insn (gen_call_gettlsoff (retval, GEN_INT (0), picreg));
3595
          }
3596
 
3597
        reg = gen_reg_rtx (Pmode);
3598
        emit_insn (gen_rtx_SET (VOIDmode, reg,
3599
                                gen_rtx_PLUS (Pmode,
3600
                                              retval, tp)));
3601
 
3602
        dest = gen_tlsmoff (addr, reg);
3603
 
3604
        /*
3605
        dest = gen_reg_rtx (Pmode);
3606
        emit_insn (gen_tlsoff_hilo (dest, addr,
3607
                                    GEN_INT (R_FRV_TLSMOFFHI)));
3608
        dest = gen_rtx_PLUS (Pmode, dest, reg);
3609
        */
3610
        break;
3611
      }
3612
    case TLS_MODEL_LOCAL_EXEC:
3613
      dest = gen_tlsmoff (addr, gen_rtx_REG (Pmode, 29));
3614
      break;
3615
    case TLS_MODEL_GLOBAL_DYNAMIC:
3616
      {
3617
        rtx retval;
3618
 
3619
        if (TARGET_INLINE_PLT)
3620
          retval = gen_inlined_tls_plt (addr);
3621
        else
3622
          {
3623
            /* call #gettlsoff(x) */
3624
            retval = gen_reg_rtx (Pmode);
3625
            emit_insn (gen_call_gettlsoff (retval, addr, picreg));
3626
          }
3627
        dest = gen_rtx_PLUS (Pmode, retval, tp);
3628
        break;
3629
      }
3630
    default:
3631
      gcc_unreachable ();
3632
    }
3633
 
3634
  return dest;
3635
}
3636
 
3637
rtx
3638
frv_legitimize_address (rtx x,
3639
                        rtx oldx ATTRIBUTE_UNUSED,
3640
                        enum machine_mode mode ATTRIBUTE_UNUSED)
3641
{
3642
  if (GET_CODE (x) == SYMBOL_REF)
3643
    {
3644
      enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
3645
      if (model != 0)
3646
        return frv_legitimize_tls_address (x, model);
3647
    }
3648
 
3649
  return x;
3650
}
3651
 
3652
/* Test whether a local function descriptor is canonical, i.e.,
3653
   whether we can use FUNCDESC_GOTOFF to compute the address of the
3654
   function.  */
3655
 
3656
static bool
3657
frv_local_funcdesc_p (rtx fnx)
3658
{
3659
  tree fn;
3660
  enum symbol_visibility vis;
3661
  bool ret;
3662
 
3663
  if (! SYMBOL_REF_LOCAL_P (fnx))
3664
    return FALSE;
3665
 
3666
  fn = SYMBOL_REF_DECL (fnx);
3667
 
3668
  if (! fn)
3669
    return FALSE;
3670
 
3671
  vis = DECL_VISIBILITY (fn);
3672
 
3673
  if (vis == VISIBILITY_PROTECTED)
3674
    /* Private function descriptors for protected functions are not
3675
       canonical.  Temporarily change the visibility to global.  */
3676
    vis = VISIBILITY_DEFAULT;
3677
  else if (flag_shlib)
3678
    /* If we're already compiling for a shared library (that, unlike
3679
       executables, can't assume that the existence of a definition
3680
       implies local binding), we can skip the re-testing.  */
3681
    return TRUE;
3682
 
3683
  ret = default_binds_local_p_1 (fn, flag_pic);
3684
 
3685
  DECL_VISIBILITY (fn) = vis;
3686
 
3687
  return ret;
3688
}
3689
 
3690
/* Load the _gp symbol into DEST.  SRC is supposed to be the FDPIC
3691
   register.  */
3692
 
3693
rtx
3694
frv_gen_GPsym2reg (rtx dest, rtx src)
3695
{
3696
  tree gp = get_identifier ("_gp");
3697
  rtx gp_sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (gp));
3698
 
3699
  return gen_symGOT2reg (dest, gp_sym, src, GEN_INT (R_FRV_GOT12));
3700
}
3701
 
3702
static const char *
3703
unspec_got_name (int i)
3704
{
3705
  switch (i)
3706
    {
3707
    case R_FRV_GOT12: return "got12";
3708
    case R_FRV_GOTHI: return "gothi";
3709
    case R_FRV_GOTLO: return "gotlo";
3710
    case R_FRV_FUNCDESC: return "funcdesc";
3711
    case R_FRV_FUNCDESC_GOT12: return "gotfuncdesc12";
3712
    case R_FRV_FUNCDESC_GOTHI: return "gotfuncdeschi";
3713
    case R_FRV_FUNCDESC_GOTLO: return "gotfuncdesclo";
3714
    case R_FRV_FUNCDESC_VALUE: return "funcdescvalue";
3715
    case R_FRV_FUNCDESC_GOTOFF12: return "gotofffuncdesc12";
3716
    case R_FRV_FUNCDESC_GOTOFFHI: return "gotofffuncdeschi";
3717
    case R_FRV_FUNCDESC_GOTOFFLO: return "gotofffuncdesclo";
3718
    case R_FRV_GOTOFF12: return "gotoff12";
3719
    case R_FRV_GOTOFFHI: return "gotoffhi";
3720
    case R_FRV_GOTOFFLO: return "gotofflo";
3721
    case R_FRV_GPREL12: return "gprel12";
3722
    case R_FRV_GPRELHI: return "gprelhi";
3723
    case R_FRV_GPRELLO: return "gprello";
3724
    case R_FRV_GOTTLSOFF_HI: return "gottlsoffhi";
3725
    case R_FRV_GOTTLSOFF_LO: return "gottlsofflo";
3726
    case R_FRV_TLSMOFFHI: return "tlsmoffhi";
3727
    case R_FRV_TLSMOFFLO: return "tlsmofflo";
3728
    case R_FRV_TLSMOFF12: return "tlsmoff12";
3729
    case R_FRV_TLSDESCHI: return "tlsdeschi";
3730
    case R_FRV_TLSDESCLO: return "tlsdesclo";
3731
    case R_FRV_GOTTLSDESCHI: return "gottlsdeschi";
3732
    case R_FRV_GOTTLSDESCLO: return "gottlsdesclo";
3733
    default: gcc_unreachable ();
3734
    }
3735
}
3736
 
3737
/* Write the assembler syntax for UNSPEC to STREAM.  Note that any offset
3738
   is added inside the relocation operator.  */
3739
 
3740
static void
3741
frv_output_const_unspec (FILE *stream, const struct frv_unspec *unspec)
3742
{
3743
  fprintf (stream, "#%s(", unspec_got_name (unspec->reloc));
3744
  output_addr_const (stream, plus_constant (unspec->symbol, unspec->offset));
3745
  fputs (")", stream);
3746
}
3747
 
3748
/* Implement FIND_BASE_TERM.  See whether ORIG_X represents #gprel12(foo)
3749
   or #gotoff12(foo) for some small data symbol foo.  If so, return foo,
3750
   otherwise return ORIG_X.  */
3751
 
3752
rtx
3753
frv_find_base_term (rtx x)
3754
{
3755
  struct frv_unspec unspec;
3756
 
3757
  if (frv_const_unspec_p (x, &unspec)
3758
      && frv_small_data_reloc_p (unspec.symbol, unspec.reloc))
3759
    return plus_constant (unspec.symbol, unspec.offset);
3760
 
3761
  return x;
3762
}
3763
 
3764
/* Return 1 if operand is a valid FRV address.  CONDEXEC_P is true if
3765
   the operand is used by a predicated instruction.  */
3766
 
3767
int
3768
frv_legitimate_memory_operand (rtx op, enum machine_mode mode, int condexec_p)
3769
{
3770
  return ((GET_MODE (op) == mode || mode == VOIDmode)
3771
          && GET_CODE (op) == MEM
3772
          && frv_legitimate_address_p_1 (mode, XEXP (op, 0),
3773
                                         reload_completed, condexec_p, FALSE));
3774
}
3775
 
3776
void
3777
frv_expand_fdpic_call (rtx *operands, bool ret_value, bool sibcall)
3778
{
3779
  rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
3780
  rtx picreg = get_hard_reg_initial_val (SImode, FDPIC_REG);
3781
  rtx c, rvrtx=0;
3782
  rtx addr;
3783
 
3784
  if (ret_value)
3785
    {
3786
      rvrtx = operands[0];
3787
      operands ++;
3788
    }
3789
 
3790
  addr = XEXP (operands[0], 0);
3791
 
3792
  /* Inline PLTs if we're optimizing for speed.  We'd like to inline
3793
     any calls that would involve a PLT, but can't tell, since we
3794
     don't know whether an extern function is going to be provided by
3795
     a separate translation unit or imported from a separate module.
3796
     When compiling for shared libraries, if the function has default
3797
     visibility, we assume it's overridable, so we inline the PLT, but
3798
     for executables, we don't really have a way to make a good
3799
     decision: a function is as likely to be imported from a shared
3800
     library as it is to be defined in the executable itself.  We
3801
     assume executables will get global functions defined locally,
3802
     whereas shared libraries will have them potentially overridden,
3803
     so we only inline PLTs when compiling for shared libraries.
3804
 
3805
     In order to mark a function as local to a shared library, any
3806
     non-default visibility attribute suffices.  Unfortunately,
3807
     there's no simple way to tag a function declaration as ``in a
3808
     different module'', which we could then use to trigger PLT
3809
     inlining on executables.  There's -minline-plt, but it affects
3810
     all external functions, so one would have to also mark function
3811
     declarations available in the same module with non-default
3812
     visibility, which is advantageous in itself.  */
3813
  if (GET_CODE (addr) == SYMBOL_REF
3814
      && ((!SYMBOL_REF_LOCAL_P (addr) && TARGET_INLINE_PLT)
3815
          || sibcall))
3816
    {
3817
      rtx x, dest;
3818
      dest = gen_reg_rtx (SImode);
3819
      if (flag_pic != 1)
3820
        x = gen_symGOTOFF2reg_hilo (dest, addr, OUR_FDPIC_REG,
3821
                                    GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3822
      else
3823
        x = gen_symGOTOFF2reg (dest, addr, OUR_FDPIC_REG,
3824
                               GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3825
      emit_insn (x);
3826
      crtl->uses_pic_offset_table = TRUE;
3827
      addr = dest;
3828
    }
3829
  else if (GET_CODE (addr) == SYMBOL_REF)
3830
    {
3831
      /* These are always either local, or handled through a local
3832
         PLT.  */
3833
      if (ret_value)
3834
        c = gen_call_value_fdpicsi (rvrtx, addr, operands[1],
3835
                                    operands[2], picreg, lr);
3836
      else
3837
        c = gen_call_fdpicsi (addr, operands[1], operands[2], picreg, lr);
3838
      emit_call_insn (c);
3839
      return;
3840
    }
3841
  else if (! ldd_address_operand (addr, Pmode))
3842
    addr = force_reg (Pmode, addr);
3843
 
3844
  picreg = gen_reg_rtx (DImode);
3845
  emit_insn (gen_movdi_ldd (picreg, addr));
3846
 
3847
  if (sibcall && ret_value)
3848
    c = gen_sibcall_value_fdpicdi (rvrtx, picreg, const0_rtx);
3849
  else if (sibcall)
3850
    c = gen_sibcall_fdpicdi (picreg, const0_rtx);
3851
  else if (ret_value)
3852
    c = gen_call_value_fdpicdi (rvrtx, picreg, const0_rtx, lr);
3853
  else
3854
    c = gen_call_fdpicdi (picreg, const0_rtx, lr);
3855
  emit_call_insn (c);
3856
}
3857
 
3858
/* Look for a SYMBOL_REF of a function in an rtx.  We always want to
3859
   process these separately from any offsets, such that we add any
3860
   offsets to the function descriptor (the actual pointer), not to the
3861
   function address.  */
3862
 
3863
static bool
3864
frv_function_symbol_referenced_p (rtx x)
3865
{
3866
  const char *format;
3867
  int length;
3868
  int j;
3869
 
3870
  if (GET_CODE (x) == SYMBOL_REF)
3871
    return SYMBOL_REF_FUNCTION_P (x);
3872
 
3873
  length = GET_RTX_LENGTH (GET_CODE (x));
3874
  format = GET_RTX_FORMAT (GET_CODE (x));
3875
 
3876
  for (j = 0; j < length; ++j)
3877
    {
3878
      switch (format[j])
3879
        {
3880
        case 'e':
3881
          if (frv_function_symbol_referenced_p (XEXP (x, j)))
3882
            return TRUE;
3883
          break;
3884
 
3885
        case 'V':
3886
        case 'E':
3887
          if (XVEC (x, j) != 0)
3888
            {
3889
              int k;
3890
              for (k = 0; k < XVECLEN (x, j); ++k)
3891
                if (frv_function_symbol_referenced_p (XVECEXP (x, j, k)))
3892
                  return TRUE;
3893
            }
3894
          break;
3895
 
3896
        default:
3897
          /* Nothing to do.  */
3898
          break;
3899
        }
3900
    }
3901
 
3902
  return FALSE;
3903
}
3904
 
3905
/* Return true if the memory operand is one that can be conditionally
3906
   executed.  */
3907
 
3908
int
3909
condexec_memory_operand (rtx op, enum machine_mode mode)
3910
{
3911
  enum machine_mode op_mode = GET_MODE (op);
3912
  rtx addr;
3913
 
3914
  if (mode != VOIDmode && op_mode != mode)
3915
    return FALSE;
3916
 
3917
  switch (op_mode)
3918
    {
3919
    default:
3920
      return FALSE;
3921
 
3922
    case QImode:
3923
    case HImode:
3924
    case SImode:
3925
    case SFmode:
3926
      break;
3927
    }
3928
 
3929
  if (GET_CODE (op) != MEM)
3930
    return FALSE;
3931
 
3932
  addr = XEXP (op, 0);
3933
  return frv_legitimate_address_p_1 (mode, addr, reload_completed, TRUE, FALSE);
3934
}
3935
 
3936
/* Return true if the bare return instruction can be used outside of the
3937
   epilog code.  For frv, we only do it if there was no stack allocation.  */
3938
 
3939
int
3940
direct_return_p (void)
3941
{
3942
  frv_stack_t *info;
3943
 
3944
  if (!reload_completed)
3945
    return FALSE;
3946
 
3947
  info = frv_stack_info ();
3948
  return (info->total_size == 0);
3949
}
3950
 
3951
 
3952
void
3953
frv_emit_move (enum machine_mode mode, rtx dest, rtx src)
3954
{
3955
  if (GET_CODE (src) == SYMBOL_REF)
3956
    {
3957
      enum tls_model model = SYMBOL_REF_TLS_MODEL (src);
3958
      if (model != 0)
3959
        src = frv_legitimize_tls_address (src, model);
3960
    }
3961
 
3962
  switch (mode)
3963
    {
3964
    case SImode:
3965
      if (frv_emit_movsi (dest, src))
3966
        return;
3967
      break;
3968
 
3969
    case QImode:
3970
    case HImode:
3971
    case DImode:
3972
    case SFmode:
3973
    case DFmode:
3974
      if (!reload_in_progress
3975
          && !reload_completed
3976
          && !register_operand (dest, mode)
3977
          && !reg_or_0_operand (src, mode))
3978
        src = copy_to_mode_reg (mode, src);
3979
      break;
3980
 
3981
    default:
3982
      gcc_unreachable ();
3983
    }
3984
 
3985
  emit_insn (gen_rtx_SET (VOIDmode, dest, src));
3986
}
3987
 
3988
/* Emit code to handle a MOVSI, adding in the small data register or pic
3989
   register if needed to load up addresses.  Return TRUE if the appropriate
3990
   instructions are emitted.  */
3991
 
3992
int
3993
frv_emit_movsi (rtx dest, rtx src)
3994
{
3995
  int base_regno = -1;
3996
  int unspec = 0;
3997
  rtx sym = src;
3998
  struct frv_unspec old_unspec;
3999
 
4000
  if (!reload_in_progress
4001
      && !reload_completed
4002
      && !register_operand (dest, SImode)
4003
      && (!reg_or_0_operand (src, SImode)
4004
             /* Virtual registers will almost always be replaced by an
4005
                add instruction, so expose this to CSE by copying to
4006
                an intermediate register.  */
4007
          || (GET_CODE (src) == REG
4008
              && IN_RANGE (REGNO (src),
4009
                           FIRST_VIRTUAL_REGISTER,
4010
                           LAST_VIRTUAL_POINTER_REGISTER))))
4011
    {
4012
      emit_insn (gen_rtx_SET (VOIDmode, dest, copy_to_mode_reg (SImode, src)));
4013
      return TRUE;
4014
    }
4015
 
4016
  /* Explicitly add in the PIC or small data register if needed.  */
4017
  switch (GET_CODE (src))
4018
    {
4019
    default:
4020
      break;
4021
 
4022
    case LABEL_REF:
4023
    handle_label:
4024
      if (TARGET_FDPIC)
4025
        {
4026
          /* Using GPREL12, we use a single GOT entry for all symbols
4027
             in read-only sections, but trade sequences such as:
4028
 
4029
             sethi #gothi(label), gr#
4030
             setlo #gotlo(label), gr#
4031
             ld    @(gr15,gr#), gr#
4032
 
4033
             for
4034
 
4035
             ld    @(gr15,#got12(_gp)), gr#
4036
             sethi #gprelhi(label), gr##
4037
             setlo #gprello(label), gr##
4038
             add   gr#, gr##, gr##
4039
 
4040
             We may often be able to share gr# for multiple
4041
             computations of GPREL addresses, and we may often fold
4042
             the final add into the pair of registers of a load or
4043
             store instruction, so it's often profitable.  Even when
4044
             optimizing for size, we're trading a GOT entry for an
4045
             additional instruction, which trades GOT space
4046
             (read-write) for code size (read-only, shareable), as
4047
             long as the symbol is not used in more than two different
4048
             locations.
4049
 
4050
             With -fpie/-fpic, we'd be trading a single load for a
4051
             sequence of 4 instructions, because the offset of the
4052
             label can't be assumed to be addressable with 12 bits, so
4053
             we don't do this.  */
4054
          if (TARGET_GPREL_RO)
4055
            unspec = R_FRV_GPREL12;
4056
          else
4057
            unspec = R_FRV_GOT12;
4058
        }
4059
      else if (flag_pic)
4060
        base_regno = PIC_REGNO;
4061
 
4062
      break;
4063
 
4064
    case CONST:
4065
      if (frv_const_unspec_p (src, &old_unspec))
4066
        break;
4067
 
4068
      if (TARGET_FDPIC && frv_function_symbol_referenced_p (XEXP (src, 0)))
4069
        {
4070
        handle_whatever:
4071
          src = force_reg (GET_MODE (XEXP (src, 0)), XEXP (src, 0));
4072
          emit_move_insn (dest, src);
4073
          return TRUE;
4074
        }
4075
      else
4076
        {
4077
          sym = XEXP (sym, 0);
4078
          if (GET_CODE (sym) == PLUS
4079
              && GET_CODE (XEXP (sym, 0)) == SYMBOL_REF
4080
              && GET_CODE (XEXP (sym, 1)) == CONST_INT)
4081
            sym = XEXP (sym, 0);
4082
          if (GET_CODE (sym) == SYMBOL_REF)
4083
            goto handle_sym;
4084
          else if (GET_CODE (sym) == LABEL_REF)
4085
            goto handle_label;
4086
          else
4087
            goto handle_whatever;
4088
        }
4089
      break;
4090
 
4091
    case SYMBOL_REF:
4092
    handle_sym:
4093
      if (TARGET_FDPIC)
4094
        {
4095
          enum tls_model model = SYMBOL_REF_TLS_MODEL (sym);
4096
 
4097
          if (model != 0)
4098
            {
4099
              src = frv_legitimize_tls_address (src, model);
4100
              emit_move_insn (dest, src);
4101
              return TRUE;
4102
            }
4103
 
4104
          if (SYMBOL_REF_FUNCTION_P (sym))
4105
            {
4106
              if (frv_local_funcdesc_p (sym))
4107
                unspec = R_FRV_FUNCDESC_GOTOFF12;
4108
              else
4109
                unspec = R_FRV_FUNCDESC_GOT12;
4110
            }
4111
          else
4112
            {
4113
              if (CONSTANT_POOL_ADDRESS_P (sym))
4114
                switch (GET_CODE (get_pool_constant (sym)))
4115
                  {
4116
                  case CONST:
4117
                  case SYMBOL_REF:
4118
                  case LABEL_REF:
4119
                    if (flag_pic)
4120
                      {
4121
                        unspec = R_FRV_GOTOFF12;
4122
                        break;
4123
                      }
4124
                    /* Fall through.  */
4125
                  default:
4126
                    if (TARGET_GPREL_RO)
4127
                      unspec = R_FRV_GPREL12;
4128
                    else
4129
                      unspec = R_FRV_GOT12;
4130
                    break;
4131
                  }
4132
              else if (SYMBOL_REF_LOCAL_P (sym)
4133
                       && !SYMBOL_REF_EXTERNAL_P (sym)
4134
                       && SYMBOL_REF_DECL (sym)
4135
                       && (!DECL_P (SYMBOL_REF_DECL (sym))
4136
                           || !DECL_COMMON (SYMBOL_REF_DECL (sym))))
4137
                {
4138
                  tree decl = SYMBOL_REF_DECL (sym);
4139
                  tree init = TREE_CODE (decl) == VAR_DECL
4140
                    ? DECL_INITIAL (decl)
4141
                    : TREE_CODE (decl) == CONSTRUCTOR
4142
                    ? decl : 0;
4143
                  int reloc = 0;
4144
                  bool named_section, readonly;
4145
 
4146
                  if (init && init != error_mark_node)
4147
                    reloc = compute_reloc_for_constant (init);
4148
 
4149
                  named_section = TREE_CODE (decl) == VAR_DECL
4150
                    && lookup_attribute ("section", DECL_ATTRIBUTES (decl));
4151
                  readonly = decl_readonly_section (decl, reloc);
4152
 
4153
                  if (named_section)
4154
                    unspec = R_FRV_GOT12;
4155
                  else if (!readonly)
4156
                    unspec = R_FRV_GOTOFF12;
4157
                  else if (readonly && TARGET_GPREL_RO)
4158
                    unspec = R_FRV_GPREL12;
4159
                  else
4160
                    unspec = R_FRV_GOT12;
4161
                }
4162
              else
4163
                unspec = R_FRV_GOT12;
4164
            }
4165
        }
4166
 
4167
      else if (SYMBOL_REF_SMALL_P (sym))
4168
        base_regno = SDA_BASE_REG;
4169
 
4170
      else if (flag_pic)
4171
        base_regno = PIC_REGNO;
4172
 
4173
      break;
4174
    }
4175
 
4176
  if (base_regno >= 0)
4177
    {
4178
      if (GET_CODE (sym) == SYMBOL_REF && SYMBOL_REF_SMALL_P (sym))
4179
        emit_insn (gen_symGOTOFF2reg (dest, src,
4180
                                      gen_rtx_REG (Pmode, base_regno),
4181
                                      GEN_INT (R_FRV_GPREL12)));
4182
      else
4183
        emit_insn (gen_symGOTOFF2reg_hilo (dest, src,
4184
                                           gen_rtx_REG (Pmode, base_regno),
4185
                                           GEN_INT (R_FRV_GPREL12)));
4186
      if (base_regno == PIC_REGNO)
4187
        crtl->uses_pic_offset_table = TRUE;
4188
      return TRUE;
4189
    }
4190
 
4191
  if (unspec)
4192
    {
4193
      rtx x;
4194
 
4195
      /* Since OUR_FDPIC_REG is a pseudo register, we can't safely introduce
4196
         new uses of it once reload has begun.  */
4197
      gcc_assert (!reload_in_progress && !reload_completed);
4198
 
4199
      switch (unspec)
4200
        {
4201
        case R_FRV_GOTOFF12:
4202
          if (!frv_small_data_reloc_p (sym, unspec))
4203
            x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
4204
                                        GEN_INT (unspec));
4205
          else
4206
            x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4207
          break;
4208
        case R_FRV_GPREL12:
4209
          if (!frv_small_data_reloc_p (sym, unspec))
4210
            x = gen_symGPREL2reg_hilo (dest, src, OUR_FDPIC_REG,
4211
                                       GEN_INT (unspec));
4212
          else
4213
            x = gen_symGPREL2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4214
          break;
4215
        case R_FRV_FUNCDESC_GOTOFF12:
4216
          if (flag_pic != 1)
4217
            x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
4218
                                        GEN_INT (unspec));
4219
          else
4220
            x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4221
          break;
4222
        default:
4223
          if (flag_pic != 1)
4224
            x = gen_symGOT2reg_hilo (dest, src, OUR_FDPIC_REG,
4225
                                     GEN_INT (unspec));
4226
          else
4227
            x = gen_symGOT2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4228
          break;
4229
        }
4230
      emit_insn (x);
4231
      crtl->uses_pic_offset_table = TRUE;
4232
      return TRUE;
4233
    }
4234
 
4235
 
4236
  return FALSE;
4237
}
4238
 
4239
 
4240
/* Return a string to output a single word move.  */
4241
 
4242
const char *
4243
output_move_single (rtx operands[], rtx insn)
4244
{
4245
  rtx dest = operands[0];
4246
  rtx src  = operands[1];
4247
 
4248
  if (GET_CODE (dest) == REG)
4249
    {
4250
      int dest_regno = REGNO (dest);
4251
      enum machine_mode mode = GET_MODE (dest);
4252
 
4253
      if (GPR_P (dest_regno))
4254
        {
4255
          if (GET_CODE (src) == REG)
4256
            {
4257
              /* gpr <- some sort of register */
4258
              int src_regno = REGNO (src);
4259
 
4260
              if (GPR_P (src_regno))
4261
                return "mov %1, %0";
4262
 
4263
              else if (FPR_P (src_regno))
4264
                return "movfg %1, %0";
4265
 
4266
              else if (SPR_P (src_regno))
4267
                return "movsg %1, %0";
4268
            }
4269
 
4270
          else if (GET_CODE (src) == MEM)
4271
            {
4272
              /* gpr <- memory */
4273
              switch (mode)
4274
                {
4275
                default:
4276
                  break;
4277
 
4278
                case QImode:
4279
                  return "ldsb%I1%U1 %M1,%0";
4280
 
4281
                case HImode:
4282
                  return "ldsh%I1%U1 %M1,%0";
4283
 
4284
                case SImode:
4285
                case SFmode:
4286
                  return "ld%I1%U1 %M1, %0";
4287
                }
4288
            }
4289
 
4290
          else if (GET_CODE (src) == CONST_INT
4291
                   || GET_CODE (src) == CONST_DOUBLE)
4292
            {
4293
              /* gpr <- integer/floating constant */
4294
              HOST_WIDE_INT value;
4295
 
4296
              if (GET_CODE (src) == CONST_INT)
4297
                value = INTVAL (src);
4298
 
4299
              else if (mode == SFmode)
4300
                {
4301
                  REAL_VALUE_TYPE rv;
4302
                  long l;
4303
 
4304
                  REAL_VALUE_FROM_CONST_DOUBLE (rv, src);
4305
                  REAL_VALUE_TO_TARGET_SINGLE (rv, l);
4306
                  value = l;
4307
                }
4308
 
4309
              else
4310
                value = CONST_DOUBLE_LOW (src);
4311
 
4312
              if (IN_RANGE (value, -32768, 32767))
4313
                return "setlos %1, %0";
4314
 
4315
              return "#";
4316
            }
4317
 
4318
          else if (GET_CODE (src) == SYMBOL_REF
4319
                   || GET_CODE (src) == LABEL_REF
4320
                   || GET_CODE (src) == CONST)
4321
            {
4322
              return "#";
4323
            }
4324
        }
4325
 
4326
      else if (FPR_P (dest_regno))
4327
        {
4328
          if (GET_CODE (src) == REG)
4329
            {
4330
              /* fpr <- some sort of register */
4331
              int src_regno = REGNO (src);
4332
 
4333
              if (GPR_P (src_regno))
4334
                return "movgf %1, %0";
4335
 
4336
              else if (FPR_P (src_regno))
4337
                {
4338
                  if (TARGET_HARD_FLOAT)
4339
                    return "fmovs %1, %0";
4340
                  else
4341
                    return "mor %1, %1, %0";
4342
                }
4343
            }
4344
 
4345
          else if (GET_CODE (src) == MEM)
4346
            {
4347
              /* fpr <- memory */
4348
              switch (mode)
4349
                {
4350
                default:
4351
                  break;
4352
 
4353
                case QImode:
4354
                  return "ldbf%I1%U1 %M1,%0";
4355
 
4356
                case HImode:
4357
                  return "ldhf%I1%U1 %M1,%0";
4358
 
4359
                case SImode:
4360
                case SFmode:
4361
                  return "ldf%I1%U1 %M1, %0";
4362
                }
4363
            }
4364
 
4365
          else if (ZERO_P (src))
4366
            return "movgf %., %0";
4367
        }
4368
 
4369
      else if (SPR_P (dest_regno))
4370
        {
4371
          if (GET_CODE (src) == REG)
4372
            {
4373
              /* spr <- some sort of register */
4374
              int src_regno = REGNO (src);
4375
 
4376
              if (GPR_P (src_regno))
4377
                return "movgs %1, %0";
4378
            }
4379
          else if (ZERO_P (src))
4380
            return "movgs %., %0";
4381
        }
4382
    }
4383
 
4384
  else if (GET_CODE (dest) == MEM)
4385
    {
4386
      if (GET_CODE (src) == REG)
4387
        {
4388
          int src_regno = REGNO (src);
4389
          enum machine_mode mode = GET_MODE (dest);
4390
 
4391
          if (GPR_P (src_regno))
4392
            {
4393
              switch (mode)
4394
                {
4395
                default:
4396
                  break;
4397
 
4398
                case QImode:
4399
                  return "stb%I0%U0 %1, %M0";
4400
 
4401
                case HImode:
4402
                  return "sth%I0%U0 %1, %M0";
4403
 
4404
                case SImode:
4405
                case SFmode:
4406
                  return "st%I0%U0 %1, %M0";
4407
                }
4408
            }
4409
 
4410
          else if (FPR_P (src_regno))
4411
            {
4412
              switch (mode)
4413
                {
4414
                default:
4415
                  break;
4416
 
4417
                case QImode:
4418
                  return "stbf%I0%U0 %1, %M0";
4419
 
4420
                case HImode:
4421
                  return "sthf%I0%U0 %1, %M0";
4422
 
4423
                case SImode:
4424
                case SFmode:
4425
                  return "stf%I0%U0 %1, %M0";
4426
                }
4427
            }
4428
        }
4429
 
4430
      else if (ZERO_P (src))
4431
        {
4432
          switch (GET_MODE (dest))
4433
            {
4434
            default:
4435
              break;
4436
 
4437
            case QImode:
4438
              return "stb%I0%U0 %., %M0";
4439
 
4440
            case HImode:
4441
              return "sth%I0%U0 %., %M0";
4442
 
4443
            case SImode:
4444
            case SFmode:
4445
              return "st%I0%U0 %., %M0";
4446
            }
4447
        }
4448
    }
4449
 
4450
  fatal_insn ("bad output_move_single operand", insn);
4451
  return "";
4452
}
4453
 
4454
 
4455
/* Return a string to output a double word move.  */
4456
 
4457
const char *
4458
output_move_double (rtx operands[], rtx insn)
4459
{
4460
  rtx dest = operands[0];
4461
  rtx src  = operands[1];
4462
  enum machine_mode mode = GET_MODE (dest);
4463
 
4464
  if (GET_CODE (dest) == REG)
4465
    {
4466
      int dest_regno = REGNO (dest);
4467
 
4468
      if (GPR_P (dest_regno))
4469
        {
4470
          if (GET_CODE (src) == REG)
4471
            {
4472
              /* gpr <- some sort of register */
4473
              int src_regno = REGNO (src);
4474
 
4475
              if (GPR_P (src_regno))
4476
                return "#";
4477
 
4478
              else if (FPR_P (src_regno))
4479
                {
4480
                  if (((dest_regno - GPR_FIRST) & 1) == 0
4481
                      && ((src_regno - FPR_FIRST) & 1) == 0)
4482
                    return "movfgd %1, %0";
4483
 
4484
                  return "#";
4485
                }
4486
            }
4487
 
4488
          else if (GET_CODE (src) == MEM)
4489
            {
4490
              /* gpr <- memory */
4491
              if (dbl_memory_one_insn_operand (src, mode))
4492
                return "ldd%I1%U1 %M1, %0";
4493
 
4494
              return "#";
4495
            }
4496
 
4497
          else if (GET_CODE (src) == CONST_INT
4498
                   || GET_CODE (src) == CONST_DOUBLE)
4499
            return "#";
4500
        }
4501
 
4502
      else if (FPR_P (dest_regno))
4503
        {
4504
          if (GET_CODE (src) == REG)
4505
            {
4506
              /* fpr <- some sort of register */
4507
              int src_regno = REGNO (src);
4508
 
4509
              if (GPR_P (src_regno))
4510
                {
4511
                  if (((dest_regno - FPR_FIRST) & 1) == 0
4512
                      && ((src_regno - GPR_FIRST) & 1) == 0)
4513
                    return "movgfd %1, %0";
4514
 
4515
                  return "#";
4516
                }
4517
 
4518
              else if (FPR_P (src_regno))
4519
                {
4520
                  if (TARGET_DOUBLE
4521
                      && ((dest_regno - FPR_FIRST) & 1) == 0
4522
                      && ((src_regno - FPR_FIRST) & 1) == 0)
4523
                    return "fmovd %1, %0";
4524
 
4525
                  return "#";
4526
                }
4527
            }
4528
 
4529
          else if (GET_CODE (src) == MEM)
4530
            {
4531
              /* fpr <- memory */
4532
              if (dbl_memory_one_insn_operand (src, mode))
4533
                return "lddf%I1%U1 %M1, %0";
4534
 
4535
              return "#";
4536
            }
4537
 
4538
          else if (ZERO_P (src))
4539
            return "#";
4540
        }
4541
    }
4542
 
4543
  else if (GET_CODE (dest) == MEM)
4544
    {
4545
      if (GET_CODE (src) == REG)
4546
        {
4547
          int src_regno = REGNO (src);
4548
 
4549
          if (GPR_P (src_regno))
4550
            {
4551
              if (((src_regno - GPR_FIRST) & 1) == 0
4552
                  && dbl_memory_one_insn_operand (dest, mode))
4553
                return "std%I0%U0 %1, %M0";
4554
 
4555
              return "#";
4556
            }
4557
 
4558
          if (FPR_P (src_regno))
4559
            {
4560
              if (((src_regno - FPR_FIRST) & 1) == 0
4561
                  && dbl_memory_one_insn_operand (dest, mode))
4562
                return "stdf%I0%U0 %1, %M0";
4563
 
4564
              return "#";
4565
            }
4566
        }
4567
 
4568
      else if (ZERO_P (src))
4569
        {
4570
          if (dbl_memory_one_insn_operand (dest, mode))
4571
            return "std%I0%U0 %., %M0";
4572
 
4573
          return "#";
4574
        }
4575
    }
4576
 
4577
  fatal_insn ("bad output_move_double operand", insn);
4578
  return "";
4579
}
4580
 
4581
 
4582
/* Return a string to output a single word conditional move.
4583
   Operand0 -- EQ/NE of ccr register and 0
4584
   Operand1 -- CCR register
4585
   Operand2 -- destination
4586
   Operand3 -- source  */
4587
 
4588
const char *
4589
output_condmove_single (rtx operands[], rtx insn)
4590
{
4591
  rtx dest = operands[2];
4592
  rtx src  = operands[3];
4593
 
4594
  if (GET_CODE (dest) == REG)
4595
    {
4596
      int dest_regno = REGNO (dest);
4597
      enum machine_mode mode = GET_MODE (dest);
4598
 
4599
      if (GPR_P (dest_regno))
4600
        {
4601
          if (GET_CODE (src) == REG)
4602
            {
4603
              /* gpr <- some sort of register */
4604
              int src_regno = REGNO (src);
4605
 
4606
              if (GPR_P (src_regno))
4607
                return "cmov %z3, %2, %1, %e0";
4608
 
4609
              else if (FPR_P (src_regno))
4610
                return "cmovfg %3, %2, %1, %e0";
4611
            }
4612
 
4613
          else if (GET_CODE (src) == MEM)
4614
            {
4615
              /* gpr <- memory */
4616
              switch (mode)
4617
                {
4618
                default:
4619
                  break;
4620
 
4621
                case QImode:
4622
                  return "cldsb%I3%U3 %M3, %2, %1, %e0";
4623
 
4624
                case HImode:
4625
                  return "cldsh%I3%U3 %M3, %2, %1, %e0";
4626
 
4627
                case SImode:
4628
                case SFmode:
4629
                  return "cld%I3%U3 %M3, %2, %1, %e0";
4630
                }
4631
            }
4632
 
4633
          else if (ZERO_P (src))
4634
            return "cmov %., %2, %1, %e0";
4635
        }
4636
 
4637
      else if (FPR_P (dest_regno))
4638
        {
4639
          if (GET_CODE (src) == REG)
4640
            {
4641
              /* fpr <- some sort of register */
4642
              int src_regno = REGNO (src);
4643
 
4644
              if (GPR_P (src_regno))
4645
                return "cmovgf %3, %2, %1, %e0";
4646
 
4647
              else if (FPR_P (src_regno))
4648
                {
4649
                  if (TARGET_HARD_FLOAT)
4650
                    return "cfmovs %3,%2,%1,%e0";
4651
                  else
4652
                    return "cmor %3, %3, %2, %1, %e0";
4653
                }
4654
            }
4655
 
4656
          else if (GET_CODE (src) == MEM)
4657
            {
4658
              /* fpr <- memory */
4659
              if (mode == SImode || mode == SFmode)
4660
                return "cldf%I3%U3 %M3, %2, %1, %e0";
4661
            }
4662
 
4663
          else if (ZERO_P (src))
4664
            return "cmovgf %., %2, %1, %e0";
4665
        }
4666
    }
4667
 
4668
  else if (GET_CODE (dest) == MEM)
4669
    {
4670
      if (GET_CODE (src) == REG)
4671
        {
4672
          int src_regno = REGNO (src);
4673
          enum machine_mode mode = GET_MODE (dest);
4674
 
4675
          if (GPR_P (src_regno))
4676
            {
4677
              switch (mode)
4678
                {
4679
                default:
4680
                  break;
4681
 
4682
                case QImode:
4683
                  return "cstb%I2%U2 %3, %M2, %1, %e0";
4684
 
4685
                case HImode:
4686
                  return "csth%I2%U2 %3, %M2, %1, %e0";
4687
 
4688
                case SImode:
4689
                case SFmode:
4690
                  return "cst%I2%U2 %3, %M2, %1, %e0";
4691
                }
4692
            }
4693
 
4694
          else if (FPR_P (src_regno) && (mode == SImode || mode == SFmode))
4695
            return "cstf%I2%U2 %3, %M2, %1, %e0";
4696
        }
4697
 
4698
      else if (ZERO_P (src))
4699
        {
4700
          enum machine_mode mode = GET_MODE (dest);
4701
          switch (mode)
4702
            {
4703
            default:
4704
              break;
4705
 
4706
            case QImode:
4707
              return "cstb%I2%U2 %., %M2, %1, %e0";
4708
 
4709
            case HImode:
4710
              return "csth%I2%U2 %., %M2, %1, %e0";
4711
 
4712
            case SImode:
4713
            case SFmode:
4714
              return "cst%I2%U2 %., %M2, %1, %e0";
4715
            }
4716
        }
4717
    }
4718
 
4719
  fatal_insn ("bad output_condmove_single operand", insn);
4720
  return "";
4721
}
4722
 
4723
 
4724
/* Emit the appropriate code to do a comparison, returning the register the
4725
   comparison was done it.  */
4726
 
4727
static rtx
4728
frv_emit_comparison (enum rtx_code test, rtx op0, rtx op1)
4729
{
4730
  enum machine_mode cc_mode;
4731
  rtx cc_reg;
4732
 
4733
  /* Floating point doesn't have comparison against a constant.  */
4734
  if (GET_MODE (op0) == CC_FPmode && GET_CODE (op1) != REG)
4735
    op1 = force_reg (GET_MODE (op0), op1);
4736
 
4737
  /* Possibly disable using anything but a fixed register in order to work
4738
     around cse moving comparisons past function calls.  */
4739
  cc_mode = SELECT_CC_MODE (test, op0, op1);
4740
  cc_reg = ((TARGET_ALLOC_CC)
4741
            ? gen_reg_rtx (cc_mode)
4742
            : gen_rtx_REG (cc_mode,
4743
                           (cc_mode == CC_FPmode) ? FCC_FIRST : ICC_FIRST));
4744
 
4745
  emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
4746
                          gen_rtx_COMPARE (cc_mode, op0, op1)));
4747
 
4748
  return cc_reg;
4749
}
4750
 
4751
 
4752
/* Emit code for a conditional branch.
4753
   XXX: I originally wanted to add a clobber of a CCR register to use in
4754
   conditional execution, but that confuses the rest of the compiler.  */
4755
 
4756
int
4757
frv_emit_cond_branch (rtx operands[])
4758
{
4759
  rtx test_rtx;
4760
  rtx label_ref;
4761
  rtx if_else;
4762
  enum rtx_code test = GET_CODE (operands[0]);
4763
  rtx cc_reg = frv_emit_comparison (test, operands[1], operands[2]);
4764
  enum machine_mode cc_mode = GET_MODE (cc_reg);
4765
 
4766
  /* Branches generate:
4767
        (set (pc)
4768
             (if_then_else (<test>, <cc_reg>, (const_int 0))
4769
                            (label_ref <branch_label>)
4770
                            (pc))) */
4771
  label_ref = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
4772
  test_rtx = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
4773
  if_else = gen_rtx_IF_THEN_ELSE (cc_mode, test_rtx, label_ref, pc_rtx);
4774
  emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, if_else));
4775
  return TRUE;
4776
}
4777
 
4778
 
4779
/* Emit code to set a gpr to 1/0 based on a comparison.  */
4780
 
4781
int
4782
frv_emit_scc (rtx operands[])
4783
{
4784
  rtx set;
4785
  rtx test_rtx;
4786
  rtx clobber;
4787
  rtx cr_reg;
4788
  enum rtx_code test = GET_CODE (operands[1]);
4789
  rtx cc_reg = frv_emit_comparison (test, operands[2], operands[3]);
4790
 
4791
  /* SCC instructions generate:
4792
        (parallel [(set <target> (<test>, <cc_reg>, (const_int 0))
4793
                   (clobber (<ccr_reg>))])  */
4794
  test_rtx = gen_rtx_fmt_ee (test, SImode, cc_reg, const0_rtx);
4795
  set = gen_rtx_SET (VOIDmode, operands[0], test_rtx);
4796
 
4797
  cr_reg = ((TARGET_ALLOC_CC)
4798
            ? gen_reg_rtx (CC_CCRmode)
4799
            : gen_rtx_REG (CC_CCRmode,
4800
                           ((GET_MODE (cc_reg) == CC_FPmode)
4801
                            ? FCR_FIRST
4802
                            : ICR_FIRST)));
4803
 
4804
  clobber = gen_rtx_CLOBBER (VOIDmode, cr_reg);
4805
  emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
4806
  return TRUE;
4807
}
4808
 
4809
 
4810
/* Split a SCC instruction into component parts, returning a SEQUENCE to hold
4811
   the separate insns.  */
4812
 
4813
rtx
4814
frv_split_scc (rtx dest, rtx test, rtx cc_reg, rtx cr_reg, HOST_WIDE_INT value)
4815
{
4816
  rtx ret;
4817
 
4818
  start_sequence ();
4819
 
4820
  /* Set the appropriate CCR bit.  */
4821
  emit_insn (gen_rtx_SET (VOIDmode,
4822
                          cr_reg,
4823
                          gen_rtx_fmt_ee (GET_CODE (test),
4824
                                          GET_MODE (cr_reg),
4825
                                          cc_reg,
4826
                                          const0_rtx)));
4827
 
4828
  /* Move the value into the destination.  */
4829
  emit_move_insn (dest, GEN_INT (value));
4830
 
4831
  /* Move 0 into the destination if the test failed */
4832
  emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4833
                                gen_rtx_EQ (GET_MODE (cr_reg),
4834
                                            cr_reg,
4835
                                            const0_rtx),
4836
                                gen_rtx_SET (VOIDmode, dest, const0_rtx)));
4837
 
4838
  /* Finish up, return sequence.  */
4839
  ret = get_insns ();
4840
  end_sequence ();
4841
  return ret;
4842
}
4843
 
4844
 
4845
/* Emit the code for a conditional move, return TRUE if we could do the
4846
   move.  */
4847
 
4848
int
4849
frv_emit_cond_move (rtx dest, rtx test_rtx, rtx src1, rtx src2)
4850
{
4851
  rtx set;
4852
  rtx clobber_cc;
4853
  rtx test2;
4854
  rtx cr_reg;
4855
  rtx if_rtx;
4856
  enum rtx_code test = GET_CODE (test_rtx);
4857
  rtx cc_reg = frv_emit_comparison (test,
4858
                                    XEXP (test_rtx, 0), XEXP (test_rtx, 1));
4859
  enum machine_mode cc_mode = GET_MODE (cc_reg);
4860
 
4861
  /* Conditional move instructions generate:
4862
        (parallel [(set <target>
4863
                        (if_then_else (<test> <cc_reg> (const_int 0))
4864
                                      <src1>
4865
                                      <src2>))
4866
                   (clobber (<ccr_reg>))])  */
4867
 
4868
  /* Handle various cases of conditional move involving two constants.  */
4869
  if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
4870
    {
4871
      HOST_WIDE_INT value1 = INTVAL (src1);
4872
      HOST_WIDE_INT value2 = INTVAL (src2);
4873
 
4874
      /* Having 0 as one of the constants can be done by loading the other
4875
         constant, and optionally moving in gr0.  */
4876
      if (value1 == 0 || value2 == 0)
4877
        ;
4878
 
4879
      /* If the first value is within an addi range and also the difference
4880
         between the two fits in an addi's range, load up the difference, then
4881
         conditionally move in 0, and then unconditionally add the first
4882
         value.  */
4883
      else if (IN_RANGE (value1, -2048, 2047)
4884
               && IN_RANGE (value2 - value1, -2048, 2047))
4885
        ;
4886
 
4887
      /* If neither condition holds, just force the constant into a
4888
         register.  */
4889
      else
4890
        {
4891
          src1 = force_reg (GET_MODE (dest), src1);
4892
          src2 = force_reg (GET_MODE (dest), src2);
4893
        }
4894
    }
4895
 
4896
  /* If one value is a register, insure the other value is either 0 or a
4897
     register.  */
4898
  else
4899
    {
4900
      if (GET_CODE (src1) == CONST_INT && INTVAL (src1) != 0)
4901
        src1 = force_reg (GET_MODE (dest), src1);
4902
 
4903
      if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
4904
        src2 = force_reg (GET_MODE (dest), src2);
4905
    }
4906
 
4907
  test2 = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
4908
  if_rtx = gen_rtx_IF_THEN_ELSE (GET_MODE (dest), test2, src1, src2);
4909
 
4910
  set = gen_rtx_SET (VOIDmode, dest, if_rtx);
4911
 
4912
  cr_reg = ((TARGET_ALLOC_CC)
4913
            ? gen_reg_rtx (CC_CCRmode)
4914
            : gen_rtx_REG (CC_CCRmode,
4915
                           (cc_mode == CC_FPmode) ? FCR_FIRST : ICR_FIRST));
4916
 
4917
  clobber_cc = gen_rtx_CLOBBER (VOIDmode, cr_reg);
4918
  emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber_cc)));
4919
  return TRUE;
4920
}
4921
 
4922
 
4923
/* Split a conditional move into constituent parts, returning a SEQUENCE
4924
   containing all of the insns.  */
4925
 
4926
rtx
4927
frv_split_cond_move (rtx operands[])
4928
{
4929
  rtx dest      = operands[0];
4930
  rtx test      = operands[1];
4931
  rtx cc_reg    = operands[2];
4932
  rtx src1      = operands[3];
4933
  rtx src2      = operands[4];
4934
  rtx cr_reg    = operands[5];
4935
  rtx ret;
4936
  enum machine_mode cr_mode = GET_MODE (cr_reg);
4937
 
4938
  start_sequence ();
4939
 
4940
  /* Set the appropriate CCR bit.  */
4941
  emit_insn (gen_rtx_SET (VOIDmode,
4942
                          cr_reg,
4943
                          gen_rtx_fmt_ee (GET_CODE (test),
4944
                                          GET_MODE (cr_reg),
4945
                                          cc_reg,
4946
                                          const0_rtx)));
4947
 
4948
  /* Handle various cases of conditional move involving two constants.  */
4949
  if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
4950
    {
4951
      HOST_WIDE_INT value1 = INTVAL (src1);
4952
      HOST_WIDE_INT value2 = INTVAL (src2);
4953
 
4954
      /* Having 0 as one of the constants can be done by loading the other
4955
         constant, and optionally moving in gr0.  */
4956
      if (value1 == 0)
4957
        {
4958
          emit_move_insn (dest, src2);
4959
          emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4960
                                        gen_rtx_NE (cr_mode, cr_reg,
4961
                                                    const0_rtx),
4962
                                        gen_rtx_SET (VOIDmode, dest, src1)));
4963
        }
4964
 
4965
      else if (value2 == 0)
4966
        {
4967
          emit_move_insn (dest, src1);
4968
          emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4969
                                        gen_rtx_EQ (cr_mode, cr_reg,
4970
                                                    const0_rtx),
4971
                                        gen_rtx_SET (VOIDmode, dest, src2)));
4972
        }
4973
 
4974
      /* If the first value is within an addi range and also the difference
4975
         between the two fits in an addi's range, load up the difference, then
4976
         conditionally move in 0, and then unconditionally add the first
4977
         value.  */
4978
      else if (IN_RANGE (value1, -2048, 2047)
4979
               && IN_RANGE (value2 - value1, -2048, 2047))
4980
        {
4981
          rtx dest_si = ((GET_MODE (dest) == SImode)
4982
                         ? dest
4983
                         : gen_rtx_SUBREG (SImode, dest, 0));
4984
 
4985
          emit_move_insn (dest_si, GEN_INT (value2 - value1));
4986
          emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4987
                                        gen_rtx_NE (cr_mode, cr_reg,
4988
                                                    const0_rtx),
4989
                                        gen_rtx_SET (VOIDmode, dest_si,
4990
                                                     const0_rtx)));
4991
          emit_insn (gen_addsi3 (dest_si, dest_si, src1));
4992
        }
4993
 
4994
      else
4995
        gcc_unreachable ();
4996
    }
4997
  else
4998
    {
4999
      /* Emit the conditional move for the test being true if needed.  */
5000
      if (! rtx_equal_p (dest, src1))
5001
        emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5002
                                      gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5003
                                      gen_rtx_SET (VOIDmode, dest, src1)));
5004
 
5005
      /* Emit the conditional move for the test being false if needed.  */
5006
      if (! rtx_equal_p (dest, src2))
5007
        emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5008
                                      gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
5009
                                      gen_rtx_SET (VOIDmode, dest, src2)));
5010
    }
5011
 
5012
  /* Finish up, return sequence.  */
5013
  ret = get_insns ();
5014
  end_sequence ();
5015
  return ret;
5016
}
5017
 
5018
 
5019
/* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a
5020
   memory location that is not known to be dword-aligned.  */
5021
void
5022
frv_split_double_load (rtx dest, rtx source)
5023
{
5024
  int regno = REGNO (dest);
5025
  rtx dest1 = gen_highpart (SImode, dest);
5026
  rtx dest2 = gen_lowpart (SImode, dest);
5027
  rtx address = XEXP (source, 0);
5028
 
5029
  /* If the address is pre-modified, load the lower-numbered register
5030
     first, then load the other register using an integer offset from
5031
     the modified base register.  This order should always be safe,
5032
     since the pre-modification cannot affect the same registers as the
5033
     load does.
5034
 
5035
     The situation for other loads is more complicated.  Loading one
5036
     of the registers could affect the value of ADDRESS, so we must
5037
     be careful which order we do them in.  */
5038
  if (GET_CODE (address) == PRE_MODIFY
5039
      || ! refers_to_regno_p (regno, regno + 1, address, NULL))
5040
    {
5041
      /* It is safe to load the lower-numbered register first.  */
5042
      emit_move_insn (dest1, change_address (source, SImode, NULL));
5043
      emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
5044
    }
5045
  else
5046
    {
5047
      /* ADDRESS is not pre-modified and the address depends on the
5048
         lower-numbered register.  Load the higher-numbered register
5049
         first.  */
5050
      emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
5051
      emit_move_insn (dest1, change_address (source, SImode, NULL));
5052
    }
5053
}
5054
 
5055
/* Split (set DEST SOURCE), where DEST refers to a dword memory location
5056
   and SOURCE is either a double register or the constant zero.  */
5057
void
5058
frv_split_double_store (rtx dest, rtx source)
5059
{
5060
  rtx dest1 = change_address (dest, SImode, NULL);
5061
  rtx dest2 = frv_index_memory (dest, SImode, 1);
5062
  if (ZERO_P (source))
5063
    {
5064
      emit_move_insn (dest1, CONST0_RTX (SImode));
5065
      emit_move_insn (dest2, CONST0_RTX (SImode));
5066
    }
5067
  else
5068
    {
5069
      emit_move_insn (dest1, gen_highpart (SImode, source));
5070
      emit_move_insn (dest2, gen_lowpart (SImode, source));
5071
    }
5072
}
5073
 
5074
 
5075
/* Split a min/max operation returning a SEQUENCE containing all of the
5076
   insns.  */
5077
 
5078
rtx
5079
frv_split_minmax (rtx operands[])
5080
{
5081
  rtx dest      = operands[0];
5082
  rtx minmax    = operands[1];
5083
  rtx src1      = operands[2];
5084
  rtx src2      = operands[3];
5085
  rtx cc_reg    = operands[4];
5086
  rtx cr_reg    = operands[5];
5087
  rtx ret;
5088
  enum rtx_code test_code;
5089
  enum machine_mode cr_mode = GET_MODE (cr_reg);
5090
 
5091
  start_sequence ();
5092
 
5093
  /* Figure out which test to use.  */
5094
  switch (GET_CODE (minmax))
5095
    {
5096
    default:
5097
      gcc_unreachable ();
5098
 
5099
    case SMIN: test_code = LT;  break;
5100
    case SMAX: test_code = GT;  break;
5101
    case UMIN: test_code = LTU; break;
5102
    case UMAX: test_code = GTU; break;
5103
    }
5104
 
5105
  /* Issue the compare instruction.  */
5106
  emit_insn (gen_rtx_SET (VOIDmode,
5107
                          cc_reg,
5108
                          gen_rtx_COMPARE (GET_MODE (cc_reg),
5109
                                           src1, src2)));
5110
 
5111
  /* Set the appropriate CCR bit.  */
5112
  emit_insn (gen_rtx_SET (VOIDmode,
5113
                          cr_reg,
5114
                          gen_rtx_fmt_ee (test_code,
5115
                                          GET_MODE (cr_reg),
5116
                                          cc_reg,
5117
                                          const0_rtx)));
5118
 
5119
  /* If are taking the min/max of a nonzero constant, load that first, and
5120
     then do a conditional move of the other value.  */
5121
  if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
5122
    {
5123
      gcc_assert (!rtx_equal_p (dest, src1));
5124
 
5125
      emit_move_insn (dest, src2);
5126
      emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5127
                                    gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5128
                                    gen_rtx_SET (VOIDmode, dest, src1)));
5129
    }
5130
 
5131
  /* Otherwise, do each half of the move.  */
5132
  else
5133
    {
5134
      /* Emit the conditional move for the test being true if needed.  */
5135
      if (! rtx_equal_p (dest, src1))
5136
        emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5137
                                      gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5138
                                      gen_rtx_SET (VOIDmode, dest, src1)));
5139
 
5140
      /* Emit the conditional move for the test being false if needed.  */
5141
      if (! rtx_equal_p (dest, src2))
5142
        emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5143
                                      gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
5144
                                      gen_rtx_SET (VOIDmode, dest, src2)));
5145
    }
5146
 
5147
  /* Finish up, return sequence.  */
5148
  ret = get_insns ();
5149
  end_sequence ();
5150
  return ret;
5151
}
5152
 
5153
 
5154
/* Split an integer abs operation returning a SEQUENCE containing all of the
5155
   insns.  */
5156
 
5157
rtx
5158
frv_split_abs (rtx operands[])
5159
{
5160
  rtx dest      = operands[0];
5161
  rtx src       = operands[1];
5162
  rtx cc_reg    = operands[2];
5163
  rtx cr_reg    = operands[3];
5164
  rtx ret;
5165
 
5166
  start_sequence ();
5167
 
5168
  /* Issue the compare < 0 instruction.  */
5169
  emit_insn (gen_rtx_SET (VOIDmode,
5170
                          cc_reg,
5171
                          gen_rtx_COMPARE (CCmode, src, const0_rtx)));
5172
 
5173
  /* Set the appropriate CCR bit.  */
5174
  emit_insn (gen_rtx_SET (VOIDmode,
5175
                          cr_reg,
5176
                          gen_rtx_fmt_ee (LT, CC_CCRmode, cc_reg, const0_rtx)));
5177
 
5178
  /* Emit the conditional negate if the value is negative.  */
5179
  emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5180
                                gen_rtx_NE (CC_CCRmode, cr_reg, const0_rtx),
5181
                                gen_negsi2 (dest, src)));
5182
 
5183
  /* Emit the conditional move for the test being false if needed.  */
5184
  if (! rtx_equal_p (dest, src))
5185
    emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5186
                                  gen_rtx_EQ (CC_CCRmode, cr_reg, const0_rtx),
5187
                                  gen_rtx_SET (VOIDmode, dest, src)));
5188
 
5189
  /* Finish up, return sequence.  */
5190
  ret = get_insns ();
5191
  end_sequence ();
5192
  return ret;
5193
}
5194
 
5195
 
5196
/* An internal function called by for_each_rtx to clear in a hard_reg set each
5197
   register used in an insn.  */
5198
 
5199
static int
5200
frv_clear_registers_used (rtx *ptr, void *data)
5201
{
5202
  if (GET_CODE (*ptr) == REG)
5203
    {
5204
      int regno = REGNO (*ptr);
5205
      HARD_REG_SET *p_regs = (HARD_REG_SET *)data;
5206
 
5207
      if (regno < FIRST_PSEUDO_REGISTER)
5208
        {
5209
          int reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (*ptr));
5210
 
5211
          while (regno < reg_max)
5212
            {
5213
              CLEAR_HARD_REG_BIT (*p_regs, regno);
5214
              regno++;
5215
            }
5216
        }
5217
    }
5218
 
5219
  return 0;
5220
}
5221
 
5222
 
5223
/* Initialize the extra fields provided by IFCVT_EXTRA_FIELDS.  */
5224
 
5225
/* On the FR-V, we don't have any extra fields per se, but it is useful hook to
5226
   initialize the static storage.  */
5227
void
5228
frv_ifcvt_init_extra_fields (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
5229
{
5230
  frv_ifcvt.added_insns_list = NULL_RTX;
5231
  frv_ifcvt.cur_scratch_regs = 0;
5232
  frv_ifcvt.num_nested_cond_exec = 0;
5233
  frv_ifcvt.cr_reg = NULL_RTX;
5234
  frv_ifcvt.nested_cc_reg = NULL_RTX;
5235
  frv_ifcvt.extra_int_cr = NULL_RTX;
5236
  frv_ifcvt.extra_fp_cr = NULL_RTX;
5237
  frv_ifcvt.last_nested_if_cr = NULL_RTX;
5238
}
5239
 
5240
 
5241
/* Internal function to add a potential insn to the list of insns to be inserted
5242
   if the conditional execution conversion is successful.  */
5243
 
5244
static void
5245
frv_ifcvt_add_insn (rtx pattern, rtx insn, int before_p)
5246
{
5247
  rtx link = alloc_EXPR_LIST (VOIDmode, pattern, insn);
5248
 
5249
  link->jump = before_p;        /* Mark to add this before or after insn.  */
5250
  frv_ifcvt.added_insns_list = alloc_EXPR_LIST (VOIDmode, link,
5251
                                                frv_ifcvt.added_insns_list);
5252
 
5253
  if (TARGET_DEBUG_COND_EXEC)
5254
    {
5255
      fprintf (stderr,
5256
               "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n",
5257
               (before_p) ? "before" : "after",
5258
               (int)INSN_UID (insn));
5259
 
5260
      debug_rtx (pattern);
5261
    }
5262
}
5263
 
5264
 
5265
/* A C expression to modify the code described by the conditional if
5266
   information CE_INFO, possibly updating the tests in TRUE_EXPR, and
5267
   FALSE_EXPR for converting if-then and if-then-else code to conditional
5268
   instructions.  Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the
5269
   tests cannot be converted.  */
5270
 
5271
void
5272
frv_ifcvt_modify_tests (ce_if_block_t *ce_info, rtx *p_true, rtx *p_false)
5273
{
5274
  basic_block test_bb = ce_info->test_bb;       /* test basic block */
5275
  basic_block then_bb = ce_info->then_bb;       /* THEN */
5276
  basic_block else_bb = ce_info->else_bb;       /* ELSE or NULL */
5277
  basic_block join_bb = ce_info->join_bb;       /* join block or NULL */
5278
  rtx true_expr = *p_true;
5279
  rtx cr;
5280
  rtx cc;
5281
  rtx nested_cc;
5282
  enum machine_mode mode = GET_MODE (true_expr);
5283
  int j;
5284
  basic_block *bb;
5285
  int num_bb;
5286
  frv_tmp_reg_t *tmp_reg = &frv_ifcvt.tmp_reg;
5287
  rtx check_insn;
5288
  rtx sub_cond_exec_reg;
5289
  enum rtx_code code;
5290
  enum rtx_code code_true;
5291
  enum rtx_code code_false;
5292
  enum reg_class cc_class;
5293
  enum reg_class cr_class;
5294
  int cc_first;
5295
  int cc_last;
5296
  reg_set_iterator rsi;
5297
 
5298
  /* Make sure we are only dealing with hard registers.  Also honor the
5299
     -mno-cond-exec switch, and -mno-nested-cond-exec switches if
5300
     applicable.  */
5301
  if (!reload_completed || !TARGET_COND_EXEC
5302
      || (!TARGET_NESTED_CE && ce_info->pass > 1))
5303
    goto fail;
5304
 
5305
  /* Figure out which registers we can allocate for our own purposes.  Only
5306
     consider registers that are not preserved across function calls and are
5307
     not fixed.  However, allow the ICC/ICR temporary registers to be allocated
5308
     if we did not need to use them in reloading other registers.  */
5309
  memset (&tmp_reg->regs, 0, sizeof (tmp_reg->regs));
5310
  COPY_HARD_REG_SET (tmp_reg->regs, call_used_reg_set);
5311
  AND_COMPL_HARD_REG_SET (tmp_reg->regs, fixed_reg_set);
5312
  SET_HARD_REG_BIT (tmp_reg->regs, ICC_TEMP);
5313
  SET_HARD_REG_BIT (tmp_reg->regs, ICR_TEMP);
5314
 
5315
  /* If this is a nested IF, we need to discover whether the CC registers that
5316
     are set/used inside of the block are used anywhere else.  If not, we can
5317
     change them to be the CC register that is paired with the CR register that
5318
     controls the outermost IF block.  */
5319
  if (ce_info->pass > 1)
5320
    {
5321
      CLEAR_HARD_REG_SET (frv_ifcvt.nested_cc_ok_rewrite);
5322
      for (j = CC_FIRST; j <= CC_LAST; j++)
5323
        if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5324
          {
5325
            if (REGNO_REG_SET_P (df_get_live_in (then_bb), j))
5326
              continue;
5327
 
5328
            if (else_bb
5329
                && REGNO_REG_SET_P (df_get_live_in (else_bb), j))
5330
              continue;
5331
 
5332
            if (join_bb
5333
                && REGNO_REG_SET_P (df_get_live_in (join_bb), j))
5334
              continue;
5335
 
5336
            SET_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j);
5337
          }
5338
    }
5339
 
5340
  for (j = 0; j < frv_ifcvt.cur_scratch_regs; j++)
5341
    frv_ifcvt.scratch_regs[j] = NULL_RTX;
5342
 
5343
  frv_ifcvt.added_insns_list = NULL_RTX;
5344
  frv_ifcvt.cur_scratch_regs = 0;
5345
 
5346
  bb = (basic_block *) alloca ((2 + ce_info->num_multiple_test_blocks)
5347
                               * sizeof (basic_block));
5348
 
5349
  if (join_bb)
5350
    {
5351
      unsigned int regno;
5352
 
5353
      /* Remove anything live at the beginning of the join block from being
5354
         available for allocation.  */
5355
      EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (join_bb), 0, regno, rsi)
5356
        {
5357
          if (regno < FIRST_PSEUDO_REGISTER)
5358
            CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
5359
        }
5360
    }
5361
 
5362
  /* Add in all of the blocks in multiple &&/|| blocks to be scanned.  */
5363
  num_bb = 0;
5364
  if (ce_info->num_multiple_test_blocks)
5365
    {
5366
      basic_block multiple_test_bb = ce_info->last_test_bb;
5367
 
5368
      while (multiple_test_bb != test_bb)
5369
        {
5370
          bb[num_bb++] = multiple_test_bb;
5371
          multiple_test_bb = EDGE_PRED (multiple_test_bb, 0)->src;
5372
        }
5373
    }
5374
 
5375
  /* Add in the THEN and ELSE blocks to be scanned.  */
5376
  bb[num_bb++] = then_bb;
5377
  if (else_bb)
5378
    bb[num_bb++] = else_bb;
5379
 
5380
  sub_cond_exec_reg = NULL_RTX;
5381
  frv_ifcvt.num_nested_cond_exec = 0;
5382
 
5383
  /* Scan all of the blocks for registers that must not be allocated.  */
5384
  for (j = 0; j < num_bb; j++)
5385
    {
5386
      rtx last_insn = BB_END (bb[j]);
5387
      rtx insn = BB_HEAD (bb[j]);
5388
      unsigned int regno;
5389
 
5390
      if (dump_file)
5391
        fprintf (dump_file, "Scanning %s block %d, start %d, end %d\n",
5392
                 (bb[j] == else_bb) ? "else" : ((bb[j] == then_bb) ? "then" : "test"),
5393
                 (int) bb[j]->index,
5394
                 (int) INSN_UID (BB_HEAD (bb[j])),
5395
                 (int) INSN_UID (BB_END (bb[j])));
5396
 
5397
      /* Anything live at the beginning of the block is obviously unavailable
5398
         for allocation.  */
5399
      EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (bb[j]), 0, regno, rsi)
5400
        {
5401
          if (regno < FIRST_PSEUDO_REGISTER)
5402
            CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
5403
        }
5404
 
5405
      /* Loop through the insns in the block.  */
5406
      for (;;)
5407
        {
5408
          /* Mark any new registers that are created as being unavailable for
5409
             allocation.  Also see if the CC register used in nested IFs can be
5410
             reallocated.  */
5411
          if (INSN_P (insn))
5412
            {
5413
              rtx pattern;
5414
              rtx set;
5415
              int skip_nested_if = FALSE;
5416
 
5417
              for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
5418
                            (void *)&tmp_reg->regs);
5419
 
5420
              pattern = PATTERN (insn);
5421
              if (GET_CODE (pattern) == COND_EXEC)
5422
                {
5423
                  rtx reg = XEXP (COND_EXEC_TEST (pattern), 0);
5424
 
5425
                  if (reg != sub_cond_exec_reg)
5426
                    {
5427
                      sub_cond_exec_reg = reg;
5428
                      frv_ifcvt.num_nested_cond_exec++;
5429
                    }
5430
                }
5431
 
5432
              set = single_set_pattern (pattern);
5433
              if (set)
5434
                {
5435
                  rtx dest = SET_DEST (set);
5436
                  rtx src = SET_SRC (set);
5437
 
5438
                  if (GET_CODE (dest) == REG)
5439
                    {
5440
                      int regno = REGNO (dest);
5441
                      enum rtx_code src_code = GET_CODE (src);
5442
 
5443
                      if (CC_P (regno) && src_code == COMPARE)
5444
                        skip_nested_if = TRUE;
5445
 
5446
                      else if (CR_P (regno)
5447
                               && (src_code == IF_THEN_ELSE
5448
                                   || COMPARISON_P (src)))
5449
                        skip_nested_if = TRUE;
5450
                    }
5451
                }
5452
 
5453
              if (! skip_nested_if)
5454
                for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
5455
                              (void *)&frv_ifcvt.nested_cc_ok_rewrite);
5456
            }
5457
 
5458
          if (insn == last_insn)
5459
            break;
5460
 
5461
          insn = NEXT_INSN (insn);
5462
        }
5463
    }
5464
 
5465
  /* If this is a nested if, rewrite the CC registers that are available to
5466
     include the ones that can be rewritten, to increase the chance of being
5467
     able to allocate a paired CC/CR register combination.  */
5468
  if (ce_info->pass > 1)
5469
    {
5470
      for (j = CC_FIRST; j <= CC_LAST; j++)
5471
        if (TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j))
5472
          SET_HARD_REG_BIT (tmp_reg->regs, j);
5473
        else
5474
          CLEAR_HARD_REG_BIT (tmp_reg->regs, j);
5475
    }
5476
 
5477
  if (dump_file)
5478
    {
5479
      int num_gprs = 0;
5480
      fprintf (dump_file, "Available GPRs: ");
5481
 
5482
      for (j = GPR_FIRST; j <= GPR_LAST; j++)
5483
        if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5484
          {
5485
            fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5486
            if (++num_gprs > GPR_TEMP_NUM+2)
5487
              break;
5488
          }
5489
 
5490
      fprintf (dump_file, "%s\nAvailable CRs:  ",
5491
               (num_gprs > GPR_TEMP_NUM+2) ? " ..." : "");
5492
 
5493
      for (j = CR_FIRST; j <= CR_LAST; j++)
5494
        if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5495
          fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5496
 
5497
      fputs ("\n", dump_file);
5498
 
5499
      if (ce_info->pass > 1)
5500
        {
5501
          fprintf (dump_file, "Modifiable CCs: ");
5502
          for (j = CC_FIRST; j <= CC_LAST; j++)
5503
            if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5504
              fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5505
 
5506
          fprintf (dump_file, "\n%d nested COND_EXEC statements\n",
5507
                   frv_ifcvt.num_nested_cond_exec);
5508
        }
5509
    }
5510
 
5511
  /* Allocate the appropriate temporary condition code register.  Try to
5512
     allocate the ICR/FCR register that corresponds to the ICC/FCC register so
5513
     that conditional cmp's can be done.  */
5514
  if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
5515
    {
5516
      cr_class = ICR_REGS;
5517
      cc_class = ICC_REGS;
5518
      cc_first = ICC_FIRST;
5519
      cc_last = ICC_LAST;
5520
    }
5521
  else if (mode == CC_FPmode)
5522
    {
5523
      cr_class = FCR_REGS;
5524
      cc_class = FCC_REGS;
5525
      cc_first = FCC_FIRST;
5526
      cc_last = FCC_LAST;
5527
    }
5528
  else
5529
    {
5530
      cc_first = cc_last = 0;
5531
      cr_class = cc_class = NO_REGS;
5532
    }
5533
 
5534
  cc = XEXP (true_expr, 0);
5535
  nested_cc = cr = NULL_RTX;
5536
  if (cc_class != NO_REGS)
5537
    {
5538
      /* For nested IFs and &&/||, see if we can find a CC and CR register pair
5539
         so we can execute a csubcc/caddcc/cfcmps instruction.  */
5540
      int cc_regno;
5541
 
5542
      for (cc_regno = cc_first; cc_regno <= cc_last; cc_regno++)
5543
        {
5544
          int cr_regno = cc_regno - CC_FIRST + CR_FIRST;
5545
 
5546
          if (TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cc_regno)
5547
              && TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cr_regno))
5548
            {
5549
              frv_ifcvt.tmp_reg.next_reg[ (int)cr_class ] = cr_regno;
5550
              cr = frv_alloc_temp_reg (tmp_reg, cr_class, CC_CCRmode, TRUE,
5551
                                       TRUE);
5552
 
5553
              frv_ifcvt.tmp_reg.next_reg[ (int)cc_class ] = cc_regno;
5554
              nested_cc = frv_alloc_temp_reg (tmp_reg, cc_class, CCmode,
5555
                                                  TRUE, TRUE);
5556
              break;
5557
            }
5558
        }
5559
    }
5560
 
5561
  if (! cr)
5562
    {
5563
      if (dump_file)
5564
        fprintf (dump_file, "Could not allocate a CR temporary register\n");
5565
 
5566
      goto fail;
5567
    }
5568
 
5569
  if (dump_file)
5570
    fprintf (dump_file,
5571
             "Will use %s for conditional execution, %s for nested comparisons\n",
5572
             reg_names[ REGNO (cr)],
5573
             (nested_cc) ? reg_names[ REGNO (nested_cc) ] : "<none>");
5574
 
5575
  /* Set the CCR bit.  Note for integer tests, we reverse the condition so that
5576
     in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR
5577
     bit being true.  We don't do this for floating point, because of NaNs.  */
5578
  code = GET_CODE (true_expr);
5579
  if (GET_MODE (cc) != CC_FPmode)
5580
    {
5581
      code = reverse_condition (code);
5582
      code_true = EQ;
5583
      code_false = NE;
5584
    }
5585
  else
5586
    {
5587
      code_true = NE;
5588
      code_false = EQ;
5589
    }
5590
 
5591
  check_insn = gen_rtx_SET (VOIDmode, cr,
5592
                            gen_rtx_fmt_ee (code, CC_CCRmode, cc, const0_rtx));
5593
 
5594
  /* Record the check insn to be inserted later.  */
5595
  frv_ifcvt_add_insn (check_insn, BB_END (test_bb), TRUE);
5596
 
5597
  /* Update the tests.  */
5598
  frv_ifcvt.cr_reg = cr;
5599
  frv_ifcvt.nested_cc_reg = nested_cc;
5600
  *p_true = gen_rtx_fmt_ee (code_true, CC_CCRmode, cr, const0_rtx);
5601
  *p_false = gen_rtx_fmt_ee (code_false, CC_CCRmode, cr, const0_rtx);
5602
  return;
5603
 
5604
  /* Fail, don't do this conditional execution.  */
5605
 fail:
5606
  *p_true = NULL_RTX;
5607
  *p_false = NULL_RTX;
5608
  if (dump_file)
5609
    fprintf (dump_file, "Disabling this conditional execution.\n");
5610
 
5611
  return;
5612
}
5613
 
5614
 
5615
/* A C expression to modify the code described by the conditional if
5616
   information CE_INFO, for the basic block BB, possibly updating the tests in
5617
   TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or
5618
   if-then-else code to conditional instructions.  Set either TRUE_EXPR or
5619
   FALSE_EXPR to a null pointer if the tests cannot be converted.  */
5620
 
5621
/* p_true and p_false are given expressions of the form:
5622
 
5623
        (and (eq:CC_CCR (reg:CC_CCR)
5624
                        (const_int 0))
5625
             (eq:CC (reg:CC)
5626
                    (const_int 0))) */
5627
 
5628
void
5629
frv_ifcvt_modify_multiple_tests (ce_if_block_t *ce_info,
5630
                                 basic_block bb,
5631
                                 rtx *p_true,
5632
                                 rtx *p_false)
5633
{
5634
  rtx old_true = XEXP (*p_true, 0);
5635
  rtx old_false = XEXP (*p_false, 0);
5636
  rtx true_expr = XEXP (*p_true, 1);
5637
  rtx false_expr = XEXP (*p_false, 1);
5638
  rtx test_expr;
5639
  rtx old_test;
5640
  rtx cr = XEXP (old_true, 0);
5641
  rtx check_insn;
5642
  rtx new_cr = NULL_RTX;
5643
  rtx *p_new_cr = (rtx *)0;
5644
  rtx if_else;
5645
  rtx compare;
5646
  rtx cc;
5647
  enum reg_class cr_class;
5648
  enum machine_mode mode = GET_MODE (true_expr);
5649
  rtx (*logical_func)(rtx, rtx, rtx);
5650
 
5651
  if (TARGET_DEBUG_COND_EXEC)
5652
    {
5653
      fprintf (stderr,
5654
               "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n",
5655
               ce_info->and_and_p ? "&&" : "||");
5656
 
5657
      debug_rtx (*p_true);
5658
 
5659
      fputs ("\nfalse insn:\n", stderr);
5660
      debug_rtx (*p_false);
5661
    }
5662
 
5663
  if (!TARGET_MULTI_CE)
5664
    goto fail;
5665
 
5666
  if (GET_CODE (cr) != REG)
5667
    goto fail;
5668
 
5669
  if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
5670
    {
5671
      cr_class = ICR_REGS;
5672
      p_new_cr = &frv_ifcvt.extra_int_cr;
5673
    }
5674
  else if (mode == CC_FPmode)
5675
    {
5676
      cr_class = FCR_REGS;
5677
      p_new_cr = &frv_ifcvt.extra_fp_cr;
5678
    }
5679
  else
5680
    goto fail;
5681
 
5682
  /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or
5683
     more &&/|| tests.  */
5684
  new_cr = *p_new_cr;
5685
  if (! new_cr)
5686
    {
5687
      new_cr = *p_new_cr = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, cr_class,
5688
                                               CC_CCRmode, TRUE, TRUE);
5689
      if (! new_cr)
5690
        goto fail;
5691
    }
5692
 
5693
  if (ce_info->and_and_p)
5694
    {
5695
      old_test = old_false;
5696
      test_expr = true_expr;
5697
      logical_func = (GET_CODE (old_true) == EQ) ? gen_andcr : gen_andncr;
5698
      *p_true = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
5699
      *p_false = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
5700
    }
5701
  else
5702
    {
5703
      old_test = old_false;
5704
      test_expr = false_expr;
5705
      logical_func = (GET_CODE (old_false) == EQ) ? gen_orcr : gen_orncr;
5706
      *p_true = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
5707
      *p_false = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
5708
    }
5709
 
5710
  /* First add the andcr/andncr/orcr/orncr, which will be added after the
5711
     conditional check instruction, due to frv_ifcvt_add_insn being a LIFO
5712
     stack.  */
5713
  frv_ifcvt_add_insn ((*logical_func) (cr, cr, new_cr), BB_END (bb), TRUE);
5714
 
5715
  /* Now add the conditional check insn.  */
5716
  cc = XEXP (test_expr, 0);
5717
  compare = gen_rtx_fmt_ee (GET_CODE (test_expr), CC_CCRmode, cc, const0_rtx);
5718
  if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, old_test, compare, const0_rtx);
5719
 
5720
  check_insn = gen_rtx_SET (VOIDmode, new_cr, if_else);
5721
 
5722
  /* Add the new check insn to the list of check insns that need to be
5723
     inserted.  */
5724
  frv_ifcvt_add_insn (check_insn, BB_END (bb), TRUE);
5725
 
5726
  if (TARGET_DEBUG_COND_EXEC)
5727
    {
5728
      fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n",
5729
             stderr);
5730
 
5731
      debug_rtx (*p_true);
5732
 
5733
      fputs ("\nfalse insn:\n", stderr);
5734
      debug_rtx (*p_false);
5735
    }
5736
 
5737
  return;
5738
 
5739
 fail:
5740
  *p_true = *p_false = NULL_RTX;
5741
 
5742
  /* If we allocated a CR register, release it.  */
5743
  if (new_cr)
5744
    {
5745
      CLEAR_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, REGNO (new_cr));
5746
      *p_new_cr = NULL_RTX;
5747
    }
5748
 
5749
  if (TARGET_DEBUG_COND_EXEC)
5750
    fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr);
5751
 
5752
  return;
5753
}
5754
 
5755
 
5756
/* Return a register which will be loaded with a value if an IF block is
5757
   converted to conditional execution.  This is used to rewrite instructions
5758
   that use constants to ones that just use registers.  */
5759
 
5760
static rtx
5761
frv_ifcvt_load_value (rtx value, rtx insn ATTRIBUTE_UNUSED)
5762
{
5763
  int num_alloc = frv_ifcvt.cur_scratch_regs;
5764
  int i;
5765
  rtx reg;
5766
 
5767
  /* We know gr0 == 0, so replace any errant uses.  */
5768
  if (value == const0_rtx)
5769
    return gen_rtx_REG (SImode, GPR_FIRST);
5770
 
5771
  /* First search all registers currently loaded to see if we have an
5772
     applicable constant.  */
5773
  if (CONSTANT_P (value)
5774
      || (GET_CODE (value) == REG && REGNO (value) == LR_REGNO))
5775
    {
5776
      for (i = 0; i < num_alloc; i++)
5777
        {
5778
          if (rtx_equal_p (SET_SRC (frv_ifcvt.scratch_regs[i]), value))
5779
            return SET_DEST (frv_ifcvt.scratch_regs[i]);
5780
        }
5781
    }
5782
 
5783
  /* Have we exhausted the number of registers available?  */
5784
  if (num_alloc >= GPR_TEMP_NUM)
5785
    {
5786
      if (dump_file)
5787
        fprintf (dump_file, "Too many temporary registers allocated\n");
5788
 
5789
      return NULL_RTX;
5790
    }
5791
 
5792
  /* Allocate the new register.  */
5793
  reg = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, GPR_REGS, SImode, TRUE, TRUE);
5794
  if (! reg)
5795
    {
5796
      if (dump_file)
5797
        fputs ("Could not find a scratch register\n", dump_file);
5798
 
5799
      return NULL_RTX;
5800
    }
5801
 
5802
  frv_ifcvt.cur_scratch_regs++;
5803
  frv_ifcvt.scratch_regs[num_alloc] = gen_rtx_SET (VOIDmode, reg, value);
5804
 
5805
  if (dump_file)
5806
    {
5807
      if (GET_CODE (value) == CONST_INT)
5808
        fprintf (dump_file, "Register %s will hold %ld\n",
5809
                 reg_names[ REGNO (reg)], (long)INTVAL (value));
5810
 
5811
      else if (GET_CODE (value) == REG && REGNO (value) == LR_REGNO)
5812
        fprintf (dump_file, "Register %s will hold LR\n",
5813
                 reg_names[ REGNO (reg)]);
5814
 
5815
      else
5816
        fprintf (dump_file, "Register %s will hold a saved value\n",
5817
                 reg_names[ REGNO (reg)]);
5818
    }
5819
 
5820
  return reg;
5821
}
5822
 
5823
 
5824
/* Update a MEM used in conditional code that might contain an offset to put
5825
   the offset into a scratch register, so that the conditional load/store
5826
   operations can be used.  This function returns the original pointer if the
5827
   MEM is valid to use in conditional code, NULL if we can't load up the offset
5828
   into a temporary register, or the new MEM if we were successful.  */
5829
 
5830
static rtx
5831
frv_ifcvt_rewrite_mem (rtx mem, enum machine_mode mode, rtx insn)
5832
{
5833
  rtx addr = XEXP (mem, 0);
5834
 
5835
  if (!frv_legitimate_address_p_1 (mode, addr, reload_completed, TRUE, FALSE))
5836
    {
5837
      if (GET_CODE (addr) == PLUS)
5838
        {
5839
          rtx addr_op0 = XEXP (addr, 0);
5840
          rtx addr_op1 = XEXP (addr, 1);
5841
 
5842
          if (GET_CODE (addr_op0) == REG && CONSTANT_P (addr_op1))
5843
            {
5844
              rtx reg = frv_ifcvt_load_value (addr_op1, insn);
5845
              if (!reg)
5846
                return NULL_RTX;
5847
 
5848
              addr = gen_rtx_PLUS (Pmode, addr_op0, reg);
5849
            }
5850
 
5851
          else
5852
            return NULL_RTX;
5853
        }
5854
 
5855
      else if (CONSTANT_P (addr))
5856
        addr = frv_ifcvt_load_value (addr, insn);
5857
 
5858
      else
5859
        return NULL_RTX;
5860
 
5861
      if (addr == NULL_RTX)
5862
        return NULL_RTX;
5863
 
5864
      else if (XEXP (mem, 0) != addr)
5865
        return change_address (mem, mode, addr);
5866
    }
5867
 
5868
  return mem;
5869
}
5870
 
5871
 
5872
/* Given a PATTERN, return a SET expression if this PATTERN has only a single
5873
   SET, possibly conditionally executed.  It may also have CLOBBERs, USEs.  */
5874
 
5875
static rtx
5876
single_set_pattern (rtx pattern)
5877
{
5878
  rtx set;
5879
  int i;
5880
 
5881
  if (GET_CODE (pattern) == COND_EXEC)
5882
    pattern = COND_EXEC_CODE (pattern);
5883
 
5884
  if (GET_CODE (pattern) == SET)
5885
    return pattern;
5886
 
5887
  else if (GET_CODE (pattern) == PARALLEL)
5888
    {
5889
      for (i = 0, set = 0; i < XVECLEN (pattern, 0); i++)
5890
        {
5891
          rtx sub = XVECEXP (pattern, 0, i);
5892
 
5893
          switch (GET_CODE (sub))
5894
            {
5895
            case USE:
5896
            case CLOBBER:
5897
              break;
5898
 
5899
            case SET:
5900
              if (set)
5901
                return 0;
5902
              else
5903
                set = sub;
5904
              break;
5905
 
5906
            default:
5907
              return 0;
5908
            }
5909
        }
5910
      return set;
5911
    }
5912
 
5913
  return 0;
5914
}
5915
 
5916
 
5917
/* A C expression to modify the code described by the conditional if
5918
   information CE_INFO with the new PATTERN in INSN.  If PATTERN is a null
5919
   pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that
5920
   insn cannot be converted to be executed conditionally.  */
5921
 
5922
rtx
5923
frv_ifcvt_modify_insn (ce_if_block_t *ce_info,
5924
                       rtx pattern,
5925
                       rtx insn)
5926
{
5927
  rtx orig_ce_pattern = pattern;
5928
  rtx set;
5929
  rtx op0;
5930
  rtx op1;
5931
  rtx test;
5932
 
5933
  gcc_assert (GET_CODE (pattern) == COND_EXEC);
5934
 
5935
  test = COND_EXEC_TEST (pattern);
5936
  if (GET_CODE (test) == AND)
5937
    {
5938
      rtx cr = frv_ifcvt.cr_reg;
5939
      rtx test_reg;
5940
 
5941
      op0 = XEXP (test, 0);
5942
      if (! rtx_equal_p (cr, XEXP (op0, 0)))
5943
        goto fail;
5944
 
5945
      op1 = XEXP (test, 1);
5946
      test_reg = XEXP (op1, 0);
5947
      if (GET_CODE (test_reg) != REG)
5948
        goto fail;
5949
 
5950
      /* Is this the first nested if block in this sequence?  If so, generate
5951
         an andcr or andncr.  */
5952
      if (! frv_ifcvt.last_nested_if_cr)
5953
        {
5954
          rtx and_op;
5955
 
5956
          frv_ifcvt.last_nested_if_cr = test_reg;
5957
          if (GET_CODE (op0) == NE)
5958
            and_op = gen_andcr (test_reg, cr, test_reg);
5959
          else
5960
            and_op = gen_andncr (test_reg, cr, test_reg);
5961
 
5962
          frv_ifcvt_add_insn (and_op, insn, TRUE);
5963
        }
5964
 
5965
      /* If this isn't the first statement in the nested if sequence, see if we
5966
         are dealing with the same register.  */
5967
      else if (! rtx_equal_p (test_reg, frv_ifcvt.last_nested_if_cr))
5968
        goto fail;
5969
 
5970
      COND_EXEC_TEST (pattern) = test = op1;
5971
    }
5972
 
5973
  /* If this isn't a nested if, reset state variables.  */
5974
  else
5975
    {
5976
      frv_ifcvt.last_nested_if_cr = NULL_RTX;
5977
    }
5978
 
5979
  set = single_set_pattern (pattern);
5980
  if (set)
5981
    {
5982
      rtx dest = SET_DEST (set);
5983
      rtx src = SET_SRC (set);
5984
      enum machine_mode mode = GET_MODE (dest);
5985
 
5986
      /* Check for normal binary operators.  */
5987
      if (mode == SImode && ARITHMETIC_P (src))
5988
        {
5989
          op0 = XEXP (src, 0);
5990
          op1 = XEXP (src, 1);
5991
 
5992
          if (integer_register_operand (op0, SImode) && CONSTANT_P (op1))
5993
            {
5994
              op1 = frv_ifcvt_load_value (op1, insn);
5995
              if (op1)
5996
                COND_EXEC_CODE (pattern)
5997
                  = gen_rtx_SET (VOIDmode, dest, gen_rtx_fmt_ee (GET_CODE (src),
5998
                                                                 GET_MODE (src),
5999
                                                                 op0, op1));
6000
              else
6001
                goto fail;
6002
            }
6003
        }
6004
 
6005
      /* For multiply by a constant, we need to handle the sign extending
6006
         correctly.  Add a USE of the value after the multiply to prevent flow
6007
         from cratering because only one register out of the two were used.  */
6008
      else if (mode == DImode && GET_CODE (src) == MULT)
6009
        {
6010
          op0 = XEXP (src, 0);
6011
          op1 = XEXP (src, 1);
6012
          if (GET_CODE (op0) == SIGN_EXTEND && GET_CODE (op1) == CONST_INT)
6013
            {
6014
              op1 = frv_ifcvt_load_value (op1, insn);
6015
              if (op1)
6016
                {
6017
                  op1 = gen_rtx_SIGN_EXTEND (DImode, op1);
6018
                  COND_EXEC_CODE (pattern)
6019
                    = gen_rtx_SET (VOIDmode, dest,
6020
                                   gen_rtx_MULT (DImode, op0, op1));
6021
                }
6022
              else
6023
                goto fail;
6024
            }
6025
 
6026
          frv_ifcvt_add_insn (gen_use (dest), insn, FALSE);
6027
        }
6028
 
6029
      /* If we are just loading a constant created for a nested conditional
6030
         execution statement, just load the constant without any conditional
6031
         execution, since we know that the constant will not interfere with any
6032
         other registers.  */
6033
      else if (frv_ifcvt.scratch_insns_bitmap
6034
               && bitmap_bit_p (frv_ifcvt.scratch_insns_bitmap,
6035
                                INSN_UID (insn))
6036
               && REG_P (SET_DEST (set))
6037
               /* We must not unconditionally set a scratch reg chosen
6038
                  for a nested if-converted block if its incoming
6039
                  value from the TEST block (or the result of the THEN
6040
                  branch) could/should propagate to the JOIN block.
6041
                  It suffices to test whether the register is live at
6042
                  the JOIN point: if it's live there, we can infer
6043
                  that we set it in the former JOIN block of the
6044
                  nested if-converted block (otherwise it wouldn't
6045
                  have been available as a scratch register), and it
6046
                  is either propagated through or set in the other
6047
                  conditional block.  It's probably not worth trying
6048
                  to catch the latter case, and it could actually
6049
                  limit scheduling of the combined block quite
6050
                  severely.  */
6051
               && ce_info->join_bb
6052
               && ! (REGNO_REG_SET_P (df_get_live_in (ce_info->join_bb),
6053
                                      REGNO (SET_DEST (set))))
6054
               /* Similarly, we must not unconditionally set a reg
6055
                  used as scratch in the THEN branch if the same reg
6056
                  is live in the ELSE branch.  */
6057
               && (! ce_info->else_bb
6058
                   || BLOCK_FOR_INSN (insn) == ce_info->else_bb
6059
                   || ! (REGNO_REG_SET_P (df_get_live_in (ce_info->else_bb),
6060
                                          REGNO (SET_DEST (set))))))
6061
        pattern = set;
6062
 
6063
      else if (mode == QImode || mode == HImode || mode == SImode
6064
               || mode == SFmode)
6065
        {
6066
          int changed_p = FALSE;
6067
 
6068
          /* Check for just loading up a constant */
6069
          if (CONSTANT_P (src) && integer_register_operand (dest, mode))
6070
            {
6071
              src = frv_ifcvt_load_value (src, insn);
6072
              if (!src)
6073
                goto fail;
6074
 
6075
              changed_p = TRUE;
6076
            }
6077
 
6078
          /* See if we need to fix up stores */
6079
          if (GET_CODE (dest) == MEM)
6080
            {
6081
              rtx new_mem = frv_ifcvt_rewrite_mem (dest, mode, insn);
6082
 
6083
              if (!new_mem)
6084
                goto fail;
6085
 
6086
              else if (new_mem != dest)
6087
                {
6088
                  changed_p = TRUE;
6089
                  dest = new_mem;
6090
                }
6091
            }
6092
 
6093
          /* See if we need to fix up loads */
6094
          if (GET_CODE (src) == MEM)
6095
            {
6096
              rtx new_mem = frv_ifcvt_rewrite_mem (src, mode, insn);
6097
 
6098
              if (!new_mem)
6099
                goto fail;
6100
 
6101
              else if (new_mem != src)
6102
                {
6103
                  changed_p = TRUE;
6104
                  src = new_mem;
6105
                }
6106
            }
6107
 
6108
          /* If either src or destination changed, redo SET.  */
6109
          if (changed_p)
6110
            COND_EXEC_CODE (pattern) = gen_rtx_SET (VOIDmode, dest, src);
6111
        }
6112
 
6113
      /* Rewrite a nested set cccr in terms of IF_THEN_ELSE.  Also deal with
6114
         rewriting the CC register to be the same as the paired CC/CR register
6115
         for nested ifs.  */
6116
      else if (mode == CC_CCRmode && COMPARISON_P (src))
6117
        {
6118
          int regno = REGNO (XEXP (src, 0));
6119
          rtx if_else;
6120
 
6121
          if (ce_info->pass > 1
6122
              && regno != (int)REGNO (frv_ifcvt.nested_cc_reg)
6123
              && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, regno))
6124
            {
6125
              src = gen_rtx_fmt_ee (GET_CODE (src),
6126
                                    CC_CCRmode,
6127
                                    frv_ifcvt.nested_cc_reg,
6128
                                    XEXP (src, 1));
6129
            }
6130
 
6131
          if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, test, src, const0_rtx);
6132
          pattern = gen_rtx_SET (VOIDmode, dest, if_else);
6133
        }
6134
 
6135
      /* Remap a nested compare instruction to use the paired CC/CR reg.  */
6136
      else if (ce_info->pass > 1
6137
               && GET_CODE (dest) == REG
6138
               && CC_P (REGNO (dest))
6139
               && REGNO (dest) != REGNO (frv_ifcvt.nested_cc_reg)
6140
               && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite,
6141
                                     REGNO (dest))
6142
               && GET_CODE (src) == COMPARE)
6143
        {
6144
          PUT_MODE (frv_ifcvt.nested_cc_reg, GET_MODE (dest));
6145
          COND_EXEC_CODE (pattern)
6146
            = gen_rtx_SET (VOIDmode, frv_ifcvt.nested_cc_reg, copy_rtx (src));
6147
        }
6148
    }
6149
 
6150
  if (TARGET_DEBUG_COND_EXEC)
6151
    {
6152
      rtx orig_pattern = PATTERN (insn);
6153
 
6154
      PATTERN (insn) = pattern;
6155
      fprintf (stderr,
6156
               "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n",
6157
               ce_info->pass);
6158
 
6159
      debug_rtx (insn);
6160
      PATTERN (insn) = orig_pattern;
6161
    }
6162
 
6163
  return pattern;
6164
 
6165
 fail:
6166
  if (TARGET_DEBUG_COND_EXEC)
6167
    {
6168
      rtx orig_pattern = PATTERN (insn);
6169
 
6170
      PATTERN (insn) = orig_ce_pattern;
6171
      fprintf (stderr,
6172
               "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n",
6173
               ce_info->pass);
6174
 
6175
      debug_rtx (insn);
6176
      PATTERN (insn) = orig_pattern;
6177
    }
6178
 
6179
  return NULL_RTX;
6180
}
6181
 
6182
 
6183
/* A C expression to perform any final machine dependent modifications in
6184
   converting code to conditional execution in the code described by the
6185
   conditional if information CE_INFO.  */
6186
 
6187
void
6188
frv_ifcvt_modify_final (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
6189
{
6190
  rtx existing_insn;
6191
  rtx check_insn;
6192
  rtx p = frv_ifcvt.added_insns_list;
6193
  int i;
6194
 
6195
  /* Loop inserting the check insns.  The last check insn is the first test,
6196
     and is the appropriate place to insert constants.  */
6197
  gcc_assert (p);
6198
 
6199
  do
6200
    {
6201
      rtx check_and_insert_insns = XEXP (p, 0);
6202
      rtx old_p = p;
6203
 
6204
      check_insn = XEXP (check_and_insert_insns, 0);
6205
      existing_insn = XEXP (check_and_insert_insns, 1);
6206
      p = XEXP (p, 1);
6207
 
6208
      /* The jump bit is used to say that the new insn is to be inserted BEFORE
6209
         the existing insn, otherwise it is to be inserted AFTER.  */
6210
      if (check_and_insert_insns->jump)
6211
        {
6212
          emit_insn_before (check_insn, existing_insn);
6213
          check_and_insert_insns->jump = 0;
6214
        }
6215
      else
6216
        emit_insn_after (check_insn, existing_insn);
6217
 
6218
      free_EXPR_LIST_node (check_and_insert_insns);
6219
      free_EXPR_LIST_node (old_p);
6220
    }
6221
  while (p != NULL_RTX);
6222
 
6223
  /* Load up any constants needed into temp gprs */
6224
  for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
6225
    {
6226
      rtx insn = emit_insn_before (frv_ifcvt.scratch_regs[i], existing_insn);
6227
      if (! frv_ifcvt.scratch_insns_bitmap)
6228
        frv_ifcvt.scratch_insns_bitmap = BITMAP_ALLOC (NULL);
6229
      bitmap_set_bit (frv_ifcvt.scratch_insns_bitmap, INSN_UID (insn));
6230
      frv_ifcvt.scratch_regs[i] = NULL_RTX;
6231
    }
6232
 
6233
  frv_ifcvt.added_insns_list = NULL_RTX;
6234
  frv_ifcvt.cur_scratch_regs = 0;
6235
}
6236
 
6237
 
6238
/* A C expression to cancel any machine dependent modifications in converting
6239
   code to conditional execution in the code described by the conditional if
6240
   information CE_INFO.  */
6241
 
6242
void
6243
frv_ifcvt_modify_cancel (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
6244
{
6245
  int i;
6246
  rtx p = frv_ifcvt.added_insns_list;
6247
 
6248
  /* Loop freeing up the EXPR_LIST's allocated.  */
6249
  while (p != NULL_RTX)
6250
    {
6251
      rtx check_and_jump = XEXP (p, 0);
6252
      rtx old_p = p;
6253
 
6254
      p = XEXP (p, 1);
6255
      free_EXPR_LIST_node (check_and_jump);
6256
      free_EXPR_LIST_node (old_p);
6257
    }
6258
 
6259
  /* Release any temporary gprs allocated.  */
6260
  for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
6261
    frv_ifcvt.scratch_regs[i] = NULL_RTX;
6262
 
6263
  frv_ifcvt.added_insns_list = NULL_RTX;
6264
  frv_ifcvt.cur_scratch_regs = 0;
6265
  return;
6266
}
6267
 
6268
/* A C expression for the size in bytes of the trampoline, as an integer.
6269
   The template is:
6270
 
6271
        setlo #0, <jmp_reg>
6272
        setlo #0, <static_chain>
6273
        sethi #0, <jmp_reg>
6274
        sethi #0, <static_chain>
6275
        jmpl @(gr0,<jmp_reg>) */
6276
 
6277
int
6278
frv_trampoline_size (void)
6279
{
6280
  if (TARGET_FDPIC)
6281
    /* Allocate room for the function descriptor and the lddi
6282
       instruction.  */
6283
    return 8 + 6 * 4;
6284
  return 5 /* instructions */ * 4 /* instruction size.  */;
6285
}
6286
 
6287
 
6288
/* A C statement to initialize the variable parts of a trampoline.  ADDR is an
6289
   RTX for the address of the trampoline; FNADDR is an RTX for the address of
6290
   the nested function; STATIC_CHAIN is an RTX for the static chain value that
6291
   should be passed to the function when it is called.
6292
 
6293
   The template is:
6294
 
6295
        setlo #0, <jmp_reg>
6296
        setlo #0, <static_chain>
6297
        sethi #0, <jmp_reg>
6298
        sethi #0, <static_chain>
6299
        jmpl @(gr0,<jmp_reg>) */
6300
 
6301
static void
6302
frv_trampoline_init (rtx m_tramp, tree fndecl, rtx static_chain)
6303
{
6304
  rtx addr = XEXP (m_tramp, 0);
6305
  rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
6306
  rtx sc_reg = force_reg (Pmode, static_chain);
6307
 
6308
  emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
6309
                     LCT_NORMAL, VOIDmode, 4,
6310
                     addr, Pmode,
6311
                     GEN_INT (frv_trampoline_size ()), SImode,
6312
                     fnaddr, Pmode,
6313
                     sc_reg, Pmode);
6314
}
6315
 
6316
 
6317
/* Many machines have some registers that cannot be copied directly to or from
6318
   memory or even from other types of registers.  An example is the `MQ'
6319
   register, which on most machines, can only be copied to or from general
6320
   registers, but not memory.  Some machines allow copying all registers to and
6321
   from memory, but require a scratch register for stores to some memory
6322
   locations (e.g., those with symbolic address on the RT, and those with
6323
   certain symbolic address on the SPARC when compiling PIC).  In some cases,
6324
   both an intermediate and a scratch register are required.
6325
 
6326
   You should define these macros to indicate to the reload phase that it may
6327
   need to allocate at least one register for a reload in addition to the
6328
   register to contain the data.  Specifically, if copying X to a register
6329
   RCLASS in MODE requires an intermediate register, you should define
6330
   `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
6331
   whose registers can be used as intermediate registers or scratch registers.
6332
 
6333
   If copying a register RCLASS in MODE to X requires an intermediate or scratch
6334
   register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
6335
   largest register class required.  If the requirements for input and output
6336
   reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
6337
   instead of defining both macros identically.
6338
 
6339
   The values returned by these macros are often `GENERAL_REGS'.  Return
6340
   `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
6341
   to or from a register of RCLASS in MODE without requiring a scratch register.
6342
   Do not define this macro if it would always return `NO_REGS'.
6343
 
6344
   If a scratch register is required (either with or without an intermediate
6345
   register), you should define patterns for `reload_inM' or `reload_outM', as
6346
   required..  These patterns, which will normally be implemented with a
6347
   `define_expand', should be similar to the `movM' patterns, except that
6348
   operand 2 is the scratch register.
6349
 
6350
   Define constraints for the reload register and scratch register that contain
6351
   a single register class.  If the original reload register (whose class is
6352
   RCLASS) can meet the constraint given in the pattern, the value returned by
6353
   these macros is used for the class of the scratch register.  Otherwise, two
6354
   additional reload registers are required.  Their classes are obtained from
6355
   the constraints in the insn pattern.
6356
 
6357
   X might be a pseudo-register or a `subreg' of a pseudo-register, which could
6358
   either be in a hard register or in memory.  Use `true_regnum' to find out;
6359
   it will return -1 if the pseudo is in memory and the hard register number if
6360
   it is in a register.
6361
 
6362
   These macros should not be used in the case where a particular class of
6363
   registers can only be copied to memory and not to another class of
6364
   registers.  In that case, secondary reload registers are not needed and
6365
   would not be helpful.  Instead, a stack location must be used to perform the
6366
   copy and the `movM' pattern should use memory as an intermediate storage.
6367
   This case often occurs between floating-point and general registers.  */
6368
 
6369
enum reg_class
6370
frv_secondary_reload_class (enum reg_class rclass,
6371
                            enum machine_mode mode ATTRIBUTE_UNUSED,
6372
                            rtx x)
6373
{
6374
  enum reg_class ret;
6375
 
6376
  switch (rclass)
6377
    {
6378
    default:
6379
      ret = NO_REGS;
6380
      break;
6381
 
6382
      /* Accumulators/Accumulator guard registers need to go through floating
6383
         point registers.  */
6384
    case QUAD_REGS:
6385
    case GPR_REGS:
6386
      ret = NO_REGS;
6387
      if (x && GET_CODE (x) == REG)
6388
        {
6389
          int regno = REGNO (x);
6390
 
6391
          if (ACC_P (regno) || ACCG_P (regno))
6392
            ret = FPR_REGS;
6393
        }
6394
      break;
6395
 
6396
      /* Nonzero constants should be loaded into an FPR through a GPR.  */
6397
    case QUAD_FPR_REGS:
6398
      if (x && CONSTANT_P (x) && !ZERO_P (x))
6399
        ret = GPR_REGS;
6400
      else
6401
        ret = NO_REGS;
6402
      break;
6403
 
6404
      /* All of these types need gpr registers.  */
6405
    case ICC_REGS:
6406
    case FCC_REGS:
6407
    case CC_REGS:
6408
    case ICR_REGS:
6409
    case FCR_REGS:
6410
    case CR_REGS:
6411
    case LCR_REG:
6412
    case LR_REG:
6413
      ret = GPR_REGS;
6414
      break;
6415
 
6416
      /* The accumulators need fpr registers.  */
6417
    case QUAD_ACC_REGS:
6418
    case ACCG_REGS:
6419
      ret = FPR_REGS;
6420
      break;
6421
    }
6422
 
6423
  return ret;
6424
}
6425
 
6426
/* This hook exists to catch the case where secondary_reload_class() is
6427
   called from init_reg_autoinc() in regclass.c - before the reload optabs
6428
   have been initialised.  */
6429
 
6430
static reg_class_t
6431
frv_secondary_reload (bool in_p, rtx x, reg_class_t reload_class_i,
6432
                      enum machine_mode reload_mode,
6433
                      secondary_reload_info * sri)
6434
{
6435
  enum reg_class rclass = NO_REGS;
6436
  enum reg_class reload_class = (enum reg_class) reload_class_i;
6437
 
6438
  if (sri->prev_sri && sri->prev_sri->t_icode != CODE_FOR_nothing)
6439
    {
6440
      sri->icode = sri->prev_sri->t_icode;
6441
      return NO_REGS;
6442
    }
6443
 
6444
  rclass = frv_secondary_reload_class (reload_class, reload_mode, x);
6445
 
6446
  if (rclass != NO_REGS)
6447
    {
6448
      enum insn_code icode
6449
        = direct_optab_handler (in_p ? reload_in_optab : reload_out_optab,
6450
                                reload_mode);
6451
      if (icode == 0)
6452
        {
6453
          /* This happens when then the reload_[in|out]_optabs have
6454
             not been initialised.  */
6455
          sri->t_icode = CODE_FOR_nothing;
6456
          return rclass;
6457
        }
6458
    }
6459
 
6460
  /* Fall back to the default secondary reload handler.  */
6461
  return default_secondary_reload (in_p, x, reload_class, reload_mode, sri);
6462
 
6463
}
6464
 
6465
/* Worker function for TARGET_CLASS_LIKELY_SPILLED_P.  */
6466
 
6467
static bool
6468
frv_class_likely_spilled_p (reg_class_t rclass)
6469
{
6470
  switch (rclass)
6471
    {
6472
    default:
6473
      break;
6474
 
6475
    case GR8_REGS:
6476
    case GR9_REGS:
6477
    case GR89_REGS:
6478
    case FDPIC_FPTR_REGS:
6479
    case FDPIC_REGS:
6480
    case ICC_REGS:
6481
    case FCC_REGS:
6482
    case CC_REGS:
6483
    case ICR_REGS:
6484
    case FCR_REGS:
6485
    case CR_REGS:
6486
    case LCR_REG:
6487
    case LR_REG:
6488
    case SPR_REGS:
6489
    case QUAD_ACC_REGS:
6490
    case ACCG_REGS:
6491
      return true;
6492
    }
6493
 
6494
  return false;
6495
}
6496
 
6497
 
6498
/* An expression for the alignment of a structure field FIELD if the
6499
   alignment computed in the usual way is COMPUTED.  GCC uses this
6500
   value instead of the value in `BIGGEST_ALIGNMENT' or
6501
   `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only.  */
6502
 
6503
/* The definition type of the bit field data is either char, short, long or
6504
   long long. The maximum bit size is the number of bits of its own type.
6505
 
6506
   The bit field data is assigned to a storage unit that has an adequate size
6507
   for bit field data retention and is located at the smallest address.
6508
 
6509
   Consecutive bit field data are packed at consecutive bits having the same
6510
   storage unit, with regard to the type, beginning with the MSB and continuing
6511
   toward the LSB.
6512
 
6513
   If a field to be assigned lies over a bit field type boundary, its
6514
   assignment is completed by aligning it with a boundary suitable for the
6515
   type.
6516
 
6517
   When a bit field having a bit length of 0 is declared, it is forcibly
6518
   assigned to the next storage unit.
6519
 
6520
   e.g)
6521
        struct {
6522
                int     a:2;
6523
                int     b:6;
6524
                char    c:4;
6525
                int     d:10;
6526
                int      :0;
6527
                int     f:2;
6528
        } x;
6529
 
6530
                +0        +1        +2        +3
6531
        &x      00000000  00000000  00000000  00000000
6532
                MLM----L
6533
                a    b
6534
        &x+4    00000000  00000000  00000000  00000000
6535
                M--L
6536
                c
6537
        &x+8    00000000  00000000  00000000  00000000
6538
                M----------L
6539
                d
6540
        &x+12   00000000  00000000  00000000  00000000
6541
                ML
6542
                f
6543
*/
6544
 
6545
int
6546
frv_adjust_field_align (tree field, int computed)
6547
{
6548
  /* Make sure that the bitfield is not wider than the type.  */
6549
  if (DECL_BIT_FIELD (field)
6550
      && !DECL_ARTIFICIAL (field))
6551
    {
6552
      tree parent = DECL_CONTEXT (field);
6553
      tree prev = NULL_TREE;
6554
      tree cur;
6555
 
6556
      for (cur = TYPE_FIELDS (parent); cur && cur != field; cur = DECL_CHAIN (cur))
6557
        {
6558
          if (TREE_CODE (cur) != FIELD_DECL)
6559
            continue;
6560
 
6561
          prev = cur;
6562
        }
6563
 
6564
      gcc_assert (cur);
6565
 
6566
      /* If this isn't a :0 field and if the previous element is a bitfield
6567
         also, see if the type is different, if so, we will need to align the
6568
         bit-field to the next boundary.  */
6569
      if (prev
6570
          && ! DECL_PACKED (field)
6571
          && ! integer_zerop (DECL_SIZE (field))
6572
          && DECL_BIT_FIELD_TYPE (field) != DECL_BIT_FIELD_TYPE (prev))
6573
        {
6574
          int prev_align = TYPE_ALIGN (TREE_TYPE (prev));
6575
          int cur_align  = TYPE_ALIGN (TREE_TYPE (field));
6576
          computed = (prev_align > cur_align) ? prev_align : cur_align;
6577
        }
6578
    }
6579
 
6580
  return computed;
6581
}
6582
 
6583
 
6584
/* A C expression that is nonzero if it is permissible to store a value of mode
6585
   MODE in hard register number REGNO (or in several registers starting with
6586
   that one).  For a machine where all registers are equivalent, a suitable
6587
   definition is
6588
 
6589
        #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
6590
 
6591
   It is not necessary for this macro to check for the numbers of fixed
6592
   registers, because the allocation mechanism considers them to be always
6593
   occupied.
6594
 
6595
   On some machines, double-precision values must be kept in even/odd register
6596
   pairs.  The way to implement that is to define this macro to reject odd
6597
   register numbers for such modes.
6598
 
6599
   The minimum requirement for a mode to be OK in a register is that the
6600
   `movMODE' instruction pattern support moves between the register and any
6601
   other hard register for which the mode is OK; and that moving a value into
6602
   the register and back out not alter it.
6603
 
6604
   Since the same instruction used to move `SImode' will work for all narrower
6605
   integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
6606
   to distinguish between these modes, provided you define patterns `movhi',
6607
   etc., to take advantage of this.  This is useful because of the interaction
6608
   between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
6609
   all integer modes to be tieable.
6610
 
6611
   Many machines have special registers for floating point arithmetic.  Often
6612
   people assume that floating point machine modes are allowed only in floating
6613
   point registers.  This is not true.  Any registers that can hold integers
6614
   can safely *hold* a floating point machine mode, whether or not floating
6615
   arithmetic can be done on it in those registers.  Integer move instructions
6616
   can be used to move the values.
6617
 
6618
   On some machines, though, the converse is true: fixed-point machine modes
6619
   may not go in floating registers.  This is true if the floating registers
6620
   normalize any value stored in them, because storing a non-floating value
6621
   there would garble it.  In this case, `HARD_REGNO_MODE_OK' should reject
6622
   fixed-point machine modes in floating registers.  But if the floating
6623
   registers do not automatically normalize, if you can store any bit pattern
6624
   in one and retrieve it unchanged without a trap, then any machine mode may
6625
   go in a floating register, so you can define this macro to say so.
6626
 
6627
   The primary significance of special floating registers is rather that they
6628
   are the registers acceptable in floating point arithmetic instructions.
6629
   However, this is of no concern to `HARD_REGNO_MODE_OK'.  You handle it by
6630
   writing the proper constraints for those instructions.
6631
 
6632
   On some machines, the floating registers are especially slow to access, so
6633
   that it is better to store a value in a stack frame than in such a register
6634
   if floating point arithmetic is not being done.  As long as the floating
6635
   registers are not in class `GENERAL_REGS', they will not be used unless some
6636
   pattern's constraint asks for one.  */
6637
 
6638
int
6639
frv_hard_regno_mode_ok (int regno, enum machine_mode mode)
6640
{
6641
  int base;
6642
  int mask;
6643
 
6644
  switch (mode)
6645
    {
6646
    case CCmode:
6647
    case CC_UNSmode:
6648
    case CC_NZmode:
6649
      return ICC_P (regno) || GPR_P (regno);
6650
 
6651
    case CC_CCRmode:
6652
      return CR_P (regno) || GPR_P (regno);
6653
 
6654
    case CC_FPmode:
6655
      return FCC_P (regno) || GPR_P (regno);
6656
 
6657
    default:
6658
      break;
6659
    }
6660
 
6661
  /* Set BASE to the first register in REGNO's class.  Set MASK to the
6662
     bits that must be clear in (REGNO - BASE) for the register to be
6663
     well-aligned.  */
6664
  if (INTEGRAL_MODE_P (mode) || FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode))
6665
    {
6666
      if (ACCG_P (regno))
6667
        {
6668
          /* ACCGs store one byte.  Two-byte quantities must start in
6669
             even-numbered registers, four-byte ones in registers whose
6670
             numbers are divisible by four, and so on.  */
6671
          base = ACCG_FIRST;
6672
          mask = GET_MODE_SIZE (mode) - 1;
6673
        }
6674
      else
6675
        {
6676
           /* The other registers store one word.  */
6677
          if (GPR_P (regno) || regno == AP_FIRST)
6678
            base = GPR_FIRST;
6679
 
6680
          else if (FPR_P (regno))
6681
            base = FPR_FIRST;
6682
 
6683
          else if (ACC_P (regno))
6684
            base = ACC_FIRST;
6685
 
6686
          else if (SPR_P (regno))
6687
            return mode == SImode;
6688
 
6689
          /* Fill in the table.  */
6690
          else
6691
            return 0;
6692
 
6693
          /* Anything smaller than an SI is OK in any word-sized register.  */
6694
          if (GET_MODE_SIZE (mode) < 4)
6695
            return 1;
6696
 
6697
          mask = (GET_MODE_SIZE (mode) / 4) - 1;
6698
        }
6699
      return (((regno - base) & mask) == 0);
6700
    }
6701
 
6702
  return 0;
6703
}
6704
 
6705
 
6706
/* A C expression for the number of consecutive hard registers, starting at
6707
   register number REGNO, required to hold a value of mode MODE.
6708
 
6709
   On a machine where all registers are exactly one word, a suitable definition
6710
   of this macro is
6711
 
6712
        #define HARD_REGNO_NREGS(REGNO, MODE)            \
6713
           ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1)  \
6714
            / UNITS_PER_WORD))  */
6715
 
6716
/* On the FRV, make the CC_FP mode take 3 words in the integer registers, so
6717
   that we can build the appropriate instructions to properly reload the
6718
   values.  Also, make the byte-sized accumulator guards use one guard
6719
   for each byte.  */
6720
 
6721
int
6722
frv_hard_regno_nregs (int regno, enum machine_mode mode)
6723
{
6724
  if (ACCG_P (regno))
6725
    return GET_MODE_SIZE (mode);
6726
  else
6727
    return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6728
}
6729
 
6730
 
6731
/* A C expression for the maximum number of consecutive registers of
6732
   class RCLASS needed to hold a value of mode MODE.
6733
 
6734
   This is closely related to the macro `HARD_REGNO_NREGS'.  In fact, the value
6735
   of the macro `CLASS_MAX_NREGS (RCLASS, MODE)' should be the maximum value of
6736
   `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class RCLASS.
6737
 
6738
   This macro helps control the handling of multiple-word values in
6739
   the reload pass.
6740
 
6741
   This declaration is required.  */
6742
 
6743
int
6744
frv_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
6745
{
6746
  if (rclass == ACCG_REGS)
6747
    /* An N-byte value requires N accumulator guards.  */
6748
    return GET_MODE_SIZE (mode);
6749
  else
6750
    return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6751
}
6752
 
6753
 
6754
/* A C expression that is nonzero if X is a legitimate constant for an
6755
   immediate operand on the target machine.  You can assume that X satisfies
6756
   `CONSTANT_P', so you need not check this.  In fact, `1' is a suitable
6757
   definition for this macro on machines where anything `CONSTANT_P' is valid.  */
6758
 
6759
static bool
6760
frv_legitimate_constant_p (enum machine_mode mode, rtx x)
6761
{
6762
  /* frv_cannot_force_const_mem always returns true for FDPIC.  This
6763
     means that the move expanders will be expected to deal with most
6764
     kinds of constant, regardless of what we return here.
6765
 
6766
     However, among its other duties, frv_legitimate_constant_p decides whether
6767
     a constant can be entered into reg_equiv_constant[].  If we return true,
6768
     reload can create new instances of the constant whenever it likes.
6769
 
6770
     The idea is therefore to accept as many constants as possible (to give
6771
     reload more freedom) while rejecting constants that can only be created
6772
     at certain times.  In particular, anything with a symbolic component will
6773
     require use of the pseudo FDPIC register, which is only available before
6774
     reload.  */
6775
  if (TARGET_FDPIC)
6776
    return LEGITIMATE_PIC_OPERAND_P (x);
6777
 
6778
  /* All of the integer constants are ok.  */
6779
  if (GET_CODE (x) != CONST_DOUBLE)
6780
    return TRUE;
6781
 
6782
  /* double integer constants are ok.  */
6783
  if (GET_MODE (x) == VOIDmode || mode == DImode)
6784
    return TRUE;
6785
 
6786
  /* 0 is always ok.  */
6787
  if (x == CONST0_RTX (mode))
6788
    return TRUE;
6789
 
6790
  /* If floating point is just emulated, allow any constant, since it will be
6791
     constructed in the GPRs.  */
6792
  if (!TARGET_HAS_FPRS)
6793
    return TRUE;
6794
 
6795
  if (mode == DFmode && !TARGET_DOUBLE)
6796
    return TRUE;
6797
 
6798
  /* Otherwise store the constant away and do a load.  */
6799
  return FALSE;
6800
}
6801
 
6802
/* Implement SELECT_CC_MODE.  Choose CC_FP for floating-point comparisons,
6803
   CC_NZ for comparisons against zero in which a single Z or N flag test
6804
   is enough, CC_UNS for other unsigned comparisons, and CC for other
6805
   signed comparisons.  */
6806
 
6807
enum machine_mode
6808
frv_select_cc_mode (enum rtx_code code, rtx x, rtx y)
6809
{
6810
  if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
6811
    return CC_FPmode;
6812
 
6813
  switch (code)
6814
    {
6815
    case EQ:
6816
    case NE:
6817
    case LT:
6818
    case GE:
6819
      return y == const0_rtx ? CC_NZmode : CCmode;
6820
 
6821
    case GTU:
6822
    case GEU:
6823
    case LTU:
6824
    case LEU:
6825
      return y == const0_rtx ? CC_NZmode : CC_UNSmode;
6826
 
6827
    default:
6828
      return CCmode;
6829
    }
6830
}
6831
 
6832
 
6833
/* Worker function for TARGET_REGISTER_MOVE_COST.  */
6834
 
6835
#define HIGH_COST 40
6836
#define MEDIUM_COST 3
6837
#define LOW_COST 1
6838
 
6839
static int
6840
frv_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
6841
                        reg_class_t from, reg_class_t to)
6842
{
6843
  switch (from)
6844
    {
6845
    default:
6846
      break;
6847
 
6848
    case QUAD_REGS:
6849
    case GPR_REGS:
6850
    case GR8_REGS:
6851
    case GR9_REGS:
6852
    case GR89_REGS:
6853
    case FDPIC_REGS:
6854
    case FDPIC_FPTR_REGS:
6855
    case FDPIC_CALL_REGS:
6856
 
6857
      switch (to)
6858
        {
6859
        default:
6860
          break;
6861
 
6862
        case QUAD_REGS:
6863
        case GPR_REGS:
6864
        case GR8_REGS:
6865
        case GR9_REGS:
6866
        case GR89_REGS:
6867
        case FDPIC_REGS:
6868
        case FDPIC_FPTR_REGS:
6869
        case FDPIC_CALL_REGS:
6870
 
6871
          return LOW_COST;
6872
 
6873
        case FPR_REGS:
6874
          return LOW_COST;
6875
 
6876
        case LCR_REG:
6877
        case LR_REG:
6878
        case SPR_REGS:
6879
          return LOW_COST;
6880
        }
6881
 
6882
    case QUAD_FPR_REGS:
6883
      switch (to)
6884
        {
6885
        default:
6886
          break;
6887
 
6888
        case QUAD_REGS:
6889
        case GPR_REGS:
6890
        case GR8_REGS:
6891
        case GR9_REGS:
6892
        case GR89_REGS:
6893
        case FDPIC_REGS:
6894
        case FDPIC_FPTR_REGS:
6895
        case FDPIC_CALL_REGS:
6896
 
6897
        case QUAD_ACC_REGS:
6898
        case ACCG_REGS:
6899
          return MEDIUM_COST;
6900
 
6901
        case QUAD_FPR_REGS:
6902
          return LOW_COST;
6903
        }
6904
 
6905
    case LCR_REG:
6906
    case LR_REG:
6907
    case SPR_REGS:
6908
      switch (to)
6909
        {
6910
        default:
6911
          break;
6912
 
6913
        case QUAD_REGS:
6914
        case GPR_REGS:
6915
        case GR8_REGS:
6916
        case GR9_REGS:
6917
        case GR89_REGS:
6918
        case FDPIC_REGS:
6919
        case FDPIC_FPTR_REGS:
6920
        case FDPIC_CALL_REGS:
6921
 
6922
          return MEDIUM_COST;
6923
        }
6924
 
6925
    case QUAD_ACC_REGS:
6926
    case ACCG_REGS:
6927
      switch (to)
6928
        {
6929
        default:
6930
          break;
6931
 
6932
        case QUAD_FPR_REGS:
6933
          return MEDIUM_COST;
6934
 
6935
        }
6936
    }
6937
 
6938
  return HIGH_COST;
6939
}
6940
 
6941
/* Worker function for TARGET_MEMORY_MOVE_COST.  */
6942
 
6943
static int
6944
frv_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
6945
                      reg_class_t rclass ATTRIBUTE_UNUSED,
6946
                      bool in ATTRIBUTE_UNUSED)
6947
{
6948
  return 4;
6949
}
6950
 
6951
 
6952
/* Implementation of TARGET_ASM_INTEGER.  In the FRV case we need to
6953
   use ".picptr" to generate safe relocations for PIC code.  We also
6954
   need a fixup entry for aligned (non-debugging) code.  */
6955
 
6956
static bool
6957
frv_assemble_integer (rtx value, unsigned int size, int aligned_p)
6958
{
6959
  if ((flag_pic || TARGET_FDPIC) && size == UNITS_PER_WORD)
6960
    {
6961
      if (GET_CODE (value) == CONST
6962
          || GET_CODE (value) == SYMBOL_REF
6963
          || GET_CODE (value) == LABEL_REF)
6964
        {
6965
          if (TARGET_FDPIC && GET_CODE (value) == SYMBOL_REF
6966
              && SYMBOL_REF_FUNCTION_P (value))
6967
            {
6968
              fputs ("\t.picptr\tfuncdesc(", asm_out_file);
6969
              output_addr_const (asm_out_file, value);
6970
              fputs (")\n", asm_out_file);
6971
              return true;
6972
            }
6973
          else if (TARGET_FDPIC && GET_CODE (value) == CONST
6974
                   && frv_function_symbol_referenced_p (value))
6975
            return false;
6976
          if (aligned_p && !TARGET_FDPIC)
6977
            {
6978
              static int label_num = 0;
6979
              char buf[256];
6980
              const char *p;
6981
 
6982
              ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", label_num++);
6983
              p = (* targetm.strip_name_encoding) (buf);
6984
 
6985
              fprintf (asm_out_file, "%s:\n", p);
6986
              fprintf (asm_out_file, "%s\n", FIXUP_SECTION_ASM_OP);
6987
              fprintf (asm_out_file, "\t.picptr\t%s\n", p);
6988
              fprintf (asm_out_file, "\t.previous\n");
6989
            }
6990
          assemble_integer_with_op ("\t.picptr\t", value);
6991
          return true;
6992
        }
6993
      if (!aligned_p)
6994
        {
6995
          /* We've set the unaligned SI op to NULL, so we always have to
6996
             handle the unaligned case here.  */
6997
          assemble_integer_with_op ("\t.4byte\t", value);
6998
          return true;
6999
        }
7000
    }
7001
  return default_assemble_integer (value, size, aligned_p);
7002
}
7003
 
7004
/* Function to set up the backend function structure.  */
7005
 
7006
static struct machine_function *
7007
frv_init_machine_status (void)
7008
{
7009
  return ggc_alloc_cleared_machine_function ();
7010
}
7011
 
7012
/* Implement TARGET_SCHED_ISSUE_RATE.  */
7013
 
7014
int
7015
frv_issue_rate (void)
7016
{
7017
  if (!TARGET_PACK)
7018
    return 1;
7019
 
7020
  switch (frv_cpu_type)
7021
    {
7022
    default:
7023
    case FRV_CPU_FR300:
7024
    case FRV_CPU_SIMPLE:
7025
      return 1;
7026
 
7027
    case FRV_CPU_FR400:
7028
    case FRV_CPU_FR405:
7029
    case FRV_CPU_FR450:
7030
      return 2;
7031
 
7032
    case FRV_CPU_GENERIC:
7033
    case FRV_CPU_FR500:
7034
    case FRV_CPU_TOMCAT:
7035
      return 4;
7036
 
7037
    case FRV_CPU_FR550:
7038
      return 8;
7039
    }
7040
}
7041
 
7042
/* A for_each_rtx callback.  If X refers to an accumulator, return
7043
   ACC_GROUP_ODD if the bit 2 of the register number is set and
7044
   ACC_GROUP_EVEN if it is clear.  Return 0 (ACC_GROUP_NONE)
7045
   otherwise.  */
7046
 
7047
static int
7048
frv_acc_group_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
7049
{
7050
  if (REG_P (*x))
7051
    {
7052
      if (ACC_P (REGNO (*x)))
7053
        return (REGNO (*x) - ACC_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN;
7054
      if (ACCG_P (REGNO (*x)))
7055
        return (REGNO (*x) - ACCG_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN;
7056
    }
7057
  return 0;
7058
}
7059
 
7060
/* Return the value of INSN's acc_group attribute.  */
7061
 
7062
int
7063
frv_acc_group (rtx insn)
7064
{
7065
  /* This distinction only applies to the FR550 packing constraints.  */
7066
  if (frv_cpu_type != FRV_CPU_FR550)
7067
    return ACC_GROUP_NONE;
7068
  return for_each_rtx (&PATTERN (insn), frv_acc_group_1, 0);
7069
}
7070
 
7071
/* Return the index of the DFA unit in FRV_UNIT_NAMES[] that instruction
7072
   INSN will try to claim first.  Since this value depends only on the
7073
   type attribute, we can cache the results in FRV_TYPE_TO_UNIT[].  */
7074
 
7075
static unsigned int
7076
frv_insn_unit (rtx insn)
7077
{
7078
  enum attr_type type;
7079
 
7080
  type = get_attr_type (insn);
7081
  if (frv_type_to_unit[type] == ARRAY_SIZE (frv_unit_codes))
7082
    {
7083
      /* We haven't seen this type of instruction before.  */
7084
      state_t state;
7085
      unsigned int unit;
7086
 
7087
      /* Issue the instruction on its own to see which unit it prefers.  */
7088
      state = alloca (state_size ());
7089
      state_reset (state);
7090
      state_transition (state, insn);
7091
 
7092
      /* Find out which unit was taken.  */
7093
      for (unit = 0; unit < ARRAY_SIZE (frv_unit_codes); unit++)
7094
        if (cpu_unit_reservation_p (state, frv_unit_codes[unit]))
7095
          break;
7096
 
7097
      gcc_assert (unit != ARRAY_SIZE (frv_unit_codes));
7098
 
7099
      frv_type_to_unit[type] = unit;
7100
    }
7101
  return frv_type_to_unit[type];
7102
}
7103
 
7104
/* Return true if INSN issues to a branch unit.  */
7105
 
7106
static bool
7107
frv_issues_to_branch_unit_p (rtx insn)
7108
{
7109
  return frv_unit_groups[frv_insn_unit (insn)] == GROUP_B;
7110
}
7111
 
7112
/* The instructions in the packet, partitioned into groups.  */
7113
struct frv_packet_group {
7114
  /* How many instructions in the packet belong to this group.  */
7115
  unsigned int num_insns;
7116
 
7117
  /* A list of the instructions that belong to this group, in the order
7118
     they appear in the rtl stream.  */
7119
  rtx insns[ARRAY_SIZE (frv_unit_codes)];
7120
 
7121
  /* The contents of INSNS after they have been sorted into the correct
7122
     assembly-language order.  Element X issues to unit X.  The list may
7123
     contain extra nops.  */
7124
  rtx sorted[ARRAY_SIZE (frv_unit_codes)];
7125
 
7126
  /* The member of frv_nops[] to use in sorted[].  */
7127
  rtx nop;
7128
};
7129
 
7130
/* The current state of the packing pass, implemented by frv_pack_insns.  */
7131
static struct {
7132
  /* The state of the pipeline DFA.  */
7133
  state_t dfa_state;
7134
 
7135
  /* Which hardware registers are set within the current packet,
7136
     and the conditions under which they are set.  */
7137
  regstate_t regstate[FIRST_PSEUDO_REGISTER];
7138
 
7139
  /* The memory locations that have been modified so far in this
7140
     packet.  MEM is the memref and COND is the regstate_t condition
7141
     under which it is set.  */
7142
  struct {
7143
    rtx mem;
7144
    regstate_t cond;
7145
  } mems[2];
7146
 
7147
  /* The number of valid entries in MEMS.  The value is larger than
7148
     ARRAY_SIZE (mems) if there were too many mems to record.  */
7149
  unsigned int num_mems;
7150
 
7151
  /* The maximum number of instructions that can be packed together.  */
7152
  unsigned int issue_rate;
7153
 
7154
  /* The instructions in the packet, partitioned into groups.  */
7155
  struct frv_packet_group groups[NUM_GROUPS];
7156
 
7157
  /* The instructions that make up the current packet.  */
7158
  rtx insns[ARRAY_SIZE (frv_unit_codes)];
7159
  unsigned int num_insns;
7160
} frv_packet;
7161
 
7162
/* Return the regstate_t flags for the given COND_EXEC condition.
7163
   Abort if the condition isn't in the right form.  */
7164
 
7165
static int
7166
frv_cond_flags (rtx cond)
7167
{
7168
  gcc_assert ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
7169
              && GET_CODE (XEXP (cond, 0)) == REG
7170
              && CR_P (REGNO (XEXP (cond, 0)))
7171
              && XEXP (cond, 1) == const0_rtx);
7172
  return ((REGNO (XEXP (cond, 0)) - CR_FIRST)
7173
          | (GET_CODE (cond) == NE
7174
             ? REGSTATE_IF_TRUE
7175
             : REGSTATE_IF_FALSE));
7176
}
7177
 
7178
 
7179
/* Return true if something accessed under condition COND2 can
7180
   conflict with something written under condition COND1.  */
7181
 
7182
static bool
7183
frv_regstate_conflict_p (regstate_t cond1, regstate_t cond2)
7184
{
7185
  /* If either reference was unconditional, we have a conflict.  */
7186
  if ((cond1 & REGSTATE_IF_EITHER) == 0
7187
      || (cond2 & REGSTATE_IF_EITHER) == 0)
7188
    return true;
7189
 
7190
  /* The references might conflict if they were controlled by
7191
     different CRs.  */
7192
  if ((cond1 & REGSTATE_CC_MASK) != (cond2 & REGSTATE_CC_MASK))
7193
    return true;
7194
 
7195
  /* They definitely conflict if they are controlled by the
7196
     same condition.  */
7197
  if ((cond1 & cond2 & REGSTATE_IF_EITHER) != 0)
7198
    return true;
7199
 
7200
  return false;
7201
}
7202
 
7203
 
7204
/* A for_each_rtx callback.  Return 1 if *X depends on an instruction in
7205
   the current packet.  DATA points to a regstate_t that describes the
7206
   condition under which *X might be set or used.  */
7207
 
7208
static int
7209
frv_registers_conflict_p_1 (rtx *x, void *data)
7210
{
7211
  unsigned int regno, i;
7212
  regstate_t cond;
7213
 
7214
  cond = *(regstate_t *) data;
7215
 
7216
  if (GET_CODE (*x) == REG)
7217
    FOR_EACH_REGNO (regno, *x)
7218
      if ((frv_packet.regstate[regno] & REGSTATE_MODIFIED) != 0)
7219
        if (frv_regstate_conflict_p (frv_packet.regstate[regno], cond))
7220
          return 1;
7221
 
7222
  if (GET_CODE (*x) == MEM)
7223
    {
7224
      /* If we ran out of memory slots, assume a conflict.  */
7225
      if (frv_packet.num_mems > ARRAY_SIZE (frv_packet.mems))
7226
        return 1;
7227
 
7228
      /* Check for output or true dependencies with earlier MEMs.  */
7229
      for (i = 0; i < frv_packet.num_mems; i++)
7230
        if (frv_regstate_conflict_p (frv_packet.mems[i].cond, cond))
7231
          {
7232
            if (true_dependence (frv_packet.mems[i].mem, VOIDmode, *x))
7233
              return 1;
7234
 
7235
            if (output_dependence (frv_packet.mems[i].mem, *x))
7236
              return 1;
7237
          }
7238
    }
7239
 
7240
  /* The return values of calls aren't significant: they describe
7241
     the effect of the call as a whole, not of the insn itself.  */
7242
  if (GET_CODE (*x) == SET && GET_CODE (SET_SRC (*x)) == CALL)
7243
    {
7244
      if (for_each_rtx (&SET_SRC (*x), frv_registers_conflict_p_1, data))
7245
        return 1;
7246
      return -1;
7247
    }
7248
 
7249
  /* Check subexpressions.  */
7250
  return 0;
7251
}
7252
 
7253
 
7254
/* Return true if something in X might depend on an instruction
7255
   in the current packet.  */
7256
 
7257
static bool
7258
frv_registers_conflict_p (rtx x)
7259
{
7260
  regstate_t flags;
7261
 
7262
  flags = 0;
7263
  if (GET_CODE (x) == COND_EXEC)
7264
    {
7265
      if (for_each_rtx (&XEXP (x, 0), frv_registers_conflict_p_1, &flags))
7266
        return true;
7267
 
7268
      flags |= frv_cond_flags (XEXP (x, 0));
7269
      x = XEXP (x, 1);
7270
    }
7271
  return for_each_rtx (&x, frv_registers_conflict_p_1, &flags);
7272
}
7273
 
7274
 
7275
/* A note_stores callback.  DATA points to the regstate_t condition
7276
   under which X is modified.  Update FRV_PACKET accordingly.  */
7277
 
7278
static void
7279
frv_registers_update_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7280
{
7281
  unsigned int regno;
7282
 
7283
  if (GET_CODE (x) == REG)
7284
    FOR_EACH_REGNO (regno, x)
7285
      frv_packet.regstate[regno] |= *(regstate_t *) data;
7286
 
7287
  if (GET_CODE (x) == MEM)
7288
    {
7289
      if (frv_packet.num_mems < ARRAY_SIZE (frv_packet.mems))
7290
        {
7291
          frv_packet.mems[frv_packet.num_mems].mem = x;
7292
          frv_packet.mems[frv_packet.num_mems].cond = *(regstate_t *) data;
7293
        }
7294
      frv_packet.num_mems++;
7295
    }
7296
}
7297
 
7298
 
7299
/* Update the register state information for an instruction whose
7300
   body is X.  */
7301
 
7302
static void
7303
frv_registers_update (rtx x)
7304
{
7305
  regstate_t flags;
7306
 
7307
  flags = REGSTATE_MODIFIED;
7308
  if (GET_CODE (x) == COND_EXEC)
7309
    {
7310
      flags |= frv_cond_flags (XEXP (x, 0));
7311
      x = XEXP (x, 1);
7312
    }
7313
  note_stores (x, frv_registers_update_1, &flags);
7314
}
7315
 
7316
 
7317
/* Initialize frv_packet for the start of a new packet.  */
7318
 
7319
static void
7320
frv_start_packet (void)
7321
{
7322
  enum frv_insn_group group;
7323
 
7324
  memset (frv_packet.regstate, 0, sizeof (frv_packet.regstate));
7325
  frv_packet.num_mems = 0;
7326
  frv_packet.num_insns = 0;
7327
  for (group =  GROUP_I; group < NUM_GROUPS;
7328
       group = (enum frv_insn_group) (group + 1))
7329
    frv_packet.groups[group].num_insns = 0;
7330
}
7331
 
7332
 
7333
/* Likewise for the start of a new basic block.  */
7334
 
7335
static void
7336
frv_start_packet_block (void)
7337
{
7338
  state_reset (frv_packet.dfa_state);
7339
  frv_start_packet ();
7340
}
7341
 
7342
 
7343
/* Finish the current packet, if any, and start a new one.  Call
7344
   HANDLE_PACKET with FRV_PACKET describing the completed packet.  */
7345
 
7346
static void
7347
frv_finish_packet (void (*handle_packet) (void))
7348
{
7349
  if (frv_packet.num_insns > 0)
7350
    {
7351
      handle_packet ();
7352
      state_transition (frv_packet.dfa_state, 0);
7353
      frv_start_packet ();
7354
    }
7355
}
7356
 
7357
 
7358
/* Return true if INSN can be added to the current packet.  Update
7359
   the DFA state on success.  */
7360
 
7361
static bool
7362
frv_pack_insn_p (rtx insn)
7363
{
7364
  /* See if the packet is already as long as it can be.  */
7365
  if (frv_packet.num_insns == frv_packet.issue_rate)
7366
    return false;
7367
 
7368
  /* If the scheduler thought that an instruction should start a packet,
7369
     it's usually a good idea to believe it.  It knows much more about
7370
     the latencies than we do.
7371
 
7372
     There are some exceptions though:
7373
 
7374
       - Conditional instructions are scheduled on the assumption that
7375
         they will be executed.  This is usually a good thing, since it
7376
         tends to avoid unnecessary stalls in the conditional code.
7377
         But we want to pack conditional instructions as tightly as
7378
         possible, in order to optimize the case where they aren't
7379
         executed.
7380
 
7381
       - The scheduler will always put branches on their own, even
7382
         if there's no real dependency.
7383
 
7384
       - There's no point putting a call in its own packet unless
7385
         we have to.  */
7386
  if (frv_packet.num_insns > 0
7387
      && GET_CODE (insn) == INSN
7388
      && GET_MODE (insn) == TImode
7389
      && GET_CODE (PATTERN (insn)) != COND_EXEC)
7390
    return false;
7391
 
7392
  /* Check for register conflicts.  Don't do this for setlo since any
7393
     conflict will be with the partnering sethi, with which it can
7394
     be packed.  */
7395
  if (get_attr_type (insn) != TYPE_SETLO)
7396
    if (frv_registers_conflict_p (PATTERN (insn)))
7397
      return false;
7398
 
7399
  return state_transition (frv_packet.dfa_state, insn) < 0;
7400
}
7401
 
7402
 
7403
/* Add instruction INSN to the current packet.  */
7404
 
7405
static void
7406
frv_add_insn_to_packet (rtx insn)
7407
{
7408
  struct frv_packet_group *packet_group;
7409
 
7410
  packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]];
7411
  packet_group->insns[packet_group->num_insns++] = insn;
7412
  frv_packet.insns[frv_packet.num_insns++] = insn;
7413
 
7414
  frv_registers_update (PATTERN (insn));
7415
}
7416
 
7417
 
7418
/* Insert INSN (a member of frv_nops[]) into the current packet.  If the
7419
   packet ends in a branch or call, insert the nop before it, otherwise
7420
   add to the end.  */
7421
 
7422
static void
7423
frv_insert_nop_in_packet (rtx insn)
7424
{
7425
  struct frv_packet_group *packet_group;
7426
  rtx last;
7427
 
7428
  packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]];
7429
  last = frv_packet.insns[frv_packet.num_insns - 1];
7430
  if (GET_CODE (last) != INSN)
7431
    {
7432
      insn = emit_insn_before (PATTERN (insn), last);
7433
      frv_packet.insns[frv_packet.num_insns - 1] = insn;
7434
      frv_packet.insns[frv_packet.num_insns++] = last;
7435
    }
7436
  else
7437
    {
7438
      insn = emit_insn_after (PATTERN (insn), last);
7439
      frv_packet.insns[frv_packet.num_insns++] = insn;
7440
    }
7441
  packet_group->insns[packet_group->num_insns++] = insn;
7442
}
7443
 
7444
 
7445
/* If packing is enabled, divide the instructions into packets and
7446
   return true.  Call HANDLE_PACKET for each complete packet.  */
7447
 
7448
static bool
7449
frv_for_each_packet (void (*handle_packet) (void))
7450
{
7451
  rtx insn, next_insn;
7452
 
7453
  frv_packet.issue_rate = frv_issue_rate ();
7454
 
7455
  /* Early exit if we don't want to pack insns.  */
7456
  if (!optimize
7457
      || !flag_schedule_insns_after_reload
7458
      || !TARGET_VLIW_BRANCH
7459
      || frv_packet.issue_rate == 1)
7460
    return false;
7461
 
7462
  /* Set up the initial packing state.  */
7463
  dfa_start ();
7464
  frv_packet.dfa_state = alloca (state_size ());
7465
 
7466
  frv_start_packet_block ();
7467
  for (insn = get_insns (); insn != 0; insn = next_insn)
7468
    {
7469
      enum rtx_code code;
7470
      bool eh_insn_p;
7471
 
7472
      code = GET_CODE (insn);
7473
      next_insn = NEXT_INSN (insn);
7474
 
7475
      if (code == CODE_LABEL)
7476
        {
7477
          frv_finish_packet (handle_packet);
7478
          frv_start_packet_block ();
7479
        }
7480
 
7481
      if (INSN_P (insn))
7482
        switch (GET_CODE (PATTERN (insn)))
7483
          {
7484
          case USE:
7485
          case CLOBBER:
7486
          case ADDR_VEC:
7487
          case ADDR_DIFF_VEC:
7488
            break;
7489
 
7490
          default:
7491
            /* Calls mustn't be packed on a TOMCAT.  */
7492
            if (GET_CODE (insn) == CALL_INSN && frv_cpu_type == FRV_CPU_TOMCAT)
7493
              frv_finish_packet (handle_packet);
7494
 
7495
            /* Since the last instruction in a packet determines the EH
7496
               region, any exception-throwing instruction must come at
7497
               the end of reordered packet.  Insns that issue to a
7498
               branch unit are bound to come last; for others it's
7499
               too hard to predict.  */
7500
            eh_insn_p = (find_reg_note (insn, REG_EH_REGION, NULL) != NULL);
7501
            if (eh_insn_p && !frv_issues_to_branch_unit_p (insn))
7502
              frv_finish_packet (handle_packet);
7503
 
7504
            /* Finish the current packet if we can't add INSN to it.
7505
               Simulate cycles until INSN is ready to issue.  */
7506
            if (!frv_pack_insn_p (insn))
7507
              {
7508
                frv_finish_packet (handle_packet);
7509
                while (!frv_pack_insn_p (insn))
7510
                  state_transition (frv_packet.dfa_state, 0);
7511
              }
7512
 
7513
            /* Add the instruction to the packet.  */
7514
            frv_add_insn_to_packet (insn);
7515
 
7516
            /* Calls and jumps end a packet, as do insns that throw
7517
               an exception.  */
7518
            if (code == CALL_INSN || code == JUMP_INSN || eh_insn_p)
7519
              frv_finish_packet (handle_packet);
7520
            break;
7521
          }
7522
    }
7523
  frv_finish_packet (handle_packet);
7524
  dfa_finish ();
7525
  return true;
7526
}
7527
 
7528
/* Subroutine of frv_sort_insn_group.  We are trying to sort
7529
   frv_packet.groups[GROUP].sorted[0...NUM_INSNS-1] into assembly
7530
   language order.  We have already picked a new position for
7531
   frv_packet.groups[GROUP].sorted[X] if bit X of ISSUED is set.
7532
   These instructions will occupy elements [0, LOWER_SLOT) and
7533
   [UPPER_SLOT, NUM_INSNS) of the final (sorted) array.  STATE is
7534
   the DFA state after issuing these instructions.
7535
 
7536
   Try filling elements [LOWER_SLOT, UPPER_SLOT) with every permutation
7537
   of the unused instructions.  Return true if one such permutation gives
7538
   a valid ordering, leaving the successful permutation in sorted[].
7539
   Do not modify sorted[] until a valid permutation is found.  */
7540
 
7541
static bool
7542
frv_sort_insn_group_1 (enum frv_insn_group group,
7543
                       unsigned int lower_slot, unsigned int upper_slot,
7544
                       unsigned int issued, unsigned int num_insns,
7545
                       state_t state)
7546
{
7547
  struct frv_packet_group *packet_group;
7548
  unsigned int i;
7549
  state_t test_state;
7550
  size_t dfa_size;
7551
  rtx insn;
7552
 
7553
  /* Early success if we've filled all the slots.  */
7554
  if (lower_slot == upper_slot)
7555
    return true;
7556
 
7557
  packet_group = &frv_packet.groups[group];
7558
  dfa_size = state_size ();
7559
  test_state = alloca (dfa_size);
7560
 
7561
  /* Try issuing each unused instruction.  */
7562
  for (i = num_insns - 1; i + 1 != 0; i--)
7563
    if (~issued & (1 << i))
7564
      {
7565
        insn = packet_group->sorted[i];
7566
        memcpy (test_state, state, dfa_size);
7567
        if (state_transition (test_state, insn) < 0
7568
            && cpu_unit_reservation_p (test_state,
7569
                                       NTH_UNIT (group, upper_slot - 1))
7570
            && frv_sort_insn_group_1 (group, lower_slot, upper_slot - 1,
7571
                                      issued | (1 << i), num_insns,
7572
                                      test_state))
7573
          {
7574
            packet_group->sorted[upper_slot - 1] = insn;
7575
            return true;
7576
          }
7577
      }
7578
 
7579
  return false;
7580
}
7581
 
7582
/* Compare two instructions by their frv_insn_unit.  */
7583
 
7584
static int
7585
frv_compare_insns (const void *first, const void *second)
7586
{
7587
  const rtx *const insn1 = (rtx const *) first,
7588
    *const insn2 = (rtx const *) second;
7589
  return frv_insn_unit (*insn1) - frv_insn_unit (*insn2);
7590
}
7591
 
7592
/* Copy frv_packet.groups[GROUP].insns[] to frv_packet.groups[GROUP].sorted[]
7593
   and sort it into assembly language order.  See frv.md for a description of
7594
   the algorithm.  */
7595
 
7596
static void
7597
frv_sort_insn_group (enum frv_insn_group group)
7598
{
7599
  struct frv_packet_group *packet_group;
7600
  unsigned int first, i, nop, max_unit, num_slots;
7601
  state_t state, test_state;
7602
  size_t dfa_size;
7603
 
7604
  packet_group = &frv_packet.groups[group];
7605
 
7606
  /* Assume no nop is needed.  */
7607
  packet_group->nop = 0;
7608
 
7609
  if (packet_group->num_insns == 0)
7610
    return;
7611
 
7612
  /* Copy insns[] to sorted[].  */
7613
  memcpy (packet_group->sorted, packet_group->insns,
7614
          sizeof (rtx) * packet_group->num_insns);
7615
 
7616
  /* Sort sorted[] by the unit that each insn tries to take first.  */
7617
  if (packet_group->num_insns > 1)
7618
    qsort (packet_group->sorted, packet_group->num_insns,
7619
           sizeof (rtx), frv_compare_insns);
7620
 
7621
  /* That's always enough for branch and control insns.  */
7622
  if (group == GROUP_B || group == GROUP_C)
7623
    return;
7624
 
7625
  dfa_size = state_size ();
7626
  state = alloca (dfa_size);
7627
  test_state = alloca (dfa_size);
7628
 
7629
  /* Find the highest FIRST such that sorted[0...FIRST-1] can issue
7630
     consecutively and such that the DFA takes unit X when sorted[X]
7631
     is added.  Set STATE to the new DFA state.  */
7632
  state_reset (test_state);
7633
  for (first = 0; first < packet_group->num_insns; first++)
7634
    {
7635
      memcpy (state, test_state, dfa_size);
7636
      if (state_transition (test_state, packet_group->sorted[first]) >= 0
7637
          || !cpu_unit_reservation_p (test_state, NTH_UNIT (group, first)))
7638
        break;
7639
    }
7640
 
7641
  /* If all the instructions issued in ascending order, we're done.  */
7642
  if (first == packet_group->num_insns)
7643
    return;
7644
 
7645
  /* Add nops to the end of sorted[] and try each permutation until
7646
     we find one that works.  */
7647
  for (nop = 0; nop < frv_num_nops; nop++)
7648
    {
7649
      max_unit = frv_insn_unit (frv_nops[nop]);
7650
      if (frv_unit_groups[max_unit] == group)
7651
        {
7652
          packet_group->nop = frv_nops[nop];
7653
          num_slots = UNIT_NUMBER (max_unit) + 1;
7654
          for (i = packet_group->num_insns; i < num_slots; i++)
7655
            packet_group->sorted[i] = frv_nops[nop];
7656
          if (frv_sort_insn_group_1 (group, first, num_slots,
7657
                                     (1 << first) - 1, num_slots, state))
7658
            return;
7659
        }
7660
    }
7661
  gcc_unreachable ();
7662
}
7663
 
7664
/* Sort the current packet into assembly-language order.  Set packing
7665
   flags as appropriate.  */
7666
 
7667
static void
7668
frv_reorder_packet (void)
7669
{
7670
  unsigned int cursor[NUM_GROUPS];
7671
  rtx insns[ARRAY_SIZE (frv_unit_groups)];
7672
  unsigned int unit, to, from;
7673
  enum frv_insn_group group;
7674
  struct frv_packet_group *packet_group;
7675
 
7676
  /* First sort each group individually.  */
7677
  for (group = GROUP_I; group < NUM_GROUPS;
7678
       group = (enum frv_insn_group) (group + 1))
7679
    {
7680
      cursor[group] = 0;
7681
      frv_sort_insn_group (group);
7682
    }
7683
 
7684
  /* Go through the unit template and try add an instruction from
7685
     that unit's group.  */
7686
  to = 0;
7687
  for (unit = 0; unit < ARRAY_SIZE (frv_unit_groups); unit++)
7688
    {
7689
      group = frv_unit_groups[unit];
7690
      packet_group = &frv_packet.groups[group];
7691
      if (cursor[group] < packet_group->num_insns)
7692
        {
7693
          /* frv_reorg should have added nops for us.  */
7694
          gcc_assert (packet_group->sorted[cursor[group]]
7695
                      != packet_group->nop);
7696
          insns[to++] = packet_group->sorted[cursor[group]++];
7697
        }
7698
    }
7699
 
7700
  gcc_assert (to == frv_packet.num_insns);
7701
 
7702
  /* Clear the last instruction's packing flag, thus marking the end of
7703
     a packet.  Reorder the other instructions relative to it.  */
7704
  CLEAR_PACKING_FLAG (insns[to - 1]);
7705
  for (from = 0; from < to - 1; from++)
7706
    {
7707
      remove_insn (insns[from]);
7708
      add_insn_before (insns[from], insns[to - 1], NULL);
7709
      SET_PACKING_FLAG (insns[from]);
7710
    }
7711
}
7712
 
7713
 
7714
/* Divide instructions into packets.  Reorder the contents of each
7715
   packet so that they are in the correct assembly-language order.
7716
 
7717
   Since this pass can change the raw meaning of the rtl stream, it must
7718
   only be called at the last minute, just before the instructions are
7719
   written out.  */
7720
 
7721
static void
7722
frv_pack_insns (void)
7723
{
7724
  if (frv_for_each_packet (frv_reorder_packet))
7725
    frv_insn_packing_flag = 0;
7726
  else
7727
    frv_insn_packing_flag = -1;
7728
}
7729
 
7730
/* See whether we need to add nops to group GROUP in order to
7731
   make a valid packet.  */
7732
 
7733
static void
7734
frv_fill_unused_units (enum frv_insn_group group)
7735
{
7736
  unsigned int non_nops, nops, i;
7737
  struct frv_packet_group *packet_group;
7738
 
7739
  packet_group = &frv_packet.groups[group];
7740
 
7741
  /* Sort the instructions into assembly-language order.
7742
     Use nops to fill slots that are otherwise unused.  */
7743
  frv_sort_insn_group (group);
7744
 
7745
  /* See how many nops are needed before the final useful instruction.  */
7746
  i = nops = 0;
7747
  for (non_nops = 0; non_nops < packet_group->num_insns; non_nops++)
7748
    while (packet_group->sorted[i++] == packet_group->nop)
7749
      nops++;
7750
 
7751
  /* Insert that many nops into the instruction stream.  */
7752
  while (nops-- > 0)
7753
    frv_insert_nop_in_packet (packet_group->nop);
7754
}
7755
 
7756
/* Return true if accesses IO1 and IO2 refer to the same doubleword.  */
7757
 
7758
static bool
7759
frv_same_doubleword_p (const struct frv_io *io1, const struct frv_io *io2)
7760
{
7761
  if (io1->const_address != 0 && io2->const_address != 0)
7762
    return io1->const_address == io2->const_address;
7763
 
7764
  if (io1->var_address != 0 && io2->var_address != 0)
7765
    return rtx_equal_p (io1->var_address, io2->var_address);
7766
 
7767
  return false;
7768
}
7769
 
7770
/* Return true if operations IO1 and IO2 are guaranteed to complete
7771
   in order.  */
7772
 
7773
static bool
7774
frv_io_fixed_order_p (const struct frv_io *io1, const struct frv_io *io2)
7775
{
7776
  /* The order of writes is always preserved.  */
7777
  if (io1->type == FRV_IO_WRITE && io2->type == FRV_IO_WRITE)
7778
    return true;
7779
 
7780
  /* The order of reads isn't preserved.  */
7781
  if (io1->type != FRV_IO_WRITE && io2->type != FRV_IO_WRITE)
7782
    return false;
7783
 
7784
  /* One operation is a write and the other is (or could be) a read.
7785
     The order is only guaranteed if the accesses are to the same
7786
     doubleword.  */
7787
  return frv_same_doubleword_p (io1, io2);
7788
}
7789
 
7790
/* Generalize I/O operation X so that it covers both X and Y. */
7791
 
7792
static void
7793
frv_io_union (struct frv_io *x, const struct frv_io *y)
7794
{
7795
  if (x->type != y->type)
7796
    x->type = FRV_IO_UNKNOWN;
7797
  if (!frv_same_doubleword_p (x, y))
7798
    {
7799
      x->const_address = 0;
7800
      x->var_address = 0;
7801
    }
7802
}
7803
 
7804
/* Fill IO with information about the load or store associated with
7805
   membar instruction INSN.  */
7806
 
7807
static void
7808
frv_extract_membar (struct frv_io *io, rtx insn)
7809
{
7810
  extract_insn (insn);
7811
  io->type = (enum frv_io_type) INTVAL (recog_data.operand[2]);
7812
  io->const_address = INTVAL (recog_data.operand[1]);
7813
  io->var_address = XEXP (recog_data.operand[0], 0);
7814
}
7815
 
7816
/* A note_stores callback for which DATA points to an rtx.  Nullify *DATA
7817
   if X is a register and *DATA depends on X.  */
7818
 
7819
static void
7820
frv_io_check_address (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7821
{
7822
  rtx *other = (rtx *) data;
7823
 
7824
  if (REG_P (x) && *other != 0 && reg_overlap_mentioned_p (x, *other))
7825
    *other = 0;
7826
}
7827
 
7828
/* A note_stores callback for which DATA points to a HARD_REG_SET.
7829
   Remove every modified register from the set.  */
7830
 
7831
static void
7832
frv_io_handle_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7833
{
7834
  HARD_REG_SET *set = (HARD_REG_SET *) data;
7835
  unsigned int regno;
7836
 
7837
  if (REG_P (x))
7838
    FOR_EACH_REGNO (regno, x)
7839
      CLEAR_HARD_REG_BIT (*set, regno);
7840
}
7841
 
7842
/* A for_each_rtx callback for which DATA points to a HARD_REG_SET.
7843
   Add every register in *X to the set.  */
7844
 
7845
static int
7846
frv_io_handle_use_1 (rtx *x, void *data)
7847
{
7848
  HARD_REG_SET *set = (HARD_REG_SET *) data;
7849
  unsigned int regno;
7850
 
7851
  if (REG_P (*x))
7852
    FOR_EACH_REGNO (regno, *x)
7853
      SET_HARD_REG_BIT (*set, regno);
7854
 
7855
  return 0;
7856
}
7857
 
7858
/* A note_stores callback that applies frv_io_handle_use_1 to an
7859
   entire rhs value.  */
7860
 
7861
static void
7862
frv_io_handle_use (rtx *x, void *data)
7863
{
7864
  for_each_rtx (x, frv_io_handle_use_1, data);
7865
}
7866
 
7867
/* Go through block BB looking for membars to remove.  There are two
7868
   cases where intra-block analysis is enough:
7869
 
7870
   - a membar is redundant if it occurs between two consecutive I/O
7871
   operations and if those operations are guaranteed to complete
7872
   in order.
7873
 
7874
   - a membar for a __builtin_read is redundant if the result is
7875
   used before the next I/O operation is issued.
7876
 
7877
   If the last membar in the block could not be removed, and there
7878
   are guaranteed to be no I/O operations between that membar and
7879
   the end of the block, store the membar in *LAST_MEMBAR, otherwise
7880
   store null.
7881
 
7882
   Describe the block's first I/O operation in *NEXT_IO.  Describe
7883
   an unknown operation if the block doesn't do any I/O.  */
7884
 
7885
static void
7886
frv_optimize_membar_local (basic_block bb, struct frv_io *next_io,
7887
                           rtx *last_membar)
7888
{
7889
  HARD_REG_SET used_regs;
7890
  rtx next_membar, set, insn;
7891
  bool next_is_end_p;
7892
 
7893
  /* NEXT_IO is the next I/O operation to be performed after the current
7894
     instruction.  It starts off as being an unknown operation.  */
7895
  memset (next_io, 0, sizeof (*next_io));
7896
 
7897
  /* NEXT_IS_END_P is true if NEXT_IO describes the end of the block.  */
7898
  next_is_end_p = true;
7899
 
7900
  /* If the current instruction is a __builtin_read or __builtin_write,
7901
     NEXT_MEMBAR is the membar instruction associated with it.  NEXT_MEMBAR
7902
     is null if the membar has already been deleted.
7903
 
7904
     Note that the initialization here should only be needed to
7905
     suppress warnings.  */
7906
  next_membar = 0;
7907
 
7908
  /* USED_REGS is the set of registers that are used before the
7909
     next I/O instruction.  */
7910
  CLEAR_HARD_REG_SET (used_regs);
7911
 
7912
  for (insn = BB_END (bb); insn != BB_HEAD (bb); insn = PREV_INSN (insn))
7913
    if (GET_CODE (insn) == CALL_INSN)
7914
      {
7915
        /* We can't predict what a call will do to volatile memory.  */
7916
        memset (next_io, 0, sizeof (struct frv_io));
7917
        next_is_end_p = false;
7918
        CLEAR_HARD_REG_SET (used_regs);
7919
      }
7920
    else if (INSN_P (insn))
7921
      switch (recog_memoized (insn))
7922
        {
7923
        case CODE_FOR_optional_membar_qi:
7924
        case CODE_FOR_optional_membar_hi:
7925
        case CODE_FOR_optional_membar_si:
7926
        case CODE_FOR_optional_membar_di:
7927
          next_membar = insn;
7928
          if (next_is_end_p)
7929
            {
7930
              /* Local information isn't enough to decide whether this
7931
                 membar is needed.  Stash it away for later.  */
7932
              *last_membar = insn;
7933
              frv_extract_membar (next_io, insn);
7934
              next_is_end_p = false;
7935
            }
7936
          else
7937
            {
7938
              /* Check whether the I/O operation before INSN could be
7939
                 reordered with one described by NEXT_IO.  If it can't,
7940
                 INSN will not be needed.  */
7941
              struct frv_io prev_io;
7942
 
7943
              frv_extract_membar (&prev_io, insn);
7944
              if (frv_io_fixed_order_p (&prev_io, next_io))
7945
                {
7946
                  if (dump_file)
7947
                    fprintf (dump_file,
7948
                             ";; [Local] Removing membar %d since order"
7949
                             " of accesses is guaranteed\n",
7950
                             INSN_UID (next_membar));
7951
 
7952
                  insn = NEXT_INSN (insn);
7953
                  delete_insn (next_membar);
7954
                  next_membar = 0;
7955
                }
7956
              *next_io = prev_io;
7957
            }
7958
          break;
7959
 
7960
        default:
7961
          /* Invalidate NEXT_IO's address if it depends on something that
7962
             is clobbered by INSN.  */
7963
          if (next_io->var_address)
7964
            note_stores (PATTERN (insn), frv_io_check_address,
7965
                         &next_io->var_address);
7966
 
7967
          /* If the next membar is associated with a __builtin_read,
7968
             see if INSN reads from that address.  If it does, and if
7969
             the destination register is used before the next I/O access,
7970
             there is no need for the membar.  */
7971
          set = PATTERN (insn);
7972
          if (next_io->type == FRV_IO_READ
7973
              && next_io->var_address != 0
7974
              && next_membar != 0
7975
              && GET_CODE (set) == SET
7976
              && GET_CODE (SET_DEST (set)) == REG
7977
              && TEST_HARD_REG_BIT (used_regs, REGNO (SET_DEST (set))))
7978
            {
7979
              rtx src;
7980
 
7981
              src = SET_SRC (set);
7982
              if (GET_CODE (src) == ZERO_EXTEND)
7983
                src = XEXP (src, 0);
7984
 
7985
              if (GET_CODE (src) == MEM
7986
                  && rtx_equal_p (XEXP (src, 0), next_io->var_address))
7987
                {
7988
                  if (dump_file)
7989
                    fprintf (dump_file,
7990
                             ";; [Local] Removing membar %d since the target"
7991
                             " of %d is used before the I/O operation\n",
7992
                             INSN_UID (next_membar), INSN_UID (insn));
7993
 
7994
                  if (next_membar == *last_membar)
7995
                    *last_membar = 0;
7996
 
7997
                  delete_insn (next_membar);
7998
                  next_membar = 0;
7999
                }
8000
            }
8001
 
8002
          /* If INSN has volatile references, forget about any registers
8003
             that are used after it.  Otherwise forget about uses that
8004
             are (or might be) defined by INSN.  */
8005
          if (volatile_refs_p (PATTERN (insn)))
8006
            CLEAR_HARD_REG_SET (used_regs);
8007
          else
8008
            note_stores (PATTERN (insn), frv_io_handle_set, &used_regs);
8009
 
8010
          note_uses (&PATTERN (insn), frv_io_handle_use, &used_regs);
8011
          break;
8012
        }
8013
}
8014
 
8015
/* See if MEMBAR, the last membar instruction in BB, can be removed.
8016
   FIRST_IO[X] describes the first operation performed by basic block X.  */
8017
 
8018
static void
8019
frv_optimize_membar_global (basic_block bb, struct frv_io *first_io,
8020
                            rtx membar)
8021
{
8022
  struct frv_io this_io, next_io;
8023
  edge succ;
8024
  edge_iterator ei;
8025
 
8026
  /* We need to keep the membar if there is an edge to the exit block.  */
8027
  FOR_EACH_EDGE (succ, ei, bb->succs)
8028
  /* for (succ = bb->succ; succ != 0; succ = succ->succ_next) */
8029
    if (succ->dest == EXIT_BLOCK_PTR)
8030
      return;
8031
 
8032
  /* Work out the union of all successor blocks.  */
8033
  ei = ei_start (bb->succs);
8034
  ei_cond (ei, &succ);
8035
  /* next_io = first_io[bb->succ->dest->index]; */
8036
  next_io = first_io[succ->dest->index];
8037
  ei = ei_start (bb->succs);
8038
  if (ei_cond (ei, &succ))
8039
    {
8040
      for (ei_next (&ei); ei_cond (ei, &succ); ei_next (&ei))
8041
        /*for (succ = bb->succ->succ_next; succ != 0; succ = succ->succ_next)*/
8042
        frv_io_union (&next_io, &first_io[succ->dest->index]);
8043
    }
8044
  else
8045
    gcc_unreachable ();
8046
 
8047
  frv_extract_membar (&this_io, membar);
8048
  if (frv_io_fixed_order_p (&this_io, &next_io))
8049
    {
8050
      if (dump_file)
8051
        fprintf (dump_file,
8052
                 ";; [Global] Removing membar %d since order of accesses"
8053
                 " is guaranteed\n", INSN_UID (membar));
8054
 
8055
      delete_insn (membar);
8056
    }
8057
}
8058
 
8059
/* Remove redundant membars from the current function.  */
8060
 
8061
static void
8062
frv_optimize_membar (void)
8063
{
8064
  basic_block bb;
8065
  struct frv_io *first_io;
8066
  rtx *last_membar;
8067
 
8068
  compute_bb_for_insn ();
8069
  first_io = XCNEWVEC (struct frv_io, last_basic_block);
8070
  last_membar = XCNEWVEC (rtx, last_basic_block);
8071
 
8072
  FOR_EACH_BB (bb)
8073
    frv_optimize_membar_local (bb, &first_io[bb->index],
8074
                               &last_membar[bb->index]);
8075
 
8076
  FOR_EACH_BB (bb)
8077
    if (last_membar[bb->index] != 0)
8078
      frv_optimize_membar_global (bb, first_io, last_membar[bb->index]);
8079
 
8080
  free (first_io);
8081
  free (last_membar);
8082
}
8083
 
8084
/* Used by frv_reorg to keep track of the current packet's address.  */
8085
static unsigned int frv_packet_address;
8086
 
8087
/* If the current packet falls through to a label, try to pad the packet
8088
   with nops in order to fit the label's alignment requirements.  */
8089
 
8090
static void
8091
frv_align_label (void)
8092
{
8093
  unsigned int alignment, target, nop;
8094
  rtx x, last, barrier, label;
8095
 
8096
  /* Walk forward to the start of the next packet.  Set ALIGNMENT to the
8097
     maximum alignment of that packet, LABEL to the last label between
8098
     the packets, and BARRIER to the last barrier.  */
8099
  last = frv_packet.insns[frv_packet.num_insns - 1];
8100
  label = barrier = 0;
8101
  alignment = 4;
8102
  for (x = NEXT_INSN (last); x != 0 && !INSN_P (x); x = NEXT_INSN (x))
8103
    {
8104
      if (LABEL_P (x))
8105
        {
8106
          unsigned int subalign = 1 << label_to_alignment (x);
8107
          alignment = MAX (alignment, subalign);
8108
          label = x;
8109
        }
8110
      if (BARRIER_P (x))
8111
        barrier = x;
8112
    }
8113
 
8114
  /* If -malign-labels, and the packet falls through to an unaligned
8115
     label, try introducing a nop to align that label to 8 bytes.  */
8116
  if (TARGET_ALIGN_LABELS
8117
      && label != 0
8118
      && barrier == 0
8119
      && frv_packet.num_insns < frv_packet.issue_rate)
8120
    alignment = MAX (alignment, 8);
8121
 
8122
  /* Advance the address to the end of the current packet.  */
8123
  frv_packet_address += frv_packet.num_insns * 4;
8124
 
8125
  /* Work out the target address, after alignment.  */
8126
  target = (frv_packet_address + alignment - 1) & -alignment;
8127
 
8128
  /* If the packet falls through to the label, try to find an efficient
8129
     padding sequence.  */
8130
  if (barrier == 0)
8131
    {
8132
      /* First try adding nops to the current packet.  */
8133
      for (nop = 0; nop < frv_num_nops; nop++)
8134
        while (frv_packet_address < target && frv_pack_insn_p (frv_nops[nop]))
8135
          {
8136
            frv_insert_nop_in_packet (frv_nops[nop]);
8137
            frv_packet_address += 4;
8138
          }
8139
 
8140
      /* If we still haven't reached the target, add some new packets that
8141
         contain only nops.  If there are two types of nop, insert an
8142
         alternating sequence of frv_nops[0] and frv_nops[1], which will
8143
         lead to packets like:
8144
 
8145
                nop.p
8146
                mnop.p/fnop.p
8147
                nop.p
8148
                mnop/fnop
8149
 
8150
         etc.  Just emit frv_nops[0] if that's the only nop we have.  */
8151
      last = frv_packet.insns[frv_packet.num_insns - 1];
8152
      nop = 0;
8153
      while (frv_packet_address < target)
8154
        {
8155
          last = emit_insn_after (PATTERN (frv_nops[nop]), last);
8156
          frv_packet_address += 4;
8157
          if (frv_num_nops > 1)
8158
            nop ^= 1;
8159
        }
8160
    }
8161
 
8162
  frv_packet_address = target;
8163
}
8164
 
8165
/* Subroutine of frv_reorg, called after each packet has been constructed
8166
   in frv_packet.  */
8167
 
8168
static void
8169
frv_reorg_packet (void)
8170
{
8171
  frv_fill_unused_units (GROUP_I);
8172
  frv_fill_unused_units (GROUP_FM);
8173
  frv_align_label ();
8174
}
8175
 
8176
/* Add an instruction with pattern NOP to frv_nops[].  */
8177
 
8178
static void
8179
frv_register_nop (rtx nop)
8180
{
8181
  nop = make_insn_raw (nop);
8182
  NEXT_INSN (nop) = 0;
8183
  PREV_INSN (nop) = 0;
8184
  frv_nops[frv_num_nops++] = nop;
8185
}
8186
 
8187
/* Implement TARGET_MACHINE_DEPENDENT_REORG.  Divide the instructions
8188
   into packets and check whether we need to insert nops in order to
8189
   fulfill the processor's issue requirements.  Also, if the user has
8190
   requested a certain alignment for a label, try to meet that alignment
8191
   by inserting nops in the previous packet.  */
8192
 
8193
static void
8194
frv_reorg (void)
8195
{
8196
  if (optimize > 0 && TARGET_OPTIMIZE_MEMBAR && cfun->machine->has_membar_p)
8197
    frv_optimize_membar ();
8198
 
8199
  frv_num_nops = 0;
8200
  frv_register_nop (gen_nop ());
8201
  if (TARGET_MEDIA)
8202
    frv_register_nop (gen_mnop ());
8203
  if (TARGET_HARD_FLOAT)
8204
    frv_register_nop (gen_fnop ());
8205
 
8206
  /* Estimate the length of each branch.  Although this may change after
8207
     we've inserted nops, it will only do so in big functions.  */
8208
  shorten_branches (get_insns ());
8209
 
8210
  frv_packet_address = 0;
8211
  frv_for_each_packet (frv_reorg_packet);
8212
}
8213
 
8214
#define def_builtin(name, type, code) \
8215
  add_builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL)
8216
 
8217
struct builtin_description
8218
{
8219
  enum insn_code icode;
8220
  const char *name;
8221
  enum frv_builtins code;
8222
  enum rtx_code comparison;
8223
  unsigned int flag;
8224
};
8225
 
8226
/* Media intrinsics that take a single, constant argument.  */
8227
 
8228
static struct builtin_description bdesc_set[] =
8229
{
8230
  { CODE_FOR_mhdsets, "__MHDSETS", FRV_BUILTIN_MHDSETS, UNKNOWN, 0 }
8231
};
8232
 
8233
/* Media intrinsics that take just one argument.  */
8234
 
8235
static struct builtin_description bdesc_1arg[] =
8236
{
8237
  { CODE_FOR_mnot, "__MNOT", FRV_BUILTIN_MNOT, UNKNOWN, 0 },
8238
  { CODE_FOR_munpackh, "__MUNPACKH", FRV_BUILTIN_MUNPACKH, UNKNOWN, 0 },
8239
  { CODE_FOR_mbtoh, "__MBTOH", FRV_BUILTIN_MBTOH, UNKNOWN, 0 },
8240
  { CODE_FOR_mhtob, "__MHTOB", FRV_BUILTIN_MHTOB, UNKNOWN, 0},
8241
  { CODE_FOR_mabshs, "__MABSHS", FRV_BUILTIN_MABSHS, UNKNOWN, 0 },
8242
  { CODE_FOR_scutss, "__SCUTSS", FRV_BUILTIN_SCUTSS, UNKNOWN, 0 }
8243
};
8244
 
8245
/* Media intrinsics that take two arguments.  */
8246
 
8247
static struct builtin_description bdesc_2arg[] =
8248
{
8249
  { CODE_FOR_mand, "__MAND", FRV_BUILTIN_MAND, UNKNOWN, 0},
8250
  { CODE_FOR_mor, "__MOR", FRV_BUILTIN_MOR, UNKNOWN, 0},
8251
  { CODE_FOR_mxor, "__MXOR", FRV_BUILTIN_MXOR, UNKNOWN, 0},
8252
  { CODE_FOR_maveh, "__MAVEH", FRV_BUILTIN_MAVEH, UNKNOWN, 0},
8253
  { CODE_FOR_msaths, "__MSATHS", FRV_BUILTIN_MSATHS, UNKNOWN, 0},
8254
  { CODE_FOR_msathu, "__MSATHU", FRV_BUILTIN_MSATHU, UNKNOWN, 0},
8255
  { CODE_FOR_maddhss, "__MADDHSS", FRV_BUILTIN_MADDHSS, UNKNOWN, 0},
8256
  { CODE_FOR_maddhus, "__MADDHUS", FRV_BUILTIN_MADDHUS, UNKNOWN, 0},
8257
  { CODE_FOR_msubhss, "__MSUBHSS", FRV_BUILTIN_MSUBHSS, UNKNOWN, 0},
8258
  { CODE_FOR_msubhus, "__MSUBHUS", FRV_BUILTIN_MSUBHUS, UNKNOWN, 0},
8259
  { CODE_FOR_mqaddhss, "__MQADDHSS", FRV_BUILTIN_MQADDHSS, UNKNOWN, 0},
8260
  { CODE_FOR_mqaddhus, "__MQADDHUS", FRV_BUILTIN_MQADDHUS, UNKNOWN, 0},
8261
  { CODE_FOR_mqsubhss, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS, UNKNOWN, 0},
8262
  { CODE_FOR_mqsubhus, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS, UNKNOWN, 0},
8263
  { CODE_FOR_mpackh, "__MPACKH", FRV_BUILTIN_MPACKH, UNKNOWN, 0},
8264
  { CODE_FOR_mcop1, "__Mcop1", FRV_BUILTIN_MCOP1, UNKNOWN, 0},
8265
  { CODE_FOR_mcop2, "__Mcop2", FRV_BUILTIN_MCOP2, UNKNOWN, 0},
8266
  { CODE_FOR_mwcut, "__MWCUT", FRV_BUILTIN_MWCUT, UNKNOWN, 0},
8267
  { CODE_FOR_mqsaths, "__MQSATHS", FRV_BUILTIN_MQSATHS, UNKNOWN, 0},
8268
  { CODE_FOR_mqlclrhs, "__MQLCLRHS", FRV_BUILTIN_MQLCLRHS, UNKNOWN, 0},
8269
  { CODE_FOR_mqlmths, "__MQLMTHS", FRV_BUILTIN_MQLMTHS, UNKNOWN, 0},
8270
  { CODE_FOR_smul, "__SMUL", FRV_BUILTIN_SMUL, UNKNOWN, 0},
8271
  { CODE_FOR_umul, "__UMUL", FRV_BUILTIN_UMUL, UNKNOWN, 0},
8272
  { CODE_FOR_addss, "__ADDSS", FRV_BUILTIN_ADDSS, UNKNOWN, 0},
8273
  { CODE_FOR_subss, "__SUBSS", FRV_BUILTIN_SUBSS, UNKNOWN, 0},
8274
  { CODE_FOR_slass, "__SLASS", FRV_BUILTIN_SLASS, UNKNOWN, 0},
8275
  { CODE_FOR_scan, "__SCAN", FRV_BUILTIN_SCAN, UNKNOWN, 0}
8276
};
8277
 
8278
/* Integer intrinsics that take two arguments and have no return value.  */
8279
 
8280
static struct builtin_description bdesc_int_void2arg[] =
8281
{
8282
  { CODE_FOR_smass, "__SMASS", FRV_BUILTIN_SMASS, UNKNOWN, 0},
8283
  { CODE_FOR_smsss, "__SMSSS", FRV_BUILTIN_SMSSS, UNKNOWN, 0},
8284
  { CODE_FOR_smu, "__SMU", FRV_BUILTIN_SMU, UNKNOWN, 0}
8285
};
8286
 
8287
static struct builtin_description bdesc_prefetches[] =
8288
{
8289
  { CODE_FOR_frv_prefetch0, "__data_prefetch0", FRV_BUILTIN_PREFETCH0, UNKNOWN,
8290
    0},
8291
  { CODE_FOR_frv_prefetch, "__data_prefetch", FRV_BUILTIN_PREFETCH, UNKNOWN, 0}
8292
};
8293
 
8294
/* Media intrinsics that take two arguments, the first being an ACC number.  */
8295
 
8296
static struct builtin_description bdesc_cut[] =
8297
{
8298
  { CODE_FOR_mcut, "__MCUT", FRV_BUILTIN_MCUT, UNKNOWN, 0},
8299
  { CODE_FOR_mcutss, "__MCUTSS", FRV_BUILTIN_MCUTSS, UNKNOWN, 0},
8300
  { CODE_FOR_mdcutssi, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI, UNKNOWN, 0}
8301
};
8302
 
8303
/* Two-argument media intrinsics with an immediate second argument.  */
8304
 
8305
static struct builtin_description bdesc_2argimm[] =
8306
{
8307
  { CODE_FOR_mrotli, "__MROTLI", FRV_BUILTIN_MROTLI, UNKNOWN, 0},
8308
  { CODE_FOR_mrotri, "__MROTRI", FRV_BUILTIN_MROTRI, UNKNOWN, 0},
8309
  { CODE_FOR_msllhi, "__MSLLHI", FRV_BUILTIN_MSLLHI, UNKNOWN, 0},
8310
  { CODE_FOR_msrlhi, "__MSRLHI", FRV_BUILTIN_MSRLHI, UNKNOWN, 0},
8311
  { CODE_FOR_msrahi, "__MSRAHI", FRV_BUILTIN_MSRAHI, UNKNOWN, 0},
8312
  { CODE_FOR_mexpdhw, "__MEXPDHW", FRV_BUILTIN_MEXPDHW, UNKNOWN, 0},
8313
  { CODE_FOR_mexpdhd, "__MEXPDHD", FRV_BUILTIN_MEXPDHD, UNKNOWN, 0},
8314
  { CODE_FOR_mdrotli, "__MDROTLI", FRV_BUILTIN_MDROTLI, UNKNOWN, 0},
8315
  { CODE_FOR_mcplhi, "__MCPLHI", FRV_BUILTIN_MCPLHI, UNKNOWN, 0},
8316
  { CODE_FOR_mcpli, "__MCPLI", FRV_BUILTIN_MCPLI, UNKNOWN, 0},
8317
  { CODE_FOR_mhsetlos, "__MHSETLOS", FRV_BUILTIN_MHSETLOS, UNKNOWN, 0},
8318
  { CODE_FOR_mhsetloh, "__MHSETLOH", FRV_BUILTIN_MHSETLOH, UNKNOWN, 0},
8319
  { CODE_FOR_mhsethis, "__MHSETHIS", FRV_BUILTIN_MHSETHIS, UNKNOWN, 0},
8320
  { CODE_FOR_mhsethih, "__MHSETHIH", FRV_BUILTIN_MHSETHIH, UNKNOWN, 0},
8321
  { CODE_FOR_mhdseth, "__MHDSETH", FRV_BUILTIN_MHDSETH, UNKNOWN, 0},
8322
  { CODE_FOR_mqsllhi, "__MQSLLHI", FRV_BUILTIN_MQSLLHI, UNKNOWN, 0},
8323
  { CODE_FOR_mqsrahi, "__MQSRAHI", FRV_BUILTIN_MQSRAHI, UNKNOWN, 0}
8324
};
8325
 
8326
/* Media intrinsics that take two arguments and return void, the first argument
8327
   being a pointer to 4 words in memory.  */
8328
 
8329
static struct builtin_description bdesc_void2arg[] =
8330
{
8331
  { CODE_FOR_mdunpackh, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH, UNKNOWN, 0},
8332
  { CODE_FOR_mbtohe, "__MBTOHE", FRV_BUILTIN_MBTOHE, UNKNOWN, 0},
8333
};
8334
 
8335
/* Media intrinsics that take three arguments, the first being a const_int that
8336
   denotes an accumulator, and that return void.  */
8337
 
8338
static struct builtin_description bdesc_void3arg[] =
8339
{
8340
  { CODE_FOR_mcpxrs, "__MCPXRS", FRV_BUILTIN_MCPXRS, UNKNOWN, 0},
8341
  { CODE_FOR_mcpxru, "__MCPXRU", FRV_BUILTIN_MCPXRU, UNKNOWN, 0},
8342
  { CODE_FOR_mcpxis, "__MCPXIS", FRV_BUILTIN_MCPXIS, UNKNOWN, 0},
8343
  { CODE_FOR_mcpxiu, "__MCPXIU", FRV_BUILTIN_MCPXIU, UNKNOWN, 0},
8344
  { CODE_FOR_mmulhs, "__MMULHS", FRV_BUILTIN_MMULHS, UNKNOWN, 0},
8345
  { CODE_FOR_mmulhu, "__MMULHU", FRV_BUILTIN_MMULHU, UNKNOWN, 0},
8346
  { CODE_FOR_mmulxhs, "__MMULXHS", FRV_BUILTIN_MMULXHS, UNKNOWN, 0},
8347
  { CODE_FOR_mmulxhu, "__MMULXHU", FRV_BUILTIN_MMULXHU, UNKNOWN, 0},
8348
  { CODE_FOR_mmachs, "__MMACHS", FRV_BUILTIN_MMACHS, UNKNOWN, 0},
8349
  { CODE_FOR_mmachu, "__MMACHU", FRV_BUILTIN_MMACHU, UNKNOWN, 0},
8350
  { CODE_FOR_mmrdhs, "__MMRDHS", FRV_BUILTIN_MMRDHS, UNKNOWN, 0},
8351
  { CODE_FOR_mmrdhu, "__MMRDHU", FRV_BUILTIN_MMRDHU, UNKNOWN, 0},
8352
  { CODE_FOR_mqcpxrs, "__MQCPXRS", FRV_BUILTIN_MQCPXRS, UNKNOWN, 0},
8353
  { CODE_FOR_mqcpxru, "__MQCPXRU", FRV_BUILTIN_MQCPXRU, UNKNOWN, 0},
8354
  { CODE_FOR_mqcpxis, "__MQCPXIS", FRV_BUILTIN_MQCPXIS, UNKNOWN, 0},
8355
  { CODE_FOR_mqcpxiu, "__MQCPXIU", FRV_BUILTIN_MQCPXIU, UNKNOWN, 0},
8356
  { CODE_FOR_mqmulhs, "__MQMULHS", FRV_BUILTIN_MQMULHS, UNKNOWN, 0},
8357
  { CODE_FOR_mqmulhu, "__MQMULHU", FRV_BUILTIN_MQMULHU, UNKNOWN, 0},
8358
  { CODE_FOR_mqmulxhs, "__MQMULXHS", FRV_BUILTIN_MQMULXHS, UNKNOWN, 0},
8359
  { CODE_FOR_mqmulxhu, "__MQMULXHU", FRV_BUILTIN_MQMULXHU, UNKNOWN, 0},
8360
  { CODE_FOR_mqmachs, "__MQMACHS", FRV_BUILTIN_MQMACHS, UNKNOWN, 0},
8361
  { CODE_FOR_mqmachu, "__MQMACHU", FRV_BUILTIN_MQMACHU, UNKNOWN, 0},
8362
  { CODE_FOR_mqxmachs, "__MQXMACHS", FRV_BUILTIN_MQXMACHS, UNKNOWN, 0},
8363
  { CODE_FOR_mqxmacxhs, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS, UNKNOWN, 0},
8364
  { CODE_FOR_mqmacxhs, "__MQMACXHS", FRV_BUILTIN_MQMACXHS, UNKNOWN, 0}
8365
};
8366
 
8367
/* Media intrinsics that take two accumulator numbers as argument and
8368
   return void.  */
8369
 
8370
static struct builtin_description bdesc_voidacc[] =
8371
{
8372
  { CODE_FOR_maddaccs, "__MADDACCS", FRV_BUILTIN_MADDACCS, UNKNOWN, 0},
8373
  { CODE_FOR_msubaccs, "__MSUBACCS", FRV_BUILTIN_MSUBACCS, UNKNOWN, 0},
8374
  { CODE_FOR_masaccs, "__MASACCS", FRV_BUILTIN_MASACCS, UNKNOWN, 0},
8375
  { CODE_FOR_mdaddaccs, "__MDADDACCS", FRV_BUILTIN_MDADDACCS, UNKNOWN, 0},
8376
  { CODE_FOR_mdsubaccs, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS, UNKNOWN, 0},
8377
  { CODE_FOR_mdasaccs, "__MDASACCS", FRV_BUILTIN_MDASACCS, UNKNOWN, 0}
8378
};
8379
 
8380
/* Intrinsics that load a value and then issue a MEMBAR.  The load is
8381
   a normal move and the ICODE is for the membar.  */
8382
 
8383
static struct builtin_description bdesc_loads[] =
8384
{
8385
  { CODE_FOR_optional_membar_qi, "__builtin_read8",
8386
    FRV_BUILTIN_READ8, UNKNOWN, 0},
8387
  { CODE_FOR_optional_membar_hi, "__builtin_read16",
8388
    FRV_BUILTIN_READ16, UNKNOWN, 0},
8389
  { CODE_FOR_optional_membar_si, "__builtin_read32",
8390
    FRV_BUILTIN_READ32, UNKNOWN, 0},
8391
  { CODE_FOR_optional_membar_di, "__builtin_read64",
8392
    FRV_BUILTIN_READ64, UNKNOWN, 0}
8393
};
8394
 
8395
/* Likewise stores.  */
8396
 
8397
static struct builtin_description bdesc_stores[] =
8398
{
8399
  { CODE_FOR_optional_membar_qi, "__builtin_write8",
8400
    FRV_BUILTIN_WRITE8, UNKNOWN, 0},
8401
  { CODE_FOR_optional_membar_hi, "__builtin_write16",
8402
    FRV_BUILTIN_WRITE16, UNKNOWN, 0},
8403
  { CODE_FOR_optional_membar_si, "__builtin_write32",
8404
    FRV_BUILTIN_WRITE32, UNKNOWN, 0},
8405
  { CODE_FOR_optional_membar_di, "__builtin_write64",
8406
    FRV_BUILTIN_WRITE64, UNKNOWN, 0},
8407
};
8408
 
8409
/* Initialize media builtins.  */
8410
 
8411
static void
8412
frv_init_builtins (void)
8413
{
8414
  tree accumulator = integer_type_node;
8415
  tree integer = integer_type_node;
8416
  tree voidt = void_type_node;
8417
  tree uhalf = short_unsigned_type_node;
8418
  tree sword1 = long_integer_type_node;
8419
  tree uword1 = long_unsigned_type_node;
8420
  tree sword2 = long_long_integer_type_node;
8421
  tree uword2 = long_long_unsigned_type_node;
8422
  tree uword4 = build_pointer_type (uword1);
8423
  tree vptr   = build_pointer_type (build_type_variant (void_type_node, 0, 1));
8424
  tree ubyte  = unsigned_char_type_node;
8425
  tree iacc   = integer_type_node;
8426
 
8427
#define UNARY(RET, T1) \
8428
  build_function_type_list (RET, T1, NULL_TREE)
8429
 
8430
#define BINARY(RET, T1, T2) \
8431
  build_function_type_list (RET, T1, T2, NULL_TREE)
8432
 
8433
#define TRINARY(RET, T1, T2, T3) \
8434
  build_function_type_list (RET, T1, T2, T3, NULL_TREE)
8435
 
8436
#define QUAD(RET, T1, T2, T3, T4) \
8437
  build_function_type_list (RET, T1, T2, T3, NULL_TREE)
8438
 
8439
  tree void_ftype_void = build_function_type_list (voidt, NULL_TREE);
8440
 
8441
  tree void_ftype_acc = UNARY (voidt, accumulator);
8442
  tree void_ftype_uw4_uw1 = BINARY (voidt, uword4, uword1);
8443
  tree void_ftype_uw4_uw2 = BINARY (voidt, uword4, uword2);
8444
  tree void_ftype_acc_uw1 = BINARY (voidt, accumulator, uword1);
8445
  tree void_ftype_acc_acc = BINARY (voidt, accumulator, accumulator);
8446
  tree void_ftype_acc_uw1_uw1 = TRINARY (voidt, accumulator, uword1, uword1);
8447
  tree void_ftype_acc_sw1_sw1 = TRINARY (voidt, accumulator, sword1, sword1);
8448
  tree void_ftype_acc_uw2_uw2 = TRINARY (voidt, accumulator, uword2, uword2);
8449
  tree void_ftype_acc_sw2_sw2 = TRINARY (voidt, accumulator, sword2, sword2);
8450
 
8451
  tree uw1_ftype_uw1 = UNARY (uword1, uword1);
8452
  tree uw1_ftype_sw1 = UNARY (uword1, sword1);
8453
  tree uw1_ftype_uw2 = UNARY (uword1, uword2);
8454
  tree uw1_ftype_acc = UNARY (uword1, accumulator);
8455
  tree uw1_ftype_uh_uh = BINARY (uword1, uhalf, uhalf);
8456
  tree uw1_ftype_uw1_uw1 = BINARY (uword1, uword1, uword1);
8457
  tree uw1_ftype_uw1_int = BINARY (uword1, uword1, integer);
8458
  tree uw1_ftype_acc_uw1 = BINARY (uword1, accumulator, uword1);
8459
  tree uw1_ftype_acc_sw1 = BINARY (uword1, accumulator, sword1);
8460
  tree uw1_ftype_uw2_uw1 = BINARY (uword1, uword2, uword1);
8461
  tree uw1_ftype_uw2_int = BINARY (uword1, uword2, integer);
8462
 
8463
  tree sw1_ftype_int = UNARY (sword1, integer);
8464
  tree sw1_ftype_sw1_sw1 = BINARY (sword1, sword1, sword1);
8465
  tree sw1_ftype_sw1_int = BINARY (sword1, sword1, integer);
8466
 
8467
  tree uw2_ftype_uw1 = UNARY (uword2, uword1);
8468
  tree uw2_ftype_uw1_int = BINARY (uword2, uword1, integer);
8469
  tree uw2_ftype_uw2_uw2 = BINARY (uword2, uword2, uword2);
8470
  tree uw2_ftype_uw2_int = BINARY (uword2, uword2, integer);
8471
  tree uw2_ftype_acc_int = BINARY (uword2, accumulator, integer);
8472
  tree uw2_ftype_uh_uh_uh_uh = QUAD (uword2, uhalf, uhalf, uhalf, uhalf);
8473
 
8474
  tree sw2_ftype_sw2_sw2 = BINARY (sword2, sword2, sword2);
8475
  tree sw2_ftype_sw2_int   = BINARY (sword2, sword2, integer);
8476
  tree uw2_ftype_uw1_uw1   = BINARY (uword2, uword1, uword1);
8477
  tree sw2_ftype_sw1_sw1   = BINARY (sword2, sword1, sword1);
8478
  tree void_ftype_sw1_sw1  = BINARY (voidt, sword1, sword1);
8479
  tree void_ftype_iacc_sw2 = BINARY (voidt, iacc, sword2);
8480
  tree void_ftype_iacc_sw1 = BINARY (voidt, iacc, sword1);
8481
  tree sw1_ftype_sw1       = UNARY (sword1, sword1);
8482
  tree sw2_ftype_iacc      = UNARY (sword2, iacc);
8483
  tree sw1_ftype_iacc      = UNARY (sword1, iacc);
8484
  tree void_ftype_ptr      = UNARY (voidt, const_ptr_type_node);
8485
  tree uw1_ftype_vptr      = UNARY (uword1, vptr);
8486
  tree uw2_ftype_vptr      = UNARY (uword2, vptr);
8487
  tree void_ftype_vptr_ub  = BINARY (voidt, vptr, ubyte);
8488
  tree void_ftype_vptr_uh  = BINARY (voidt, vptr, uhalf);
8489
  tree void_ftype_vptr_uw1 = BINARY (voidt, vptr, uword1);
8490
  tree void_ftype_vptr_uw2 = BINARY (voidt, vptr, uword2);
8491
 
8492
  def_builtin ("__MAND", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAND);
8493
  def_builtin ("__MOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MOR);
8494
  def_builtin ("__MXOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MXOR);
8495
  def_builtin ("__MNOT", uw1_ftype_uw1, FRV_BUILTIN_MNOT);
8496
  def_builtin ("__MROTLI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTLI);
8497
  def_builtin ("__MROTRI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTRI);
8498
  def_builtin ("__MWCUT", uw1_ftype_uw2_uw1, FRV_BUILTIN_MWCUT);
8499
  def_builtin ("__MAVEH", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAVEH);
8500
  def_builtin ("__MSLLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSLLHI);
8501
  def_builtin ("__MSRLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSRLHI);
8502
  def_builtin ("__MSRAHI", sw1_ftype_sw1_int, FRV_BUILTIN_MSRAHI);
8503
  def_builtin ("__MSATHS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSATHS);
8504
  def_builtin ("__MSATHU", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSATHU);
8505
  def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MADDHSS);
8506
  def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MADDHUS);
8507
  def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSUBHSS);
8508
  def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSUBHUS);
8509
  def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULHS);
8510
  def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULHU);
8511
  def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULXHS);
8512
  def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULXHU);
8513
  def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMACHS);
8514
  def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMACHU);
8515
  def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMRDHS);
8516
  def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMRDHU);
8517
  def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQADDHSS);
8518
  def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQADDHUS);
8519
  def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSUBHSS);
8520
  def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQSUBHUS);
8521
  def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULHS);
8522
  def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULHU);
8523
  def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULXHS);
8524
  def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULXHU);
8525
  def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACHS);
8526
  def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMACHU);
8527
  def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXRS);
8528
  def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXRU);
8529
  def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXIS);
8530
  def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXIU);
8531
  def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXRS);
8532
  def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXRU);
8533
  def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXIS);
8534
  def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXIU);
8535
  def_builtin ("__MCUT", uw1_ftype_acc_uw1, FRV_BUILTIN_MCUT);
8536
  def_builtin ("__MCUTSS", uw1_ftype_acc_sw1, FRV_BUILTIN_MCUTSS);
8537
  def_builtin ("__MEXPDHW", uw1_ftype_uw1_int, FRV_BUILTIN_MEXPDHW);
8538
  def_builtin ("__MEXPDHD", uw2_ftype_uw1_int, FRV_BUILTIN_MEXPDHD);
8539
  def_builtin ("__MPACKH", uw1_ftype_uh_uh, FRV_BUILTIN_MPACKH);
8540
  def_builtin ("__MUNPACKH", uw2_ftype_uw1, FRV_BUILTIN_MUNPACKH);
8541
  def_builtin ("__MDPACKH", uw2_ftype_uh_uh_uh_uh, FRV_BUILTIN_MDPACKH);
8542
  def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2, FRV_BUILTIN_MDUNPACKH);
8543
  def_builtin ("__MBTOH", uw2_ftype_uw1, FRV_BUILTIN_MBTOH);
8544
  def_builtin ("__MHTOB", uw1_ftype_uw2, FRV_BUILTIN_MHTOB);
8545
  def_builtin ("__MBTOHE", void_ftype_uw4_uw1, FRV_BUILTIN_MBTOHE);
8546
  def_builtin ("__MCLRACC", void_ftype_acc, FRV_BUILTIN_MCLRACC);
8547
  def_builtin ("__MCLRACCA", void_ftype_void, FRV_BUILTIN_MCLRACCA);
8548
  def_builtin ("__MRDACC", uw1_ftype_acc, FRV_BUILTIN_MRDACC);
8549
  def_builtin ("__MRDACCG", uw1_ftype_acc, FRV_BUILTIN_MRDACCG);
8550
  def_builtin ("__MWTACC", void_ftype_acc_uw1, FRV_BUILTIN_MWTACC);
8551
  def_builtin ("__MWTACCG", void_ftype_acc_uw1, FRV_BUILTIN_MWTACCG);
8552
  def_builtin ("__Mcop1", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP1);
8553
  def_builtin ("__Mcop2", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP2);
8554
  def_builtin ("__MTRAP", void_ftype_void, FRV_BUILTIN_MTRAP);
8555
  def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACHS);
8556
  def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACXHS);
8557
  def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACXHS);
8558
  def_builtin ("__MADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MADDACCS);
8559
  def_builtin ("__MSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MSUBACCS);
8560
  def_builtin ("__MASACCS", void_ftype_acc_acc, FRV_BUILTIN_MASACCS);
8561
  def_builtin ("__MDADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MDADDACCS);
8562
  def_builtin ("__MDSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MDSUBACCS);
8563
  def_builtin ("__MDASACCS", void_ftype_acc_acc, FRV_BUILTIN_MDASACCS);
8564
  def_builtin ("__MABSHS", uw1_ftype_sw1, FRV_BUILTIN_MABSHS);
8565
  def_builtin ("__MDROTLI", uw2_ftype_uw2_int, FRV_BUILTIN_MDROTLI);
8566
  def_builtin ("__MCPLHI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLHI);
8567
  def_builtin ("__MCPLI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLI);
8568
  def_builtin ("__MDCUTSSI", uw2_ftype_acc_int, FRV_BUILTIN_MDCUTSSI);
8569
  def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSATHS);
8570
  def_builtin ("__MHSETLOS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETLOS);
8571
  def_builtin ("__MHSETHIS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETHIS);
8572
  def_builtin ("__MHDSETS", sw1_ftype_int, FRV_BUILTIN_MHDSETS);
8573
  def_builtin ("__MHSETLOH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETLOH);
8574
  def_builtin ("__MHSETHIH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETHIH);
8575
  def_builtin ("__MHDSETH", uw1_ftype_uw1_int, FRV_BUILTIN_MHDSETH);
8576
  def_builtin ("__MQLCLRHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLCLRHS);
8577
  def_builtin ("__MQLMTHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLMTHS);
8578
  def_builtin ("__MQSLLHI", uw2_ftype_uw2_int, FRV_BUILTIN_MQSLLHI);
8579
  def_builtin ("__MQSRAHI", sw2_ftype_sw2_int, FRV_BUILTIN_MQSRAHI);
8580
  def_builtin ("__SMUL", sw2_ftype_sw1_sw1, FRV_BUILTIN_SMUL);
8581
  def_builtin ("__UMUL", uw2_ftype_uw1_uw1, FRV_BUILTIN_UMUL);
8582
  def_builtin ("__SMASS", void_ftype_sw1_sw1, FRV_BUILTIN_SMASS);
8583
  def_builtin ("__SMSSS", void_ftype_sw1_sw1, FRV_BUILTIN_SMSSS);
8584
  def_builtin ("__SMU", void_ftype_sw1_sw1, FRV_BUILTIN_SMU);
8585
  def_builtin ("__ADDSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_ADDSS);
8586
  def_builtin ("__SUBSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SUBSS);
8587
  def_builtin ("__SLASS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SLASS);
8588
  def_builtin ("__SCAN", sw1_ftype_sw1_sw1, FRV_BUILTIN_SCAN);
8589
  def_builtin ("__SCUTSS", sw1_ftype_sw1, FRV_BUILTIN_SCUTSS);
8590
  def_builtin ("__IACCreadll", sw2_ftype_iacc, FRV_BUILTIN_IACCreadll);
8591
  def_builtin ("__IACCreadl", sw1_ftype_iacc, FRV_BUILTIN_IACCreadl);
8592
  def_builtin ("__IACCsetll", void_ftype_iacc_sw2, FRV_BUILTIN_IACCsetll);
8593
  def_builtin ("__IACCsetl", void_ftype_iacc_sw1, FRV_BUILTIN_IACCsetl);
8594
  def_builtin ("__data_prefetch0", void_ftype_ptr, FRV_BUILTIN_PREFETCH0);
8595
  def_builtin ("__data_prefetch", void_ftype_ptr, FRV_BUILTIN_PREFETCH);
8596
  def_builtin ("__builtin_read8", uw1_ftype_vptr, FRV_BUILTIN_READ8);
8597
  def_builtin ("__builtin_read16", uw1_ftype_vptr, FRV_BUILTIN_READ16);
8598
  def_builtin ("__builtin_read32", uw1_ftype_vptr, FRV_BUILTIN_READ32);
8599
  def_builtin ("__builtin_read64", uw2_ftype_vptr, FRV_BUILTIN_READ64);
8600
 
8601
  def_builtin ("__builtin_write8", void_ftype_vptr_ub, FRV_BUILTIN_WRITE8);
8602
  def_builtin ("__builtin_write16", void_ftype_vptr_uh, FRV_BUILTIN_WRITE16);
8603
  def_builtin ("__builtin_write32", void_ftype_vptr_uw1, FRV_BUILTIN_WRITE32);
8604
  def_builtin ("__builtin_write64", void_ftype_vptr_uw2, FRV_BUILTIN_WRITE64);
8605
 
8606
#undef UNARY
8607
#undef BINARY
8608
#undef TRINARY
8609
#undef QUAD
8610
}
8611
 
8612
/* Set the names for various arithmetic operations according to the
8613
   FRV ABI.  */
8614
static void
8615
frv_init_libfuncs (void)
8616
{
8617
  set_optab_libfunc (smod_optab,     SImode, "__modi");
8618
  set_optab_libfunc (umod_optab,     SImode, "__umodi");
8619
 
8620
  set_optab_libfunc (add_optab,      DImode, "__addll");
8621
  set_optab_libfunc (sub_optab,      DImode, "__subll");
8622
  set_optab_libfunc (smul_optab,     DImode, "__mulll");
8623
  set_optab_libfunc (sdiv_optab,     DImode, "__divll");
8624
  set_optab_libfunc (smod_optab,     DImode, "__modll");
8625
  set_optab_libfunc (umod_optab,     DImode, "__umodll");
8626
  set_optab_libfunc (and_optab,      DImode, "__andll");
8627
  set_optab_libfunc (ior_optab,      DImode, "__orll");
8628
  set_optab_libfunc (xor_optab,      DImode, "__xorll");
8629
  set_optab_libfunc (one_cmpl_optab, DImode, "__notll");
8630
 
8631
  set_optab_libfunc (add_optab,      SFmode, "__addf");
8632
  set_optab_libfunc (sub_optab,      SFmode, "__subf");
8633
  set_optab_libfunc (smul_optab,     SFmode, "__mulf");
8634
  set_optab_libfunc (sdiv_optab,     SFmode, "__divf");
8635
 
8636
  set_optab_libfunc (add_optab,      DFmode, "__addd");
8637
  set_optab_libfunc (sub_optab,      DFmode, "__subd");
8638
  set_optab_libfunc (smul_optab,     DFmode, "__muld");
8639
  set_optab_libfunc (sdiv_optab,     DFmode, "__divd");
8640
 
8641
  set_conv_libfunc (sext_optab,   DFmode, SFmode, "__ftod");
8642
  set_conv_libfunc (trunc_optab,  SFmode, DFmode, "__dtof");
8643
 
8644
  set_conv_libfunc (sfix_optab,   SImode, SFmode, "__ftoi");
8645
  set_conv_libfunc (sfix_optab,   DImode, SFmode, "__ftoll");
8646
  set_conv_libfunc (sfix_optab,   SImode, DFmode, "__dtoi");
8647
  set_conv_libfunc (sfix_optab,   DImode, DFmode, "__dtoll");
8648
 
8649
  set_conv_libfunc (ufix_optab,   SImode, SFmode, "__ftoui");
8650
  set_conv_libfunc (ufix_optab,   DImode, SFmode, "__ftoull");
8651
  set_conv_libfunc (ufix_optab,   SImode, DFmode, "__dtoui");
8652
  set_conv_libfunc (ufix_optab,   DImode, DFmode, "__dtoull");
8653
 
8654
  set_conv_libfunc (sfloat_optab, SFmode, SImode, "__itof");
8655
  set_conv_libfunc (sfloat_optab, SFmode, DImode, "__lltof");
8656
  set_conv_libfunc (sfloat_optab, DFmode, SImode, "__itod");
8657
  set_conv_libfunc (sfloat_optab, DFmode, DImode, "__lltod");
8658
}
8659
 
8660
/* Convert an integer constant to an accumulator register.  ICODE is the
8661
   code of the target instruction, OPNUM is the number of the
8662
   accumulator operand and OPVAL is the constant integer.  Try both
8663
   ACC and ACCG registers; only report an error if neither fit the
8664
   instruction.  */
8665
 
8666
static rtx
8667
frv_int_to_acc (enum insn_code icode, int opnum, rtx opval)
8668
{
8669
  rtx reg;
8670
  int i;
8671
 
8672
  /* ACCs and ACCGs are implicit global registers if media intrinsics
8673
     are being used.  We set up this lazily to avoid creating lots of
8674
     unnecessary call_insn rtl in non-media code.  */
8675
  for (i = 0; i <= ACC_MASK; i++)
8676
    if ((i & ACC_MASK) == i)
8677
      global_regs[i + ACC_FIRST] = global_regs[i + ACCG_FIRST] = 1;
8678
 
8679
  if (GET_CODE (opval) != CONST_INT)
8680
    {
8681
      error ("accumulator is not a constant integer");
8682
      return NULL_RTX;
8683
    }
8684
  if ((INTVAL (opval) & ~ACC_MASK) != 0)
8685
    {
8686
      error ("accumulator number is out of bounds");
8687
      return NULL_RTX;
8688
    }
8689
 
8690
  reg = gen_rtx_REG (insn_data[icode].operand[opnum].mode,
8691
                     ACC_FIRST + INTVAL (opval));
8692
  if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
8693
    SET_REGNO (reg, ACCG_FIRST + INTVAL (opval));
8694
 
8695
  if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
8696
    {
8697
      error ("inappropriate accumulator for %qs", insn_data[icode].name);
8698
      return NULL_RTX;
8699
    }
8700
  return reg;
8701
}
8702
 
8703
/* If an ACC rtx has mode MODE, return the mode that the matching ACCG
8704
   should have.  */
8705
 
8706
static enum machine_mode
8707
frv_matching_accg_mode (enum machine_mode mode)
8708
{
8709
  switch (mode)
8710
    {
8711
    case V4SImode:
8712
      return V4QImode;
8713
 
8714
    case DImode:
8715
      return HImode;
8716
 
8717
    case SImode:
8718
      return QImode;
8719
 
8720
    default:
8721
      gcc_unreachable ();
8722
    }
8723
}
8724
 
8725
/* Given that a __builtin_read or __builtin_write function is accessing
8726
   address ADDRESS, return the value that should be used as operand 1
8727
   of the membar.  */
8728
 
8729
static rtx
8730
frv_io_address_cookie (rtx address)
8731
{
8732
  return (GET_CODE (address) == CONST_INT
8733
          ? GEN_INT (INTVAL (address) / 8 * 8)
8734
          : const0_rtx);
8735
}
8736
 
8737
/* Return the accumulator guard that should be paired with accumulator
8738
   register ACC.  The mode of the returned register is in the same
8739
   class as ACC, but is four times smaller.  */
8740
 
8741
rtx
8742
frv_matching_accg_for_acc (rtx acc)
8743
{
8744
  return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc)),
8745
                      REGNO (acc) - ACC_FIRST + ACCG_FIRST);
8746
}
8747
 
8748
/* Read the requested argument from the call EXP given by INDEX.
8749
   Return the value as an rtx.  */
8750
 
8751
static rtx
8752
frv_read_argument (tree exp, unsigned int index)
8753
{
8754
  return expand_normal (CALL_EXPR_ARG (exp, index));
8755
}
8756
 
8757
/* Like frv_read_argument, but interpret the argument as the number
8758
   of an IACC register and return a (reg:MODE ...) rtx for it.  */
8759
 
8760
static rtx
8761
frv_read_iacc_argument (enum machine_mode mode, tree call,
8762
                        unsigned int index)
8763
{
8764
  int i, regno;
8765
  rtx op;
8766
 
8767
  op = frv_read_argument (call, index);
8768
  if (GET_CODE (op) != CONST_INT
8769
      || INTVAL (op) < 0
8770
      || INTVAL (op) > IACC_LAST - IACC_FIRST
8771
      || ((INTVAL (op) * 4) & (GET_MODE_SIZE (mode) - 1)) != 0)
8772
    {
8773
      error ("invalid IACC argument");
8774
      op = const0_rtx;
8775
    }
8776
 
8777
  /* IACCs are implicit global registers.  We set up this lazily to
8778
     avoid creating lots of unnecessary call_insn rtl when IACCs aren't
8779
     being used.  */
8780
  regno = INTVAL (op) + IACC_FIRST;
8781
  for (i = 0; i < HARD_REGNO_NREGS (regno, mode); i++)
8782
    global_regs[regno + i] = 1;
8783
 
8784
  return gen_rtx_REG (mode, regno);
8785
}
8786
 
8787
/* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
8788
   The instruction should require a constant operand of some sort.  The
8789
   function prints an error if OPVAL is not valid.  */
8790
 
8791
static int
8792
frv_check_constant_argument (enum insn_code icode, int opnum, rtx opval)
8793
{
8794
  if (GET_CODE (opval) != CONST_INT)
8795
    {
8796
      error ("%qs expects a constant argument", insn_data[icode].name);
8797
      return FALSE;
8798
    }
8799
  if (! (*insn_data[icode].operand[opnum].predicate) (opval, VOIDmode))
8800
    {
8801
      error ("constant argument out of range for %qs", insn_data[icode].name);
8802
      return FALSE;
8803
    }
8804
  return TRUE;
8805
}
8806
 
8807
/* Return a legitimate rtx for instruction ICODE's return value.  Use TARGET
8808
   if it's not null, has the right mode, and satisfies operand 0's
8809
   predicate.  */
8810
 
8811
static rtx
8812
frv_legitimize_target (enum insn_code icode, rtx target)
8813
{
8814
  enum machine_mode mode = insn_data[icode].operand[0].mode;
8815
 
8816
  if (! target
8817
      || GET_MODE (target) != mode
8818
      || ! (*insn_data[icode].operand[0].predicate) (target, mode))
8819
    return gen_reg_rtx (mode);
8820
  else
8821
    return target;
8822
}
8823
 
8824
/* Given that ARG is being passed as operand OPNUM to instruction ICODE,
8825
   check whether ARG satisfies the operand's constraints.  If it doesn't,
8826
   copy ARG to a temporary register and return that.  Otherwise return ARG
8827
   itself.  */
8828
 
8829
static rtx
8830
frv_legitimize_argument (enum insn_code icode, int opnum, rtx arg)
8831
{
8832
  enum machine_mode mode = insn_data[icode].operand[opnum].mode;
8833
 
8834
  if ((*insn_data[icode].operand[opnum].predicate) (arg, mode))
8835
    return arg;
8836
  else
8837
    return copy_to_mode_reg (mode, arg);
8838
}
8839
 
8840
/* Return a volatile memory reference of mode MODE whose address is ARG.  */
8841
 
8842
static rtx
8843
frv_volatile_memref (enum machine_mode mode, rtx arg)
8844
{
8845
  rtx mem;
8846
 
8847
  mem = gen_rtx_MEM (mode, memory_address (mode, arg));
8848
  MEM_VOLATILE_P (mem) = 1;
8849
  return mem;
8850
}
8851
 
8852
/* Expand builtins that take a single, constant argument.  At the moment,
8853
   only MHDSETS falls into this category.  */
8854
 
8855
static rtx
8856
frv_expand_set_builtin (enum insn_code icode, tree call, rtx target)
8857
{
8858
  rtx pat;
8859
  rtx op0 = frv_read_argument (call, 0);
8860
 
8861
  if (! frv_check_constant_argument (icode, 1, op0))
8862
    return NULL_RTX;
8863
 
8864
  target = frv_legitimize_target (icode, target);
8865
  pat = GEN_FCN (icode) (target, op0);
8866
  if (! pat)
8867
    return NULL_RTX;
8868
 
8869
  emit_insn (pat);
8870
  return target;
8871
}
8872
 
8873
/* Expand builtins that take one operand.  */
8874
 
8875
static rtx
8876
frv_expand_unop_builtin (enum insn_code icode, tree call, rtx target)
8877
{
8878
  rtx pat;
8879
  rtx op0 = frv_read_argument (call, 0);
8880
 
8881
  target = frv_legitimize_target (icode, target);
8882
  op0 = frv_legitimize_argument (icode, 1, op0);
8883
  pat = GEN_FCN (icode) (target, op0);
8884
  if (! pat)
8885
    return NULL_RTX;
8886
 
8887
  emit_insn (pat);
8888
  return target;
8889
}
8890
 
8891
/* Expand builtins that take two operands.  */
8892
 
8893
static rtx
8894
frv_expand_binop_builtin (enum insn_code icode, tree call, rtx target)
8895
{
8896
  rtx pat;
8897
  rtx op0 = frv_read_argument (call, 0);
8898
  rtx op1 = frv_read_argument (call, 1);
8899
 
8900
  target = frv_legitimize_target (icode, target);
8901
  op0 = frv_legitimize_argument (icode, 1, op0);
8902
  op1 = frv_legitimize_argument (icode, 2, op1);
8903
  pat = GEN_FCN (icode) (target, op0, op1);
8904
  if (! pat)
8905
    return NULL_RTX;
8906
 
8907
  emit_insn (pat);
8908
  return target;
8909
}
8910
 
8911
/* Expand cut-style builtins, which take two operands and an implicit ACCG
8912
   one.  */
8913
 
8914
static rtx
8915
frv_expand_cut_builtin (enum insn_code icode, tree call, rtx target)
8916
{
8917
  rtx pat;
8918
  rtx op0 = frv_read_argument (call, 0);
8919
  rtx op1 = frv_read_argument (call, 1);
8920
  rtx op2;
8921
 
8922
  target = frv_legitimize_target (icode, target);
8923
  op0 = frv_int_to_acc (icode, 1, op0);
8924
  if (! op0)
8925
    return NULL_RTX;
8926
 
8927
  if (icode == CODE_FOR_mdcutssi || GET_CODE (op1) == CONST_INT)
8928
    {
8929
      if (! frv_check_constant_argument (icode, 2, op1))
8930
        return NULL_RTX;
8931
    }
8932
  else
8933
    op1 = frv_legitimize_argument (icode, 2, op1);
8934
 
8935
  op2 = frv_matching_accg_for_acc (op0);
8936
  pat = GEN_FCN (icode) (target, op0, op1, op2);
8937
  if (! pat)
8938
    return NULL_RTX;
8939
 
8940
  emit_insn (pat);
8941
  return target;
8942
}
8943
 
8944
/* Expand builtins that take two operands and the second is immediate.  */
8945
 
8946
static rtx
8947
frv_expand_binopimm_builtin (enum insn_code icode, tree call, rtx target)
8948
{
8949
  rtx pat;
8950
  rtx op0 = frv_read_argument (call, 0);
8951
  rtx op1 = frv_read_argument (call, 1);
8952
 
8953
  if (! frv_check_constant_argument (icode, 2, op1))
8954
    return NULL_RTX;
8955
 
8956
  target = frv_legitimize_target (icode, target);
8957
  op0 = frv_legitimize_argument (icode, 1, op0);
8958
  pat = GEN_FCN (icode) (target, op0, op1);
8959
  if (! pat)
8960
    return NULL_RTX;
8961
 
8962
  emit_insn (pat);
8963
  return target;
8964
}
8965
 
8966
/* Expand builtins that take two operands, the first operand being a pointer to
8967
   ints and return void.  */
8968
 
8969
static rtx
8970
frv_expand_voidbinop_builtin (enum insn_code icode, tree call)
8971
{
8972
  rtx pat;
8973
  rtx op0 = frv_read_argument (call, 0);
8974
  rtx op1 = frv_read_argument (call, 1);
8975
  enum machine_mode mode0 = insn_data[icode].operand[0].mode;
8976
  rtx addr;
8977
 
8978
  if (GET_CODE (op0) != MEM)
8979
    {
8980
      rtx reg = op0;
8981
 
8982
      if (! offsettable_address_p (0, mode0, op0))
8983
        {
8984
          reg = gen_reg_rtx (Pmode);
8985
          emit_insn (gen_rtx_SET (VOIDmode, reg, op0));
8986
        }
8987
 
8988
      op0 = gen_rtx_MEM (SImode, reg);
8989
    }
8990
 
8991
  addr = XEXP (op0, 0);
8992
  if (! offsettable_address_p (0, mode0, addr))
8993
    addr = copy_to_mode_reg (Pmode, op0);
8994
 
8995
  op0 = change_address (op0, V4SImode, addr);
8996
  op1 = frv_legitimize_argument (icode, 1, op1);
8997
  pat = GEN_FCN (icode) (op0, op1);
8998
  if (! pat)
8999
    return 0;
9000
 
9001
  emit_insn (pat);
9002
  return 0;
9003
}
9004
 
9005
/* Expand builtins that take two long operands and return void.  */
9006
 
9007
static rtx
9008
frv_expand_int_void2arg (enum insn_code icode, tree call)
9009
{
9010
  rtx pat;
9011
  rtx op0 = frv_read_argument (call, 0);
9012
  rtx op1 = frv_read_argument (call, 1);
9013
 
9014
  op0 = frv_legitimize_argument (icode, 1, op0);
9015
  op1 = frv_legitimize_argument (icode, 1, op1);
9016
  pat = GEN_FCN (icode) (op0, op1);
9017
  if (! pat)
9018
    return NULL_RTX;
9019
 
9020
  emit_insn (pat);
9021
  return NULL_RTX;
9022
}
9023
 
9024
/* Expand prefetch builtins.  These take a single address as argument.  */
9025
 
9026
static rtx
9027
frv_expand_prefetches (enum insn_code icode, tree call)
9028
{
9029
  rtx pat;
9030
  rtx op0 = frv_read_argument (call, 0);
9031
 
9032
  pat = GEN_FCN (icode) (force_reg (Pmode, op0));
9033
  if (! pat)
9034
    return 0;
9035
 
9036
  emit_insn (pat);
9037
  return 0;
9038
}
9039
 
9040
/* Expand builtins that take three operands and return void.  The first
9041
   argument must be a constant that describes a pair or quad accumulators.  A
9042
   fourth argument is created that is the accumulator guard register that
9043
   corresponds to the accumulator.  */
9044
 
9045
static rtx
9046
frv_expand_voidtriop_builtin (enum insn_code icode, tree call)
9047
{
9048
  rtx pat;
9049
  rtx op0 = frv_read_argument (call, 0);
9050
  rtx op1 = frv_read_argument (call, 1);
9051
  rtx op2 = frv_read_argument (call, 2);
9052
  rtx op3;
9053
 
9054
  op0 = frv_int_to_acc (icode, 0, op0);
9055
  if (! op0)
9056
    return NULL_RTX;
9057
 
9058
  op1 = frv_legitimize_argument (icode, 1, op1);
9059
  op2 = frv_legitimize_argument (icode, 2, op2);
9060
  op3 = frv_matching_accg_for_acc (op0);
9061
  pat = GEN_FCN (icode) (op0, op1, op2, op3);
9062
  if (! pat)
9063
    return NULL_RTX;
9064
 
9065
  emit_insn (pat);
9066
  return NULL_RTX;
9067
}
9068
 
9069
/* Expand builtins that perform accumulator-to-accumulator operations.
9070
   These builtins take two accumulator numbers as argument and return
9071
   void.  */
9072
 
9073
static rtx
9074
frv_expand_voidaccop_builtin (enum insn_code icode, tree call)
9075
{
9076
  rtx pat;
9077
  rtx op0 = frv_read_argument (call, 0);
9078
  rtx op1 = frv_read_argument (call, 1);
9079
  rtx op2;
9080
  rtx op3;
9081
 
9082
  op0 = frv_int_to_acc (icode, 0, op0);
9083
  if (! op0)
9084
    return NULL_RTX;
9085
 
9086
  op1 = frv_int_to_acc (icode, 1, op1);
9087
  if (! op1)
9088
    return NULL_RTX;
9089
 
9090
  op2 = frv_matching_accg_for_acc (op0);
9091
  op3 = frv_matching_accg_for_acc (op1);
9092
  pat = GEN_FCN (icode) (op0, op1, op2, op3);
9093
  if (! pat)
9094
    return NULL_RTX;
9095
 
9096
  emit_insn (pat);
9097
  return NULL_RTX;
9098
}
9099
 
9100
/* Expand a __builtin_read* function.  ICODE is the instruction code for the
9101
   membar and TARGET_MODE is the mode that the loaded value should have.  */
9102
 
9103
static rtx
9104
frv_expand_load_builtin (enum insn_code icode, enum machine_mode target_mode,
9105
                         tree call, rtx target)
9106
{
9107
  rtx op0 = frv_read_argument (call, 0);
9108
  rtx cookie = frv_io_address_cookie (op0);
9109
 
9110
  if (target == 0 || !REG_P (target))
9111
    target = gen_reg_rtx (target_mode);
9112
  op0 = frv_volatile_memref (insn_data[icode].operand[0].mode, op0);
9113
  convert_move (target, op0, 1);
9114
  emit_insn (GEN_FCN (icode) (copy_rtx (op0), cookie, GEN_INT (FRV_IO_READ)));
9115
  cfun->machine->has_membar_p = 1;
9116
  return target;
9117
}
9118
 
9119
/* Likewise __builtin_write* functions.  */
9120
 
9121
static rtx
9122
frv_expand_store_builtin (enum insn_code icode, tree call)
9123
{
9124
  rtx op0 = frv_read_argument (call, 0);
9125
  rtx op1 = frv_read_argument (call, 1);
9126
  rtx cookie = frv_io_address_cookie (op0);
9127
 
9128
  op0 = frv_volatile_memref (insn_data[icode].operand[0].mode, op0);
9129
  convert_move (op0, force_reg (insn_data[icode].operand[0].mode, op1), 1);
9130
  emit_insn (GEN_FCN (icode) (copy_rtx (op0), cookie, GEN_INT (FRV_IO_WRITE)));
9131
  cfun->machine->has_membar_p = 1;
9132
  return NULL_RTX;
9133
}
9134
 
9135
/* Expand the MDPACKH builtin.  It takes four unsigned short arguments and
9136
   each argument forms one word of the two double-word input registers.
9137
   CALL is the tree for the call and TARGET, if nonnull, suggests a good place
9138
   to put the return value.  */
9139
 
9140
static rtx
9141
frv_expand_mdpackh_builtin (tree call, rtx target)
9142
{
9143
  enum insn_code icode = CODE_FOR_mdpackh;
9144
  rtx pat, op0, op1;
9145
  rtx arg1 = frv_read_argument (call, 0);
9146
  rtx arg2 = frv_read_argument (call, 1);
9147
  rtx arg3 = frv_read_argument (call, 2);
9148
  rtx arg4 = frv_read_argument (call, 3);
9149
 
9150
  target = frv_legitimize_target (icode, target);
9151
  op0 = gen_reg_rtx (DImode);
9152
  op1 = gen_reg_rtx (DImode);
9153
 
9154
  /* The high half of each word is not explicitly initialized, so indicate
9155
     that the input operands are not live before this point.  */
9156
  emit_clobber (op0);
9157
  emit_clobber (op1);
9158
 
9159
  /* Move each argument into the low half of its associated input word.  */
9160
  emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 2), arg1);
9161
  emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 6), arg2);
9162
  emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 2), arg3);
9163
  emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 6), arg4);
9164
 
9165
  pat = GEN_FCN (icode) (target, op0, op1);
9166
  if (! pat)
9167
    return NULL_RTX;
9168
 
9169
  emit_insn (pat);
9170
  return target;
9171
}
9172
 
9173
/* Expand the MCLRACC builtin.  This builtin takes a single accumulator
9174
   number as argument.  */
9175
 
9176
static rtx
9177
frv_expand_mclracc_builtin (tree call)
9178
{
9179
  enum insn_code icode = CODE_FOR_mclracc;
9180
  rtx pat;
9181
  rtx op0 = frv_read_argument (call, 0);
9182
 
9183
  op0 = frv_int_to_acc (icode, 0, op0);
9184
  if (! op0)
9185
    return NULL_RTX;
9186
 
9187
  pat = GEN_FCN (icode) (op0);
9188
  if (pat)
9189
    emit_insn (pat);
9190
 
9191
  return NULL_RTX;
9192
}
9193
 
9194
/* Expand builtins that take no arguments.  */
9195
 
9196
static rtx
9197
frv_expand_noargs_builtin (enum insn_code icode)
9198
{
9199
  rtx pat = GEN_FCN (icode) (const0_rtx);
9200
  if (pat)
9201
    emit_insn (pat);
9202
 
9203
  return NULL_RTX;
9204
}
9205
 
9206
/* Expand MRDACC and MRDACCG.  These builtins take a single accumulator
9207
   number or accumulator guard number as argument and return an SI integer.  */
9208
 
9209
static rtx
9210
frv_expand_mrdacc_builtin (enum insn_code icode, tree call)
9211
{
9212
  rtx pat;
9213
  rtx target = gen_reg_rtx (SImode);
9214
  rtx op0 = frv_read_argument (call, 0);
9215
 
9216
  op0 = frv_int_to_acc (icode, 1, op0);
9217
  if (! op0)
9218
    return NULL_RTX;
9219
 
9220
  pat = GEN_FCN (icode) (target, op0);
9221
  if (! pat)
9222
    return NULL_RTX;
9223
 
9224
  emit_insn (pat);
9225
  return target;
9226
}
9227
 
9228
/* Expand MWTACC and MWTACCG.  These builtins take an accumulator or
9229
   accumulator guard as their first argument and an SImode value as their
9230
   second.  */
9231
 
9232
static rtx
9233
frv_expand_mwtacc_builtin (enum insn_code icode, tree call)
9234
{
9235
  rtx pat;
9236
  rtx op0 = frv_read_argument (call, 0);
9237
  rtx op1 = frv_read_argument (call, 1);
9238
 
9239
  op0 = frv_int_to_acc (icode, 0, op0);
9240
  if (! op0)
9241
    return NULL_RTX;
9242
 
9243
  op1 = frv_legitimize_argument (icode, 1, op1);
9244
  pat = GEN_FCN (icode) (op0, op1);
9245
  if (pat)
9246
    emit_insn (pat);
9247
 
9248
  return NULL_RTX;
9249
}
9250
 
9251
/* Emit a move from SRC to DEST in SImode chunks.  This can be used
9252
   to move DImode values into and out of IACC0.  */
9253
 
9254
static void
9255
frv_split_iacc_move (rtx dest, rtx src)
9256
{
9257
  enum machine_mode inner;
9258
  int i;
9259
 
9260
  inner = GET_MODE (dest);
9261
  for (i = 0; i < GET_MODE_SIZE (inner); i += GET_MODE_SIZE (SImode))
9262
    emit_move_insn (simplify_gen_subreg (SImode, dest, inner, i),
9263
                    simplify_gen_subreg (SImode, src, inner, i));
9264
}
9265
 
9266
/* Expand builtins.  */
9267
 
9268
static rtx
9269
frv_expand_builtin (tree exp,
9270
                    rtx target,
9271
                    rtx subtarget ATTRIBUTE_UNUSED,
9272
                    enum machine_mode mode ATTRIBUTE_UNUSED,
9273
                    int ignore ATTRIBUTE_UNUSED)
9274
{
9275
  tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
9276
  unsigned fcode = (unsigned)DECL_FUNCTION_CODE (fndecl);
9277
  unsigned i;
9278
  struct builtin_description *d;
9279
 
9280
  if (fcode < FRV_BUILTIN_FIRST_NONMEDIA && !TARGET_MEDIA)
9281
    {
9282
      error ("media functions are not available unless -mmedia is used");
9283
      return NULL_RTX;
9284
    }
9285
 
9286
  switch (fcode)
9287
    {
9288
    case FRV_BUILTIN_MCOP1:
9289
    case FRV_BUILTIN_MCOP2:
9290
    case FRV_BUILTIN_MDUNPACKH:
9291
    case FRV_BUILTIN_MBTOHE:
9292
      if (! TARGET_MEDIA_REV1)
9293
        {
9294
          error ("this media function is only available on the fr500");
9295
          return NULL_RTX;
9296
        }
9297
      break;
9298
 
9299
    case FRV_BUILTIN_MQXMACHS:
9300
    case FRV_BUILTIN_MQXMACXHS:
9301
    case FRV_BUILTIN_MQMACXHS:
9302
    case FRV_BUILTIN_MADDACCS:
9303
    case FRV_BUILTIN_MSUBACCS:
9304
    case FRV_BUILTIN_MASACCS:
9305
    case FRV_BUILTIN_MDADDACCS:
9306
    case FRV_BUILTIN_MDSUBACCS:
9307
    case FRV_BUILTIN_MDASACCS:
9308
    case FRV_BUILTIN_MABSHS:
9309
    case FRV_BUILTIN_MDROTLI:
9310
    case FRV_BUILTIN_MCPLHI:
9311
    case FRV_BUILTIN_MCPLI:
9312
    case FRV_BUILTIN_MDCUTSSI:
9313
    case FRV_BUILTIN_MQSATHS:
9314
    case FRV_BUILTIN_MHSETLOS:
9315
    case FRV_BUILTIN_MHSETLOH:
9316
    case FRV_BUILTIN_MHSETHIS:
9317
    case FRV_BUILTIN_MHSETHIH:
9318
    case FRV_BUILTIN_MHDSETS:
9319
    case FRV_BUILTIN_MHDSETH:
9320
      if (! TARGET_MEDIA_REV2)
9321
        {
9322
          error ("this media function is only available on the fr400"
9323
                 " and fr550");
9324
          return NULL_RTX;
9325
        }
9326
      break;
9327
 
9328
    case FRV_BUILTIN_SMASS:
9329
    case FRV_BUILTIN_SMSSS:
9330
    case FRV_BUILTIN_SMU:
9331
    case FRV_BUILTIN_ADDSS:
9332
    case FRV_BUILTIN_SUBSS:
9333
    case FRV_BUILTIN_SLASS:
9334
    case FRV_BUILTIN_SCUTSS:
9335
    case FRV_BUILTIN_IACCreadll:
9336
    case FRV_BUILTIN_IACCreadl:
9337
    case FRV_BUILTIN_IACCsetll:
9338
    case FRV_BUILTIN_IACCsetl:
9339
      if (!TARGET_FR405_BUILTINS)
9340
        {
9341
          error ("this builtin function is only available"
9342
                 " on the fr405 and fr450");
9343
          return NULL_RTX;
9344
        }
9345
      break;
9346
 
9347
    case FRV_BUILTIN_PREFETCH:
9348
      if (!TARGET_FR500_FR550_BUILTINS)
9349
        {
9350
          error ("this builtin function is only available on the fr500"
9351
                 " and fr550");
9352
          return NULL_RTX;
9353
        }
9354
      break;
9355
 
9356
    case FRV_BUILTIN_MQLCLRHS:
9357
    case FRV_BUILTIN_MQLMTHS:
9358
    case FRV_BUILTIN_MQSLLHI:
9359
    case FRV_BUILTIN_MQSRAHI:
9360
      if (!TARGET_MEDIA_FR450)
9361
        {
9362
          error ("this builtin function is only available on the fr450");
9363
          return NULL_RTX;
9364
        }
9365
      break;
9366
 
9367
    default:
9368
      break;
9369
    }
9370
 
9371
  /* Expand unique builtins.  */
9372
 
9373
  switch (fcode)
9374
    {
9375
    case FRV_BUILTIN_MTRAP:
9376
      return frv_expand_noargs_builtin (CODE_FOR_mtrap);
9377
 
9378
    case FRV_BUILTIN_MCLRACC:
9379
      return frv_expand_mclracc_builtin (exp);
9380
 
9381
    case FRV_BUILTIN_MCLRACCA:
9382
      if (TARGET_ACC_8)
9383
        return frv_expand_noargs_builtin (CODE_FOR_mclracca8);
9384
      else
9385
        return frv_expand_noargs_builtin (CODE_FOR_mclracca4);
9386
 
9387
    case FRV_BUILTIN_MRDACC:
9388
      return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc, exp);
9389
 
9390
    case FRV_BUILTIN_MRDACCG:
9391
      return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg, exp);
9392
 
9393
    case FRV_BUILTIN_MWTACC:
9394
      return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc, exp);
9395
 
9396
    case FRV_BUILTIN_MWTACCG:
9397
      return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg, exp);
9398
 
9399
    case FRV_BUILTIN_MDPACKH:
9400
      return frv_expand_mdpackh_builtin (exp, target);
9401
 
9402
    case FRV_BUILTIN_IACCreadll:
9403
      {
9404
        rtx src = frv_read_iacc_argument (DImode, exp, 0);
9405
        if (target == 0 || !REG_P (target))
9406
          target = gen_reg_rtx (DImode);
9407
        frv_split_iacc_move (target, src);
9408
        return target;
9409
      }
9410
 
9411
    case FRV_BUILTIN_IACCreadl:
9412
      return frv_read_iacc_argument (SImode, exp, 0);
9413
 
9414
    case FRV_BUILTIN_IACCsetll:
9415
      {
9416
        rtx dest = frv_read_iacc_argument (DImode, exp, 0);
9417
        rtx src = frv_read_argument (exp, 1);
9418
        frv_split_iacc_move (dest, force_reg (DImode, src));
9419
        return 0;
9420
      }
9421
 
9422
    case FRV_BUILTIN_IACCsetl:
9423
      {
9424
        rtx dest = frv_read_iacc_argument (SImode, exp, 0);
9425
        rtx src = frv_read_argument (exp, 1);
9426
        emit_move_insn (dest, force_reg (SImode, src));
9427
        return 0;
9428
      }
9429
 
9430
    default:
9431
      break;
9432
    }
9433
 
9434
  /* Expand groups of builtins.  */
9435
 
9436
  for (i = 0, d = bdesc_set; i < ARRAY_SIZE (bdesc_set); i++, d++)
9437
    if (d->code == fcode)
9438
      return frv_expand_set_builtin (d->icode, exp, target);
9439
 
9440
  for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
9441
    if (d->code == fcode)
9442
      return frv_expand_unop_builtin (d->icode, exp, target);
9443
 
9444
  for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
9445
    if (d->code == fcode)
9446
      return frv_expand_binop_builtin (d->icode, exp, target);
9447
 
9448
  for (i = 0, d = bdesc_cut; i < ARRAY_SIZE (bdesc_cut); i++, d++)
9449
    if (d->code == fcode)
9450
      return frv_expand_cut_builtin (d->icode, exp, target);
9451
 
9452
  for (i = 0, d = bdesc_2argimm; i < ARRAY_SIZE (bdesc_2argimm); i++, d++)
9453
    if (d->code == fcode)
9454
      return frv_expand_binopimm_builtin (d->icode, exp, target);
9455
 
9456
  for (i = 0, d = bdesc_void2arg; i < ARRAY_SIZE (bdesc_void2arg); i++, d++)
9457
    if (d->code == fcode)
9458
      return frv_expand_voidbinop_builtin (d->icode, exp);
9459
 
9460
  for (i = 0, d = bdesc_void3arg; i < ARRAY_SIZE (bdesc_void3arg); i++, d++)
9461
    if (d->code == fcode)
9462
      return frv_expand_voidtriop_builtin (d->icode, exp);
9463
 
9464
  for (i = 0, d = bdesc_voidacc; i < ARRAY_SIZE (bdesc_voidacc); i++, d++)
9465
    if (d->code == fcode)
9466
      return frv_expand_voidaccop_builtin (d->icode, exp);
9467
 
9468
  for (i = 0, d = bdesc_int_void2arg;
9469
       i < ARRAY_SIZE (bdesc_int_void2arg); i++, d++)
9470
    if (d->code == fcode)
9471
      return frv_expand_int_void2arg (d->icode, exp);
9472
 
9473
  for (i = 0, d = bdesc_prefetches;
9474
       i < ARRAY_SIZE (bdesc_prefetches); i++, d++)
9475
    if (d->code == fcode)
9476
      return frv_expand_prefetches (d->icode, exp);
9477
 
9478
  for (i = 0, d = bdesc_loads; i < ARRAY_SIZE (bdesc_loads); i++, d++)
9479
    if (d->code == fcode)
9480
      return frv_expand_load_builtin (d->icode, TYPE_MODE (TREE_TYPE (exp)),
9481
                                      exp, target);
9482
 
9483
  for (i = 0, d = bdesc_stores; i < ARRAY_SIZE (bdesc_stores); i++, d++)
9484
    if (d->code == fcode)
9485
      return frv_expand_store_builtin (d->icode, exp);
9486
 
9487
  return 0;
9488
}
9489
 
9490
static bool
9491
frv_in_small_data_p (const_tree decl)
9492
{
9493
  HOST_WIDE_INT size;
9494
  const_tree section_name;
9495
 
9496
  /* Don't apply the -G flag to internal compiler structures.  We
9497
     should leave such structures in the main data section, partly
9498
     for efficiency and partly because the size of some of them
9499
     (such as C++ typeinfos) is not known until later.  */
9500
  if (TREE_CODE (decl) != VAR_DECL || DECL_ARTIFICIAL (decl))
9501
    return false;
9502
 
9503
  /* If we already know which section the decl should be in, see if
9504
     it's a small data section.  */
9505
  section_name = DECL_SECTION_NAME (decl);
9506
  if (section_name)
9507
    {
9508
      gcc_assert (TREE_CODE (section_name) == STRING_CST);
9509
      if (frv_string_begins_with (section_name, ".sdata"))
9510
        return true;
9511
      if (frv_string_begins_with (section_name, ".sbss"))
9512
        return true;
9513
      return false;
9514
    }
9515
 
9516
  size = int_size_in_bytes (TREE_TYPE (decl));
9517
  if (size > 0 && size <= g_switch_value)
9518
    return true;
9519
 
9520
  return false;
9521
}
9522
 
9523
static bool
9524
frv_rtx_costs (rtx x,
9525
               int code ATTRIBUTE_UNUSED,
9526
               int outer_code ATTRIBUTE_UNUSED,
9527
               int opno ATTRIBUTE_UNUSED,
9528
               int *total,
9529
               bool speed ATTRIBUTE_UNUSED)
9530
{
9531
  if (outer_code == MEM)
9532
    {
9533
      /* Don't differentiate between memory addresses.  All the ones
9534
         we accept have equal cost.  */
9535
      *total = COSTS_N_INSNS (0);
9536
      return true;
9537
    }
9538
 
9539
  switch (code)
9540
    {
9541
    case CONST_INT:
9542
      /* Make 12-bit integers really cheap.  */
9543
      if (IN_RANGE (INTVAL (x), -2048, 2047))
9544
        {
9545
          *total = 0;
9546
          return true;
9547
        }
9548
      /* Fall through.  */
9549
 
9550
    case CONST:
9551
    case LABEL_REF:
9552
    case SYMBOL_REF:
9553
    case CONST_DOUBLE:
9554
      *total = COSTS_N_INSNS (2);
9555
      return true;
9556
 
9557
    case PLUS:
9558
    case MINUS:
9559
    case AND:
9560
    case IOR:
9561
    case XOR:
9562
    case ASHIFT:
9563
    case ASHIFTRT:
9564
    case LSHIFTRT:
9565
    case NOT:
9566
    case NEG:
9567
    case COMPARE:
9568
      if (GET_MODE (x) == SImode)
9569
        *total = COSTS_N_INSNS (1);
9570
      else if (GET_MODE (x) == DImode)
9571
        *total = COSTS_N_INSNS (2);
9572
      else
9573
        *total = COSTS_N_INSNS (3);
9574
      return true;
9575
 
9576
    case MULT:
9577
      if (GET_MODE (x) == SImode)
9578
        *total = COSTS_N_INSNS (2);
9579
      else
9580
        *total = COSTS_N_INSNS (6);     /* guess */
9581
      return true;
9582
 
9583
    case DIV:
9584
    case UDIV:
9585
    case MOD:
9586
    case UMOD:
9587
      *total = COSTS_N_INSNS (18);
9588
      return true;
9589
 
9590
    case MEM:
9591
      *total = COSTS_N_INSNS (3);
9592
      return true;
9593
 
9594
    default:
9595
      return false;
9596
    }
9597
}
9598
 
9599
static void
9600
frv_asm_out_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9601
{
9602
  switch_to_section (ctors_section);
9603
  assemble_align (POINTER_SIZE);
9604
  if (TARGET_FDPIC)
9605
    {
9606
      int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1);
9607
 
9608
      gcc_assert (ok);
9609
      return;
9610
    }
9611
  assemble_integer_with_op ("\t.picptr\t", symbol);
9612
}
9613
 
9614
static void
9615
frv_asm_out_destructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9616
{
9617
  switch_to_section (dtors_section);
9618
  assemble_align (POINTER_SIZE);
9619
  if (TARGET_FDPIC)
9620
    {
9621
      int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1);
9622
 
9623
      gcc_assert (ok);
9624
      return;
9625
    }
9626
  assemble_integer_with_op ("\t.picptr\t", symbol);
9627
}
9628
 
9629
/* Worker function for TARGET_STRUCT_VALUE_RTX.  */
9630
 
9631
static rtx
9632
frv_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
9633
                      int incoming ATTRIBUTE_UNUSED)
9634
{
9635
  return gen_rtx_REG (Pmode, FRV_STRUCT_VALUE_REGNUM);
9636
}
9637
 
9638
#define TLS_BIAS (2048 - 16)
9639
 
9640
/* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
9641
   We need to emit DTP-relative relocations.  */
9642
 
9643
static void
9644
frv_output_dwarf_dtprel (FILE *file, int size, rtx x)
9645
{
9646
  gcc_assert (size == 4);
9647
  fputs ("\t.picptr\ttlsmoff(", file);
9648
  /* We want the unbiased TLS offset, so add the bias to the
9649
     expression, such that the implicit biasing cancels out.  */
9650
  output_addr_const (file, plus_constant (x, TLS_BIAS));
9651
  fputs (")", file);
9652
}
9653
 
9654
#include "gt-frv.h"

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.