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jeremybenn |
/* Target macros for the FRV port of GCC.
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Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009,
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2010, 2011
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Free Software Foundation, Inc.
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Contributed by Red Hat Inc.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published
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by the Free Software Foundation; either version 3, or (at your
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option) any later version.
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GCC is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with GCC; see the file COPYING3. If not see
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<http://www.gnu.org/licenses/>. */
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#ifndef __FRV_H__
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#define __FRV_H__
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/* Frv general purpose macros. */
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/* Align an address. */
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#define ADDR_ALIGN(addr,align) (((addr) + (align) - 1) & ~((align) - 1))
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/* Driver configuration. */
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/* -fpic and -fPIC used to imply the -mlibrary-pic multilib, but with
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FDPIC which multilib to use depends on whether FDPIC is in use or
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not. The trick we use is to introduce -multilib-library-pic as a
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pseudo-flag that selects the library-pic multilib, and map fpic
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and fPIC to it only if fdpic is not selected. Also, if fdpic is
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selected and no PIC/PIE options are present, we imply -fPIE.
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Otherwise, if -fpic or -fPIC are enabled and we're optimizing for
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speed, or if we have -On with n>=3, enable inlining of PLTs. As
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for -mgprel-ro, we want to enable it by default, but not for -fpic or
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-fpie. */
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#define DRIVER_SELF_SPECS SUBTARGET_DRIVER_SELF_SPECS \
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"%{mno-pack:\
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%{!mhard-float:-msoft-float}\
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%{!mmedia:-mno-media}}\
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%{!mfdpic:%{fpic|fPIC: -multilib-library-pic}}\
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%{mfdpic:%{!fpic:%{!fpie:%{!fPIC:%{!fPIE:\
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%{!fno-pic:%{!fno-pie:%{!fno-PIC:%{!fno-PIE:-fPIE}}}}}}}} \
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%{!mno-inline-plt:%{O*:%{!O0:%{!Os:%{fpic|fPIC:-minline-plt} \
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%{!fpic:%{!fPIC:%{!O:%{!O1:%{!O2:-minline-plt}}}}}}}}} \
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%{!mno-gprel-ro:%{!fpic:%{!fpie:-mgprel-ro}}}} \
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"
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#ifndef SUBTARGET_DRIVER_SELF_SPECS
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# define SUBTARGET_DRIVER_SELF_SPECS
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#endif
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#undef ASM_SPEC
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#define ASM_SPEC "\
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%{G*} \
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%{mtomcat-stats} \
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%{!mno-eflags: \
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%{mcpu=*} \
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%{mgpr-*} %{mfpr-*} \
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%{msoft-float} %{mhard-float} \
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%{mdword} %{mno-dword} \
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%{mdouble} %{mno-double} \
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%{mmedia} %{mno-media} \
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%{mmuladd} %{mno-muladd} \
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%{mpack} %{mno-pack} \
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%{mno-fdpic:-mnopic} %{mfdpic} \
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%{fpic|fpie: -mpic} %{fPIC|fPIE: -mPIC} %{mlibrary-pic}}"
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#undef STARTFILE_SPEC
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#define STARTFILE_SPEC "crt0%O%s frvbegin%O%s"
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#undef ENDFILE_SPEC
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#define ENDFILE_SPEC "frvend%O%s"
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#define MASK_DEFAULT_FRV \
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(MASK_MEDIA \
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| MASK_DOUBLE \
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| MASK_MULADD \
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| MASK_DWORD \
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| MASK_PACK)
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#define MASK_DEFAULT_FR500 \
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(MASK_MEDIA | MASK_DWORD | MASK_PACK)
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#define MASK_DEFAULT_FR550 \
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(MASK_MEDIA | MASK_DWORD | MASK_PACK)
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#define MASK_DEFAULT_FR450 \
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(MASK_GPR_32 \
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| MASK_FPR_32 \
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| MASK_MEDIA \
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| MASK_SOFT_FLOAT \
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| MASK_DWORD \
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| MASK_PACK)
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#define MASK_DEFAULT_FR400 \
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(MASK_GPR_32 \
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| MASK_FPR_32 \
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| MASK_MEDIA \
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| MASK_ACC_4 \
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| MASK_SOFT_FLOAT \
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| MASK_DWORD \
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| MASK_PACK)
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#define MASK_DEFAULT_SIMPLE \
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(MASK_GPR_32 | MASK_SOFT_FLOAT)
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/* A C string constant that tells the GCC driver program options to pass to
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`cc1'. It can also specify how to translate options you give to GCC into
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options for GCC to pass to the `cc1'.
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Do not define this macro if it does not need to do anything. */
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/* For ABI compliance, we need to put bss data into the normal data section. */
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#define CC1_SPEC "%{G*}"
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#undef LINK_SPEC
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#define LINK_SPEC "\
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%{h*} %{v:-V} \
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%{mfdpic:-melf32frvfd -z text} \
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%{static:-dn -Bstatic} \
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%{shared:-Bdynamic} \
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%{symbolic:-Bsymbolic} \
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%{G*}"
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#undef LIB_SPEC
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#define LIB_SPEC "--start-group -lc -lsim --end-group"
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#ifndef CPU_TYPE
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#define CPU_TYPE FRV_CPU_FR500
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#endif
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/* Run-time target specifications */
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#define TARGET_CPU_CPP_BUILTINS() \
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do \
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{ \
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int issue_rate; \
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\
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builtin_define ("__frv__"); \
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builtin_assert ("machine=frv"); \
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\
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issue_rate = frv_issue_rate (); \
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if (issue_rate > 1) \
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builtin_define_with_int_value ("__FRV_VLIW__", issue_rate); \
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builtin_define_with_int_value ("__FRV_GPR__", NUM_GPRS); \
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builtin_define_with_int_value ("__FRV_FPR__", NUM_FPRS); \
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builtin_define_with_int_value ("__FRV_ACC__", NUM_ACCS); \
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\
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switch (frv_cpu_type) \
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{ \
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case FRV_CPU_GENERIC: \
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builtin_define ("__CPU_GENERIC__"); \
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break; \
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case FRV_CPU_FR550: \
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builtin_define ("__CPU_FR550__"); \
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break; \
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case FRV_CPU_FR500: \
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case FRV_CPU_TOMCAT: \
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builtin_define ("__CPU_FR500__"); \
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break; \
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case FRV_CPU_FR450: \
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builtin_define ("__CPU_FR450__"); \
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break; \
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case FRV_CPU_FR405: \
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builtin_define ("__CPU_FR405__"); \
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break; \
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case FRV_CPU_FR400: \
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builtin_define ("__CPU_FR400__"); \
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break; \
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case FRV_CPU_FR300: \
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case FRV_CPU_SIMPLE: \
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builtin_define ("__CPU_FR300__"); \
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break; \
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} \
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\
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if (TARGET_HARD_FLOAT) \
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builtin_define ("__FRV_HARD_FLOAT__"); \
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if (TARGET_DWORD) \
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builtin_define ("__FRV_DWORD__"); \
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if (TARGET_FDPIC) \
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builtin_define ("__FRV_FDPIC__"); \
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if (flag_leading_underscore > 0) \
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builtin_define ("__FRV_UNDERSCORE__"); \
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} \
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while (0)
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#define TARGET_HAS_FPRS (TARGET_HARD_FLOAT || TARGET_MEDIA)
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#define NUM_GPRS (TARGET_GPR_32? 32 : 64)
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#define NUM_FPRS (!TARGET_HAS_FPRS? 0 : TARGET_FPR_32? 32 : 64)
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#define NUM_ACCS (!TARGET_MEDIA? 0 : TARGET_ACC_4? 4 : 8)
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/* X is a valid accumulator number if (X & ACC_MASK) == X. */
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#define ACC_MASK \
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(!TARGET_MEDIA ? 0 \
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: TARGET_ACC_4 ? 3 \
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: frv_cpu_type == FRV_CPU_FR450 ? 11 \
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: 7)
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/* Macros to identify the blend of media instructions available. Revision 1
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is the one found on the FR500. Revision 2 includes the changes made for
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the FR400.
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Treat the generic processor as a revision 1 machine for now, for
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compatibility with earlier releases. */
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#define TARGET_MEDIA_REV1 \
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(TARGET_MEDIA \
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&& (frv_cpu_type == FRV_CPU_GENERIC \
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|| frv_cpu_type == FRV_CPU_FR500))
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#define TARGET_MEDIA_REV2 \
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(TARGET_MEDIA \
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&& (frv_cpu_type == FRV_CPU_FR400 \
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|| frv_cpu_type == FRV_CPU_FR405 \
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|| frv_cpu_type == FRV_CPU_FR450 \
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|| frv_cpu_type == FRV_CPU_FR550))
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#define TARGET_MEDIA_FR450 \
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(frv_cpu_type == FRV_CPU_FR450)
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#define TARGET_FR500_FR550_BUILTINS \
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(frv_cpu_type == FRV_CPU_FR500 \
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|| frv_cpu_type == FRV_CPU_FR550)
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#define TARGET_FR405_BUILTINS \
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(frv_cpu_type == FRV_CPU_FR405 \
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|| frv_cpu_type == FRV_CPU_FR450)
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#ifndef HAVE_AS_TLS
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#define HAVE_AS_TLS 0
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#endif
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#define LABEL_ALIGN_AFTER_BARRIER(LABEL) (TARGET_ALIGN_LABELS ? 3 : 0)
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/* Small Data Area Support. */
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/* Maximum size of variables that go in .sdata/.sbss.
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The -msdata=foo switch also controls how small variables are handled. */
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#ifndef SDATA_DEFAULT_SIZE
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#define SDATA_DEFAULT_SIZE 8
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#endif
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/* Storage Layout */
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/* Define this macro to have the value 1 if the most significant bit in a byte
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has the lowest number; otherwise define it to have the value zero. This
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means that bit-field instructions count from the most significant bit. If
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the machine has no bit-field instructions, then this must still be defined,
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but it doesn't matter which value it is defined to. This macro need not be
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a constant.
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This macro does not affect the way structure fields are packed into bytes or
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words; that is controlled by `BYTES_BIG_ENDIAN'. */
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#define BITS_BIG_ENDIAN 1
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| 264 |
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/* Define this macro to have the value 1 if the most significant byte in a word
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| 265 |
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has the lowest number. This macro need not be a constant. */
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| 266 |
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#define BYTES_BIG_ENDIAN 1
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| 267 |
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| 268 |
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/* Define this macro to have the value 1 if, in a multiword object, the most
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| 269 |
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significant word has the lowest number. This applies to both memory
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locations and registers; GCC fundamentally assumes that the order of
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| 271 |
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words in memory is the same as the order in registers. This macro need not
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be a constant. */
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| 273 |
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#define WORDS_BIG_ENDIAN 1
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| 274 |
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| 275 |
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/* Number of storage units in a word; normally 4. */
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| 276 |
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#define UNITS_PER_WORD 4
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| 277 |
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| 278 |
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/* A macro to update MODE and UNSIGNEDP when an object whose type is TYPE and
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| 279 |
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which has the specified mode and signedness is to be stored in a register.
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| 280 |
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This macro is only called when TYPE is a scalar type.
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| 281 |
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| 282 |
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On most RISC machines, which only have operations that operate on a full
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| 283 |
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register, define this macro to set M to `word_mode' if M is an integer mode
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| 284 |
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narrower than `BITS_PER_WORD'. In most cases, only integer modes should be
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| 285 |
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widened because wider-precision floating-point operations are usually more
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| 286 |
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expensive than their narrower counterparts.
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| 287 |
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| 288 |
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For most machines, the macro definition does not change UNSIGNEDP. However,
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| 289 |
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some machines, have instructions that preferentially handle either signed or
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| 290 |
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unsigned quantities of certain modes. For example, on the DEC Alpha, 32-bit
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| 291 |
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loads from memory and 32-bit add instructions sign-extend the result to 64
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| 292 |
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bits. On such machines, set UNSIGNEDP according to which kind of extension
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| 293 |
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is more efficient.
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| 294 |
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| 295 |
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Do not define this macro if it would never modify MODE. */
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| 296 |
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#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
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| 297 |
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do \
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| 298 |
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{ \
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| 299 |
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if (GET_MODE_CLASS (MODE) == MODE_INT \
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| 300 |
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&& GET_MODE_SIZE (MODE) < 4) \
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| 301 |
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(MODE) = SImode; \
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| 302 |
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} \
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| 303 |
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while (0)
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| 304 |
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| 305 |
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/* Normal alignment required for function parameters on the stack, in bits.
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| 306 |
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All stack parameters receive at least this much alignment regardless of data
|
| 307 |
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type. On most machines, this is the same as the size of an integer. */
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| 308 |
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#define PARM_BOUNDARY 32
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| 309 |
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| 310 |
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/* Define this macro if you wish to preserve a certain alignment for the stack
|
| 311 |
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pointer. The definition is a C expression for the desired alignment
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| 312 |
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(measured in bits).
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| 313 |
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| 314 |
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If `PUSH_ROUNDING' is not defined, the stack will always be aligned to the
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| 315 |
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specified boundary. If `PUSH_ROUNDING' is defined and specifies a less
|
| 316 |
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strict alignment than `STACK_BOUNDARY', the stack may be momentarily
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| 317 |
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unaligned while pushing arguments. */
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| 318 |
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#define STACK_BOUNDARY 64
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| 319 |
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| 320 |
|
|
/* Alignment required for a function entry point, in bits. */
|
| 321 |
|
|
#define FUNCTION_BOUNDARY 128
|
| 322 |
|
|
|
| 323 |
|
|
/* Biggest alignment that any data type can require on this machine,
|
| 324 |
|
|
in bits. */
|
| 325 |
|
|
#define BIGGEST_ALIGNMENT 64
|
| 326 |
|
|
|
| 327 |
|
|
/* @@@ A hack, needed because libobjc wants to use ADJUST_FIELD_ALIGN for
|
| 328 |
|
|
some reason. */
|
| 329 |
|
|
#ifdef IN_TARGET_LIBS
|
| 330 |
|
|
#define BIGGEST_FIELD_ALIGNMENT 64
|
| 331 |
|
|
#else
|
| 332 |
|
|
/* An expression for the alignment of a structure field FIELD if the
|
| 333 |
|
|
alignment computed in the usual way is COMPUTED. GCC uses this
|
| 334 |
|
|
value instead of the value in `BIGGEST_ALIGNMENT' or
|
| 335 |
|
|
`BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
|
| 336 |
|
|
#define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
|
| 337 |
|
|
frv_adjust_field_align (FIELD, COMPUTED)
|
| 338 |
|
|
#endif
|
| 339 |
|
|
|
| 340 |
|
|
/* If defined, a C expression to compute the alignment for a static variable.
|
| 341 |
|
|
TYPE is the data type, and ALIGN is the alignment that the object
|
| 342 |
|
|
would ordinarily have. The value of this macro is used instead of that
|
| 343 |
|
|
alignment to align the object.
|
| 344 |
|
|
|
| 345 |
|
|
If this macro is not defined, then ALIGN is used.
|
| 346 |
|
|
|
| 347 |
|
|
One use of this macro is to increase alignment of medium-size data to make
|
| 348 |
|
|
it all fit in fewer cache lines. Another is to cause character arrays to be
|
| 349 |
|
|
word-aligned so that `strcpy' calls that copy constants to character arrays
|
| 350 |
|
|
can be done inline. */
|
| 351 |
|
|
#define DATA_ALIGNMENT(TYPE, ALIGN) \
|
| 352 |
|
|
(TREE_CODE (TYPE) == ARRAY_TYPE \
|
| 353 |
|
|
&& TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
|
| 354 |
|
|
&& (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
|
| 355 |
|
|
|
| 356 |
|
|
/* If defined, a C expression to compute the alignment given to a constant that
|
| 357 |
|
|
is being placed in memory. CONSTANT is the constant and ALIGN is the
|
| 358 |
|
|
alignment that the object would ordinarily have. The value of this macro is
|
| 359 |
|
|
used instead of that alignment to align the object.
|
| 360 |
|
|
|
| 361 |
|
|
If this macro is not defined, then ALIGN is used.
|
| 362 |
|
|
|
| 363 |
|
|
The typical use of this macro is to increase alignment for string constants
|
| 364 |
|
|
to be word aligned so that `strcpy' calls that copy constants can be done
|
| 365 |
|
|
inline. */
|
| 366 |
|
|
#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
|
| 367 |
|
|
(TREE_CODE (EXP) == STRING_CST \
|
| 368 |
|
|
&& (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
|
| 369 |
|
|
|
| 370 |
|
|
/* Define this macro to be the value 1 if instructions will fail to work if
|
| 371 |
|
|
given data not on the nominal alignment. If instructions will merely go
|
| 372 |
|
|
slower in that case, define this macro as 0. */
|
| 373 |
|
|
#define STRICT_ALIGNMENT 1
|
| 374 |
|
|
|
| 375 |
|
|
#define PCC_BITFIELD_TYPE_MATTERS 1
|
| 376 |
|
|
|
| 377 |
|
|
|
| 378 |
|
|
/* Layout of Source Language Data Types. */
|
| 379 |
|
|
|
| 380 |
|
|
#define CHAR_TYPE_SIZE 8
|
| 381 |
|
|
#define SHORT_TYPE_SIZE 16
|
| 382 |
|
|
#define INT_TYPE_SIZE 32
|
| 383 |
|
|
#define LONG_TYPE_SIZE 32
|
| 384 |
|
|
#define LONG_LONG_TYPE_SIZE 64
|
| 385 |
|
|
#define FLOAT_TYPE_SIZE 32
|
| 386 |
|
|
#define DOUBLE_TYPE_SIZE 64
|
| 387 |
|
|
#define LONG_DOUBLE_TYPE_SIZE 64
|
| 388 |
|
|
|
| 389 |
|
|
/* An expression whose value is 1 or 0, according to whether the type `char'
|
| 390 |
|
|
should be signed or unsigned by default. The user can always override this
|
| 391 |
|
|
default with the options `-fsigned-char' and `-funsigned-char'. */
|
| 392 |
|
|
#define DEFAULT_SIGNED_CHAR 1
|
| 393 |
|
|
|
| 394 |
|
|
#undef SIZE_TYPE
|
| 395 |
|
|
#define SIZE_TYPE "unsigned int"
|
| 396 |
|
|
|
| 397 |
|
|
#undef PTRDIFF_TYPE
|
| 398 |
|
|
#define PTRDIFF_TYPE "int"
|
| 399 |
|
|
|
| 400 |
|
|
#undef WCHAR_TYPE
|
| 401 |
|
|
#define WCHAR_TYPE "long int"
|
| 402 |
|
|
|
| 403 |
|
|
#undef WCHAR_TYPE_SIZE
|
| 404 |
|
|
#define WCHAR_TYPE_SIZE BITS_PER_WORD
|
| 405 |
|
|
|
| 406 |
|
|
|
| 407 |
|
|
/* General purpose registers. */
|
| 408 |
|
|
#define GPR_FIRST 0 /* First gpr */
|
| 409 |
|
|
#define GPR_LAST (GPR_FIRST + 63) /* Last gpr */
|
| 410 |
|
|
#define GPR_R0 GPR_FIRST /* R0, constant 0 */
|
| 411 |
|
|
#define GPR_FP (GPR_FIRST + 2) /* Frame pointer */
|
| 412 |
|
|
#define GPR_SP (GPR_FIRST + 1) /* Stack pointer */
|
| 413 |
|
|
/* small data register */
|
| 414 |
|
|
#define SDA_BASE_REG ((unsigned)(TARGET_FDPIC ? -1 : flag_pic ? PIC_REGNO : (GPR_FIRST + 16)))
|
| 415 |
|
|
#define PIC_REGNO (GPR_FIRST + (TARGET_FDPIC?15:17)) /* PIC register. */
|
| 416 |
|
|
#define FDPIC_FPTR_REGNO (GPR_FIRST + 14) /* uClinux PIC function pointer register. */
|
| 417 |
|
|
#define FDPIC_REGNO (GPR_FIRST + 15) /* uClinux PIC register. */
|
| 418 |
|
|
|
| 419 |
|
|
#define HARD_REGNO_RENAME_OK(from,to) (TARGET_FDPIC ? ((to) != FDPIC_REG) : 1)
|
| 420 |
|
|
|
| 421 |
|
|
#define OUR_FDPIC_REG get_hard_reg_initial_val (SImode, FDPIC_REGNO)
|
| 422 |
|
|
|
| 423 |
|
|
#define FPR_FIRST 64 /* First FP reg */
|
| 424 |
|
|
#define FPR_LAST 127 /* Last FP reg */
|
| 425 |
|
|
|
| 426 |
|
|
#define GPR_TEMP_NUM frv_condexec_temps /* # gprs to reserve for temps */
|
| 427 |
|
|
|
| 428 |
|
|
/* We reserve the last CR and CCR in each category to be used as a reload
|
| 429 |
|
|
register to reload the CR/CCR registers. This is a kludge. */
|
| 430 |
|
|
#define CC_FIRST 128 /* First ICC/FCC reg */
|
| 431 |
|
|
#define CC_LAST 135 /* Last ICC/FCC reg */
|
| 432 |
|
|
#define ICC_FIRST (CC_FIRST + 4) /* First ICC reg */
|
| 433 |
|
|
#define ICC_LAST (CC_FIRST + 7) /* Last ICC reg */
|
| 434 |
|
|
#define ICC_TEMP (CC_FIRST + 7) /* Temporary ICC reg */
|
| 435 |
|
|
#define FCC_FIRST (CC_FIRST) /* First FCC reg */
|
| 436 |
|
|
#define FCC_LAST (CC_FIRST + 3) /* Last FCC reg */
|
| 437 |
|
|
|
| 438 |
|
|
/* Amount to shift a value to locate a ICC or FCC register in the CCR
|
| 439 |
|
|
register and shift it to the bottom 4 bits. */
|
| 440 |
|
|
#define CC_SHIFT_RIGHT(REGNO) (((REGNO) - CC_FIRST) << 2)
|
| 441 |
|
|
|
| 442 |
|
|
/* Mask to isolate a single ICC/FCC value. */
|
| 443 |
|
|
#define CC_MASK 0xf
|
| 444 |
|
|
|
| 445 |
|
|
/* Masks to isolate the various bits in an ICC field. */
|
| 446 |
|
|
#define ICC_MASK_N 0x8 /* negative */
|
| 447 |
|
|
#define ICC_MASK_Z 0x4 /* zero */
|
| 448 |
|
|
#define ICC_MASK_V 0x2 /* overflow */
|
| 449 |
|
|
#define ICC_MASK_C 0x1 /* carry */
|
| 450 |
|
|
|
| 451 |
|
|
/* Mask to isolate the N/Z flags in an ICC. */
|
| 452 |
|
|
#define ICC_MASK_NZ (ICC_MASK_N | ICC_MASK_Z)
|
| 453 |
|
|
|
| 454 |
|
|
/* Mask to isolate the Z/C flags in an ICC. */
|
| 455 |
|
|
#define ICC_MASK_ZC (ICC_MASK_Z | ICC_MASK_C)
|
| 456 |
|
|
|
| 457 |
|
|
/* Masks to isolate the various bits in a FCC field. */
|
| 458 |
|
|
#define FCC_MASK_E 0x8 /* equal */
|
| 459 |
|
|
#define FCC_MASK_L 0x4 /* less than */
|
| 460 |
|
|
#define FCC_MASK_G 0x2 /* greater than */
|
| 461 |
|
|
#define FCC_MASK_U 0x1 /* unordered */
|
| 462 |
|
|
|
| 463 |
|
|
/* For CCR registers, the machine wants CR4..CR7 to be used for integer
|
| 464 |
|
|
code and CR0..CR3 to be used for floating point. */
|
| 465 |
|
|
#define CR_FIRST 136 /* First CCR */
|
| 466 |
|
|
#define CR_LAST 143 /* Last CCR */
|
| 467 |
|
|
#define CR_NUM (CR_LAST-CR_FIRST+1) /* # of CCRs (8) */
|
| 468 |
|
|
#define ICR_FIRST (CR_FIRST + 4) /* First integer CCR */
|
| 469 |
|
|
#define ICR_LAST (CR_FIRST + 7) /* Last integer CCR */
|
| 470 |
|
|
#define ICR_TEMP ICR_LAST /* Temp integer CCR */
|
| 471 |
|
|
#define FCR_FIRST (CR_FIRST + 0) /* First float CCR */
|
| 472 |
|
|
#define FCR_LAST (CR_FIRST + 3) /* Last float CCR */
|
| 473 |
|
|
|
| 474 |
|
|
/* Amount to shift a value to locate a CR register in the CCCR special purpose
|
| 475 |
|
|
register and shift it to the bottom 2 bits. */
|
| 476 |
|
|
#define CR_SHIFT_RIGHT(REGNO) (((REGNO) - CR_FIRST) << 1)
|
| 477 |
|
|
|
| 478 |
|
|
/* Mask to isolate a single CR value. */
|
| 479 |
|
|
#define CR_MASK 0x3
|
| 480 |
|
|
|
| 481 |
|
|
#define ACC_FIRST 144 /* First acc register */
|
| 482 |
|
|
#define ACC_LAST 155 /* Last acc register */
|
| 483 |
|
|
|
| 484 |
|
|
#define ACCG_FIRST 156 /* First accg register */
|
| 485 |
|
|
#define ACCG_LAST 167 /* Last accg register */
|
| 486 |
|
|
|
| 487 |
|
|
#define AP_FIRST 168 /* fake argument pointer */
|
| 488 |
|
|
|
| 489 |
|
|
#define SPR_FIRST 169
|
| 490 |
|
|
#define SPR_LAST 172
|
| 491 |
|
|
#define LR_REGNO (SPR_FIRST)
|
| 492 |
|
|
#define LCR_REGNO (SPR_FIRST + 1)
|
| 493 |
|
|
#define IACC_FIRST (SPR_FIRST + 2)
|
| 494 |
|
|
#define IACC_LAST (SPR_FIRST + 3)
|
| 495 |
|
|
|
| 496 |
|
|
#define GPR_P(R) IN_RANGE (R, GPR_FIRST, GPR_LAST)
|
| 497 |
|
|
#define GPR_OR_AP_P(R) (GPR_P (R) || (R) == ARG_POINTER_REGNUM)
|
| 498 |
|
|
#define FPR_P(R) IN_RANGE (R, FPR_FIRST, FPR_LAST)
|
| 499 |
|
|
#define CC_P(R) IN_RANGE (R, CC_FIRST, CC_LAST)
|
| 500 |
|
|
#define ICC_P(R) IN_RANGE (R, ICC_FIRST, ICC_LAST)
|
| 501 |
|
|
#define FCC_P(R) IN_RANGE (R, FCC_FIRST, FCC_LAST)
|
| 502 |
|
|
#define CR_P(R) IN_RANGE (R, CR_FIRST, CR_LAST)
|
| 503 |
|
|
#define ICR_P(R) IN_RANGE (R, ICR_FIRST, ICR_LAST)
|
| 504 |
|
|
#define FCR_P(R) IN_RANGE (R, FCR_FIRST, FCR_LAST)
|
| 505 |
|
|
#define ACC_P(R) IN_RANGE (R, ACC_FIRST, ACC_LAST)
|
| 506 |
|
|
#define ACCG_P(R) IN_RANGE (R, ACCG_FIRST, ACCG_LAST)
|
| 507 |
|
|
#define SPR_P(R) IN_RANGE (R, SPR_FIRST, SPR_LAST)
|
| 508 |
|
|
|
| 509 |
|
|
#define GPR_OR_PSEUDO_P(R) (GPR_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
|
| 510 |
|
|
#define FPR_OR_PSEUDO_P(R) (FPR_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
|
| 511 |
|
|
#define GPR_AP_OR_PSEUDO_P(R) (GPR_OR_AP_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
|
| 512 |
|
|
#define CC_OR_PSEUDO_P(R) (CC_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
|
| 513 |
|
|
#define ICC_OR_PSEUDO_P(R) (ICC_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
|
| 514 |
|
|
#define FCC_OR_PSEUDO_P(R) (FCC_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
|
| 515 |
|
|
#define CR_OR_PSEUDO_P(R) (CR_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
|
| 516 |
|
|
#define ICR_OR_PSEUDO_P(R) (ICR_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
|
| 517 |
|
|
#define FCR_OR_PSEUDO_P(R) (FCR_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
|
| 518 |
|
|
#define ACC_OR_PSEUDO_P(R) (ACC_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
|
| 519 |
|
|
#define ACCG_OR_PSEUDO_P(R) (ACCG_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
|
| 520 |
|
|
|
| 521 |
|
|
#define MAX_STACK_IMMEDIATE_OFFSET 2047
|
| 522 |
|
|
|
| 523 |
|
|
|
| 524 |
|
|
/* Register Basics. */
|
| 525 |
|
|
|
| 526 |
|
|
/* Number of hardware registers known to the compiler. They receive numbers 0
|
| 527 |
|
|
through `FIRST_PSEUDO_REGISTER-1'; thus, the first pseudo register's number
|
| 528 |
|
|
really is assigned the number `FIRST_PSEUDO_REGISTER'. */
|
| 529 |
|
|
#define FIRST_PSEUDO_REGISTER (SPR_LAST + 1)
|
| 530 |
|
|
|
| 531 |
|
|
/* The first/last register that can contain the arguments to a function. */
|
| 532 |
|
|
#define FIRST_ARG_REGNUM (GPR_FIRST + 8)
|
| 533 |
|
|
#define LAST_ARG_REGNUM (FIRST_ARG_REGNUM + FRV_NUM_ARG_REGS - 1)
|
| 534 |
|
|
|
| 535 |
|
|
/* Registers used by the exception handling functions. These should be
|
| 536 |
|
|
registers that are not otherwise used by the calling sequence. */
|
| 537 |
|
|
#define FIRST_EH_REGNUM 14
|
| 538 |
|
|
#define LAST_EH_REGNUM 15
|
| 539 |
|
|
|
| 540 |
|
|
/* Scratch registers used in the prologue, epilogue and thunks.
|
| 541 |
|
|
OFFSET_REGNO is for loading constant addends that are too big for a
|
| 542 |
|
|
single instruction. TEMP_REGNO is used for transferring SPRs to and from
|
| 543 |
|
|
the stack, and various other activities. */
|
| 544 |
|
|
#define OFFSET_REGNO 4
|
| 545 |
|
|
#define TEMP_REGNO 5
|
| 546 |
|
|
|
| 547 |
|
|
/* Registers used in the prologue. OLD_SP_REGNO is the old stack pointer,
|
| 548 |
|
|
which is sometimes used to set up the frame pointer. */
|
| 549 |
|
|
#define OLD_SP_REGNO 6
|
| 550 |
|
|
|
| 551 |
|
|
/* Registers used in the epilogue. STACKADJ_REGNO stores the exception
|
| 552 |
|
|
handler's stack adjustment. */
|
| 553 |
|
|
#define STACKADJ_REGNO 6
|
| 554 |
|
|
|
| 555 |
|
|
/* Registers used in thunks. JMP_REGNO is used for loading the target
|
| 556 |
|
|
address. */
|
| 557 |
|
|
#define JUMP_REGNO 6
|
| 558 |
|
|
|
| 559 |
|
|
#define EH_RETURN_DATA_REGNO(N) ((N) <= (LAST_EH_REGNUM - FIRST_EH_REGNUM)? \
|
| 560 |
|
|
(N) + FIRST_EH_REGNUM : INVALID_REGNUM)
|
| 561 |
|
|
#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, STACKADJ_REGNO)
|
| 562 |
|
|
#define EH_RETURN_HANDLER_RTX RETURN_ADDR_RTX (0, frame_pointer_rtx)
|
| 563 |
|
|
|
| 564 |
|
|
#define EPILOGUE_USES(REGNO) ((REGNO) == LR_REGNO)
|
| 565 |
|
|
|
| 566 |
|
|
/* An initializer that says which registers are used for fixed purposes all
|
| 567 |
|
|
throughout the compiled code and are therefore not available for general
|
| 568 |
|
|
allocation. These would include the stack pointer, the frame pointer
|
| 569 |
|
|
(except on machines where that can be used as a general register when no
|
| 570 |
|
|
frame pointer is needed), the program counter on machines where that is
|
| 571 |
|
|
considered one of the addressable registers, and any other numbered register
|
| 572 |
|
|
with a standard use.
|
| 573 |
|
|
|
| 574 |
|
|
This information is expressed as a sequence of numbers, separated by commas
|
| 575 |
|
|
and surrounded by braces. The Nth number is 1 if register N is fixed, 0
|
| 576 |
|
|
otherwise.
|
| 577 |
|
|
|
| 578 |
|
|
The table initialized from this macro, and the table initialized by the
|
| 579 |
|
|
following one, may be overridden at run time either automatically, by the
|
| 580 |
|
|
actions of the macro `CONDITIONAL_REGISTER_USAGE', or by the user with the
|
| 581 |
|
|
command options `-ffixed-REG', `-fcall-used-REG' and `-fcall-saved-REG'. */
|
| 582 |
|
|
|
| 583 |
|
|
/* gr0 -- Hard Zero
|
| 584 |
|
|
gr1 -- Stack Pointer
|
| 585 |
|
|
gr2 -- Frame Pointer
|
| 586 |
|
|
gr3 -- Hidden Parameter
|
| 587 |
|
|
gr16 -- Small Data reserved
|
| 588 |
|
|
gr17 -- Pic reserved
|
| 589 |
|
|
gr28 -- OS reserved
|
| 590 |
|
|
gr29 -- OS reserved
|
| 591 |
|
|
gr30 -- OS reserved
|
| 592 |
|
|
gr31 -- OS reserved
|
| 593 |
|
|
cr3 -- reserved to reload FCC registers.
|
| 594 |
|
|
cr7 -- reserved to reload ICC registers. */
|
| 595 |
|
|
#define FIXED_REGISTERS \
|
| 596 |
|
|
{ /* Integer Registers */ \
|
| 597 |
|
|
1, 1, 1, 1, 0, 0, 0, 0, /* 000-007, gr0 - gr7 */ \
|
| 598 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, /* 008-015, gr8 - gr15 */ \
|
| 599 |
|
|
1, 1, 0, 0, 0, 0, 0, 0, /* 016-023, gr16 - gr23 */ \
|
| 600 |
|
|
0, 0, 0, 0, 1, 1, 1, 1, /* 024-031, gr24 - gr31 */ \
|
| 601 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, /* 032-039, gr32 - gr39 */ \
|
| 602 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, /* 040-040, gr48 - gr47 */ \
|
| 603 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, /* 048-055, gr48 - gr55 */ \
|
| 604 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, /* 056-063, gr56 - gr63 */ \
|
| 605 |
|
|
/* Float Registers */ \
|
| 606 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, /* 064-071, fr0 - fr7 */ \
|
| 607 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, /* 072-079, fr8 - fr15 */ \
|
| 608 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, /* 080-087, fr16 - fr23 */ \
|
| 609 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, /* 088-095, fr24 - fr31 */ \
|
| 610 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, /* 096-103, fr32 - fr39 */ \
|
| 611 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, /* 104-111, fr48 - fr47 */ \
|
| 612 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, /* 112-119, fr48 - fr55 */ \
|
| 613 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, /* 120-127, fr56 - fr63 */ \
|
| 614 |
|
|
/* Condition Code Registers */ \
|
| 615 |
|
|
0, 0, 0, 0, /* 128-131, fcc0 - fcc3 */ \
|
| 616 |
|
|
0, 0, 0, 1, /* 132-135, icc0 - icc3 */ \
|
| 617 |
|
|
/* Conditional execution Registers (CCR) */ \
|
| 618 |
|
|
0, 0, 0, 0, 0, 0, 0, 1, /* 136-143, cr0 - cr7 */ \
|
| 619 |
|
|
/* Accumulators */ \
|
| 620 |
|
|
1, 1, 1, 1, 1, 1, 1, 1, /* 144-151, acc0 - acc7 */ \
|
| 621 |
|
|
1, 1, 1, 1, /* 152-155, acc8 - acc11 */ \
|
| 622 |
|
|
1, 1, 1, 1, 1, 1, 1, 1, /* 156-163, accg0 - accg7 */ \
|
| 623 |
|
|
1, 1, 1, 1, /* 164-167, accg8 - accg11 */ \
|
| 624 |
|
|
/* Other registers */ \
|
| 625 |
|
|
1, /* 168, AP - fake arg ptr */ \
|
| 626 |
|
|
1, /* 169, LR - Link register*/ \
|
| 627 |
|
|
0, /* 170, LCR - Loop count reg*/ \
|
| 628 |
|
|
1, 1 /* 171-172, iacc0 */ \
|
| 629 |
|
|
}
|
| 630 |
|
|
|
| 631 |
|
|
/* Like `FIXED_REGISTERS' but has 1 for each register that is clobbered (in
|
| 632 |
|
|
general) by function calls as well as for fixed registers. This macro
|
| 633 |
|
|
therefore identifies the registers that are not available for general
|
| 634 |
|
|
allocation of values that must live across function calls.
|
| 635 |
|
|
|
| 636 |
|
|
If a register has 0 in `CALL_USED_REGISTERS', the compiler automatically
|
| 637 |
|
|
saves it on function entry and restores it on function exit, if the register
|
| 638 |
|
|
is used within the function. */
|
| 639 |
|
|
#define CALL_USED_REGISTERS \
|
| 640 |
|
|
{ /* Integer Registers */ \
|
| 641 |
|
|
1, 1, 1, 1, 1, 1, 1, 1, /* 000-007, gr0 - gr7 */ \
|
| 642 |
|
|
1, 1, 1, 1, 1, 1, 1, 1, /* 008-015, gr8 - gr15 */ \
|
| 643 |
|
|
1, 1, 0, 0, 0, 0, 0, 0, /* 016-023, gr16 - gr23 */ \
|
| 644 |
|
|
0, 0, 0, 0, 1, 1, 1, 1, /* 024-031, gr24 - gr31 */ \
|
| 645 |
|
|
1, 1, 1, 1, 1, 1, 1, 1, /* 032-039, gr32 - gr39 */ \
|
| 646 |
|
|
1, 1, 1, 1, 1, 1, 1, 1, /* 040-040, gr48 - gr47 */ \
|
| 647 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, /* 048-055, gr48 - gr55 */ \
|
| 648 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, /* 056-063, gr56 - gr63 */ \
|
| 649 |
|
|
/* Float Registers */ \
|
| 650 |
|
|
1, 1, 1, 1, 1, 1, 1, 1, /* 064-071, fr0 - fr7 */ \
|
| 651 |
|
|
1, 1, 1, 1, 1, 1, 1, 1, /* 072-079, fr8 - fr15 */ \
|
| 652 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, /* 080-087, fr16 - fr23 */ \
|
| 653 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, /* 088-095, fr24 - fr31 */ \
|
| 654 |
|
|
1, 1, 1, 1, 1, 1, 1, 1, /* 096-103, fr32 - fr39 */ \
|
| 655 |
|
|
1, 1, 1, 1, 1, 1, 1, 1, /* 104-111, fr48 - fr47 */ \
|
| 656 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, /* 112-119, fr48 - fr55 */ \
|
| 657 |
|
|
0, 0, 0, 0, 0, 0, 0, 0, /* 120-127, fr56 - fr63 */ \
|
| 658 |
|
|
/* Condition Code Registers */ \
|
| 659 |
|
|
1, 1, 1, 1, /* 128-131, fcc0 - fcc3 */ \
|
| 660 |
|
|
1, 1, 1, 1, /* 132-135, icc0 - icc3 */ \
|
| 661 |
|
|
/* Conditional execution Registers (CCR) */ \
|
| 662 |
|
|
1, 1, 1, 1, 1, 1, 1, 1, /* 136-143, cr0 - cr7 */ \
|
| 663 |
|
|
/* Accumulators */ \
|
| 664 |
|
|
1, 1, 1, 1, 1, 1, 1, 1, /* 144-151, acc0 - acc7 */ \
|
| 665 |
|
|
1, 1, 1, 1, /* 152-155, acc8 - acc11 */ \
|
| 666 |
|
|
1, 1, 1, 1, 1, 1, 1, 1, /* 156-163, accg0 - accg7 */ \
|
| 667 |
|
|
1, 1, 1, 1, /* 164-167, accg8 - accg11 */ \
|
| 668 |
|
|
/* Other registers */ \
|
| 669 |
|
|
1, /* 168, AP - fake arg ptr */ \
|
| 670 |
|
|
1, /* 169, LR - Link register*/ \
|
| 671 |
|
|
1, /* 170, LCR - Loop count reg */ \
|
| 672 |
|
|
1, 1 /* 171-172, iacc0 */ \
|
| 673 |
|
|
}
|
| 674 |
|
|
|
| 675 |
|
|
|
| 676 |
|
|
/* Order of allocation of registers. */
|
| 677 |
|
|
|
| 678 |
|
|
/* If defined, an initializer for a vector of integers, containing the numbers
|
| 679 |
|
|
of hard registers in the order in which GCC should prefer to use them
|
| 680 |
|
|
(from most preferred to least).
|
| 681 |
|
|
|
| 682 |
|
|
If this macro is not defined, registers are used lowest numbered first (all
|
| 683 |
|
|
else being equal).
|
| 684 |
|
|
|
| 685 |
|
|
One use of this macro is on machines where the highest numbered registers
|
| 686 |
|
|
must always be saved and the save-multiple-registers instruction supports
|
| 687 |
|
|
only sequences of consecutive registers. On such machines, define
|
| 688 |
|
|
`REG_ALLOC_ORDER' to be an initializer that lists the highest numbered
|
| 689 |
|
|
allocatable register first. */
|
| 690 |
|
|
|
| 691 |
|
|
/* On the FRV, allocate GR16 and GR17 after other saved registers so that we
|
| 692 |
|
|
have a better chance of allocating 2 registers at a time and can use the
|
| 693 |
|
|
double word load/store instructions in the prologue. */
|
| 694 |
|
|
#define REG_ALLOC_ORDER \
|
| 695 |
|
|
{ \
|
| 696 |
|
|
/* volatile registers */ \
|
| 697 |
|
|
GPR_FIRST + 4, GPR_FIRST + 5, GPR_FIRST + 6, GPR_FIRST + 7, \
|
| 698 |
|
|
GPR_FIRST + 8, GPR_FIRST + 9, GPR_FIRST + 10, GPR_FIRST + 11, \
|
| 699 |
|
|
GPR_FIRST + 12, GPR_FIRST + 13, GPR_FIRST + 14, GPR_FIRST + 15, \
|
| 700 |
|
|
GPR_FIRST + 32, GPR_FIRST + 33, GPR_FIRST + 34, GPR_FIRST + 35, \
|
| 701 |
|
|
GPR_FIRST + 36, GPR_FIRST + 37, GPR_FIRST + 38, GPR_FIRST + 39, \
|
| 702 |
|
|
GPR_FIRST + 40, GPR_FIRST + 41, GPR_FIRST + 42, GPR_FIRST + 43, \
|
| 703 |
|
|
GPR_FIRST + 44, GPR_FIRST + 45, GPR_FIRST + 46, GPR_FIRST + 47, \
|
| 704 |
|
|
\
|
| 705 |
|
|
FPR_FIRST + 0, FPR_FIRST + 1, FPR_FIRST + 2, FPR_FIRST + 3, \
|
| 706 |
|
|
FPR_FIRST + 4, FPR_FIRST + 5, FPR_FIRST + 6, FPR_FIRST + 7, \
|
| 707 |
|
|
FPR_FIRST + 8, FPR_FIRST + 9, FPR_FIRST + 10, FPR_FIRST + 11, \
|
| 708 |
|
|
FPR_FIRST + 12, FPR_FIRST + 13, FPR_FIRST + 14, FPR_FIRST + 15, \
|
| 709 |
|
|
FPR_FIRST + 32, FPR_FIRST + 33, FPR_FIRST + 34, FPR_FIRST + 35, \
|
| 710 |
|
|
FPR_FIRST + 36, FPR_FIRST + 37, FPR_FIRST + 38, FPR_FIRST + 39, \
|
| 711 |
|
|
FPR_FIRST + 40, FPR_FIRST + 41, FPR_FIRST + 42, FPR_FIRST + 43, \
|
| 712 |
|
|
FPR_FIRST + 44, FPR_FIRST + 45, FPR_FIRST + 46, FPR_FIRST + 47, \
|
| 713 |
|
|
\
|
| 714 |
|
|
ICC_FIRST + 0, ICC_FIRST + 1, ICC_FIRST + 2, ICC_FIRST + 3, \
|
| 715 |
|
|
FCC_FIRST + 0, FCC_FIRST + 1, FCC_FIRST + 2, FCC_FIRST + 3, \
|
| 716 |
|
|
CR_FIRST + 0, CR_FIRST + 1, CR_FIRST + 2, CR_FIRST + 3, \
|
| 717 |
|
|
CR_FIRST + 4, CR_FIRST + 5, CR_FIRST + 6, CR_FIRST + 7, \
|
| 718 |
|
|
\
|
| 719 |
|
|
/* saved registers */ \
|
| 720 |
|
|
GPR_FIRST + 18, GPR_FIRST + 19, \
|
| 721 |
|
|
GPR_FIRST + 20, GPR_FIRST + 21, GPR_FIRST + 22, GPR_FIRST + 23, \
|
| 722 |
|
|
GPR_FIRST + 24, GPR_FIRST + 25, GPR_FIRST + 26, GPR_FIRST + 27, \
|
| 723 |
|
|
GPR_FIRST + 48, GPR_FIRST + 49, GPR_FIRST + 50, GPR_FIRST + 51, \
|
| 724 |
|
|
GPR_FIRST + 52, GPR_FIRST + 53, GPR_FIRST + 54, GPR_FIRST + 55, \
|
| 725 |
|
|
GPR_FIRST + 56, GPR_FIRST + 57, GPR_FIRST + 58, GPR_FIRST + 59, \
|
| 726 |
|
|
GPR_FIRST + 60, GPR_FIRST + 61, GPR_FIRST + 62, GPR_FIRST + 63, \
|
| 727 |
|
|
GPR_FIRST + 16, GPR_FIRST + 17, \
|
| 728 |
|
|
\
|
| 729 |
|
|
FPR_FIRST + 16, FPR_FIRST + 17, FPR_FIRST + 18, FPR_FIRST + 19, \
|
| 730 |
|
|
FPR_FIRST + 20, FPR_FIRST + 21, FPR_FIRST + 22, FPR_FIRST + 23, \
|
| 731 |
|
|
FPR_FIRST + 24, FPR_FIRST + 25, FPR_FIRST + 26, FPR_FIRST + 27, \
|
| 732 |
|
|
FPR_FIRST + 28, FPR_FIRST + 29, FPR_FIRST + 30, FPR_FIRST + 31, \
|
| 733 |
|
|
FPR_FIRST + 48, FPR_FIRST + 49, FPR_FIRST + 50, FPR_FIRST + 51, \
|
| 734 |
|
|
FPR_FIRST + 52, FPR_FIRST + 53, FPR_FIRST + 54, FPR_FIRST + 55, \
|
| 735 |
|
|
FPR_FIRST + 56, FPR_FIRST + 57, FPR_FIRST + 58, FPR_FIRST + 59, \
|
| 736 |
|
|
FPR_FIRST + 60, FPR_FIRST + 61, FPR_FIRST + 62, FPR_FIRST + 63, \
|
| 737 |
|
|
\
|
| 738 |
|
|
/* special or fixed registers */ \
|
| 739 |
|
|
GPR_FIRST + 0, GPR_FIRST + 1, GPR_FIRST + 2, GPR_FIRST + 3, \
|
| 740 |
|
|
GPR_FIRST + 28, GPR_FIRST + 29, GPR_FIRST + 30, GPR_FIRST + 31, \
|
| 741 |
|
|
ACC_FIRST + 0, ACC_FIRST + 1, ACC_FIRST + 2, ACC_FIRST + 3, \
|
| 742 |
|
|
ACC_FIRST + 4, ACC_FIRST + 5, ACC_FIRST + 6, ACC_FIRST + 7, \
|
| 743 |
|
|
ACC_FIRST + 8, ACC_FIRST + 9, ACC_FIRST + 10, ACC_FIRST + 11, \
|
| 744 |
|
|
ACCG_FIRST + 0, ACCG_FIRST + 1, ACCG_FIRST + 2, ACCG_FIRST + 3, \
|
| 745 |
|
|
ACCG_FIRST + 4, ACCG_FIRST + 5, ACCG_FIRST + 6, ACCG_FIRST + 7, \
|
| 746 |
|
|
ACCG_FIRST + 8, ACCG_FIRST + 9, ACCG_FIRST + 10, ACCG_FIRST + 11, \
|
| 747 |
|
|
AP_FIRST, LR_REGNO, LCR_REGNO, \
|
| 748 |
|
|
IACC_FIRST + 0, IACC_FIRST + 1 \
|
| 749 |
|
|
}
|
| 750 |
|
|
|
| 751 |
|
|
|
| 752 |
|
|
/* How Values Fit in Registers. */
|
| 753 |
|
|
|
| 754 |
|
|
/* A C expression for the number of consecutive hard registers, starting at
|
| 755 |
|
|
register number REGNO, required to hold a value of mode MODE.
|
| 756 |
|
|
|
| 757 |
|
|
On a machine where all registers are exactly one word, a suitable definition
|
| 758 |
|
|
of this macro is
|
| 759 |
|
|
|
| 760 |
|
|
#define HARD_REGNO_NREGS(REGNO, MODE) \
|
| 761 |
|
|
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
|
| 762 |
|
|
/ UNITS_PER_WORD)) */
|
| 763 |
|
|
|
| 764 |
|
|
/* On the FRV, make the CC modes take 3 words in the integer registers, so that
|
| 765 |
|
|
we can build the appropriate instructions to properly reload the values. */
|
| 766 |
|
|
#define HARD_REGNO_NREGS(REGNO, MODE) frv_hard_regno_nregs (REGNO, MODE)
|
| 767 |
|
|
|
| 768 |
|
|
/* A C expression that is nonzero if it is permissible to store a value of mode
|
| 769 |
|
|
MODE in hard register number REGNO (or in several registers starting with
|
| 770 |
|
|
that one). For a machine where all registers are equivalent, a suitable
|
| 771 |
|
|
definition is
|
| 772 |
|
|
|
| 773 |
|
|
#define HARD_REGNO_MODE_OK(REGNO, MODE) 1
|
| 774 |
|
|
|
| 775 |
|
|
It is not necessary for this macro to check for the numbers of fixed
|
| 776 |
|
|
registers, because the allocation mechanism considers them to be always
|
| 777 |
|
|
occupied.
|
| 778 |
|
|
|
| 779 |
|
|
On some machines, double-precision values must be kept in even/odd register
|
| 780 |
|
|
pairs. The way to implement that is to define this macro to reject odd
|
| 781 |
|
|
register numbers for such modes.
|
| 782 |
|
|
|
| 783 |
|
|
The minimum requirement for a mode to be OK in a register is that the
|
| 784 |
|
|
`movMODE' instruction pattern support moves between the register and any
|
| 785 |
|
|
other hard register for which the mode is OK; and that moving a value into
|
| 786 |
|
|
the register and back out not alter it.
|
| 787 |
|
|
|
| 788 |
|
|
Since the same instruction used to move `SImode' will work for all narrower
|
| 789 |
|
|
integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
|
| 790 |
|
|
to distinguish between these modes, provided you define patterns `movhi',
|
| 791 |
|
|
etc., to take advantage of this. This is useful because of the interaction
|
| 792 |
|
|
between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
|
| 793 |
|
|
all integer modes to be tieable.
|
| 794 |
|
|
|
| 795 |
|
|
Many machines have special registers for floating point arithmetic. Often
|
| 796 |
|
|
people assume that floating point machine modes are allowed only in floating
|
| 797 |
|
|
point registers. This is not true. Any registers that can hold integers
|
| 798 |
|
|
can safely *hold* a floating point machine mode, whether or not floating
|
| 799 |
|
|
arithmetic can be done on it in those registers. Integer move instructions
|
| 800 |
|
|
can be used to move the values.
|
| 801 |
|
|
|
| 802 |
|
|
On some machines, though, the converse is true: fixed-point machine modes
|
| 803 |
|
|
may not go in floating registers. This is true if the floating registers
|
| 804 |
|
|
normalize any value stored in them, because storing a non-floating value
|
| 805 |
|
|
there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
|
| 806 |
|
|
fixed-point machine modes in floating registers. But if the floating
|
| 807 |
|
|
registers do not automatically normalize, if you can store any bit pattern
|
| 808 |
|
|
in one and retrieve it unchanged without a trap, then any machine mode may
|
| 809 |
|
|
go in a floating register, so you can define this macro to say so.
|
| 810 |
|
|
|
| 811 |
|
|
The primary significance of special floating registers is rather that they
|
| 812 |
|
|
are the registers acceptable in floating point arithmetic instructions.
|
| 813 |
|
|
However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
|
| 814 |
|
|
writing the proper constraints for those instructions.
|
| 815 |
|
|
|
| 816 |
|
|
On some machines, the floating registers are especially slow to access, so
|
| 817 |
|
|
that it is better to store a value in a stack frame than in such a register
|
| 818 |
|
|
if floating point arithmetic is not being done. As long as the floating
|
| 819 |
|
|
registers are not in class `GENERAL_REGS', they will not be used unless some
|
| 820 |
|
|
pattern's constraint asks for one. */
|
| 821 |
|
|
#define HARD_REGNO_MODE_OK(REGNO, MODE) frv_hard_regno_mode_ok (REGNO, MODE)
|
| 822 |
|
|
|
| 823 |
|
|
/* A C expression that is nonzero if it is desirable to choose register
|
| 824 |
|
|
allocation so as to avoid move instructions between a value of mode MODE1
|
| 825 |
|
|
and a value of mode MODE2.
|
| 826 |
|
|
|
| 827 |
|
|
If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, MODE2)' are
|
| 828 |
|
|
ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be
|
| 829 |
|
|
zero. */
|
| 830 |
|
|
#define MODES_TIEABLE_P(MODE1, MODE2) (MODE1 == MODE2)
|
| 831 |
|
|
|
| 832 |
|
|
/* Define this macro if the compiler should avoid copies to/from CCmode
|
| 833 |
|
|
registers. You should only define this macro if support fo copying to/from
|
| 834 |
|
|
CCmode is incomplete. */
|
| 835 |
|
|
#define AVOID_CCMODE_COPIES
|
| 836 |
|
|
|
| 837 |
|
|
|
| 838 |
|
|
/* Register Classes. */
|
| 839 |
|
|
|
| 840 |
|
|
/* An enumeral type that must be defined with all the register class names as
|
| 841 |
|
|
enumeral values. `NO_REGS' must be first. `ALL_REGS' must be the last
|
| 842 |
|
|
register class, followed by one more enumeral value, `LIM_REG_CLASSES',
|
| 843 |
|
|
which is not a register class but rather tells how many classes there are.
|
| 844 |
|
|
|
| 845 |
|
|
Each register class has a number, which is the value of casting the class
|
| 846 |
|
|
name to type `int'. The number serves as an index in many of the tables
|
| 847 |
|
|
described below. */
|
| 848 |
|
|
enum reg_class
|
| 849 |
|
|
{
|
| 850 |
|
|
NO_REGS,
|
| 851 |
|
|
ICC_REGS,
|
| 852 |
|
|
FCC_REGS,
|
| 853 |
|
|
CC_REGS,
|
| 854 |
|
|
ICR_REGS,
|
| 855 |
|
|
FCR_REGS,
|
| 856 |
|
|
CR_REGS,
|
| 857 |
|
|
LCR_REG,
|
| 858 |
|
|
LR_REG,
|
| 859 |
|
|
GR8_REGS,
|
| 860 |
|
|
GR9_REGS,
|
| 861 |
|
|
GR89_REGS,
|
| 862 |
|
|
FDPIC_REGS,
|
| 863 |
|
|
FDPIC_FPTR_REGS,
|
| 864 |
|
|
FDPIC_CALL_REGS,
|
| 865 |
|
|
SPR_REGS,
|
| 866 |
|
|
QUAD_ACC_REGS,
|
| 867 |
|
|
ACCG_REGS,
|
| 868 |
|
|
QUAD_FPR_REGS,
|
| 869 |
|
|
QUAD_REGS,
|
| 870 |
|
|
GPR_REGS,
|
| 871 |
|
|
ALL_REGS,
|
| 872 |
|
|
LIM_REG_CLASSES
|
| 873 |
|
|
};
|
| 874 |
|
|
|
| 875 |
|
|
#define GENERAL_REGS GPR_REGS
|
| 876 |
|
|
|
| 877 |
|
|
/* The number of distinct register classes, defined as follows:
|
| 878 |
|
|
|
| 879 |
|
|
#define N_REG_CLASSES (int) LIM_REG_CLASSES */
|
| 880 |
|
|
#define N_REG_CLASSES ((int) LIM_REG_CLASSES)
|
| 881 |
|
|
|
| 882 |
|
|
/* An initializer containing the names of the register classes as C string
|
| 883 |
|
|
constants. These names are used in writing some of the debugging dumps. */
|
| 884 |
|
|
#define REG_CLASS_NAMES { \
|
| 885 |
|
|
"NO_REGS", \
|
| 886 |
|
|
"ICC_REGS", \
|
| 887 |
|
|
"FCC_REGS", \
|
| 888 |
|
|
"CC_REGS", \
|
| 889 |
|
|
"ICR_REGS", \
|
| 890 |
|
|
"FCR_REGS", \
|
| 891 |
|
|
"CR_REGS", \
|
| 892 |
|
|
"LCR_REG", \
|
| 893 |
|
|
"LR_REG", \
|
| 894 |
|
|
"GR8_REGS", \
|
| 895 |
|
|
"GR9_REGS", \
|
| 896 |
|
|
"GR89_REGS", \
|
| 897 |
|
|
"FDPIC_REGS", \
|
| 898 |
|
|
"FDPIC_FPTR_REGS", \
|
| 899 |
|
|
"FDPIC_CALL_REGS", \
|
| 900 |
|
|
"SPR_REGS", \
|
| 901 |
|
|
"QUAD_ACC_REGS", \
|
| 902 |
|
|
"ACCG_REGS", \
|
| 903 |
|
|
"QUAD_FPR_REGS", \
|
| 904 |
|
|
"QUAD_REGS", \
|
| 905 |
|
|
"GPR_REGS", \
|
| 906 |
|
|
"ALL_REGS" \
|
| 907 |
|
|
}
|
| 908 |
|
|
|
| 909 |
|
|
/* An initializer containing the contents of the register classes, as integers
|
| 910 |
|
|
which are bit masks. The Nth integer specifies the contents of class N.
|
| 911 |
|
|
The way the integer MASK is interpreted is that register R is in the class
|
| 912 |
|
|
if `MASK & (1 << R)' is 1.
|
| 913 |
|
|
|
| 914 |
|
|
When the machine has more than 32 registers, an integer does not suffice.
|
| 915 |
|
|
Then the integers are replaced by sub-initializers, braced groupings
|
| 916 |
|
|
containing several integers. Each sub-initializer must be suitable as an
|
| 917 |
|
|
initializer for the type `HARD_REG_SET' which is defined in
|
| 918 |
|
|
`hard-reg-set.h'. */
|
| 919 |
|
|
#define REG_CLASS_CONTENTS \
|
| 920 |
|
|
{ /* gr0-gr31 gr32-gr63 fr0-fr31 fr32-fr-63 cc/ccr/acc ap/spr */ \
|
| 921 |
|
|
{ 0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x0}, /* NO_REGS */\
|
| 922 |
|
|
{ 0x00000000,0x00000000,0x00000000,0x00000000,0x000000f0,0x0}, /* ICC_REGS */\
|
| 923 |
|
|
{ 0x00000000,0x00000000,0x00000000,0x00000000,0x0000000f,0x0}, /* FCC_REGS */\
|
| 924 |
|
|
{ 0x00000000,0x00000000,0x00000000,0x00000000,0x000000ff,0x0}, /* CC_REGS */\
|
| 925 |
|
|
{ 0x00000000,0x00000000,0x00000000,0x00000000,0x0000f000,0x0}, /* ICR_REGS */\
|
| 926 |
|
|
{ 0x00000000,0x00000000,0x00000000,0x00000000,0x00000f00,0x0}, /* FCR_REGS */\
|
| 927 |
|
|
{ 0x00000000,0x00000000,0x00000000,0x00000000,0x0000ff00,0x0}, /* CR_REGS */\
|
| 928 |
|
|
{ 0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x400}, /* LCR_REGS */\
|
| 929 |
|
|
{ 0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x200}, /* LR_REGS */\
|
| 930 |
|
|
{ 0x00000100,0x00000000,0x00000000,0x00000000,0x00000000,0x0}, /* GR8_REGS */\
|
| 931 |
|
|
{ 0x00000200,0x00000000,0x00000000,0x00000000,0x00000000,0x0}, /* GR9_REGS */\
|
| 932 |
|
|
{ 0x00000300,0x00000000,0x00000000,0x00000000,0x00000000,0x0}, /* GR89_REGS */\
|
| 933 |
|
|
{ 0x00008000,0x00000000,0x00000000,0x00000000,0x00000000,0x0}, /* FDPIC_REGS */\
|
| 934 |
|
|
{ 0x00004000,0x00000000,0x00000000,0x00000000,0x00000000,0x0}, /* FDPIC_FPTR_REGS */\
|
| 935 |
|
|
{ 0x0000c000,0x00000000,0x00000000,0x00000000,0x00000000,0x0}, /* FDPIC_CALL_REGS */\
|
| 936 |
|
|
{ 0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x1e00}, /* SPR_REGS */\
|
| 937 |
|
|
{ 0x00000000,0x00000000,0x00000000,0x00000000,0x0fff0000,0x0}, /* QUAD_ACC */\
|
| 938 |
|
|
{ 0x00000000,0x00000000,0x00000000,0x00000000,0xf0000000,0xff}, /* ACCG_REGS*/\
|
| 939 |
|
|
{ 0x00000000,0x00000000,0xffffffff,0xffffffff,0x00000000,0x0}, /* QUAD_FPR */\
|
| 940 |
|
|
{ 0x0ffffffc,0xffffffff,0x00000000,0x00000000,0x00000000,0x0}, /* QUAD_REGS*/\
|
| 941 |
|
|
{ 0xffffffff,0xffffffff,0x00000000,0x00000000,0x00000000,0x100}, /* GPR_REGS */\
|
| 942 |
|
|
{ 0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0x1fff}, /* ALL_REGS */\
|
| 943 |
|
|
}
|
| 944 |
|
|
|
| 945 |
|
|
#define EVEN_ACC_REGS QUAD_ACC_REGS
|
| 946 |
|
|
#define ACC_REGS QUAD_ACC_REGS
|
| 947 |
|
|
#define FEVEN_REGS QUAD_FPR_REGS
|
| 948 |
|
|
#define FPR_REGS QUAD_FPR_REGS
|
| 949 |
|
|
#define EVEN_REGS QUAD_REGS
|
| 950 |
|
|
|
| 951 |
|
|
/* A C expression whose value is a register class containing hard register
|
| 952 |
|
|
REGNO. In general there is more than one such class; choose a class which
|
| 953 |
|
|
is "minimal", meaning that no smaller class also contains the register. */
|
| 954 |
|
|
|
| 955 |
|
|
extern enum reg_class regno_reg_class[];
|
| 956 |
|
|
#define REGNO_REG_CLASS(REGNO) regno_reg_class [REGNO]
|
| 957 |
|
|
|
| 958 |
|
|
/* A macro whose definition is the name of the class to which a valid base
|
| 959 |
|
|
register must belong. A base register is one used in an address which is
|
| 960 |
|
|
the register value plus a displacement. */
|
| 961 |
|
|
#define BASE_REG_CLASS GPR_REGS
|
| 962 |
|
|
|
| 963 |
|
|
/* A macro whose definition is the name of the class to which a valid index
|
| 964 |
|
|
register must belong. An index register is one used in an address where its
|
| 965 |
|
|
value is either multiplied by a scale factor or added to another register
|
| 966 |
|
|
(as well as added to a displacement). */
|
| 967 |
|
|
#define INDEX_REG_CLASS GPR_REGS
|
| 968 |
|
|
|
| 969 |
|
|
/* A C expression which is nonzero if register number NUM is suitable for use
|
| 970 |
|
|
as a base register in operand addresses. It may be either a suitable hard
|
| 971 |
|
|
register or a pseudo register that has been allocated such a hard register. */
|
| 972 |
|
|
#define REGNO_OK_FOR_BASE_P(NUM) \
|
| 973 |
|
|
((NUM) < FIRST_PSEUDO_REGISTER \
|
| 974 |
|
|
? GPR_P (NUM) \
|
| 975 |
|
|
: (reg_renumber [NUM] >= 0 && GPR_P (reg_renumber [NUM])))
|
| 976 |
|
|
|
| 977 |
|
|
/* A C expression which is nonzero if register number NUM is suitable for use
|
| 978 |
|
|
as an index register in operand addresses. It may be either a suitable hard
|
| 979 |
|
|
register or a pseudo register that has been allocated such a hard register.
|
| 980 |
|
|
|
| 981 |
|
|
The difference between an index register and a base register is that the
|
| 982 |
|
|
index register may be scaled. If an address involves the sum of two
|
| 983 |
|
|
registers, neither one of them scaled, then either one may be labeled the
|
| 984 |
|
|
"base" and the other the "index"; but whichever labeling is used must fit
|
| 985 |
|
|
the machine's constraints of which registers may serve in each capacity.
|
| 986 |
|
|
The compiler will try both labelings, looking for one that is valid, and
|
| 987 |
|
|
will reload one or both registers only if neither labeling works. */
|
| 988 |
|
|
#define REGNO_OK_FOR_INDEX_P(NUM) \
|
| 989 |
|
|
((NUM) < FIRST_PSEUDO_REGISTER \
|
| 990 |
|
|
? GPR_P (NUM) \
|
| 991 |
|
|
: (reg_renumber [NUM] >= 0 && GPR_P (reg_renumber [NUM])))
|
| 992 |
|
|
|
| 993 |
|
|
#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
|
| 994 |
|
|
frv_secondary_reload_class (CLASS, MODE, X)
|
| 995 |
|
|
|
| 996 |
|
|
#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
|
| 997 |
|
|
frv_secondary_reload_class (CLASS, MODE, X)
|
| 998 |
|
|
|
| 999 |
|
|
/* A C expression for the maximum number of consecutive registers of
|
| 1000 |
|
|
class CLASS needed to hold a value of mode MODE.
|
| 1001 |
|
|
|
| 1002 |
|
|
This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value
|
| 1003 |
|
|
of the macro `CLASS_MAX_NREGS (CLASS, MODE)' should be the maximum value of
|
| 1004 |
|
|
`HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class CLASS.
|
| 1005 |
|
|
|
| 1006 |
|
|
This macro helps control the handling of multiple-word values in
|
| 1007 |
|
|
the reload pass.
|
| 1008 |
|
|
|
| 1009 |
|
|
This declaration is required. */
|
| 1010 |
|
|
#define CLASS_MAX_NREGS(CLASS, MODE) frv_class_max_nregs (CLASS, MODE)
|
| 1011 |
|
|
|
| 1012 |
|
|
#define ZERO_P(x) (x == CONST0_RTX (GET_MODE (x)))
|
| 1013 |
|
|
|
| 1014 |
|
|
|
| 1015 |
|
|
/* Basic Stack Layout. */
|
| 1016 |
|
|
|
| 1017 |
|
|
/* Structure to describe information about a saved range of registers */
|
| 1018 |
|
|
|
| 1019 |
|
|
typedef struct frv_stack_regs {
|
| 1020 |
|
|
const char * name; /* name of the register ranges */
|
| 1021 |
|
|
int first; /* first register in the range */
|
| 1022 |
|
|
int last; /* last register in the range */
|
| 1023 |
|
|
int size_1word; /* # of bytes to be stored via 1 word stores */
|
| 1024 |
|
|
int size_2words; /* # of bytes to be stored via 2 word stores */
|
| 1025 |
|
|
unsigned char field_p; /* true if the registers are a single SPR */
|
| 1026 |
|
|
unsigned char dword_p; /* true if we can do dword stores */
|
| 1027 |
|
|
unsigned char special_p; /* true if the regs have a fixed save loc. */
|
| 1028 |
|
|
} frv_stack_regs_t;
|
| 1029 |
|
|
|
| 1030 |
|
|
/* Register ranges to look into saving. */
|
| 1031 |
|
|
#define STACK_REGS_GPR 0 /* Gprs (normally gr16..gr31, gr48..gr63) */
|
| 1032 |
|
|
#define STACK_REGS_FPR 1 /* Fprs (normally fr16..fr31, fr48..fr63) */
|
| 1033 |
|
|
#define STACK_REGS_LR 2 /* LR register */
|
| 1034 |
|
|
#define STACK_REGS_CC 3 /* CCrs (normally not saved) */
|
| 1035 |
|
|
#define STACK_REGS_LCR 5 /* lcr register */
|
| 1036 |
|
|
#define STACK_REGS_STDARG 6 /* stdarg registers */
|
| 1037 |
|
|
#define STACK_REGS_STRUCT 7 /* structure return (gr3) */
|
| 1038 |
|
|
#define STACK_REGS_FP 8 /* FP register */
|
| 1039 |
|
|
#define STACK_REGS_MAX 9 /* # of register ranges */
|
| 1040 |
|
|
|
| 1041 |
|
|
/* Values for save_p field. */
|
| 1042 |
|
|
#define REG_SAVE_NO_SAVE 0 /* register not saved */
|
| 1043 |
|
|
#define REG_SAVE_1WORD 1 /* save the register */
|
| 1044 |
|
|
#define REG_SAVE_2WORDS 2 /* save register and register+1 */
|
| 1045 |
|
|
|
| 1046 |
|
|
/* Structure used to define the frv stack. */
|
| 1047 |
|
|
|
| 1048 |
|
|
typedef struct frv_stack {
|
| 1049 |
|
|
int total_size; /* total bytes allocated for stack */
|
| 1050 |
|
|
int vars_size; /* variable save area size */
|
| 1051 |
|
|
int parameter_size; /* outgoing parameter size */
|
| 1052 |
|
|
int stdarg_size; /* size of regs needed to be saved for stdarg */
|
| 1053 |
|
|
int regs_size; /* size of the saved registers */
|
| 1054 |
|
|
int regs_size_1word; /* # of bytes to be stored via 1 word stores */
|
| 1055 |
|
|
int regs_size_2words; /* # of bytes to be stored via 2 word stores */
|
| 1056 |
|
|
int header_size; /* size of the old FP, struct ret., LR save */
|
| 1057 |
|
|
int pretend_size; /* size of pretend args */
|
| 1058 |
|
|
int vars_offset; /* offset to save local variables from new SP*/
|
| 1059 |
|
|
int regs_offset; /* offset to save registers from new SP */
|
| 1060 |
|
|
/* register range information */
|
| 1061 |
|
|
frv_stack_regs_t regs[STACK_REGS_MAX];
|
| 1062 |
|
|
/* offset to store each register */
|
| 1063 |
|
|
int reg_offset[FIRST_PSEUDO_REGISTER];
|
| 1064 |
|
|
/* whether to save register (& reg+1) */
|
| 1065 |
|
|
unsigned char save_p[FIRST_PSEUDO_REGISTER];
|
| 1066 |
|
|
} frv_stack_t;
|
| 1067 |
|
|
|
| 1068 |
|
|
/* Define this macro if pushing a word onto the stack moves the stack pointer
|
| 1069 |
|
|
to a smaller address. */
|
| 1070 |
|
|
#define STACK_GROWS_DOWNWARD 1
|
| 1071 |
|
|
|
| 1072 |
|
|
/* Define this macro to nonzero if the addresses of local variable slots
|
| 1073 |
|
|
are at negative offsets from the frame pointer. */
|
| 1074 |
|
|
#define FRAME_GROWS_DOWNWARD 1
|
| 1075 |
|
|
|
| 1076 |
|
|
/* Offset from the frame pointer to the first local variable slot to be
|
| 1077 |
|
|
allocated.
|
| 1078 |
|
|
|
| 1079 |
|
|
If `FRAME_GROWS_DOWNWARD', find the next slot's offset by subtracting the
|
| 1080 |
|
|
first slot's length from `STARTING_FRAME_OFFSET'. Otherwise, it is found by
|
| 1081 |
|
|
adding the length of the first slot to the value `STARTING_FRAME_OFFSET'. */
|
| 1082 |
|
|
#define STARTING_FRAME_OFFSET 0
|
| 1083 |
|
|
|
| 1084 |
|
|
/* Offset from the stack pointer register to the first location at which
|
| 1085 |
|
|
outgoing arguments are placed. If not specified, the default value of zero
|
| 1086 |
|
|
is used. This is the proper value for most machines.
|
| 1087 |
|
|
|
| 1088 |
|
|
If `ARGS_GROW_DOWNWARD', this is the offset to the location above the first
|
| 1089 |
|
|
location at which outgoing arguments are placed. */
|
| 1090 |
|
|
#define STACK_POINTER_OFFSET 0
|
| 1091 |
|
|
|
| 1092 |
|
|
/* Offset from the argument pointer register to the first argument's address.
|
| 1093 |
|
|
On some machines it may depend on the data type of the function.
|
| 1094 |
|
|
|
| 1095 |
|
|
If `ARGS_GROW_DOWNWARD', this is the offset to the location above the first
|
| 1096 |
|
|
argument's address. */
|
| 1097 |
|
|
#define FIRST_PARM_OFFSET(FUNDECL) 0
|
| 1098 |
|
|
|
| 1099 |
|
|
/* A C expression whose value is RTL representing the address in a stack frame
|
| 1100 |
|
|
where the pointer to the caller's frame is stored. Assume that FRAMEADDR is
|
| 1101 |
|
|
an RTL expression for the address of the stack frame itself.
|
| 1102 |
|
|
|
| 1103 |
|
|
If you don't define this macro, the default is to return the value of
|
| 1104 |
|
|
FRAMEADDR--that is, the stack frame address is also the address of the stack
|
| 1105 |
|
|
word that points to the previous frame. */
|
| 1106 |
|
|
#define DYNAMIC_CHAIN_ADDRESS(FRAMEADDR) frv_dynamic_chain_address (FRAMEADDR)
|
| 1107 |
|
|
|
| 1108 |
|
|
/* A C expression whose value is RTL representing the value of the return
|
| 1109 |
|
|
address for the frame COUNT steps up from the current frame, after the
|
| 1110 |
|
|
prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame
|
| 1111 |
|
|
pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
|
| 1112 |
|
|
defined.
|
| 1113 |
|
|
|
| 1114 |
|
|
The value of the expression must always be the correct address when COUNT is
|
| 1115 |
|
|
zero, but may be `NULL_RTX' if there is not way to determine the return
|
| 1116 |
|
|
address of other frames. */
|
| 1117 |
|
|
#define RETURN_ADDR_RTX(COUNT, FRAMEADDR) frv_return_addr_rtx (COUNT, FRAMEADDR)
|
| 1118 |
|
|
|
| 1119 |
|
|
#define RETURN_POINTER_REGNUM LR_REGNO
|
| 1120 |
|
|
|
| 1121 |
|
|
/* A C expression whose value is RTL representing the location of the incoming
|
| 1122 |
|
|
return address at the beginning of any function, before the prologue. This
|
| 1123 |
|
|
RTL is either a `REG', indicating that the return value is saved in `REG',
|
| 1124 |
|
|
or a `MEM' representing a location in the stack.
|
| 1125 |
|
|
|
| 1126 |
|
|
You only need to define this macro if you want to support call frame
|
| 1127 |
|
|
debugging information like that provided by DWARF 2. */
|
| 1128 |
|
|
#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (SImode, RETURN_POINTER_REGNUM)
|
| 1129 |
|
|
|
| 1130 |
|
|
|
| 1131 |
|
|
/* Register That Address the Stack Frame. */
|
| 1132 |
|
|
|
| 1133 |
|
|
/* The register number of the stack pointer register, which must also be a
|
| 1134 |
|
|
fixed register according to `FIXED_REGISTERS'. On most machines, the
|
| 1135 |
|
|
hardware determines which register this is. */
|
| 1136 |
|
|
#define STACK_POINTER_REGNUM (GPR_FIRST + 1)
|
| 1137 |
|
|
|
| 1138 |
|
|
/* The register number of the frame pointer register, which is used to access
|
| 1139 |
|
|
automatic variables in the stack frame. On some machines, the hardware
|
| 1140 |
|
|
determines which register this is. On other machines, you can choose any
|
| 1141 |
|
|
register you wish for this purpose. */
|
| 1142 |
|
|
#define FRAME_POINTER_REGNUM (GPR_FIRST + 2)
|
| 1143 |
|
|
|
| 1144 |
|
|
/* The register number of the arg pointer register, which is used to access the
|
| 1145 |
|
|
function's argument list. On some machines, this is the same as the frame
|
| 1146 |
|
|
pointer register. On some machines, the hardware determines which register
|
| 1147 |
|
|
this is. On other machines, you can choose any register you wish for this
|
| 1148 |
|
|
purpose. If this is not the same register as the frame pointer register,
|
| 1149 |
|
|
then you must mark it as a fixed register according to `FIXED_REGISTERS', or
|
| 1150 |
|
|
arrange to be able to eliminate it. */
|
| 1151 |
|
|
|
| 1152 |
|
|
/* On frv this is a fake register that is eliminated in
|
| 1153 |
|
|
terms of either the frame pointer or stack pointer. */
|
| 1154 |
|
|
#define ARG_POINTER_REGNUM AP_FIRST
|
| 1155 |
|
|
|
| 1156 |
|
|
/* Register numbers used for passing a function's static chain pointer. If
|
| 1157 |
|
|
register windows are used, the register number as seen by the called
|
| 1158 |
|
|
function is `STATIC_CHAIN_INCOMING_REGNUM', while the register number as
|
| 1159 |
|
|
seen by the calling function is `STATIC_CHAIN_REGNUM'. If these registers
|
| 1160 |
|
|
are the same, `STATIC_CHAIN_INCOMING_REGNUM' need not be defined.
|
| 1161 |
|
|
|
| 1162 |
|
|
The static chain register need not be a fixed register.
|
| 1163 |
|
|
|
| 1164 |
|
|
If the static chain is passed in memory, these macros should not be defined;
|
| 1165 |
|
|
instead, the next two macros should be defined. */
|
| 1166 |
|
|
#define STATIC_CHAIN_REGNUM (GPR_FIRST + 7)
|
| 1167 |
|
|
#define STATIC_CHAIN_INCOMING_REGNUM (GPR_FIRST + 7)
|
| 1168 |
|
|
|
| 1169 |
|
|
|
| 1170 |
|
|
/* Eliminating the Frame Pointer and the Arg Pointer. */
|
| 1171 |
|
|
|
| 1172 |
|
|
/* If defined, this macro specifies a table of register pairs used to eliminate
|
| 1173 |
|
|
unneeded registers that point into the stack frame. If it is not defined,
|
| 1174 |
|
|
the only elimination attempted by the compiler is to replace references to
|
| 1175 |
|
|
the frame pointer with references to the stack pointer.
|
| 1176 |
|
|
|
| 1177 |
|
|
The definition of this macro is a list of structure initializations, each of
|
| 1178 |
|
|
which specifies an original and replacement register.
|
| 1179 |
|
|
|
| 1180 |
|
|
On some machines, the position of the argument pointer is not known until
|
| 1181 |
|
|
the compilation is completed. In such a case, a separate hard register must
|
| 1182 |
|
|
be used for the argument pointer. This register can be eliminated by
|
| 1183 |
|
|
replacing it with either the frame pointer or the argument pointer,
|
| 1184 |
|
|
depending on whether or not the frame pointer has been eliminated.
|
| 1185 |
|
|
|
| 1186 |
|
|
In this case, you might specify:
|
| 1187 |
|
|
#define ELIMINABLE_REGS \
|
| 1188 |
|
|
{{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
|
| 1189 |
|
|
{ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
|
| 1190 |
|
|
{FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
|
| 1191 |
|
|
|
| 1192 |
|
|
Note that the elimination of the argument pointer with the stack pointer is
|
| 1193 |
|
|
specified first since that is the preferred elimination. */
|
| 1194 |
|
|
|
| 1195 |
|
|
#define ELIMINABLE_REGS \
|
| 1196 |
|
|
{ \
|
| 1197 |
|
|
{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
|
| 1198 |
|
|
{ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
|
| 1199 |
|
|
{FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM} \
|
| 1200 |
|
|
}
|
| 1201 |
|
|
|
| 1202 |
|
|
/* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the
|
| 1203 |
|
|
initial difference between the specified pair of registers. This macro must
|
| 1204 |
|
|
be defined if `ELIMINABLE_REGS' is defined. */
|
| 1205 |
|
|
|
| 1206 |
|
|
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
|
| 1207 |
|
|
(OFFSET) = frv_initial_elimination_offset (FROM, TO)
|
| 1208 |
|
|
|
| 1209 |
|
|
|
| 1210 |
|
|
/* Passing Function Arguments on the Stack. */
|
| 1211 |
|
|
|
| 1212 |
|
|
/* If defined, the maximum amount of space required for outgoing arguments will
|
| 1213 |
|
|
be computed and placed into the variable
|
| 1214 |
|
|
`crtl->outgoing_args_size'. No space will be pushed onto the
|
| 1215 |
|
|
stack for each call; instead, the function prologue should increase the
|
| 1216 |
|
|
stack frame size by this amount.
|
| 1217 |
|
|
|
| 1218 |
|
|
Defining both `PUSH_ROUNDING' and `ACCUMULATE_OUTGOING_ARGS' is not
|
| 1219 |
|
|
proper. */
|
| 1220 |
|
|
#define ACCUMULATE_OUTGOING_ARGS 1
|
| 1221 |
|
|
|
| 1222 |
|
|
|
| 1223 |
|
|
/* The number of register assigned to holding function arguments. */
|
| 1224 |
|
|
|
| 1225 |
|
|
#define FRV_NUM_ARG_REGS 6
|
| 1226 |
|
|
|
| 1227 |
|
|
/* A C type for declaring a variable that is used as the first argument of
|
| 1228 |
|
|
`FUNCTION_ARG' and other related values. For some target machines, the type
|
| 1229 |
|
|
`int' suffices and can hold the number of bytes of argument so far.
|
| 1230 |
|
|
|
| 1231 |
|
|
There is no need to record in `CUMULATIVE_ARGS' anything about the arguments
|
| 1232 |
|
|
that have been passed on the stack. The compiler has other variables to
|
| 1233 |
|
|
keep track of that. For target machines on which all arguments are passed
|
| 1234 |
|
|
on the stack, there is no need to store anything in `CUMULATIVE_ARGS';
|
| 1235 |
|
|
however, the data structure must exist and should not be empty, so use
|
| 1236 |
|
|
`int'. */
|
| 1237 |
|
|
#define CUMULATIVE_ARGS int
|
| 1238 |
|
|
|
| 1239 |
|
|
/* A C statement (sans semicolon) for initializing the variable CUM for the
|
| 1240 |
|
|
state at the beginning of the argument list. The variable has type
|
| 1241 |
|
|
`CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
|
| 1242 |
|
|
of the function which will receive the args, or 0 if the args are to a
|
| 1243 |
|
|
compiler support library function. The value of INDIRECT is nonzero when
|
| 1244 |
|
|
processing an indirect call, for example a call through a function pointer.
|
| 1245 |
|
|
The value of INDIRECT is zero for a call to an explicitly named function, a
|
| 1246 |
|
|
library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
|
| 1247 |
|
|
arguments for the function being compiled.
|
| 1248 |
|
|
|
| 1249 |
|
|
When processing a call to a compiler support library function, LIBNAME
|
| 1250 |
|
|
identifies which one. It is a `symbol_ref' rtx which contains the name of
|
| 1251 |
|
|
the function, as a string. LIBNAME is 0 when an ordinary C function call is
|
| 1252 |
|
|
being processed. Thus, each time this macro is called, either LIBNAME or
|
| 1253 |
|
|
FNTYPE is nonzero, but never both of them at once. */
|
| 1254 |
|
|
|
| 1255 |
|
|
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
|
| 1256 |
|
|
frv_init_cumulative_args (&CUM, FNTYPE, LIBNAME, FNDECL, FALSE)
|
| 1257 |
|
|
|
| 1258 |
|
|
/* Like `INIT_CUMULATIVE_ARGS' but overrides it for the purposes of finding the
|
| 1259 |
|
|
arguments for the function being compiled. If this macro is undefined,
|
| 1260 |
|
|
`INIT_CUMULATIVE_ARGS' is used instead.
|
| 1261 |
|
|
|
| 1262 |
|
|
The value passed for LIBNAME is always 0, since library routines with
|
| 1263 |
|
|
special calling conventions are never compiled with GCC. The argument
|
| 1264 |
|
|
LIBNAME exists for symmetry with `INIT_CUMULATIVE_ARGS'. */
|
| 1265 |
|
|
|
| 1266 |
|
|
#define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
|
| 1267 |
|
|
frv_init_cumulative_args (&CUM, FNTYPE, LIBNAME, NULL, TRUE)
|
| 1268 |
|
|
|
| 1269 |
|
|
/* A C expression that is nonzero if REGNO is the number of a hard register in
|
| 1270 |
|
|
which function arguments are sometimes passed. This does *not* include
|
| 1271 |
|
|
implicit arguments such as the static chain and the structure-value address.
|
| 1272 |
|
|
On many machines, no registers can be used for this purpose since all
|
| 1273 |
|
|
function arguments are pushed on the stack. */
|
| 1274 |
|
|
#define FUNCTION_ARG_REGNO_P(REGNO) \
|
| 1275 |
|
|
((REGNO) >= FIRST_ARG_REGNUM && ((REGNO) <= LAST_ARG_REGNUM))
|
| 1276 |
|
|
|
| 1277 |
|
|
|
| 1278 |
|
|
/* How Scalar Function Values are Returned. */
|
| 1279 |
|
|
|
| 1280 |
|
|
/* The number of the hard register that is used to return a scalar value from a
|
| 1281 |
|
|
function call. */
|
| 1282 |
|
|
#define RETURN_VALUE_REGNUM (GPR_FIRST + 8)
|
| 1283 |
|
|
|
| 1284 |
|
|
#define FUNCTION_VALUE_REGNO_P(REGNO) frv_function_value_regno_p (REGNO)
|
| 1285 |
|
|
|
| 1286 |
|
|
|
| 1287 |
|
|
/* How Large Values are Returned. */
|
| 1288 |
|
|
|
| 1289 |
|
|
/* The number of the register that is used to pass the structure
|
| 1290 |
|
|
value address. */
|
| 1291 |
|
|
#define FRV_STRUCT_VALUE_REGNUM (GPR_FIRST + 3)
|
| 1292 |
|
|
|
| 1293 |
|
|
|
| 1294 |
|
|
/* Function Entry and Exit. */
|
| 1295 |
|
|
|
| 1296 |
|
|
/* Define this macro as a C expression that is nonzero if the return
|
| 1297 |
|
|
instruction or the function epilogue ignores the value of the stack pointer;
|
| 1298 |
|
|
in other words, if it is safe to delete an instruction to adjust the stack
|
| 1299 |
|
|
pointer before a return from the function.
|
| 1300 |
|
|
|
| 1301 |
|
|
Note that this macro's value is relevant only for functions for which frame
|
| 1302 |
|
|
pointers are maintained. It is never safe to delete a final stack
|
| 1303 |
|
|
adjustment in a function that has no frame pointer, and the compiler knows
|
| 1304 |
|
|
this regardless of `EXIT_IGNORE_STACK'. */
|
| 1305 |
|
|
#define EXIT_IGNORE_STACK 1
|
| 1306 |
|
|
|
| 1307 |
|
|
/* Generating Code for Profiling. */
|
| 1308 |
|
|
|
| 1309 |
|
|
/* A C statement or compound statement to output to FILE some assembler code to
|
| 1310 |
|
|
call the profiling subroutine `mcount'. Before calling, the assembler code
|
| 1311 |
|
|
must load the address of a counter variable into a register where `mcount'
|
| 1312 |
|
|
expects to find the address. The name of this variable is `LP' followed by
|
| 1313 |
|
|
the number LABELNO, so you would generate the name using `LP%d' in a
|
| 1314 |
|
|
`fprintf'.
|
| 1315 |
|
|
|
| 1316 |
|
|
The details of how the address should be passed to `mcount' are determined
|
| 1317 |
|
|
by your operating system environment, not by GCC. To figure them out,
|
| 1318 |
|
|
compile a small program for profiling using the system's installed C
|
| 1319 |
|
|
compiler and look at the assembler code that results.
|
| 1320 |
|
|
|
| 1321 |
|
|
This declaration must be present, but it can be an abort if profiling is
|
| 1322 |
|
|
not implemented. */
|
| 1323 |
|
|
|
| 1324 |
|
|
#define FUNCTION_PROFILER(FILE, LABELNO)
|
| 1325 |
|
|
|
| 1326 |
|
|
/* Trampolines for Nested Functions. */
|
| 1327 |
|
|
|
| 1328 |
|
|
/* A C expression for the size in bytes of the trampoline, as an integer. */
|
| 1329 |
|
|
#define TRAMPOLINE_SIZE frv_trampoline_size ()
|
| 1330 |
|
|
|
| 1331 |
|
|
/* Alignment required for trampolines, in bits.
|
| 1332 |
|
|
|
| 1333 |
|
|
If you don't define this macro, the value of `BIGGEST_ALIGNMENT' is used for
|
| 1334 |
|
|
aligning trampolines. */
|
| 1335 |
|
|
#define TRAMPOLINE_ALIGNMENT (TARGET_FDPIC ? 64 : 32)
|
| 1336 |
|
|
|
| 1337 |
|
|
/* Define this macro if trampolines need a special subroutine to do their work.
|
| 1338 |
|
|
The macro should expand to a series of `asm' statements which will be
|
| 1339 |
|
|
compiled with GCC. They go in a library function named
|
| 1340 |
|
|
`__transfer_from_trampoline'.
|
| 1341 |
|
|
|
| 1342 |
|
|
If you need to avoid executing the ordinary prologue code of a compiled C
|
| 1343 |
|
|
function when you jump to the subroutine, you can do so by placing a special
|
| 1344 |
|
|
label of your own in the assembler code. Use one `asm' statement to
|
| 1345 |
|
|
generate an assembler label, and another to make the label global. Then
|
| 1346 |
|
|
trampolines can use that label to jump directly to your special assembler
|
| 1347 |
|
|
code. */
|
| 1348 |
|
|
|
| 1349 |
|
|
#ifdef __FRV_UNDERSCORE__
|
| 1350 |
|
|
#define TRAMPOLINE_TEMPLATE_NAME "___trampoline_template"
|
| 1351 |
|
|
#else
|
| 1352 |
|
|
#define TRAMPOLINE_TEMPLATE_NAME "__trampoline_template"
|
| 1353 |
|
|
#endif
|
| 1354 |
|
|
|
| 1355 |
|
|
#define Twrite _write
|
| 1356 |
|
|
|
| 1357 |
|
|
#if ! __FRV_FDPIC__
|
| 1358 |
|
|
#define TRANSFER_FROM_TRAMPOLINE \
|
| 1359 |
|
|
extern int Twrite (int, const void *, unsigned); \
|
| 1360 |
|
|
\
|
| 1361 |
|
|
void \
|
| 1362 |
|
|
__trampoline_setup (short * addr, int size, int fnaddr, int sc) \
|
| 1363 |
|
|
{ \
|
| 1364 |
|
|
extern short __trampoline_template[]; \
|
| 1365 |
|
|
short * to = addr; \
|
| 1366 |
|
|
short * from = &__trampoline_template[0]; \
|
| 1367 |
|
|
int i; \
|
| 1368 |
|
|
\
|
| 1369 |
|
|
if (size < 20) \
|
| 1370 |
|
|
{ \
|
| 1371 |
|
|
Twrite (2, "__trampoline_setup bad size\n", \
|
| 1372 |
|
|
sizeof ("__trampoline_setup bad size\n") - 1); \
|
| 1373 |
|
|
exit (-1); \
|
| 1374 |
|
|
} \
|
| 1375 |
|
|
\
|
| 1376 |
|
|
to[0] = from[0]; \
|
| 1377 |
|
|
to[1] = (short)(fnaddr); \
|
| 1378 |
|
|
to[2] = from[2]; \
|
| 1379 |
|
|
to[3] = (short)(sc); \
|
| 1380 |
|
|
to[4] = from[4]; \
|
| 1381 |
|
|
to[5] = (short)(fnaddr >> 16); \
|
| 1382 |
|
|
to[6] = from[6]; \
|
| 1383 |
|
|
to[7] = (short)(sc >> 16); \
|
| 1384 |
|
|
to[8] = from[8]; \
|
| 1385 |
|
|
to[9] = from[9]; \
|
| 1386 |
|
|
\
|
| 1387 |
|
|
for (i = 0; i < 20; i++) \
|
| 1388 |
|
|
__asm__ volatile ("dcf @(%0,%1)\n\tici @(%0,%1)" :: "r" (to), "r" (i)); \
|
| 1389 |
|
|
} \
|
| 1390 |
|
|
\
|
| 1391 |
|
|
__asm__("\n" \
|
| 1392 |
|
|
"\t.globl " TRAMPOLINE_TEMPLATE_NAME "\n" \
|
| 1393 |
|
|
"\t.text\n" \
|
| 1394 |
|
|
TRAMPOLINE_TEMPLATE_NAME ":\n" \
|
| 1395 |
|
|
"\tsetlos #0, gr6\n" /* jump register */ \
|
| 1396 |
|
|
"\tsetlos #0, gr7\n" /* static chain */ \
|
| 1397 |
|
|
"\tsethi #0, gr6\n" \
|
| 1398 |
|
|
"\tsethi #0, gr7\n" \
|
| 1399 |
|
|
"\tjmpl @(gr0,gr6)\n");
|
| 1400 |
|
|
#else
|
| 1401 |
|
|
#define TRANSFER_FROM_TRAMPOLINE \
|
| 1402 |
|
|
extern int Twrite (int, const void *, unsigned); \
|
| 1403 |
|
|
\
|
| 1404 |
|
|
void \
|
| 1405 |
|
|
__trampoline_setup (addr, size, fnaddr, sc) \
|
| 1406 |
|
|
short * addr; \
|
| 1407 |
|
|
int size; \
|
| 1408 |
|
|
int fnaddr; \
|
| 1409 |
|
|
int sc; \
|
| 1410 |
|
|
{ \
|
| 1411 |
|
|
extern short __trampoline_template[]; \
|
| 1412 |
|
|
short * from = &__trampoline_template[0]; \
|
| 1413 |
|
|
int i; \
|
| 1414 |
|
|
short **desc = (short **)addr; \
|
| 1415 |
|
|
short * to = addr + 4; \
|
| 1416 |
|
|
\
|
| 1417 |
|
|
if (size != 32) \
|
| 1418 |
|
|
{ \
|
| 1419 |
|
|
Twrite (2, "__trampoline_setup bad size\n", \
|
| 1420 |
|
|
sizeof ("__trampoline_setup bad size\n") - 1); \
|
| 1421 |
|
|
exit (-1); \
|
| 1422 |
|
|
} \
|
| 1423 |
|
|
\
|
| 1424 |
|
|
/* Create a function descriptor with the address of the code below \
|
| 1425 |
|
|
and NULL as the FDPIC value. We don't need the real GOT value \
|
| 1426 |
|
|
here, since we don't use it, so we use NULL, that is just as \
|
| 1427 |
|
|
good. */ \
|
| 1428 |
|
|
desc[0] = to; \
|
| 1429 |
|
|
desc[1] = NULL; \
|
| 1430 |
|
|
size -= 8; \
|
| 1431 |
|
|
\
|
| 1432 |
|
|
to[0] = from[0]; \
|
| 1433 |
|
|
to[1] = (short)(fnaddr); \
|
| 1434 |
|
|
to[2] = from[2]; \
|
| 1435 |
|
|
to[3] = (short)(sc); \
|
| 1436 |
|
|
to[4] = from[4]; \
|
| 1437 |
|
|
to[5] = (short)(fnaddr >> 16); \
|
| 1438 |
|
|
to[6] = from[6]; \
|
| 1439 |
|
|
to[7] = (short)(sc >> 16); \
|
| 1440 |
|
|
to[8] = from[8]; \
|
| 1441 |
|
|
to[9] = from[9]; \
|
| 1442 |
|
|
to[10] = from[10]; \
|
| 1443 |
|
|
to[11] = from[11]; \
|
| 1444 |
|
|
\
|
| 1445 |
|
|
for (i = 0; i < size; i++) \
|
| 1446 |
|
|
__asm__ volatile ("dcf @(%0,%1)\n\tici @(%0,%1)" :: "r" (to), "r" (i)); \
|
| 1447 |
|
|
} \
|
| 1448 |
|
|
\
|
| 1449 |
|
|
__asm__("\n" \
|
| 1450 |
|
|
"\t.globl " TRAMPOLINE_TEMPLATE_NAME "\n" \
|
| 1451 |
|
|
"\t.text\n" \
|
| 1452 |
|
|
TRAMPOLINE_TEMPLATE_NAME ":\n" \
|
| 1453 |
|
|
"\tsetlos #0, gr6\n" /* Jump register. */ \
|
| 1454 |
|
|
"\tsetlos #0, gr7\n" /* Static chain. */ \
|
| 1455 |
|
|
"\tsethi #0, gr6\n" \
|
| 1456 |
|
|
"\tsethi #0, gr7\n" \
|
| 1457 |
|
|
"\tldd @(gr6,gr0),gr14\n" \
|
| 1458 |
|
|
"\tjmpl @(gr14,gr0)\n" \
|
| 1459 |
|
|
);
|
| 1460 |
|
|
#endif
|
| 1461 |
|
|
|
| 1462 |
|
|
|
| 1463 |
|
|
/* Addressing Modes. */
|
| 1464 |
|
|
|
| 1465 |
|
|
/* A number, the maximum number of registers that can appear in a valid memory
|
| 1466 |
|
|
address. Note that it is up to you to specify a value equal to the maximum
|
| 1467 |
|
|
number that `TARGET_LEGITIMATE_ADDRESS_P' would ever accept. */
|
| 1468 |
|
|
#define MAX_REGS_PER_ADDRESS 2
|
| 1469 |
|
|
|
| 1470 |
|
|
/* A C expression that is nonzero if X (assumed to be a `reg' RTX) is valid for
|
| 1471 |
|
|
use as a base register. For hard registers, it should always accept those
|
| 1472 |
|
|
which the hardware permits and reject the others. Whether the macro accepts
|
| 1473 |
|
|
or rejects pseudo registers must be controlled by `REG_OK_STRICT' as
|
| 1474 |
|
|
described above. This usually requires two variant definitions, of which
|
| 1475 |
|
|
`REG_OK_STRICT' controls the one actually used. */
|
| 1476 |
|
|
#ifdef REG_OK_STRICT
|
| 1477 |
|
|
#define REG_OK_FOR_BASE_P(X) GPR_P (REGNO (X))
|
| 1478 |
|
|
#else
|
| 1479 |
|
|
#define REG_OK_FOR_BASE_P(X) GPR_AP_OR_PSEUDO_P (REGNO (X))
|
| 1480 |
|
|
#endif
|
| 1481 |
|
|
|
| 1482 |
|
|
/* A C expression that is nonzero if X (assumed to be a `reg' RTX) is valid for
|
| 1483 |
|
|
use as an index register.
|
| 1484 |
|
|
|
| 1485 |
|
|
The difference between an index register and a base register is that the
|
| 1486 |
|
|
index register may be scaled. If an address involves the sum of two
|
| 1487 |
|
|
registers, neither one of them scaled, then either one may be labeled the
|
| 1488 |
|
|
"base" and the other the "index"; but whichever labeling is used must fit
|
| 1489 |
|
|
the machine's constraints of which registers may serve in each capacity.
|
| 1490 |
|
|
The compiler will try both labelings, looking for one that is valid, and
|
| 1491 |
|
|
will reload one or both registers only if neither labeling works. */
|
| 1492 |
|
|
#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
|
| 1493 |
|
|
|
| 1494 |
|
|
#define FIND_BASE_TERM frv_find_base_term
|
| 1495 |
|
|
|
| 1496 |
|
|
/* The load-and-update commands allow pre-modification in addresses.
|
| 1497 |
|
|
The index has to be in a register. */
|
| 1498 |
|
|
#define HAVE_PRE_MODIFY_REG 1
|
| 1499 |
|
|
|
| 1500 |
|
|
|
| 1501 |
|
|
/* We define extra CC modes in frv-modes.def so we need a selector. */
|
| 1502 |
|
|
|
| 1503 |
|
|
#define SELECT_CC_MODE frv_select_cc_mode
|
| 1504 |
|
|
|
| 1505 |
|
|
/* A C expression whose value is one if it is always safe to reverse a
|
| 1506 |
|
|
comparison whose mode is MODE. If `SELECT_CC_MODE' can ever return MODE for
|
| 1507 |
|
|
a floating-point inequality comparison, then `REVERSIBLE_CC_MODE (MODE)'
|
| 1508 |
|
|
must be zero.
|
| 1509 |
|
|
|
| 1510 |
|
|
You need not define this macro if it would always returns zero or if the
|
| 1511 |
|
|
floating-point format is anything other than `IEEE_FLOAT_FORMAT'. For
|
| 1512 |
|
|
example, here is the definition used on the SPARC, where floating-point
|
| 1513 |
|
|
inequality comparisons are always given `CCFPEmode':
|
| 1514 |
|
|
|
| 1515 |
|
|
#define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode) */
|
| 1516 |
|
|
|
| 1517 |
|
|
/* On frv, don't consider floating point comparisons to be reversible. In
|
| 1518 |
|
|
theory, fp equality comparisons can be reversible. */
|
| 1519 |
|
|
#define REVERSIBLE_CC_MODE(MODE) \
|
| 1520 |
|
|
((MODE) == CCmode || (MODE) == CC_UNSmode || (MODE) == CC_NZmode)
|
| 1521 |
|
|
|
| 1522 |
|
|
/* Frv CCR_MODE's are not reversible. */
|
| 1523 |
|
|
#define REVERSE_CONDEXEC_PREDICATES_P(x,y) 0
|
| 1524 |
|
|
|
| 1525 |
|
|
|
| 1526 |
|
|
/* Describing Relative Costs of Operations. */
|
| 1527 |
|
|
|
| 1528 |
|
|
/* A C expression for the cost of a branch instruction. A value of 1 is the
|
| 1529 |
|
|
default; other values are interpreted relative to that. */
|
| 1530 |
|
|
#define BRANCH_COST(speed_p, predictable_p) frv_branch_cost_int
|
| 1531 |
|
|
|
| 1532 |
|
|
/* Define this macro as a C expression which is nonzero if accessing less than
|
| 1533 |
|
|
a word of memory (i.e. a `char' or a `short') is no faster than accessing a
|
| 1534 |
|
|
word of memory, i.e., if such access require more than one instruction or if
|
| 1535 |
|
|
there is no difference in cost between byte and (aligned) word loads.
|
| 1536 |
|
|
|
| 1537 |
|
|
When this macro is not defined, the compiler will access a field by finding
|
| 1538 |
|
|
the smallest containing object; when it is defined, a fullword load will be
|
| 1539 |
|
|
used if alignment permits. Unless bytes accesses are faster than word
|
| 1540 |
|
|
accesses, using word accesses is preferable since it may eliminate
|
| 1541 |
|
|
subsequent memory access if subsequent accesses occur to other fields in the
|
| 1542 |
|
|
same word of the structure, but to different bytes. */
|
| 1543 |
|
|
#define SLOW_BYTE_ACCESS 1
|
| 1544 |
|
|
|
| 1545 |
|
|
/* Define this macro if it is as good or better to call a constant function
|
| 1546 |
|
|
address than to call an address kept in a register. */
|
| 1547 |
|
|
#define NO_FUNCTION_CSE
|
| 1548 |
|
|
|
| 1549 |
|
|
|
| 1550 |
|
|
/* Dividing the output into sections. */
|
| 1551 |
|
|
|
| 1552 |
|
|
/* A C expression whose value is a string containing the assembler operation
|
| 1553 |
|
|
that should precede instructions and read-only data. Normally `".text"' is
|
| 1554 |
|
|
right. */
|
| 1555 |
|
|
#define TEXT_SECTION_ASM_OP "\t.text"
|
| 1556 |
|
|
|
| 1557 |
|
|
/* A C expression whose value is a string containing the assembler operation to
|
| 1558 |
|
|
identify the following data as writable initialized data. Normally
|
| 1559 |
|
|
`".data"' is right. */
|
| 1560 |
|
|
#define DATA_SECTION_ASM_OP "\t.data"
|
| 1561 |
|
|
|
| 1562 |
|
|
#define BSS_SECTION_ASM_OP "\t.section .bss,\"aw\""
|
| 1563 |
|
|
|
| 1564 |
|
|
/* Short Data Support */
|
| 1565 |
|
|
#define SDATA_SECTION_ASM_OP "\t.section .sdata,\"aw\""
|
| 1566 |
|
|
|
| 1567 |
|
|
#undef INIT_SECTION_ASM_OP
|
| 1568 |
|
|
#undef FINI_SECTION_ASM_OP
|
| 1569 |
|
|
#define INIT_SECTION_ASM_OP "\t.section .init,\"ax\""
|
| 1570 |
|
|
#define FINI_SECTION_ASM_OP "\t.section .fini,\"ax\""
|
| 1571 |
|
|
|
| 1572 |
|
|
#undef CTORS_SECTION_ASM_OP
|
| 1573 |
|
|
#undef DTORS_SECTION_ASM_OP
|
| 1574 |
|
|
#define CTORS_SECTION_ASM_OP "\t.section\t.ctors,\"a\""
|
| 1575 |
|
|
#define DTORS_SECTION_ASM_OP "\t.section\t.dtors,\"a\""
|
| 1576 |
|
|
|
| 1577 |
|
|
/* A C expression whose value is a string containing the assembler operation to
|
| 1578 |
|
|
switch to the fixup section that records all initialized pointers in a -fpic
|
| 1579 |
|
|
program so they can be changed program startup time if the program is loaded
|
| 1580 |
|
|
at a different address than linked for. */
|
| 1581 |
|
|
#define FIXUP_SECTION_ASM_OP "\t.section .rofixup,\"a\""
|
| 1582 |
|
|
|
| 1583 |
|
|
/* Position Independent Code. */
|
| 1584 |
|
|
|
| 1585 |
|
|
/* A C expression that is nonzero if X is a legitimate immediate operand on the
|
| 1586 |
|
|
target machine when generating position independent code. You can assume
|
| 1587 |
|
|
that X satisfies `CONSTANT_P', so you need not check this. You can also
|
| 1588 |
|
|
assume FLAG_PIC is true, so you need not check it either. You need not
|
| 1589 |
|
|
define this macro if all constants (including `SYMBOL_REF') can be immediate
|
| 1590 |
|
|
operands when generating position independent code. */
|
| 1591 |
|
|
#define LEGITIMATE_PIC_OPERAND_P(X) \
|
| 1592 |
|
|
( GET_CODE (X) == CONST_INT \
|
| 1593 |
|
|
|| GET_CODE (X) == CONST_DOUBLE \
|
| 1594 |
|
|
|| (GET_CODE (X) == HIGH && GET_CODE (XEXP (X, 0)) == CONST_INT) \
|
| 1595 |
|
|
|| got12_operand (X, VOIDmode)) \
|
| 1596 |
|
|
|
| 1597 |
|
|
|
| 1598 |
|
|
/* The Overall Framework of an Assembler File. */
|
| 1599 |
|
|
|
| 1600 |
|
|
/* A C string constant describing how to begin a comment in the target
|
| 1601 |
|
|
assembler language. The compiler assumes that the comment will end at the
|
| 1602 |
|
|
end of the line. */
|
| 1603 |
|
|
#define ASM_COMMENT_START ";"
|
| 1604 |
|
|
|
| 1605 |
|
|
/* A C string constant for text to be output before each `asm' statement or
|
| 1606 |
|
|
group of consecutive ones. Normally this is `"#APP"', which is a comment
|
| 1607 |
|
|
that has no effect on most assemblers but tells the GNU assembler that it
|
| 1608 |
|
|
must check the lines that follow for all valid assembler constructs. */
|
| 1609 |
|
|
#define ASM_APP_ON "#APP\n"
|
| 1610 |
|
|
|
| 1611 |
|
|
/* A C string constant for text to be output after each `asm' statement or
|
| 1612 |
|
|
group of consecutive ones. Normally this is `"#NO_APP"', which tells the
|
| 1613 |
|
|
GNU assembler to resume making the time-saving assumptions that are valid
|
| 1614 |
|
|
for ordinary compiler output. */
|
| 1615 |
|
|
#define ASM_APP_OFF "#NO_APP\n"
|
| 1616 |
|
|
|
| 1617 |
|
|
|
| 1618 |
|
|
/* Output of Data. */
|
| 1619 |
|
|
|
| 1620 |
|
|
/* This is how to output a label to dwarf/dwarf2. */
|
| 1621 |
|
|
#define ASM_OUTPUT_DWARF_ADDR(STREAM, LABEL) \
|
| 1622 |
|
|
do { \
|
| 1623 |
|
|
fprintf (STREAM, "\t.picptr\t"); \
|
| 1624 |
|
|
assemble_name (STREAM, LABEL); \
|
| 1625 |
|
|
} while (0)
|
| 1626 |
|
|
|
| 1627 |
|
|
/* Whether to emit the gas specific dwarf2 line number support. */
|
| 1628 |
|
|
#define DWARF2_ASM_LINE_DEBUG_INFO (TARGET_DEBUG_LOC)
|
| 1629 |
|
|
|
| 1630 |
|
|
/* Output of Uninitialized Variables. */
|
| 1631 |
|
|
|
| 1632 |
|
|
/* A C statement (sans semicolon) to output to the stdio stream STREAM the
|
| 1633 |
|
|
assembler definition of a local-common-label named NAME whose size is SIZE
|
| 1634 |
|
|
bytes. The variable ROUNDED is the size rounded up to whatever alignment
|
| 1635 |
|
|
the caller wants.
|
| 1636 |
|
|
|
| 1637 |
|
|
Use the expression `assemble_name (STREAM, NAME)' to output the name itself;
|
| 1638 |
|
|
before and after that, output the additional assembler syntax for defining
|
| 1639 |
|
|
the name, and a newline.
|
| 1640 |
|
|
|
| 1641 |
|
|
This macro controls how the assembler definitions of uninitialized static
|
| 1642 |
|
|
variables are output. */
|
| 1643 |
|
|
#undef ASM_OUTPUT_LOCAL
|
| 1644 |
|
|
|
| 1645 |
|
|
#undef ASM_OUTPUT_ALIGNED_LOCAL
|
| 1646 |
|
|
|
| 1647 |
|
|
/* This is for final.c, because it is used by ASM_DECLARE_OBJECT_NAME. */
|
| 1648 |
|
|
extern int size_directive_output;
|
| 1649 |
|
|
|
| 1650 |
|
|
/* Like `ASM_OUTPUT_ALIGNED_LOCAL' except that it takes an additional
|
| 1651 |
|
|
parameter - the DECL of variable to be output, if there is one.
|
| 1652 |
|
|
This macro can be called with DECL == NULL_TREE. If you define
|
| 1653 |
|
|
this macro, it is used in place of `ASM_OUTPUT_LOCAL' and
|
| 1654 |
|
|
`ASM_OUTPUT_ALIGNED_LOCAL', and gives you more flexibility in
|
| 1655 |
|
|
handling the destination of the variable. */
|
| 1656 |
|
|
#undef ASM_OUTPUT_ALIGNED_DECL_LOCAL
|
| 1657 |
|
|
#define ASM_OUTPUT_ALIGNED_DECL_LOCAL(STREAM, DECL, NAME, SIZE, ALIGN) \
|
| 1658 |
|
|
do { \
|
| 1659 |
|
|
if ((SIZE) > 0 && (SIZE) <= (unsigned HOST_WIDE_INT) g_switch_value) \
|
| 1660 |
|
|
switch_to_section (get_named_section (NULL, ".sbss", 0)); \
|
| 1661 |
|
|
else \
|
| 1662 |
|
|
switch_to_section (bss_section); \
|
| 1663 |
|
|
ASM_OUTPUT_ALIGN (STREAM, floor_log2 ((ALIGN) / BITS_PER_UNIT)); \
|
| 1664 |
|
|
ASM_DECLARE_OBJECT_NAME (STREAM, NAME, DECL); \
|
| 1665 |
|
|
ASM_OUTPUT_SKIP (STREAM, (SIZE) ? (SIZE) : 1); \
|
| 1666 |
|
|
} while (0)
|
| 1667 |
|
|
|
| 1668 |
|
|
|
| 1669 |
|
|
/* Output and Generation of Labels. */
|
| 1670 |
|
|
|
| 1671 |
|
|
/* A C statement (sans semicolon) to output to the stdio stream STREAM the
|
| 1672 |
|
|
assembler definition of a label named NAME. Use the expression
|
| 1673 |
|
|
`assemble_name (STREAM, NAME)' to output the name itself; before and after
|
| 1674 |
|
|
that, output the additional assembler syntax for defining the name, and a
|
| 1675 |
|
|
newline. */
|
| 1676 |
|
|
#define ASM_OUTPUT_LABEL(STREAM, NAME) \
|
| 1677 |
|
|
do { \
|
| 1678 |
|
|
assemble_name (STREAM, NAME); \
|
| 1679 |
|
|
fputs (":\n", STREAM); \
|
| 1680 |
|
|
} while (0)
|
| 1681 |
|
|
|
| 1682 |
|
|
/* Globalizing directive for a label. */
|
| 1683 |
|
|
#define GLOBAL_ASM_OP "\t.globl "
|
| 1684 |
|
|
|
| 1685 |
|
|
#undef ASM_GENERATE_INTERNAL_LABEL
|
| 1686 |
|
|
#define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \
|
| 1687 |
|
|
do { \
|
| 1688 |
|
|
sprintf (LABEL, "*.%s%ld", PREFIX, (long)NUM); \
|
| 1689 |
|
|
} while (0)
|
| 1690 |
|
|
|
| 1691 |
|
|
|
| 1692 |
|
|
/* Macros Controlling Initialization Routines. */
|
| 1693 |
|
|
|
| 1694 |
|
|
#undef INIT_SECTION_ASM_OP
|
| 1695 |
|
|
|
| 1696 |
|
|
/* If defined, `main' will call `__main' despite the presence of
|
| 1697 |
|
|
`INIT_SECTION_ASM_OP'. This macro should be defined for systems where the
|
| 1698 |
|
|
init section is not actually run automatically, but is still useful for
|
| 1699 |
|
|
collecting the lists of constructors and destructors. */
|
| 1700 |
|
|
#define INVOKE__main
|
| 1701 |
|
|
|
| 1702 |
|
|
/* Output of Assembler Instructions. */
|
| 1703 |
|
|
|
| 1704 |
|
|
/* A C initializer containing the assembler's names for the machine registers,
|
| 1705 |
|
|
each one as a C string constant. This is what translates register numbers
|
| 1706 |
|
|
in the compiler into assembler language. */
|
| 1707 |
|
|
#define REGISTER_NAMES \
|
| 1708 |
|
|
{ \
|
| 1709 |
|
|
"gr0", "sp", "fp", "gr3", "gr4", "gr5", "gr6", "gr7", \
|
| 1710 |
|
|
"gr8", "gr9", "gr10", "gr11", "gr12", "gr13", "gr14", "gr15", \
|
| 1711 |
|
|
"gr16", "gr17", "gr18", "gr19", "gr20", "gr21", "gr22", "gr23", \
|
| 1712 |
|
|
"gr24", "gr25", "gr26", "gr27", "gr28", "gr29", "gr30", "gr31", \
|
| 1713 |
|
|
"gr32", "gr33", "gr34", "gr35", "gr36", "gr37", "gr38", "gr39", \
|
| 1714 |
|
|
"gr40", "gr41", "gr42", "gr43", "gr44", "gr45", "gr46", "gr47", \
|
| 1715 |
|
|
"gr48", "gr49", "gr50", "gr51", "gr52", "gr53", "gr54", "gr55", \
|
| 1716 |
|
|
"gr56", "gr57", "gr58", "gr59", "gr60", "gr61", "gr62", "gr63", \
|
| 1717 |
|
|
\
|
| 1718 |
|
|
"fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
|
| 1719 |
|
|
"fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \
|
| 1720 |
|
|
"fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \
|
| 1721 |
|
|
"fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \
|
| 1722 |
|
|
"fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \
|
| 1723 |
|
|
"fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \
|
| 1724 |
|
|
"fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \
|
| 1725 |
|
|
"fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \
|
| 1726 |
|
|
\
|
| 1727 |
|
|
"fcc0", "fcc1", "fcc2", "fcc3", "icc0", "icc1", "icc2", "icc3", \
|
| 1728 |
|
|
"cc0", "cc1", "cc2", "cc3", "cc4", "cc5", "cc6", "cc7", \
|
| 1729 |
|
|
"acc0", "acc1", "acc2", "acc3", "acc4", "acc5", "acc6", "acc7", \
|
| 1730 |
|
|
"acc8", "acc9", "acc10", "acc11", \
|
| 1731 |
|
|
"accg0","accg1","accg2","accg3","accg4","accg5","accg6","accg7", \
|
| 1732 |
|
|
"accg8", "accg9", "accg10", "accg11", \
|
| 1733 |
|
|
"ap", "lr", "lcr", "iacc0h", "iacc0l" \
|
| 1734 |
|
|
}
|
| 1735 |
|
|
|
| 1736 |
|
|
/* Define this macro if you are using an unusual assembler that
|
| 1737 |
|
|
requires different names for the machine instructions.
|
| 1738 |
|
|
|
| 1739 |
|
|
The definition is a C statement or statements which output an
|
| 1740 |
|
|
assembler instruction opcode to the stdio stream STREAM. The
|
| 1741 |
|
|
macro-operand PTR is a variable of type `char *' which points to
|
| 1742 |
|
|
the opcode name in its "internal" form--the form that is written
|
| 1743 |
|
|
in the machine description. The definition should output the
|
| 1744 |
|
|
opcode name to STREAM, performing any translation you desire, and
|
| 1745 |
|
|
increment the variable PTR to point at the end of the opcode so
|
| 1746 |
|
|
that it will not be output twice.
|
| 1747 |
|
|
|
| 1748 |
|
|
In fact, your macro definition may process less than the entire
|
| 1749 |
|
|
opcode name, or more than the opcode name; but if you want to
|
| 1750 |
|
|
process text that includes `%'-sequences to substitute operands,
|
| 1751 |
|
|
you must take care of the substitution yourself. Just be sure to
|
| 1752 |
|
|
increment PTR over whatever text should not be output normally.
|
| 1753 |
|
|
|
| 1754 |
|
|
If you need to look at the operand values, they can be found as the
|
| 1755 |
|
|
elements of `recog_operand'.
|
| 1756 |
|
|
|
| 1757 |
|
|
If the macro definition does nothing, the instruction is output in
|
| 1758 |
|
|
the usual way. */
|
| 1759 |
|
|
|
| 1760 |
|
|
#define ASM_OUTPUT_OPCODE(STREAM, PTR)\
|
| 1761 |
|
|
(PTR) = frv_asm_output_opcode (STREAM, PTR)
|
| 1762 |
|
|
|
| 1763 |
|
|
/* If defined, a C statement to be executed just prior to the output
|
| 1764 |
|
|
of assembler code for INSN, to modify the extracted operands so
|
| 1765 |
|
|
they will be output differently.
|
| 1766 |
|
|
|
| 1767 |
|
|
Here the argument OPVEC is the vector containing the operands
|
| 1768 |
|
|
extracted from INSN, and NOPERANDS is the number of elements of
|
| 1769 |
|
|
the vector which contain meaningful data for this insn. The
|
| 1770 |
|
|
contents of this vector are what will be used to convert the insn
|
| 1771 |
|
|
template into assembler code, so you can change the assembler
|
| 1772 |
|
|
output by changing the contents of the vector.
|
| 1773 |
|
|
|
| 1774 |
|
|
This macro is useful when various assembler syntaxes share a single
|
| 1775 |
|
|
file of instruction patterns; by defining this macro differently,
|
| 1776 |
|
|
you can cause a large class of instructions to be output
|
| 1777 |
|
|
differently (such as with rearranged operands). Naturally,
|
| 1778 |
|
|
variations in assembler syntax affecting individual insn patterns
|
| 1779 |
|
|
ought to be handled by writing conditional output routines in
|
| 1780 |
|
|
those patterns.
|
| 1781 |
|
|
|
| 1782 |
|
|
If this macro is not defined, it is equivalent to a null statement. */
|
| 1783 |
|
|
|
| 1784 |
|
|
#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS)\
|
| 1785 |
|
|
frv_final_prescan_insn (INSN, OPVEC, NOPERANDS)
|
| 1786 |
|
|
|
| 1787 |
|
|
#undef USER_LABEL_PREFIX
|
| 1788 |
|
|
#define USER_LABEL_PREFIX ""
|
| 1789 |
|
|
#define REGISTER_PREFIX ""
|
| 1790 |
|
|
#define LOCAL_LABEL_PREFIX "."
|
| 1791 |
|
|
#define IMMEDIATE_PREFIX "#"
|
| 1792 |
|
|
|
| 1793 |
|
|
|
| 1794 |
|
|
/* Output of dispatch tables. */
|
| 1795 |
|
|
|
| 1796 |
|
|
/* This macro should be provided on machines where the addresses in a dispatch
|
| 1797 |
|
|
table are relative to the table's own address.
|
| 1798 |
|
|
|
| 1799 |
|
|
The definition should be a C statement to output to the stdio stream STREAM
|
| 1800 |
|
|
an assembler pseudo-instruction to generate a difference between two labels.
|
| 1801 |
|
|
VALUE and REL are the numbers of two internal labels. The definitions of
|
| 1802 |
|
|
these labels are output using `(*targetm.asm_out.internal_label)', and they must be
|
| 1803 |
|
|
printed in the same way here. For example,
|
| 1804 |
|
|
|
| 1805 |
|
|
fprintf (STREAM, "\t.word L%d-L%d\n", VALUE, REL) */
|
| 1806 |
|
|
#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
|
| 1807 |
|
|
fprintf (STREAM, "\t.word .L%d-.L%d\n", VALUE, REL)
|
| 1808 |
|
|
|
| 1809 |
|
|
/* This macro should be provided on machines where the addresses in a dispatch
|
| 1810 |
|
|
table are absolute.
|
| 1811 |
|
|
|
| 1812 |
|
|
The definition should be a C statement to output to the stdio stream STREAM
|
| 1813 |
|
|
an assembler pseudo-instruction to generate a reference to a label. VALUE
|
| 1814 |
|
|
is the number of an internal label whose definition is output using
|
| 1815 |
|
|
`(*targetm.asm_out.internal_label)'. For example,
|
| 1816 |
|
|
|
| 1817 |
|
|
fprintf (STREAM, "\t.word L%d\n", VALUE) */
|
| 1818 |
|
|
#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
|
| 1819 |
|
|
fprintf (STREAM, "\t.word .L%d\n", VALUE)
|
| 1820 |
|
|
|
| 1821 |
|
|
#define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
|
| 1822 |
|
|
|
| 1823 |
|
|
/* Assembler Commands for Exception Regions. */
|
| 1824 |
|
|
|
| 1825 |
|
|
/* Define this macro to 0 if your target supports DWARF 2 frame unwind
|
| 1826 |
|
|
information, but it does not yet work with exception handling. Otherwise,
|
| 1827 |
|
|
if your target supports this information (if it defines
|
| 1828 |
|
|
`INCOMING_RETURN_ADDR_RTX' and either `UNALIGNED_INT_ASM_OP' or
|
| 1829 |
|
|
`OBJECT_FORMAT_ELF'), GCC will provide a default definition of 1.
|
| 1830 |
|
|
|
| 1831 |
|
|
If this macro is defined to 1, the DWARF 2 unwinder will be the default
|
| 1832 |
|
|
exception handling mechanism; otherwise, setjmp/longjmp will be used by
|
| 1833 |
|
|
default.
|
| 1834 |
|
|
|
| 1835 |
|
|
If this macro is defined to anything, the DWARF 2 unwinder will be used
|
| 1836 |
|
|
instead of inline unwinders and __unwind_function in the non-setjmp case. */
|
| 1837 |
|
|
#define DWARF2_UNWIND_INFO 1
|
| 1838 |
|
|
|
| 1839 |
|
|
#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO)
|
| 1840 |
|
|
|
| 1841 |
|
|
/* Assembler Commands for Alignment. */
|
| 1842 |
|
|
|
| 1843 |
|
|
#undef ASM_OUTPUT_SKIP
|
| 1844 |
|
|
#define ASM_OUTPUT_SKIP(STREAM, NBYTES) \
|
| 1845 |
|
|
fprintf (STREAM, "\t.zero\t%u\n", (int)(NBYTES))
|
| 1846 |
|
|
|
| 1847 |
|
|
/* A C statement to output to the stdio stream STREAM an assembler command to
|
| 1848 |
|
|
advance the location counter to a multiple of 2 to the POWER bytes. POWER
|
| 1849 |
|
|
will be a C expression of type `int'. */
|
| 1850 |
|
|
#define ASM_OUTPUT_ALIGN(STREAM, POWER) \
|
| 1851 |
|
|
fprintf ((STREAM), "\t.p2align %d\n", (POWER))
|
| 1852 |
|
|
|
| 1853 |
|
|
/* Inside the text section, align with unpacked nops rather than zeros. */
|
| 1854 |
|
|
#define ASM_OUTPUT_ALIGN_WITH_NOP(STREAM, POWER) \
|
| 1855 |
|
|
fprintf ((STREAM), "\t.p2alignl %d,0x80880000\n", (POWER))
|
| 1856 |
|
|
|
| 1857 |
|
|
/* Macros Affecting all Debug Formats. */
|
| 1858 |
|
|
|
| 1859 |
|
|
/* A C expression that returns the DBX register number for the compiler
|
| 1860 |
|
|
register number REGNO. In simple cases, the value of this expression may be
|
| 1861 |
|
|
REGNO itself. But sometimes there are some registers that the compiler
|
| 1862 |
|
|
knows about and DBX does not, or vice versa. In such cases, some register
|
| 1863 |
|
|
may need to have one number in the compiler and another for DBX.
|
| 1864 |
|
|
|
| 1865 |
|
|
If two registers have consecutive numbers inside GCC, and they can be
|
| 1866 |
|
|
used as a pair to hold a multiword value, then they *must* have consecutive
|
| 1867 |
|
|
numbers after renumbering with `DBX_REGISTER_NUMBER'. Otherwise, debuggers
|
| 1868 |
|
|
will be unable to access such a pair, because they expect register pairs to
|
| 1869 |
|
|
be consecutive in their own numbering scheme.
|
| 1870 |
|
|
|
| 1871 |
|
|
If you find yourself defining `DBX_REGISTER_NUMBER' in way that does not
|
| 1872 |
|
|
preserve register pairs, then what you must do instead is redefine the
|
| 1873 |
|
|
actual register numbering scheme.
|
| 1874 |
|
|
|
| 1875 |
|
|
This declaration is required. */
|
| 1876 |
|
|
#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
|
| 1877 |
|
|
|
| 1878 |
|
|
#undef PREFERRED_DEBUGGING_TYPE
|
| 1879 |
|
|
#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
|
| 1880 |
|
|
|
| 1881 |
|
|
/* Miscellaneous Parameters. */
|
| 1882 |
|
|
|
| 1883 |
|
|
/* An alias for a machine mode name. This is the machine mode that elements of
|
| 1884 |
|
|
a jump-table should have. */
|
| 1885 |
|
|
#define CASE_VECTOR_MODE SImode
|
| 1886 |
|
|
|
| 1887 |
|
|
/* Define this macro if operations between registers with integral mode smaller
|
| 1888 |
|
|
than a word are always performed on the entire register. Most RISC machines
|
| 1889 |
|
|
have this property and most CISC machines do not. */
|
| 1890 |
|
|
#define WORD_REGISTER_OPERATIONS
|
| 1891 |
|
|
|
| 1892 |
|
|
/* Define this macro to be a C expression indicating when insns that read
|
| 1893 |
|
|
memory in MODE, an integral mode narrower than a word, set the bits outside
|
| 1894 |
|
|
of MODE to be either the sign-extension or the zero-extension of the data
|
| 1895 |
|
|
read. Return `SIGN_EXTEND' for values of MODE for which the insn
|
| 1896 |
|
|
sign-extends, `ZERO_EXTEND' for which it zero-extends, and `UNKNOWN' for other
|
| 1897 |
|
|
modes.
|
| 1898 |
|
|
|
| 1899 |
|
|
This macro is not called with MODE non-integral or with a width greater than
|
| 1900 |
|
|
or equal to `BITS_PER_WORD', so you may return any value in this case. Do
|
| 1901 |
|
|
not define this macro if it would always return `UNKNOWN'. On machines where
|
| 1902 |
|
|
this macro is defined, you will normally define it as the constant
|
| 1903 |
|
|
`SIGN_EXTEND' or `ZERO_EXTEND'. */
|
| 1904 |
|
|
#define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
|
| 1905 |
|
|
|
| 1906 |
|
|
/* Define if loading short immediate values into registers sign extends. */
|
| 1907 |
|
|
#define SHORT_IMMEDIATES_SIGN_EXTEND
|
| 1908 |
|
|
|
| 1909 |
|
|
/* The maximum number of bytes that a single instruction can move quickly from
|
| 1910 |
|
|
memory to memory. */
|
| 1911 |
|
|
#define MOVE_MAX 8
|
| 1912 |
|
|
|
| 1913 |
|
|
/* A C expression which is nonzero if on this machine it is safe to "convert"
|
| 1914 |
|
|
an integer of INPREC bits to one of OUTPREC bits (where OUTPREC is smaller
|
| 1915 |
|
|
than INPREC) by merely operating on it as if it had only OUTPREC bits.
|
| 1916 |
|
|
|
| 1917 |
|
|
On many machines, this expression can be 1.
|
| 1918 |
|
|
|
| 1919 |
|
|
When `TRULY_NOOP_TRUNCATION' returns 1 for a pair of sizes for modes for
|
| 1920 |
|
|
which `MODES_TIEABLE_P' is 0, suboptimal code can result. If this is the
|
| 1921 |
|
|
case, making `TRULY_NOOP_TRUNCATION' return 0 in such cases may improve
|
| 1922 |
|
|
things. */
|
| 1923 |
|
|
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
|
| 1924 |
|
|
|
| 1925 |
|
|
/* An alias for the machine mode for pointers. On most machines, define this
|
| 1926 |
|
|
to be the integer mode corresponding to the width of a hardware pointer;
|
| 1927 |
|
|
`SImode' on 32-bit machine or `DImode' on 64-bit machines. On some machines
|
| 1928 |
|
|
you must define this to be one of the partial integer modes, such as
|
| 1929 |
|
|
`PSImode'.
|
| 1930 |
|
|
|
| 1931 |
|
|
The width of `Pmode' must be at least as large as the value of
|
| 1932 |
|
|
`POINTER_SIZE'. If it is not equal, you must define the macro
|
| 1933 |
|
|
`POINTERS_EXTEND_UNSIGNED' to specify how pointers are extended to `Pmode'. */
|
| 1934 |
|
|
#define Pmode SImode
|
| 1935 |
|
|
|
| 1936 |
|
|
/* An alias for the machine mode used for memory references to functions being
|
| 1937 |
|
|
called, in `call' RTL expressions. On most machines this should be
|
| 1938 |
|
|
`QImode'. */
|
| 1939 |
|
|
#define FUNCTION_MODE QImode
|
| 1940 |
|
|
|
| 1941 |
|
|
/* A C expression for the maximum number of instructions to execute via
|
| 1942 |
|
|
conditional execution instructions instead of a branch. A value of
|
| 1943 |
|
|
BRANCH_COST+1 is the default if the machine does not use
|
| 1944 |
|
|
cc0, and 1 if it does use cc0. */
|
| 1945 |
|
|
#define MAX_CONDITIONAL_EXECUTE frv_condexec_insns
|
| 1946 |
|
|
|
| 1947 |
|
|
/* A C expression to modify the code described by the conditional if
|
| 1948 |
|
|
information CE_INFO, possibly updating the tests in TRUE_EXPR, and
|
| 1949 |
|
|
FALSE_EXPR for converting if-then and if-then-else code to conditional
|
| 1950 |
|
|
instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the
|
| 1951 |
|
|
tests cannot be converted. */
|
| 1952 |
|
|
#define IFCVT_MODIFY_TESTS(CE_INFO, TRUE_EXPR, FALSE_EXPR) \
|
| 1953 |
|
|
frv_ifcvt_modify_tests (CE_INFO, &TRUE_EXPR, &FALSE_EXPR)
|
| 1954 |
|
|
|
| 1955 |
|
|
/* A C expression to modify the code described by the conditional if
|
| 1956 |
|
|
information CE_INFO, for the basic block BB, possibly updating the tests in
|
| 1957 |
|
|
TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or
|
| 1958 |
|
|
if-then-else code to conditional instructions. OLD_TRUE and OLD_FALSE are
|
| 1959 |
|
|
the previous tests. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if
|
| 1960 |
|
|
the tests cannot be converted. */
|
| 1961 |
|
|
#define IFCVT_MODIFY_MULTIPLE_TESTS(CE_INFO, BB, TRUE_EXPR, FALSE_EXPR) \
|
| 1962 |
|
|
frv_ifcvt_modify_multiple_tests (CE_INFO, BB, &TRUE_EXPR, &FALSE_EXPR)
|
| 1963 |
|
|
|
| 1964 |
|
|
/* A C expression to modify the code described by the conditional if
|
| 1965 |
|
|
information CE_INFO with the new PATTERN in INSN. If PATTERN is a null
|
| 1966 |
|
|
pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that
|
| 1967 |
|
|
insn cannot be converted to be executed conditionally. */
|
| 1968 |
|
|
#define IFCVT_MODIFY_INSN(CE_INFO, PATTERN, INSN) \
|
| 1969 |
|
|
(PATTERN) = frv_ifcvt_modify_insn (CE_INFO, PATTERN, INSN)
|
| 1970 |
|
|
|
| 1971 |
|
|
/* A C expression to perform any final machine dependent modifications in
|
| 1972 |
|
|
converting code to conditional execution in the code described by the
|
| 1973 |
|
|
conditional if information CE_INFO. */
|
| 1974 |
|
|
#define IFCVT_MODIFY_FINAL(CE_INFO) frv_ifcvt_modify_final (CE_INFO)
|
| 1975 |
|
|
|
| 1976 |
|
|
/* A C expression to cancel any machine dependent modifications in converting
|
| 1977 |
|
|
code to conditional execution in the code described by the conditional if
|
| 1978 |
|
|
information CE_INFO. */
|
| 1979 |
|
|
#define IFCVT_MODIFY_CANCEL(CE_INFO) frv_ifcvt_modify_cancel (CE_INFO)
|
| 1980 |
|
|
|
| 1981 |
|
|
/* Initialize the extra fields provided by IFCVT_EXTRA_FIELDS. */
|
| 1982 |
|
|
#define IFCVT_INIT_EXTRA_FIELDS(CE_INFO) frv_ifcvt_init_extra_fields (CE_INFO)
|
| 1983 |
|
|
|
| 1984 |
|
|
/* The definition of the following macro results in that the 2nd jump
|
| 1985 |
|
|
optimization (after the 2nd insn scheduling) is minimal. It is
|
| 1986 |
|
|
necessary to define when start cycle marks of insns (TImode is used
|
| 1987 |
|
|
for this) is used for VLIW insn packing. Some jump optimizations
|
| 1988 |
|
|
make such marks invalid. These marks are corrected for some
|
| 1989 |
|
|
(minimal) optimizations. ??? Probably the macro is temporary.
|
| 1990 |
|
|
Final solution could making the 2nd jump optimizations before the
|
| 1991 |
|
|
2nd instruction scheduling or corrections of the marks for all jump
|
| 1992 |
|
|
optimizations. Although some jump optimizations are actually
|
| 1993 |
|
|
deoptimizations for VLIW (super-scalar) processors. */
|
| 1994 |
|
|
|
| 1995 |
|
|
#define MINIMAL_SECOND_JUMP_OPTIMIZATION
|
| 1996 |
|
|
|
| 1997 |
|
|
|
| 1998 |
|
|
/* If the following macro is defined and nonzero and deterministic
|
| 1999 |
|
|
finite state automata are used for pipeline hazard recognition, we
|
| 2000 |
|
|
will try to exchange insns in queue ready to improve the schedule.
|
| 2001 |
|
|
The more macro value, the more tries will be made. */
|
| 2002 |
|
|
#define FIRST_CYCLE_MULTIPASS_SCHEDULING 1
|
| 2003 |
|
|
|
| 2004 |
|
|
/* The following macro is used only when value of
|
| 2005 |
|
|
FIRST_CYCLE_MULTIPASS_SCHEDULING is nonzero. The more macro value,
|
| 2006 |
|
|
the more tries will be made to choose better schedule. If the
|
| 2007 |
|
|
macro value is zero or negative there will be no multi-pass
|
| 2008 |
|
|
scheduling. */
|
| 2009 |
|
|
#define FIRST_CYCLE_MULTIPASS_SCHEDULING_LOOKAHEAD frv_sched_lookahead
|
| 2010 |
|
|
|
| 2011 |
|
|
enum frv_builtins
|
| 2012 |
|
|
{
|
| 2013 |
|
|
FRV_BUILTIN_MAND,
|
| 2014 |
|
|
FRV_BUILTIN_MOR,
|
| 2015 |
|
|
FRV_BUILTIN_MXOR,
|
| 2016 |
|
|
FRV_BUILTIN_MNOT,
|
| 2017 |
|
|
FRV_BUILTIN_MAVEH,
|
| 2018 |
|
|
FRV_BUILTIN_MSATHS,
|
| 2019 |
|
|
FRV_BUILTIN_MSATHU,
|
| 2020 |
|
|
FRV_BUILTIN_MADDHSS,
|
| 2021 |
|
|
FRV_BUILTIN_MADDHUS,
|
| 2022 |
|
|
FRV_BUILTIN_MSUBHSS,
|
| 2023 |
|
|
FRV_BUILTIN_MSUBHUS,
|
| 2024 |
|
|
FRV_BUILTIN_MPACKH,
|
| 2025 |
|
|
FRV_BUILTIN_MQADDHSS,
|
| 2026 |
|
|
FRV_BUILTIN_MQADDHUS,
|
| 2027 |
|
|
FRV_BUILTIN_MQSUBHSS,
|
| 2028 |
|
|
FRV_BUILTIN_MQSUBHUS,
|
| 2029 |
|
|
FRV_BUILTIN_MUNPACKH,
|
| 2030 |
|
|
FRV_BUILTIN_MDPACKH,
|
| 2031 |
|
|
FRV_BUILTIN_MBTOH,
|
| 2032 |
|
|
FRV_BUILTIN_MHTOB,
|
| 2033 |
|
|
FRV_BUILTIN_MCOP1,
|
| 2034 |
|
|
FRV_BUILTIN_MCOP2,
|
| 2035 |
|
|
FRV_BUILTIN_MROTLI,
|
| 2036 |
|
|
FRV_BUILTIN_MROTRI,
|
| 2037 |
|
|
FRV_BUILTIN_MWCUT,
|
| 2038 |
|
|
FRV_BUILTIN_MSLLHI,
|
| 2039 |
|
|
FRV_BUILTIN_MSRLHI,
|
| 2040 |
|
|
FRV_BUILTIN_MSRAHI,
|
| 2041 |
|
|
FRV_BUILTIN_MEXPDHW,
|
| 2042 |
|
|
FRV_BUILTIN_MEXPDHD,
|
| 2043 |
|
|
FRV_BUILTIN_MMULHS,
|
| 2044 |
|
|
FRV_BUILTIN_MMULHU,
|
| 2045 |
|
|
FRV_BUILTIN_MMULXHS,
|
| 2046 |
|
|
FRV_BUILTIN_MMULXHU,
|
| 2047 |
|
|
FRV_BUILTIN_MMACHS,
|
| 2048 |
|
|
FRV_BUILTIN_MMACHU,
|
| 2049 |
|
|
FRV_BUILTIN_MMRDHS,
|
| 2050 |
|
|
FRV_BUILTIN_MMRDHU,
|
| 2051 |
|
|
FRV_BUILTIN_MQMULHS,
|
| 2052 |
|
|
FRV_BUILTIN_MQMULHU,
|
| 2053 |
|
|
FRV_BUILTIN_MQMULXHU,
|
| 2054 |
|
|
FRV_BUILTIN_MQMULXHS,
|
| 2055 |
|
|
FRV_BUILTIN_MQMACHS,
|
| 2056 |
|
|
FRV_BUILTIN_MQMACHU,
|
| 2057 |
|
|
FRV_BUILTIN_MCPXRS,
|
| 2058 |
|
|
FRV_BUILTIN_MCPXRU,
|
| 2059 |
|
|
FRV_BUILTIN_MCPXIS,
|
| 2060 |
|
|
FRV_BUILTIN_MCPXIU,
|
| 2061 |
|
|
FRV_BUILTIN_MQCPXRS,
|
| 2062 |
|
|
FRV_BUILTIN_MQCPXRU,
|
| 2063 |
|
|
FRV_BUILTIN_MQCPXIS,
|
| 2064 |
|
|
FRV_BUILTIN_MQCPXIU,
|
| 2065 |
|
|
FRV_BUILTIN_MCUT,
|
| 2066 |
|
|
FRV_BUILTIN_MCUTSS,
|
| 2067 |
|
|
FRV_BUILTIN_MWTACC,
|
| 2068 |
|
|
FRV_BUILTIN_MWTACCG,
|
| 2069 |
|
|
FRV_BUILTIN_MRDACC,
|
| 2070 |
|
|
FRV_BUILTIN_MRDACCG,
|
| 2071 |
|
|
FRV_BUILTIN_MTRAP,
|
| 2072 |
|
|
FRV_BUILTIN_MCLRACC,
|
| 2073 |
|
|
FRV_BUILTIN_MCLRACCA,
|
| 2074 |
|
|
FRV_BUILTIN_MDUNPACKH,
|
| 2075 |
|
|
FRV_BUILTIN_MBTOHE,
|
| 2076 |
|
|
FRV_BUILTIN_MQXMACHS,
|
| 2077 |
|
|
FRV_BUILTIN_MQXMACXHS,
|
| 2078 |
|
|
FRV_BUILTIN_MQMACXHS,
|
| 2079 |
|
|
FRV_BUILTIN_MADDACCS,
|
| 2080 |
|
|
FRV_BUILTIN_MSUBACCS,
|
| 2081 |
|
|
FRV_BUILTIN_MASACCS,
|
| 2082 |
|
|
FRV_BUILTIN_MDADDACCS,
|
| 2083 |
|
|
FRV_BUILTIN_MDSUBACCS,
|
| 2084 |
|
|
FRV_BUILTIN_MDASACCS,
|
| 2085 |
|
|
FRV_BUILTIN_MABSHS,
|
| 2086 |
|
|
FRV_BUILTIN_MDROTLI,
|
| 2087 |
|
|
FRV_BUILTIN_MCPLHI,
|
| 2088 |
|
|
FRV_BUILTIN_MCPLI,
|
| 2089 |
|
|
FRV_BUILTIN_MDCUTSSI,
|
| 2090 |
|
|
FRV_BUILTIN_MQSATHS,
|
| 2091 |
|
|
FRV_BUILTIN_MQLCLRHS,
|
| 2092 |
|
|
FRV_BUILTIN_MQLMTHS,
|
| 2093 |
|
|
FRV_BUILTIN_MQSLLHI,
|
| 2094 |
|
|
FRV_BUILTIN_MQSRAHI,
|
| 2095 |
|
|
FRV_BUILTIN_MHSETLOS,
|
| 2096 |
|
|
FRV_BUILTIN_MHSETLOH,
|
| 2097 |
|
|
FRV_BUILTIN_MHSETHIS,
|
| 2098 |
|
|
FRV_BUILTIN_MHSETHIH,
|
| 2099 |
|
|
FRV_BUILTIN_MHDSETS,
|
| 2100 |
|
|
FRV_BUILTIN_MHDSETH,
|
| 2101 |
|
|
FRV_BUILTIN_SMUL,
|
| 2102 |
|
|
FRV_BUILTIN_UMUL,
|
| 2103 |
|
|
FRV_BUILTIN_PREFETCH0,
|
| 2104 |
|
|
FRV_BUILTIN_PREFETCH,
|
| 2105 |
|
|
FRV_BUILTIN_SMASS,
|
| 2106 |
|
|
FRV_BUILTIN_SMSSS,
|
| 2107 |
|
|
FRV_BUILTIN_SMU,
|
| 2108 |
|
|
FRV_BUILTIN_SCUTSS,
|
| 2109 |
|
|
FRV_BUILTIN_ADDSS,
|
| 2110 |
|
|
FRV_BUILTIN_SUBSS,
|
| 2111 |
|
|
FRV_BUILTIN_SLASS,
|
| 2112 |
|
|
FRV_BUILTIN_IACCreadll,
|
| 2113 |
|
|
FRV_BUILTIN_IACCreadl,
|
| 2114 |
|
|
FRV_BUILTIN_IACCsetll,
|
| 2115 |
|
|
FRV_BUILTIN_IACCsetl,
|
| 2116 |
|
|
FRV_BUILTIN_SCAN,
|
| 2117 |
|
|
FRV_BUILTIN_READ8,
|
| 2118 |
|
|
FRV_BUILTIN_READ16,
|
| 2119 |
|
|
FRV_BUILTIN_READ32,
|
| 2120 |
|
|
FRV_BUILTIN_READ64,
|
| 2121 |
|
|
FRV_BUILTIN_WRITE8,
|
| 2122 |
|
|
FRV_BUILTIN_WRITE16,
|
| 2123 |
|
|
FRV_BUILTIN_WRITE32,
|
| 2124 |
|
|
FRV_BUILTIN_WRITE64
|
| 2125 |
|
|
};
|
| 2126 |
|
|
#define FRV_BUILTIN_FIRST_NONMEDIA FRV_BUILTIN_SMUL
|
| 2127 |
|
|
|
| 2128 |
|
|
/* Enable prototypes on the call rtl functions. */
|
| 2129 |
|
|
#define MD_CALL_PROTOTYPES 1
|
| 2130 |
|
|
|
| 2131 |
|
|
#define CPU_UNITS_QUERY 1
|
| 2132 |
|
|
|
| 2133 |
|
|
#ifdef __FRV_FDPIC__
|
| 2134 |
|
|
#define CRT_GET_RFIB_DATA(dbase) \
|
| 2135 |
|
|
({ extern void *_GLOBAL_OFFSET_TABLE_; (dbase) = &_GLOBAL_OFFSET_TABLE_; })
|
| 2136 |
|
|
#endif
|
| 2137 |
|
|
|
| 2138 |
|
|
#endif /* __FRV_H__ */
|
