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1 709 jeremybenn
;; Frv Machine Description
2
;; Copyright (C) 1999, 2000, 2001, 2003, 2004, 2005, 2007, 2008, 2010
3
;; Free Software Foundation, Inc.
4
;; Contributed by Red Hat, Inc.
5
 
6
;; This file is part of GCC.
7
 
8
;; GCC is free software; you can redistribute it and/or modify
9
;; it under the terms of the GNU General Public License as published by
10
;; the Free Software Foundation; either version 3, or (at your option)
11
;; any later version.
12
 
13
;; GCC is distributed in the hope that it will be useful,
14
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16
;; GNU General Public License for more details.
17
 
18
;; You should have received a copy of the GNU General Public License
19
;; along with GCC; see the file COPYING3.  If not see
20
;; .
21
 
22
;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
23
 
24
 
25
;; ::::::::::::::::::::
26
;; ::
27
;; :: Unspec's used
28
;; ::
29
;; ::::::::::::::::::::
30
 
31
;; GOT constants must go 12/HI/LO for the splitter to work
32
 
33
(define_constants
34
  [(UNSPEC_BLOCKAGE             0)
35
   (UNSPEC_CC_TO_GPR            1)
36
   (UNSPEC_GPR_TO_CC            2)
37
   (UNSPEC_PIC_PROLOGUE         3)
38
   (UNSPEC_CR_LOGIC             4)
39
   (UNSPEC_STACK_ADJUST         5)
40
   (UNSPEC_EH_RETURN_EPILOGUE   6)
41
   (UNSPEC_GOT                  7)
42
   (UNSPEC_LDD                  8)
43
   (UNSPEC_OPTIONAL_MEMBAR      9)
44
 
45
   (UNSPEC_GETTLSOFF                    200)
46
   (UNSPEC_TLS_LOAD_GOTTLSOFF12         201)
47
   (UNSPEC_TLS_INDIRECT_CALL            202)
48
   (UNSPEC_TLS_TLSDESC_LDD              203)
49
   (UNSPEC_TLS_TLSDESC_LDD_AUX          204)
50
   (UNSPEC_TLS_TLSOFF_LD                205)
51
   (UNSPEC_TLS_LDDI                     206)
52
   (UNSPEC_TLSOFF_HILO                  207)
53
 
54
   (R_FRV_GOT12                 11)
55
   (R_FRV_GOTHI                 12)
56
   (R_FRV_GOTLO                 13)
57
   (R_FRV_FUNCDESC              14)
58
   (R_FRV_FUNCDESC_GOT12        15)
59
   (R_FRV_FUNCDESC_GOTHI        16)
60
   (R_FRV_FUNCDESC_GOTLO        17)
61
   (R_FRV_FUNCDESC_VALUE        18)
62
   (R_FRV_FUNCDESC_GOTOFF12     19)
63
   (R_FRV_FUNCDESC_GOTOFFHI     20)
64
   (R_FRV_FUNCDESC_GOTOFFLO     21)
65
   (R_FRV_GOTOFF12              22)
66
   (R_FRV_GOTOFFHI              23)
67
   (R_FRV_GOTOFFLO              24)
68
   (R_FRV_GPREL12               25)
69
   (R_FRV_GPRELHI               26)
70
   (R_FRV_GPRELLO               27)
71
   (R_FRV_GOTTLSOFF_HI          28)
72
   (R_FRV_GOTTLSOFF_LO          29)
73
   (R_FRV_TLSMOFFHI             30)
74
   (R_FRV_TLSMOFFLO             31)
75
   (R_FRV_TLSMOFF12             32)
76
   (R_FRV_TLSDESCHI             33)
77
   (R_FRV_TLSDESCLO             34)
78
   (R_FRV_GOTTLSDESCHI          35)
79
   (R_FRV_GOTTLSDESCLO          36)
80
 
81
   (GR8_REG                     8)
82
   (GR9_REG                     9)
83
   (GR14_REG                    14)
84
   ;; LR_REG conflicts with definition in frv.h
85
   (LRREG                       169)
86
   (FDPIC_REG                   15)
87
   ])
88
 
89
(define_mode_iterator IMODE [QI HI SI DI])
90
(define_mode_attr IMODEsuffix [(QI "b") (HI "h") (SI "") (DI "d")])
91
(define_mode_attr BREADsuffix [(QI "ub") (HI "uh") (SI "") (DI "d")])
92
 
93
;; ::::::::::::::::::::
94
;; ::
95
;; :: Constraints
96
;; ::
97
;; ::::::::::::::::::::
98
 
99
;; Standard Constraints
100
;;
101
;; `m' A memory operand is allowed, with any kind of address that the
102
;;     machine supports in general.
103
;;
104
;; `o' A memory operand is allowed, but only if the address is
105
;;     "offsettable".  This means that adding a small integer (actually, the
106
;;     width in bytes of the operand, as determined by its machine mode) may be
107
;;     added to the address and the result is also a valid memory address.
108
;;
109
;; `V' A memory operand that is not offsettable.  In other words,
110
;;     anything that would fit the `m' constraint but not the `o' constraint.
111
;;
112
;; `<' A memory operand with autodecrement addressing (either
113
;;     predecrement or postdecrement) is allowed.
114
;;
115
;; `>' A memory operand with autoincrement addressing (either
116
;;     preincrement or postincrement) is allowed.
117
;;
118
;; `r' A register operand is allowed provided that it is in a general
119
;;     register.
120
;;
121
;; `d', `a', `f', ...
122
;;     Other letters can be defined in machine-dependent fashion to stand for
123
;;     particular classes of registers.  `d', `a' and `f' are defined on the
124
;;     68000/68020 to stand for data, address and floating point registers.
125
;;
126
;; `i' An immediate integer operand (one with constant value) is allowed.
127
;;     This includes symbolic constants whose values will be known only at
128
;;     assembly time.
129
;;
130
;; `n' An immediate integer operand with a known numeric value is allowed.
131
;;     Many systems cannot support assembly-time constants for operands less
132
;;     than a word wide.  Constraints for these operands should use `n' rather
133
;;     than `i'.
134
;;
135
;; 'I' First machine-dependent integer constant (6-bit signed ints).
136
;; 'J' Second machine-dependent integer constant (10-bit signed ints).
137
;; 'K' Third machine-dependent integer constant (-2048).
138
;; 'L' Fourth machine-dependent integer constant (16-bit signed ints).
139
;; 'M' Fifth machine-dependent integer constant (16-bit unsigned ints).
140
;; 'N' Sixth machine-dependent integer constant (-2047..-1).
141
;; 'O' Seventh machine-dependent integer constant (zero).
142
;; 'P' Eighth machine-dependent integer constant (1..2047).
143
;;
144
;;     Other letters in the range `I' through `P' may be defined in a
145
;;     machine-dependent fashion to permit immediate integer operands with
146
;;     explicit integer values in specified ranges.  For example, on the 68000,
147
;;     `I' is defined to stand for the range of values 1 to 8.  This is the
148
;;     range permitted as a shift count in the shift instructions.
149
;;
150
;; `E' An immediate floating operand (expression code `const_double') is
151
;;     allowed, but only if the target floating point format is the same as
152
;;     that of the host machine (on which the compiler is running).
153
;;
154
;; `F' An immediate floating operand (expression code `const_double') is
155
;;     allowed.
156
;;
157
;; 'G' First machine-dependent const_double.
158
;; 'H' Second machine-dependent const_double.
159
;;
160
;; `s' An immediate integer operand whose value is not an explicit
161
;;     integer is allowed.
162
;;
163
;;     This might appear strange; if an insn allows a constant operand with a
164
;;     value not known at compile time, it certainly must allow any known
165
;;     value.  So why use `s' instead of `i'?  Sometimes it allows better code
166
;;     to be generated.
167
;;
168
;;     For example, on the 68000 in a fullword instruction it is possible to
169
;;     use an immediate operand; but if the immediate value is between -128 and
170
;;     127, better code results from loading the value into a register and
171
;;     using the register.  This is because the load into the register can be
172
;;     done with a `moveq' instruction.  We arrange for this to happen by
173
;;     defining the letter `K' to mean "any integer outside the range -128 to
174
;;     127", and then specifying `Ks' in the operand constraints.
175
;;
176
;; `g' Any register, memory or immediate integer operand is allowed,
177
;;     except for registers that are not general registers.
178
;;
179
;; `X' Any operand whatsoever is allowed, even if it does not satisfy
180
;;     `general_operand'.  This is normally used in the constraint of a
181
;;     `match_scratch' when certain alternatives will not actually require a
182
;;     scratch register.
183
;;
184
;; `0' Match operand 0.
185
;; `1' Match operand 1.
186
;; `2' Match operand 2.
187
;; `3' Match operand 3.
188
;; `4' Match operand 4.
189
;; `5' Match operand 5.
190
;; `6' Match operand 6.
191
;; `7' Match operand 7.
192
;; `8' Match operand 8.
193
;; `9' Match operand 9.
194
;;
195
;;     An operand that matches the specified operand number is allowed.  If a
196
;;     digit is used together with letters within the same alternative, the
197
;;     digit should come last.
198
;;
199
;;     This is called a "matching constraint" and what it really means is that
200
;;     the assembler has only a single operand that fills two roles considered
201
;;     separate in the RTL insn.  For example, an add insn has two input
202
;;     operands and one output operand in the RTL, but on most CISC machines an
203
;;     add instruction really has only two operands, one of them an
204
;;     input-output operand:
205
;;
206
;;          addl #35,r12
207
;;
208
;;     Matching constraints are used in these circumstances.  More precisely,
209
;;     the two operands that match must include one input-only operand and one
210
;;     output-only operand.  Moreover, the digit must be a smaller number than
211
;;     the number of the operand that uses it in the constraint.
212
;;
213
;;     For operands to match in a particular case usually means that they are
214
;;     identical-looking RTL expressions.  But in a few special cases specific
215
;;     kinds of dissimilarity are allowed.  For example, `*x' as an input
216
;;     operand will match `*x++' as an output operand.  For proper results in
217
;;     such cases, the output template should always use the output-operand's
218
;;     number when printing the operand.
219
;;
220
;; `p' An operand that is a valid memory address is allowed.  This is for
221
;;     "load address" and "push address" instructions.
222
;;
223
;;     `p' in the constraint must be accompanied by `address_operand' as the
224
;;     predicate in the `match_operand'.  This predicate interprets the mode
225
;;     specified in the `match_operand' as the mode of the memory reference for
226
;;     which the address would be valid.
227
;;
228
;; `Q` First non constant, non register machine-dependent insns
229
;; `R` Second non constant, non register machine-dependent insns
230
;; `S` Third non constant, non register machine-dependent insns
231
;; `T` Fourth non constant, non register machine-dependent insns
232
;; `U` Fifth non constant, non register machine-dependent insns
233
;;
234
;;     Letters in the range `Q' through `U' may be defined in a
235
;;     machine-dependent fashion to stand for arbitrary operand types.  The
236
;;     machine description macro `EXTRA_CONSTRAINT' is passed the operand as
237
;;     its first argument and the constraint letter as its second operand.
238
;;
239
;;     A typical use for this would be to distinguish certain types of memory
240
;;     references that affect other insn operands.
241
;;
242
;;     Do not define these constraint letters to accept register references
243
;;     (`reg'); the reload pass does not expect this and would not handle it
244
;;     properly.
245
 
246
;; Multiple Alternative Constraints
247
;; `?' Disparage slightly the alternative that the `?' appears in, as a
248
;;     choice when no alternative applies exactly.  The compiler regards this
249
;;     alternative as one unit more costly for each `?' that appears in it.
250
;;
251
;; `!' Disparage severely the alternative that the `!' appears in.  This
252
;;     alternative can still be used if it fits without reloading, but if
253
;;     reloading is needed, some other alternative will be used.
254
 
255
;; Constraint modifiers
256
;; `=' Means that this operand is write-only for this instruction: the
257
;;     previous value is discarded and replaced by output data.
258
;;
259
;; `+' Means that this operand is both read and written by the
260
;;     instruction.
261
;;
262
;;     When the compiler fixes up the operands to satisfy the constraints, it
263
;;     needs to know which operands are inputs to the instruction and which are
264
;;     outputs from it.  `=' identifies an output; `+' identifies an operand
265
;;     that is both input and output; all other operands are assumed to be
266
;;     input only.
267
;;
268
;; `&' Means (in a particular alternative) that this operand is written
269
;;     before the instruction is finished using the input operands.  Therefore,
270
;;     this operand may not lie in a register that is used as an input operand
271
;;     or as part of any memory address.
272
;;
273
;;     `&' applies only to the alternative in which it is written.  In
274
;;     constraints with multiple alternatives, sometimes one alternative
275
;;     requires `&' while others do not.
276
;;
277
;;     `&' does not obviate the need to write `='.
278
;;
279
;; `%' Declares the instruction to be commutative for this operand and the
280
;;     following operand.  This means that the compiler may interchange the two
281
;;     operands if that is the cheapest way to make all operands fit the
282
;;     constraints.  This is often used in patterns for addition instructions
283
;;     that really have only two operands: the result must go in one of the
284
;;     arguments.
285
;;
286
;; `#' Says that all following characters, up to the next comma, are to be
287
;;     ignored as a constraint.  They are significant only for choosing
288
;;     register preferences.
289
;;
290
;; `*' Says that the following character should be ignored when choosing
291
;;     register preferences.  `*' has no effect on the meaning of the
292
;;     constraint as a constraint, and no effect on reloading.
293
 
294
 
295
;; ::::::::::::::::::::
296
;; ::
297
;; :: Attributes
298
;; ::
299
;; ::::::::::::::::::::
300
 
301
;; The `define_attr' expression is used to define each attribute required by
302
;; the target machine.  It looks like:
303
;;
304
;; (define_attr NAME LIST-OF-VALUES DEFAULT)
305
 
306
;; NAME is a string specifying the name of the attribute being defined.
307
 
308
;; LIST-OF-VALUES is either a string that specifies a comma-separated list of
309
;; values that can be assigned to the attribute, or a null string to indicate
310
;; that the attribute takes numeric values.
311
 
312
;; DEFAULT is an attribute expression that gives the value of this attribute
313
;; for insns that match patterns whose definition does not include an explicit
314
;; value for this attribute.
315
 
316
;; For each defined attribute, a number of definitions are written to the
317
;; `insn-attr.h' file.  For cases where an explicit set of values is specified
318
;; for an attribute, the following are defined:
319
 
320
;; * A `#define' is written for the symbol `HAVE_ATTR_NAME'.
321
;;
322
;; * An enumeral class is defined for `attr_NAME' with elements of the
323
;;   form `UPPER-NAME_UPPER-VALUE' where the attribute name and value are first
324
;;   converted to upper case.
325
;;
326
;; * A function `get_attr_NAME' is defined that is passed an insn and
327
;;   returns the attribute value for that insn.
328
 
329
;; For example, if the following is present in the `md' file:
330
;;
331
;; (define_attr "type" "branch,fp,load,store,arith" ...)
332
;;
333
;; the following lines will be written to the file `insn-attr.h'.
334
;;
335
;; #define HAVE_ATTR_type
336
;; enum attr_type {TYPE_BRANCH, TYPE_FP, TYPE_LOAD, TYPE_STORE, TYPE_ARITH};
337
;; extern enum attr_type get_attr_type ();
338
 
339
;; If the attribute takes numeric values, no `enum' type will be defined and
340
;; the function to obtain the attribute's value will return `int'.
341
 
342
(define_attr "length" "" (const_int 4))
343
 
344
;; Processor type -- this attribute must exactly match the processor_type
345
;; enumeration in frv-protos.h.
346
 
347
(define_attr "cpu" "generic,fr550,fr500,fr450,fr405,fr400,fr300,simple,tomcat"
348
  (const (symbol_ref "(enum attr_cpu) frv_cpu_type")))
349
 
350
;; Attribute is "yes" for branches and jumps that span too great a distance
351
;; to be implemented in the most natural way.  Such instructions will use
352
;; a call instruction in some way.
353
 
354
(define_attr "far_jump" "yes,no" (const_string "no"))
355
 
356
;; Instruction type
357
;; "unknown" must come last.
358
(define_attr "type"
359
  "int,sethi,setlo,mul,div,gload,gstore,fload,fstore,movfg,movgf,macc,scan,cut,branch,jump,jumpl,call,spr,trap,fnop,fsconv,fsadd,fscmp,fsmul,fsmadd,fsdiv,sqrt_single,fdconv,fdadd,fdcmp,fdmul,fdmadd,fddiv,sqrt_double,mnop,mlogic,maveh,msath,maddh,mqaddh,mpackh,munpackh,mdpackh,mbhconv,mrot,mshift,mexpdhw,mexpdhd,mwcut,mmulh,mmulxh,mmach,mmrdh,mqmulh,mqmulxh,mqmach,mcpx,mqcpx,mcut,mclracc,mclracca,mdunpackh,mbhconve,mrdacc,mwtacc,maddacc,mdaddacc,mabsh,mdrot,mcpl,mdcut,mqsath,mqlimh,mqshift,mset,ccr,multi,load_or_call,unknown"
360
  (const_string "unknown"))
361
 
362
(define_attr "acc_group" "none,even,odd"
363
  (symbol_ref "(enum attr_acc_group) frv_acc_group (insn)"))
364
 
365
;; Scheduling and Packing Overview
366
;; -------------------------------
367
;;
368
;; FR-V instructions are divided into five groups: integer, floating-point,
369
;; media, branch and control.  Each group is associated with a separate set
370
;; of processing units, the number and behavior of which depend on the target
371
;; target processor.  Integer units have names like I0 and I1, floating-point
372
;; units have names like F0 and F1, and so on.
373
;;
374
;; Each member of the FR-V family has its own restrictions on which
375
;; instructions can issue to which units.  For example, some processors
376
;; allow loads to issue to I0 or I1 while others only allow them to issue
377
;; to I0.  As well as these processor-specific restrictions, there is a
378
;; general rule that an instruction can only issue to unit X + 1 if an
379
;; instruction in the same packet issued to unit X.
380
;;
381
;; Sometimes the only way to honor these restrictions is by adding nops
382
;; to a packet.  For example, on the fr550, media instructions that access
383
;; ACC4-7 can only issue to M1 or M3.  It is therefore only possible to
384
;; execute these instructions by packing them with something that issues
385
;; to M0.  When no useful M0 instruction exists, an "mnop" can be used
386
;; instead.
387
;;
388
;; Having decided which instructions should issue to which units, the packet
389
;; should be ordered according to the following template:
390
;;
391
;;     I0 F0/M0 I1 F1/M1 .... B0 B1 ...
392
;;
393
;; Note that VLIW packets execute strictly in parallel.  Every instruction
394
;; in the packet will stall until all input operands are ready.  These
395
;; operands are then read simultaneously before any registers are modified.
396
;; This means that it's OK to have write-after-read hazards between
397
;; instructions in the same packet, even if the write is listed earlier
398
;; than the read.
399
;;
400
;; Three gcc passes are involved in generating VLIW packets:
401
;;
402
;;    (1) The scheduler.  This pass uses the standard scheduling code and
403
;;        behaves in much the same way as it would for a superscalar RISC
404
;;        architecture.
405
;;
406
;;    (2) frv_reorg.  This pass inserts nops into packets in order to meet
407
;;        the processor's issue requirements.  It also has code to optimize
408
;;        the type of padding used to align labels.
409
;;
410
;;    (3) frv_pack_insns.  The final packing phase, which puts the
411
;;        instructions into assembly language order according to the
412
;;        "I0 F0/M0 ..." template above.
413
;;
414
;; In the ideal case, these three passes will agree on which instructions
415
;; should be packed together, but this won't always happen.  In particular:
416
;;
417
;;    (a) (2) might not pack predicated instructions in the same way as (1).
418
;;        The scheduler tries to schedule predicated instructions for the
419
;;        worst case, assuming the predicate is true.  However, if we have
420
;;        something like a predicated load, it isn't always possible to
421
;;        fill the load delay with useful instructions.  (2) should then
422
;;        pack the user of the loaded value as aggressively as possible,
423
;;        in order to optimize the case when the predicate is false.
424
;;        See frv_pack_insn_p for more details.
425
;;
426
;;    (b) The final shorten_branches pass runs between (2) and (3).
427
;;        Since (2) inserts nops, it is possible that some branches
428
;;        that were thought to be in range during (2) turned out to
429
;;        out-of-range in (3).
430
;;
431
;; All three passes use DFAs to model issue restrictions.  The main
432
;; question that the DFAs are supposed to answer is simply: can these
433
;; instructions be packed together?  The DFAs are not responsible for
434
;; assigning instructions to execution units; that's the job of
435
;; frv_sort_insn_group, see below for details.
436
;;
437
;; To get the best results, the DFAs should try to allow packets to
438
;; be built in every possible order.  This gives the scheduler more
439
;; flexibility, removing the need for things like multipass lookahead.
440
;; It also means we can take more advantage of inter-packet dependencies.
441
;;
442
;; For example, suppose we're compiling for the fr400 and we have:
443
;;
444
;;      addi    gr4,#1,gr5
445
;;      ldi     @(gr6,gr0),gr4
446
;;
447
;; We can pack these instructions together by assigning the load to I0 and
448
;; the addition to I1.  However, because of the anti dependence between the
449
;; two instructions, the scheduler must schedule the addition first.
450
;; We should generally get better schedules if the DFA allows both
451
;; (ldi, addi) and (addi, ldi), leaving the final packing pass to
452
;; reorder the packet where appropriate.
453
;;
454
;; Almost all integer instructions can issue to any unit in the range I0
455
;; to Ix, where the value of "x" depends on the type of instruction and
456
;; on the target processor.  The rules for other instruction groups are
457
;; usually similar.
458
;;
459
;; When the restrictions are as regular as this, we can get the desired
460
;; behavior by claiming the DFA unit associated with the highest unused
461
;; execution unit.  For example, if an instruction can issue to I0 or I1,
462
;; the DFA first tries to take the DFA unit associated with I1, and will
463
;; only take I0's unit if I1 isn't free.  (Note that, as mentioned above,
464
;; the DFA does not assign instructions to units.  An instruction that
465
;; claims DFA unit I1 will not necessarily issue to I1 in the final packet.)
466
;;
467
;; There are some cases, such as the fr550 media restriction mentioned
468
;; above, where the rule is not as simple as "any unit between 0 and X".
469
;; Even so, allocating higher units first brings us close to the ideal.
470
;;
471
;; Having divided instructions into packets, passes (2) and (3) must
472
;; assign instructions to specific execution units.  They do this using
473
;; the following algorithm:
474
;;
475
;;    1. Partition the instructions into groups (integer, float/media, etc.)
476
;;
477
;;    2. For each group of instructions:
478
;;
479
;;       (a) Issue each instruction in the reset DFA state and use the
480
;;           DFA cpu_unit_query interface to find out which unit it picks
481
;;           first.
482
;;
483
;;       (b) Sort the instructions into ascending order of picked units.
484
;;           Instructions that pick I1 first come after those that pick
485
;;           I0 first, and so on.  Let S be the sorted sequence and S[i]
486
;;           be the ith element of it (counting from zero).
487
;;
488
;;       (c) If this is the control or branch group, goto (i)
489
;;
490
;;       (d) Find the largest L such that S[0]...S[L-1] can be issued
491
;;           consecutively from the reset state and such that the DFA
492
;;           claims unit X when S[X] is added.  Let D be the DFA state
493
;;           after instructions S[0]...S[L-1] have been issued.
494
;;
495
;;       (e) If L is the length of S, goto (i)
496
;;
497
;;       (f) Let U be the number of units belonging to this group and #S be
498
;;           the length of S.  Create a new sequence S' by concatenating
499
;;           S[L]...S[#S-1] and (U - #S) nops.
500
;;
501
;;       (g) For each permutation S'' of S', try issuing S'' from last to
502
;;           first, starting with state D.  See if the DFA claims unit
503
;;           X + L when each S''[X] is added.  If so, set S to the
504
;;           concatenation of S[0]...S[L-1] and S'', then goto (i).
505
;;
506
;;       (h) If (g) found no permutation, abort.
507
;;
508
;;       (i) S is now the sorted sequence for this group, meaning that S[X]
509
;;           issues to unit X.  Trim any unwanted nops from the end of S.
510
;;
511
;; The sequence calculated by (b) is trivially correct for control
512
;; instructions since they can't be packed.  It is also correct for branch
513
;; instructions due to their simple issue requirements.  For integer and
514
;; floating-point/media instructions, the sequence calculated by (b) is
515
;; often the correct answer; the rest of the algorithm is optimized for
516
;; the case in which it is correct.
517
;;
518
;; If there were no irregularities in the issue restrictions then step
519
;; (d) would not be needed.  It is mainly there to cope with the fr550
520
;; integer restrictions, where a store can issue to I1, but only if a store
521
;; also issues to I0.  (Note that if a packet has two stores, they will be
522
;; at the beginning of the sequence calculated by (b).)  It also copes
523
;; with fr400 M-2 instructions, which must issue to M0, and which cannot
524
;; be issued together with an mnop in M1.
525
;;
526
;; Step (g) is the main one for integer and float/media instructions.
527
;; The first permutation it tries is S' itself (because, as noted above,
528
;; the sequence calculated by (b) is often correct).  If S' doesn't work,
529
;; the implementation tries varying the beginning of the sequence first.
530
;; Thus the nops towards the end of the sequence will only move to lower
531
;; positions if absolutely necessary.
532
;;
533
;; The algorithm is theoretically exponential in the number of instructions
534
;; in a group, although it's only O(n log(n)) if the sequence calculated by
535
;; (b) is acceptable.  In practice, the algorithm completes quickly even
536
;; in the rare cases where (g) needs to try other permutations.
537
(define_automaton "integer, float_media, branch, control, idiv, div")
538
 
539
;; The main issue units.  Note that not all units are available on
540
;; all processors.
541
(define_query_cpu_unit "i0,i1,i2,i3" "integer")
542
(define_query_cpu_unit "f0,f1,f2,f3" "float_media")
543
(define_query_cpu_unit "b0,b1" "branch")
544
(define_query_cpu_unit "c" "control")
545
 
546
;; Division units.
547
(define_cpu_unit "idiv1,idiv2" "idiv")
548
(define_cpu_unit "div1,div2,root" "div")
549
 
550
;; Control instructions cannot be packed with others.
551
(define_reservation "control" "i0+i1+i2+i3+f0+f1+f2+f3+b0+b1")
552
 
553
;; Generic reservation for control insns
554
(define_insn_reservation "control" 1
555
  (eq_attr "type" "trap,spr,unknown,multi")
556
  "c + control")
557
 
558
;; Reservation for relaxable calls to gettlsoff.
559
(define_insn_reservation "load_or_call" 3
560
  (eq_attr "type" "load_or_call")
561
  "c + control")
562
 
563
;; ::::::::::::::::::::
564
;; ::
565
;; :: Generic/FR500 scheduler description
566
;; ::
567
;; ::::::::::::::::::::
568
 
569
;; Integer insns
570
;; Synthetic units used to describe issue restrictions.
571
(define_automaton "fr500_integer")
572
(define_cpu_unit "fr500_load0,fr500_load1,fr500_store0" "fr500_integer")
573
(exclusion_set "fr500_load0,fr500_load1" "fr500_store0")
574
 
575
(define_bypass 0 "fr500_i1_sethi" "fr500_i1_setlo")
576
(define_insn_reservation "fr500_i1_sethi" 1
577
  (and (eq_attr "cpu" "generic,fr500,tomcat")
578
       (eq_attr "type" "sethi"))
579
  "i1|i0")
580
 
581
(define_insn_reservation "fr500_i1_setlo" 1
582
  (and (eq_attr "cpu" "generic,fr500,tomcat")
583
       (eq_attr "type" "setlo"))
584
  "i1|i0")
585
 
586
(define_insn_reservation "fr500_i1_int" 1
587
  (and (eq_attr "cpu" "generic,fr500,tomcat")
588
       (eq_attr "type" "int"))
589
  "i1|i0")
590
 
591
(define_insn_reservation "fr500_i1_mul" 3
592
  (and (eq_attr "cpu" "generic,fr500,tomcat")
593
       (eq_attr "type" "mul"))
594
  "i1|i0")
595
 
596
(define_insn_reservation "fr500_i1_div" 19
597
  (and (eq_attr "cpu" "generic,fr500,tomcat")
598
       (eq_attr "type" "div"))
599
  "(i1|i0),(idiv1*18|idiv2*18)")
600
 
601
(define_insn_reservation "fr500_i2" 4
602
  (and (eq_attr "cpu" "generic,fr500,tomcat")
603
       (eq_attr "type" "gload,fload"))
604
  "(i1|i0) + (fr500_load0|fr500_load1)")
605
 
606
(define_insn_reservation "fr500_i3" 0
607
  (and (eq_attr "cpu" "generic,fr500,tomcat")
608
       (eq_attr "type" "gstore,fstore"))
609
  "i0 + fr500_store0")
610
 
611
(define_insn_reservation "fr500_i4" 3
612
  (and (eq_attr "cpu" "generic,fr500,tomcat")
613
       (eq_attr "type" "movgf,movfg"))
614
  "i0")
615
 
616
(define_insn_reservation "fr500_i5" 0
617
  (and (eq_attr "cpu" "generic,fr500,tomcat")
618
       (eq_attr "type" "jumpl"))
619
  "i0")
620
 
621
;;
622
;; Branch-instructions
623
;;
624
(define_insn_reservation "fr500_branch" 0
625
  (and (eq_attr "cpu" "generic,fr500,tomcat")
626
       (eq_attr "type" "jump,branch,ccr"))
627
  "b1|b0")
628
 
629
(define_insn_reservation "fr500_call" 0
630
  (and (eq_attr "cpu" "generic,fr500,tomcat")
631
       (eq_attr "type" "call"))
632
  "b0")
633
 
634
;; Floating point insns.  The default latencies are for non-media
635
;; instructions; media instructions incur an extra cycle.
636
 
637
(define_bypass 4 "fr500_farith" "fr500_m1,fr500_m2,fr500_m3,
638
                                 fr500_m4,fr500_m5,fr500_m6")
639
(define_insn_reservation "fr500_farith" 3
640
  (and (eq_attr "cpu" "generic,fr500,tomcat")
641
       (eq_attr "type" "fnop,fsconv,fsadd,fsmul,fsmadd,fdconv,fdadd,fdmul,fdmadd"))
642
  "(f1|f0)")
643
 
644
(define_insn_reservation "fr500_fcmp" 4
645
  (and (eq_attr "cpu" "generic,fr500,tomcat")
646
       (eq_attr "type" "fscmp,fdcmp"))
647
  "(f1|f0)")
648
 
649
(define_bypass 11 "fr500_fdiv" "fr500_m1,fr500_m2,fr500_m3,
650
                                fr500_m4,fr500_m5,fr500_m6")
651
(define_insn_reservation "fr500_fdiv" 10
652
  (and (eq_attr "cpu" "generic,fr500,tomcat")
653
       (eq_attr "type" "fsdiv,fddiv"))
654
  "(f1|f0),(div1*9 | div2*9)")
655
 
656
(define_bypass 16 "fr500_froot" "fr500_m1,fr500_m2,fr500_m3,
657
                                 fr500_m4,fr500_m5,fr500_m6")
658
(define_insn_reservation "fr500_froot" 15
659
  (and (eq_attr "cpu" "generic,fr500,tomcat")
660
       (eq_attr "type" "sqrt_single,sqrt_double"))
661
  "(f1|f0) + root*15")
662
 
663
;; Media insns.  Conflict table is as follows:
664
;;
665
;;           M1  M2  M3  M4  M5  M6
666
;;        M1  -   -   -   -   -   -
667
;;        M2  -   -   -   -   X   X
668
;;        M3  -   -   -   -   X   X
669
;;        M4  -   -   -   -   -   X
670
;;        M5  -   X   X   -   X   X
671
;;        M6  -   X   X   X   X   X
672
;;
673
;; where X indicates an invalid combination.
674
;;
675
;; Target registers are as follows:
676
;;
677
;;        M1 : FPRs
678
;;        M2 : FPRs
679
;;        M3 : ACCs
680
;;        M4 : ACCs
681
;;        M5 : FPRs
682
;;        M6 : ACCs
683
;;
684
;; The default FPR latencies are for integer instructions.
685
;; Floating-point instructions need one cycle more and media
686
;; instructions need one cycle less.
687
(define_automaton "fr500_media")
688
(define_cpu_unit "fr500_m2_0,fr500_m2_1" "fr500_media")
689
(define_cpu_unit "fr500_m3_0,fr500_m3_1" "fr500_media")
690
(define_cpu_unit "fr500_m4_0,fr500_m4_1" "fr500_media")
691
(define_cpu_unit "fr500_m5" "fr500_media")
692
(define_cpu_unit "fr500_m6" "fr500_media")
693
 
694
(exclusion_set "fr500_m5,fr500_m6" "fr500_m2_0,fr500_m2_1,
695
                                    fr500_m3_0,fr500_m3_1")
696
(exclusion_set "fr500_m6" "fr500_m4_0,fr500_m4_1,fr500_m5")
697
 
698
(define_bypass 2 "fr500_m1" "fr500_m1,fr500_m2,fr500_m3,
699
                             fr500_m4,fr500_m5,fr500_m6")
700
(define_bypass 4 "fr500_m1" "fr500_farith,fr500_fcmp,fr500_fdiv,fr500_froot")
701
(define_insn_reservation "fr500_m1" 3
702
  (and (eq_attr "cpu" "generic,fr500,tomcat")
703
       (eq_attr "type" "mnop,mlogic,maveh,msath,maddh,mqaddh"))
704
  "(f1|f0)")
705
 
706
(define_bypass 2 "fr500_m2" "fr500_m1,fr500_m2,fr500_m3,
707
                             fr500_m4,fr500_m5,fr500_m6")
708
(define_bypass 4 "fr500_m2" "fr500_farith,fr500_fcmp,fr500_fdiv,fr500_froot")
709
(define_insn_reservation "fr500_m2" 3
710
  (and (eq_attr "cpu" "generic,fr500,tomcat")
711
       (eq_attr "type" "mrdacc,mpackh,munpackh,mbhconv,mrot,mshift,mexpdhw,mexpdhd,mwcut,mcut,mdunpackh,mbhconve"))
712
  "(f1|f0) + (fr500_m2_0|fr500_m2_1)")
713
 
714
(define_bypass 1 "fr500_m3" "fr500_m4")
715
(define_insn_reservation "fr500_m3" 2
716
  (and (eq_attr "cpu" "generic,fr500,tomcat")
717
       (eq_attr "type" "mclracc,mwtacc"))
718
  "(f1|f0) + (fr500_m3_0|fr500_m3_1)")
719
 
720
(define_bypass 1 "fr500_m4" "fr500_m4")
721
(define_insn_reservation "fr500_m4" 2
722
  (and (eq_attr "cpu" "generic,fr500,tomcat")
723
       (eq_attr "type" "mmulh,mmulxh,mmach,mmrdh,mqmulh,mqmulxh,mqmach,mcpx,mqcpx"))
724
  "(f1|f0) + (fr500_m4_0|fr500_m4_1)")
725
 
726
(define_bypass 2 "fr500_m5" "fr500_m1,fr500_m2,fr500_m3,
727
                             fr500_m4,fr500_m5,fr500_m6")
728
(define_bypass 4 "fr500_m5" "fr500_farith,fr500_fcmp,fr500_fdiv,fr500_froot")
729
(define_insn_reservation "fr500_m5" 3
730
  (and (eq_attr "cpu" "generic,fr500,tomcat")
731
       (eq_attr "type" "mdpackh"))
732
  "(f1|f0) + fr500_m5")
733
 
734
(define_bypass 1 "fr500_m6" "fr500_m4")
735
(define_insn_reservation "fr500_m6" 2
736
  (and (eq_attr "cpu" "generic,fr500,tomcat")
737
       (eq_attr "type" "mclracca"))
738
  "(f1|f0) + fr500_m6")
739
 
740
;; ::::::::::::::::::::
741
;; ::
742
;; :: FR400 scheduler description
743
;; ::
744
;; ::::::::::::::::::::
745
 
746
;; Category 2 media instructions use both media units, but can be packed
747
;; with non-media instructions.  Use fr400_m1unit to claim the M1 unit
748
;; without claiming a slot.
749
 
750
;; Name         Class   Units   Latency
751
;; ====         =====   =====   =======
752
;; int          I1      I0/I1   1
753
;; sethi        I1      I0/I1   0       -- does not interfere with setlo
754
;; setlo        I1      I0/I1   1
755
;; mul          I1      I0      3  (*)
756
;; div          I1      I0      20 (*)
757
;; gload        I2      I0      4  (*)
758
;; fload        I2      I0      4       -- only 3 if read by a media insn
759
;; gstore       I3      I0      0       -- provides no result
760
;; fstore       I3      I0      0       -- provides no result
761
;; movfg        I4      I0      3  (*)
762
;; movgf        I4      I0      3  (*)
763
;; jumpl        I5      I0      0       -- provides no result
764
;;
765
;; (*) The results of these instructions can be read one cycle earlier
766
;; than indicated.  The penalty given is for instructions with write-after-
767
;; write dependencies.
768
 
769
;; The FR400 can only do loads and stores in I0, so we there's no danger
770
;; of memory unit collision in the same packet.  There's only one divide
771
;; unit too.
772
 
773
(define_automaton "fr400_integer")
774
(define_cpu_unit "fr400_mul" "fr400_integer")
775
 
776
(define_insn_reservation "fr400_i1_int" 1
777
  (and (eq_attr "cpu" "fr400,fr405,fr450")
778
       (eq_attr "type" "int"))
779
  "i1|i0")
780
 
781
(define_bypass 0 "fr400_i1_sethi" "fr400_i1_setlo")
782
(define_insn_reservation "fr400_i1_sethi" 1
783
  (and (eq_attr "cpu" "fr400,fr405,fr450")
784
       (eq_attr "type" "sethi"))
785
  "i1|i0")
786
 
787
(define_insn_reservation "fr400_i1_setlo" 1
788
  (and (eq_attr "cpu" "fr400,fr405,fr450")
789
       (eq_attr "type" "setlo"))
790
  "i1|i0")
791
 
792
;; 3 is the worst case (write-after-write hazard).
793
(define_insn_reservation "fr400_i1_mul" 3
794
  (and (eq_attr "cpu" "fr400,fr405")
795
       (eq_attr "type" "mul"))
796
  "i0 + fr400_mul")
797
 
798
(define_insn_reservation "fr450_i1_mul" 2
799
  (and (eq_attr "cpu" "fr450")
800
       (eq_attr "type" "mul"))
801
  "i0 + fr400_mul")
802
 
803
(define_bypass 1 "fr400_i1_macc" "fr400_i1_macc")
804
(define_insn_reservation "fr400_i1_macc" 2
805
  (and (eq_attr "cpu" "fr405,fr450")
806
       (eq_attr "type" "macc"))
807
  "(i0|i1) + fr400_mul")
808
 
809
(define_insn_reservation "fr400_i1_scan" 1
810
  (and (eq_attr "cpu" "fr400,fr405,fr450")
811
       (eq_attr "type" "scan"))
812
  "i0")
813
 
814
(define_insn_reservation "fr400_i1_cut" 2
815
  (and (eq_attr "cpu" "fr405,fr450")
816
       (eq_attr "type" "cut"))
817
  "i0 + fr400_mul")
818
 
819
;; 20 is for a write-after-write hazard.
820
(define_insn_reservation "fr400_i1_div" 20
821
  (and (eq_attr "cpu" "fr400,fr405")
822
       (eq_attr "type" "div"))
823
  "i0 + idiv1*19")
824
 
825
(define_insn_reservation "fr450_i1_div" 19
826
  (and (eq_attr "cpu" "fr450")
827
       (eq_attr "type" "div"))
828
  "i0 + idiv1*19")
829
 
830
;; 4 is for a write-after-write hazard.
831
(define_insn_reservation "fr400_i2" 4
832
  (and (eq_attr "cpu" "fr400,fr405")
833
       (eq_attr "type" "gload,fload"))
834
  "i0")
835
 
836
(define_insn_reservation "fr450_i2_gload" 3
837
  (and (eq_attr "cpu" "fr450")
838
       (eq_attr "type" "gload"))
839
  "i0")
840
 
841
;; 4 is for a write-after-write hazard.
842
(define_insn_reservation "fr450_i2_fload" 4
843
  (and (eq_attr "cpu" "fr450")
844
       (eq_attr "type" "fload"))
845
  "i0")
846
 
847
(define_insn_reservation "fr400_i3" 0
848
  (and (eq_attr "cpu" "fr400,fr405,fr450")
849
       (eq_attr "type" "gstore,fstore"))
850
  "i0")
851
 
852
;; 3 is for a write-after-write hazard.
853
(define_insn_reservation "fr400_i4" 3
854
  (and (eq_attr "cpu" "fr400,fr405")
855
       (eq_attr "type" "movfg,movgf"))
856
  "i0")
857
 
858
(define_insn_reservation "fr450_i4_movfg" 2
859
  (and (eq_attr "cpu" "fr450")
860
       (eq_attr "type" "movfg"))
861
  "i0")
862
 
863
;; 3 is for a write-after-write hazard.
864
(define_insn_reservation "fr450_i4_movgf" 3
865
  (and (eq_attr "cpu" "fr450")
866
       (eq_attr "type" "movgf"))
867
  "i0")
868
 
869
(define_insn_reservation "fr400_i5" 0
870
  (and (eq_attr "cpu" "fr400,fr405,fr450")
871
       (eq_attr "type" "jumpl"))
872
  "i0")
873
 
874
;; The bypass between FPR loads and media instructions, described above.
875
 
876
(define_bypass 3
877
  "fr400_i2"
878
  "fr400_m1_1,fr400_m1_2,\
879
   fr400_m2_1,fr400_m2_2,\
880
   fr400_m3_1,fr400_m3_2,\
881
   fr400_m4_1,fr400_m4_2,\
882
   fr400_m5")
883
 
884
;; The branch instructions all use the B unit and produce no result.
885
 
886
(define_insn_reservation "fr400_b" 0
887
  (and (eq_attr "cpu" "fr400,fr405,fr450")
888
       (eq_attr "type" "jump,branch,ccr,call"))
889
  "b0")
890
 
891
;; FP->FP moves are marked as "fsconv" instructions in the define_insns
892
;; below, but are implemented on the FR400 using "mlogic" instructions.
893
;; It's easier to class "fsconv" as a "m1:1" instruction than provide
894
;; separate define_insns for the FR400.
895
 
896
;; M1 instructions store their results in FPRs.  Any instruction can read
897
;; the result in the following cycle, so no penalty occurs.
898
 
899
(define_automaton "fr400_media")
900
(define_cpu_unit "fr400_m1a,fr400_m1b,fr400_m2a" "fr400_media")
901
(exclusion_set "fr400_m1a,fr400_m1b" "fr400_m2a")
902
 
903
(define_reservation "fr400_m1" "(f1|f0) + (fr400_m1a|fr400_m1b)")
904
(define_reservation "fr400_m2" "f0 + fr400_m2a")
905
 
906
(define_insn_reservation "fr400_m1_1" 1
907
  (and (eq_attr "cpu" "fr400,fr405")
908
       (eq_attr "type" "fsconv,mnop,mlogic,maveh,msath,maddh,mabsh,mset"))
909
  "fr400_m1")
910
 
911
(define_insn_reservation "fr400_m1_2" 1
912
  (and (eq_attr "cpu" "fr400,fr405")
913
       (eq_attr "type" "mqaddh,mqsath,mqlimh,mqshift"))
914
  "fr400_m2")
915
 
916
;; M2 instructions store their results in accumulators, which are read
917
;; by M2 or M4 media commands.  M2 instructions can read the results in
918
;; the following cycle, but M4 instructions must wait a cycle more.
919
 
920
(define_bypass 1
921
  "fr400_m2_1,fr400_m2_2"
922
  "fr400_m2_1,fr400_m2_2")
923
 
924
(define_insn_reservation "fr400_m2_1" 2
925
  (and (eq_attr "cpu" "fr400,fr405")
926
       (eq_attr "type" "mmulh,mmulxh,mmach,mmrdh,mcpx,maddacc"))
927
  "fr400_m1")
928
 
929
(define_insn_reservation "fr400_m2_2" 2
930
  (and (eq_attr "cpu" "fr400,fr405")
931
       (eq_attr "type" "mqmulh,mqmulxh,mqmach,mqcpx,mdaddacc"))
932
  "fr400_m2")
933
 
934
;; For our purposes, there seems to be little real difference between
935
;; M1 and M3 instructions.  Keep them separate anyway in case the distinction
936
;; is needed later.
937
 
938
(define_insn_reservation "fr400_m3_1" 1
939
  (and (eq_attr "cpu" "fr400,fr405")
940
       (eq_attr "type" "mpackh,mrot,mshift,mexpdhw"))
941
  "fr400_m1")
942
 
943
(define_insn_reservation "fr400_m3_2" 1
944
  (and (eq_attr "cpu" "fr400,fr405")
945
       (eq_attr "type" "munpackh,mdpackh,mbhconv,mexpdhd,mwcut,mdrot,mcpl"))
946
  "fr400_m2")
947
 
948
;; M4 instructions write to accumulators or FPRs.  MOVFG and STF
949
;; instructions can read an FPR result in the following cycle, but
950
;; M-unit instructions must wait a cycle more for either kind of result.
951
 
952
(define_bypass 1 "fr400_m4_1,fr400_m4_2" "fr400_i3,fr400_i4")
953
 
954
(define_insn_reservation "fr400_m4_1" 2
955
  (and (eq_attr "cpu" "fr400,fr405")
956
       (eq_attr "type" "mrdacc,mcut,mclracc"))
957
  "fr400_m1")
958
 
959
(define_insn_reservation "fr400_m4_2" 2
960
  (and (eq_attr "cpu" "fr400,fr405")
961
       (eq_attr "type" "mclracca,mdcut"))
962
  "fr400_m2")
963
 
964
;; M5 instructions always incur a 1-cycle penalty.
965
 
966
(define_insn_reservation "fr400_m5" 2
967
  (and (eq_attr "cpu" "fr400,fr405")
968
       (eq_attr "type" "mwtacc"))
969
  "fr400_m2")
970
 
971
;; ::::::::::::::::::::
972
;; ::
973
;; :: FR450 media scheduler description
974
;; ::
975
;; ::::::::::::::::::::
976
 
977
;; The FR451 media restrictions are similar to the FR400's, but not as
978
;; strict and not as regular.  There are 6 categories with the following
979
;; restrictions:
980
;;
981
;;                        M1
982
;;            M-1  M-2  M-3  M-4  M-5  M-6
983
;;      M-1:         x         x         x
984
;;      M-2:    x    x    x    x    x    x
985
;;  M0  M-3:         x         x         x
986
;;      M-4:    x    x    x    x
987
;;      M-5:         x         x         x
988
;;      M-6:    x    x    x    x    x    x
989
;;
990
;; where "x" indicates a conflict.
991
;;
992
;; There is no difference between M-1 and M-3 as far as issue
993
;; restrictions are concerned, so they are combined as "m13".
994
 
995
;; Units for odd-numbered categories.  There can be two of these
996
;; in a packet.
997
(define_cpu_unit "fr450_m13a,fr450_m13b" "float_media")
998
(define_cpu_unit "fr450_m5a,fr450_m5b" "float_media")
999
 
1000
;; Units for even-numbered categories.  There can only be one per packet.
1001
(define_cpu_unit "fr450_m2a,fr450_m4a,fr450_m6a" "float_media")
1002
 
1003
;; Enforce the restriction matrix above.
1004
(exclusion_set "fr450_m2a,fr450_m4a,fr450_m6a" "fr450_m13a,fr450_m13b")
1005
(exclusion_set "fr450_m2a,fr450_m6a" "fr450_m5a,fr450_m5b")
1006
(exclusion_set "fr450_m4a,fr450_m6a" "fr450_m2a")
1007
 
1008
(define_reservation "fr450_m13" "(f1|f0) + (fr450_m13a|fr450_m13b)")
1009
(define_reservation "fr450_m2" "f0 + fr450_m2a")
1010
(define_reservation "fr450_m4" "f0 + fr450_m4a")
1011
(define_reservation "fr450_m5" "(f1|f0) + (fr450_m5a|fr450_m5b)")
1012
(define_reservation "fr450_m6" "(f0|f1) + fr450_m6a")
1013
 
1014
;; MD-1, MD-3 and MD-8 instructions, which are the same as far
1015
;; as scheduling is concerned.  The inputs and outputs are FPRs.
1016
;; Instructions that have 32-bit inputs and outputs belong to M-1 while
1017
;; the rest belong to M-2.
1018
;;
1019
;; ??? Arithmetic shifts (MD-6) have an extra cycle latency, but we don't
1020
;; make the distinction between them and logical shifts.
1021
(define_insn_reservation "fr450_md138_1" 1
1022
  (and (eq_attr "cpu" "fr450")
1023
       (eq_attr "type" "fsconv,mnop,mlogic,maveh,msath,maddh,mabsh,mset,
1024
                        mrot,mshift,mexpdhw,mpackh"))
1025
  "fr450_m13")
1026
 
1027
(define_insn_reservation "fr450_md138_2" 1
1028
  (and (eq_attr "cpu" "fr450")
1029
       (eq_attr "type" "mqaddh,mqsath,mqlimh,
1030
                        mdrot,mwcut,mqshift,mexpdhd,
1031
                        munpackh,mdpackh,mbhconv,mcpl"))
1032
  "fr450_m2")
1033
 
1034
;; MD-2 instructions.  These take FPR or ACC inputs and produce an ACC output.
1035
;; Instructions that write to double ACCs belong to M-3 while those that write
1036
;; to quad ACCs belong to M-4.
1037
(define_insn_reservation "fr450_md2_3" 2
1038
  (and (eq_attr "cpu" "fr450")
1039
       (eq_attr "type" "mmulh,mmach,mcpx,mmulxh,mmrdh,maddacc"))
1040
  "fr450_m13")
1041
 
1042
(define_insn_reservation "fr450_md2_4" 2
1043
  (and (eq_attr "cpu" "fr450")
1044
       (eq_attr "type" "mqmulh,mqmach,mqcpx,mqmulxh,mdaddacc"))
1045
  "fr450_m4")
1046
 
1047
;; Another MD-2 instruction can use the result on the following cycle.
1048
(define_bypass 1 "fr450_md2_3,fr450_md2_4" "fr450_md2_3,fr450_md2_4")
1049
 
1050
;; MD-4 instructions that write to ACCs.
1051
(define_insn_reservation "fr450_md4_3" 2
1052
  (and (eq_attr "cpu" "fr450")
1053
       (eq_attr "type" "mclracc"))
1054
  "fr450_m13")
1055
 
1056
(define_insn_reservation "fr450_md4_4" 3
1057
  (and (eq_attr "cpu" "fr450")
1058
       (eq_attr "type" "mclracca"))
1059
  "fr450_m4")
1060
 
1061
;; MD-4 instructions that write to FPRs.
1062
(define_insn_reservation "fr450_md4_1" 2
1063
  (and (eq_attr "cpu" "fr450")
1064
       (eq_attr "type" "mcut"))
1065
  "fr450_m13")
1066
 
1067
(define_insn_reservation "fr450_md4_5" 2
1068
  (and (eq_attr "cpu" "fr450")
1069
       (eq_attr "type" "mrdacc"))
1070
  "fr450_m5")
1071
 
1072
(define_insn_reservation "fr450_md4_6" 2
1073
  (and (eq_attr "cpu" "fr450")
1074
       (eq_attr "type" "mdcut"))
1075
  "fr450_m6")
1076
 
1077
;; Integer instructions can read the FPR result of an MD-4 instruction on
1078
;; the following cycle.
1079
(define_bypass 1 "fr450_md4_1,fr450_md4_5,fr450_md4_6"
1080
                 "fr400_i3,fr450_i4_movfg")
1081
 
1082
;; MD-5 instructions, which belong to M-3.  They take FPR inputs and
1083
;; write to ACCs.
1084
(define_insn_reservation "fr450_md5_3" 2
1085
  (and (eq_attr "cpu" "fr450")
1086
       (eq_attr "type" "mwtacc"))
1087
  "fr450_m13")
1088
 
1089
;; ::::::::::::::::::::
1090
;; ::
1091
;; :: FR550 scheduler description
1092
;; ::
1093
;; ::::::::::::::::::::
1094
 
1095
;; Prevent loads and stores from being issued in the same packet.
1096
;; These units must go into the generic "integer" reservation because
1097
;; of the constraints on fr550_store0 and fr550_store1.
1098
(define_cpu_unit "fr550_load0,fr550_load1" "integer")
1099
(define_cpu_unit "fr550_store0,fr550_store1" "integer")
1100
(exclusion_set "fr550_load0,fr550_load1" "fr550_store0,fr550_store1")
1101
 
1102
;; A store can only issue to I1 if one has also been issued to I0.
1103
(presence_set "fr550_store1" "fr550_store0")
1104
 
1105
(define_bypass 0 "fr550_sethi" "fr550_setlo")
1106
(define_insn_reservation "fr550_sethi" 1
1107
  (and (eq_attr "cpu" "fr550")
1108
       (eq_attr "type" "sethi"))
1109
  "i3|i2|i1|i0")
1110
 
1111
(define_insn_reservation "fr550_setlo" 1
1112
  (and (eq_attr "cpu" "fr550")
1113
       (eq_attr "type" "setlo"))
1114
  "i3|i2|i1|i0")
1115
 
1116
(define_insn_reservation "fr550_int" 1
1117
  (and (eq_attr "cpu" "fr550")
1118
       (eq_attr "type" "int"))
1119
  "i3|i2|i1|i0")
1120
 
1121
(define_insn_reservation "fr550_mul" 2
1122
  (and (eq_attr "cpu" "fr550")
1123
       (eq_attr "type" "mul"))
1124
  "i1|i0")
1125
 
1126
(define_insn_reservation "fr550_div" 19
1127
  (and (eq_attr "cpu" "fr550")
1128
       (eq_attr "type" "div"))
1129
  "(i1|i0),(idiv1*18 | idiv2*18)")
1130
 
1131
(define_insn_reservation "fr550_load" 3
1132
  (and (eq_attr "cpu" "fr550")
1133
       (eq_attr "type" "gload,fload"))
1134
  "(i1|i0)+(fr550_load0|fr550_load1)")
1135
 
1136
;; We can only issue a store to I1 if one was also issued to I0.
1137
;; This means that, as far as frv_reorder_packet is concerned,
1138
;; the instruction has the same priority as an I0-only instruction.
1139
(define_insn_reservation "fr550_store" 1
1140
  (and (eq_attr "cpu" "fr550")
1141
       (eq_attr "type" "gstore,fstore"))
1142
  "(i0+fr550_store0)|(i1+fr550_store1)")
1143
 
1144
(define_insn_reservation "fr550_transfer" 2
1145
  (and (eq_attr "cpu" "fr550")
1146
       (eq_attr "type" "movgf,movfg"))
1147
  "i0")
1148
 
1149
(define_insn_reservation "fr550_jumpl" 0
1150
  (and (eq_attr "cpu" "fr550")
1151
       (eq_attr "type" "jumpl"))
1152
  "i0")
1153
 
1154
(define_cpu_unit "fr550_ccr0,fr550_ccr1" "float_media")
1155
 
1156
(define_insn_reservation "fr550_branch" 0
1157
  (and (eq_attr "cpu" "fr550")
1158
       (eq_attr "type" "jump,branch"))
1159
  "b1|b0")
1160
 
1161
(define_insn_reservation "fr550_ccr" 0
1162
  (and (eq_attr "cpu" "fr550")
1163
       (eq_attr "type" "ccr"))
1164
  "(b1|b0) + (fr550_ccr1|fr550_ccr0)")
1165
 
1166
(define_insn_reservation "fr550_call" 0
1167
  (and (eq_attr "cpu" "fr550")
1168
       (eq_attr "type" "call"))
1169
  "b0")
1170
 
1171
(define_automaton "fr550_float_media")
1172
(define_cpu_unit "fr550_add0,fr550_add1" "fr550_float_media")
1173
 
1174
;; There are three possible combinations of floating-point/media instructions:
1175
;;
1176
;;    - one media and one float
1177
;;    - up to four float, no media
1178
;;    - up to four media, no float
1179
(define_cpu_unit "fr550_f0,fr550_f1,fr550_f2,fr550_f3" "fr550_float_media")
1180
(define_cpu_unit "fr550_m0,fr550_m1,fr550_m2,fr550_m3" "fr550_float_media")
1181
(exclusion_set "fr550_f1,fr550_f2,fr550_f3" "fr550_m1,fr550_m2,fr550_m3")
1182
(exclusion_set "fr550_m0" "fr550_f1,fr550_f2,fr550_f3")
1183
;; FIXME: This next exclusion set should be defined as well, so that we do
1184
;; not get a packet containing multiple media instructions plus a single
1185
;; floating point instruction.  At the moment we can get away with not
1186
;; defining it because gcc does not seem to generate such packets.
1187
;;
1188
;; If we do enable the exclusion however the insertion of fnop insns into
1189
;; a packet containing media instructions will stop working, because the
1190
;; fnop insn counts as a floating point instruction.  The correct solution
1191
;; is to fix the reservation for the fnop insn so that it does not have the
1192
;; same restrictions as ordinary floating point insns.
1193
;;(exclusion_set "fr550_f0" "fr550_m1,fr550_m2,fr550_m3")
1194
 
1195
(define_reservation "fr550_float" "fr550_f0|fr550_f1|fr550_f2|fr550_f3")
1196
(define_reservation "fr550_media" "fr550_m0|fr550_m1|fr550_m2|fr550_m3")
1197
 
1198
(define_insn_reservation "fr550_f1" 0
1199
  (and (eq_attr "cpu" "fr550")
1200
       (eq_attr "type" "fnop"))
1201
  "(f3|f2|f1|f0) + fr550_float")
1202
 
1203
(define_insn_reservation "fr550_f2" 3
1204
  (and (eq_attr "cpu" "fr550")
1205
       (eq_attr "type" "fsconv,fsadd,fscmp"))
1206
  "(f3|f2|f1|f0) + (fr550_add0|fr550_add1) + fr550_float")
1207
 
1208
(define_insn_reservation "fr550_f3_mul" 3
1209
  (and (eq_attr "cpu" "fr550")
1210
       (eq_attr "type" "fsmul"))
1211
  "(f1|f0) + fr550_float")
1212
 
1213
(define_insn_reservation "fr550_f3_div" 10
1214
  (and (eq_attr "cpu" "fr550")
1215
       (eq_attr "type" "fsdiv"))
1216
  "(f1|f0) + fr550_float")
1217
 
1218
(define_insn_reservation "fr550_f3_sqrt" 15
1219
  (and (eq_attr "cpu" "fr550")
1220
       (eq_attr "type" "sqrt_single"))
1221
  "(f1|f0) + fr550_float")
1222
 
1223
;; Synthetic units for enforcing media issue restrictions.  Certain types
1224
;; of insn in M2 conflict with certain types in M0:
1225
;;
1226
;;                           M2
1227
;;               MNOP   MALU   MSFT   MMAC   MSET
1228
;;         MNOP     -      -      x      -      -
1229
;;         MALU     -      x      x      -      -
1230
;;   M0    MSFT     -      -      x      -      x
1231
;;         MMAC     -      -      x      x      -
1232
;;         MSET     -      -      x      -      -
1233
;;
1234
;; where "x" indicates a conflict.  The same restrictions apply to
1235
;; M3 and M1.
1236
;;
1237
;; In addition -- and this is the awkward bit! -- instructions that
1238
;; access ACC0-3 can only issue to M0 or M2.  Those that access ACC4-7
1239
;; can only issue to M1 or M3.  We refer to such instructions as "even"
1240
;; and "odd" respectively.
1241
(define_cpu_unit "fr550_malu0,fr550_malu1" "float_media")
1242
(define_cpu_unit "fr550_malu2,fr550_malu3" "float_media")
1243
(define_cpu_unit "fr550_msft0,fr550_msft1" "float_media")
1244
(define_cpu_unit "fr550_mmac0,fr550_mmac1" "float_media")
1245
(define_cpu_unit "fr550_mmac2,fr550_mmac3" "float_media")
1246
(define_cpu_unit "fr550_mset0,fr550_mset1" "float_media")
1247
(define_cpu_unit "fr550_mset2,fr550_mset3" "float_media")
1248
 
1249
(exclusion_set "fr550_malu0" "fr550_malu2")
1250
(exclusion_set "fr550_malu1" "fr550_malu3")
1251
 
1252
(exclusion_set "fr550_msft0" "fr550_mset2")
1253
(exclusion_set "fr550_msft1" "fr550_mset3")
1254
 
1255
(exclusion_set "fr550_mmac0" "fr550_mmac2")
1256
(exclusion_set "fr550_mmac1" "fr550_mmac3")
1257
 
1258
;; If an MSFT or MMAC instruction issues to a unit other than M0, we may
1259
;; need to insert some nops.  In the worst case, the packet will end up
1260
;; having 4 integer instructions and 4 media instructions, leaving no
1261
;; room for any branch instructions that the DFA might have accepted.
1262
;;
1263
;; This doesn't matter for JUMP_INSNs and CALL_INSNs because they are
1264
;; always the last instructions to be passed to the DFA, and could be
1265
;; pushed out to a separate packet once the nops have been added.
1266
;; However, it does cause problems for ccr instructions since they
1267
;; can occur anywhere in the unordered packet.
1268
(exclusion_set "fr550_msft1,fr550_mmac1,fr550_mmac2,fr550_mmac3"
1269
               "fr550_ccr0,fr550_ccr1")
1270
 
1271
(define_reservation "fr550_malu"
1272
  "(f3 + fr550_malu3) | (f2 + fr550_malu2)
1273
   | (f1 + fr550_malu1) | (f0 + fr550_malu0)")
1274
 
1275
(define_reservation "fr550_msft_even"
1276
  "f0 + fr550_msft0")
1277
 
1278
(define_reservation "fr550_msft_odd"
1279
  "f1 + fr550_msft1")
1280
 
1281
(define_reservation "fr550_msft_either"
1282
  "(f1 + fr550_msft1) | (f0 + fr550_msft0)")
1283
 
1284
(define_reservation "fr550_mmac_even"
1285
  "(f2 + fr550_mmac2) | (f0 + fr550_mmac0)")
1286
 
1287
(define_reservation "fr550_mmac_odd"
1288
  "(f3 + fr550_mmac3) | (f1 + fr550_mmac1)")
1289
 
1290
(define_reservation "fr550_mset"
1291
  "(f3 + fr550_mset3) | (f2 + fr550_mset2)
1292
    | (f1 + fr550_mset1) | (f0 + fr550_mset0)")
1293
 
1294
(define_insn_reservation "fr550_mnop" 0
1295
  (and (eq_attr "cpu" "fr550")
1296
       (eq_attr "type" "mnop"))
1297
  "fr550_media + (f3|f2|f1|f0)")
1298
 
1299
(define_insn_reservation "fr550_malu" 2
1300
  (and (eq_attr "cpu" "fr550")
1301
       (eq_attr "type" "mlogic,maveh,msath,mabsh,maddh,mqaddh,mqsath"))
1302
  "fr550_media + fr550_malu")
1303
 
1304
;; These insns only operate on FPRs and so don't need to be classified
1305
;; as even/odd.
1306
(define_insn_reservation "fr550_msft_1_either" 2
1307
  (and (eq_attr "cpu" "fr550")
1308
       (eq_attr "type" "mrot,mwcut,mshift,mexpdhw,mexpdhd,mpackh,
1309
                        munpackh,mdpackh,mbhconv,mdrot,mcpl"))
1310
  "fr550_media + fr550_msft_either")
1311
 
1312
;; These insns read from ACC0-3.
1313
(define_insn_reservation "fr550_msft_1_even" 2
1314
  (and (eq_attr "cpu" "fr550")
1315
       (and (eq_attr "type" "mcut,mrdacc,mdcut")
1316
            (eq_attr "acc_group" "even")))
1317
  "fr550_media + fr550_msft_even")
1318
 
1319
;; These insns read from ACC4-7.
1320
(define_insn_reservation "fr550_msft_1_odd" 2
1321
  (and (eq_attr "cpu" "fr550")
1322
       (and (eq_attr "type" "mcut,mrdacc,mdcut")
1323
            (eq_attr "acc_group" "odd")))
1324
  "fr550_media + fr550_msft_odd")
1325
 
1326
;; MCLRACC with A=1 can issue to either M0 or M1.
1327
(define_insn_reservation "fr550_msft_2_either" 2
1328
  (and (eq_attr "cpu" "fr550")
1329
       (eq_attr "type" "mclracca"))
1330
  "fr550_media + fr550_msft_either")
1331
 
1332
;; These insns write to ACC0-3.
1333
(define_insn_reservation "fr550_msft_2_even" 2
1334
  (and (eq_attr "cpu" "fr550")
1335
       (and (eq_attr "type" "mclracc,mwtacc")
1336
            (eq_attr "acc_group" "even")))
1337
  "fr550_media + fr550_msft_even")
1338
 
1339
;; These insns write to ACC4-7.
1340
(define_insn_reservation "fr550_msft_2_odd" 2
1341
  (and (eq_attr "cpu" "fr550")
1342
       (and (eq_attr "type" "mclracc,mwtacc")
1343
            (eq_attr "acc_group" "odd")))
1344
  "fr550_media + fr550_msft_odd")
1345
 
1346
;; These insns read from and write to ACC0-3.
1347
(define_insn_reservation "fr550_mmac_even" 2
1348
  (and (eq_attr "cpu" "fr550")
1349
       (and (eq_attr "type" "mmulh,mmulxh,mmach,mmrdh,mqmulh,mqmulxh,mqmach,
1350
                             maddacc,mdaddacc,mcpx,mqcpx")
1351
            (eq_attr "acc_group" "even")))
1352
  "fr550_media + fr550_mmac_even")
1353
 
1354
;; These insns read from and write to ACC4-7.
1355
(define_insn_reservation "fr550_mmac_odd" 2
1356
  (and (eq_attr "cpu" "fr550")
1357
       (and (eq_attr "type" "mmulh,mmulxh,mmach,mmrdh,mqmulh,mqmulxh,mqmach,
1358
                             maddacc,mdaddacc,mcpx,mqcpx")
1359
            (eq_attr "acc_group" "odd")))
1360
  "fr550_media + fr550_mmac_odd")
1361
 
1362
(define_insn_reservation "fr550_mset" 1
1363
  (and (eq_attr "cpu" "fr550")
1364
       (eq_attr "type" "mset"))
1365
  "fr550_media + fr550_mset")
1366
 
1367
;; ::::::::::::::::::::
1368
;; ::
1369
;; :: Simple/FR300 scheduler description
1370
;; ::
1371
;; ::::::::::::::::::::
1372
 
1373
;; Fr300 or simple processor.  To describe it as 1 insn issue
1374
;; processor, we use control unit.
1375
 
1376
(define_insn_reservation "fr300_lat1" 1
1377
  (and (eq_attr "cpu" "fr300,simple")
1378
       (eq_attr "type" "!gload,fload,movfg,movgf"))
1379
  "c + control")
1380
 
1381
(define_insn_reservation "fr300_lat2" 2
1382
  (and (eq_attr "cpu" "fr300,simple")
1383
       (eq_attr "type" "gload,fload,movfg,movgf"))
1384
  "c + control")
1385
 
1386
 
1387
;; ::::::::::::::::::::
1388
;; ::
1389
;; :: Delay Slots
1390
;; ::
1391
;; ::::::::::::::::::::
1392
 
1393
;; The insn attribute mechanism can be used to specify the requirements for
1394
;; delay slots, if any, on a target machine.  An instruction is said to require
1395
;; a "delay slot" if some instructions that are physically after the
1396
;; instruction are executed as if they were located before it.  Classic
1397
;; examples are branch and call instructions, which often execute the following
1398
;; instruction before the branch or call is performed.
1399
 
1400
;; On some machines, conditional branch instructions can optionally "annul"
1401
;; instructions in the delay slot.  This means that the instruction will not be
1402
;; executed for certain branch outcomes.  Both instructions that annul if the
1403
;; branch is true and instructions that annul if the branch is false are
1404
;; supported.
1405
 
1406
;; Delay slot scheduling differs from instruction scheduling in that
1407
;; determining whether an instruction needs a delay slot is dependent only
1408
;; on the type of instruction being generated, not on data flow between the
1409
;; instructions.  See the next section for a discussion of data-dependent
1410
;; instruction scheduling.
1411
 
1412
;; The requirement of an insn needing one or more delay slots is indicated via
1413
;; the `define_delay' expression.  It has the following form:
1414
;;
1415
;; (define_delay TEST
1416
;;   [DELAY-1 ANNUL-TRUE-1 ANNUL-FALSE-1
1417
;;    DELAY-2 ANNUL-TRUE-2 ANNUL-FALSE-2
1418
;;    ...])
1419
 
1420
;; TEST is an attribute test that indicates whether this `define_delay' applies
1421
;; to a particular insn.  If so, the number of required delay slots is
1422
;; determined by the length of the vector specified as the second argument.  An
1423
;; insn placed in delay slot N must satisfy attribute test DELAY-N.
1424
;; ANNUL-TRUE-N is an attribute test that specifies which insns may be annulled
1425
;; if the branch is true.  Similarly, ANNUL-FALSE-N specifies which insns in
1426
;; the delay slot may be annulled if the branch is false.  If annulling is not
1427
;; supported for that delay slot, `(nil)' should be coded.
1428
 
1429
;; For example, in the common case where branch and call insns require a single
1430
;; delay slot, which may contain any insn other than a branch or call, the
1431
;; following would be placed in the `md' file:
1432
 
1433
;; (define_delay (eq_attr "type" "branch,call")
1434
;;               [(eq_attr "type" "!branch,call") (nil) (nil)])
1435
 
1436
;; Multiple `define_delay' expressions may be specified.  In this case, each
1437
;; such expression specifies different delay slot requirements and there must
1438
;; be no insn for which tests in two `define_delay' expressions are both true.
1439
 
1440
;; For example, if we have a machine that requires one delay slot for branches
1441
;; but two for calls, no delay slot can contain a branch or call insn, and any
1442
;; valid insn in the delay slot for the branch can be annulled if the branch is
1443
;; true, we might represent this as follows:
1444
 
1445
;; (define_delay (eq_attr "type" "branch")
1446
;;   [(eq_attr "type" "!branch,call")
1447
;;    (eq_attr "type" "!branch,call")
1448
;;    (nil)])
1449
;;
1450
;; (define_delay (eq_attr "type" "call")
1451
;;   [(eq_attr "type" "!branch,call") (nil) (nil)
1452
;;    (eq_attr "type" "!branch,call") (nil) (nil)])
1453
 
1454
;; Note - it is the backend's responsibility to fill any unfilled delay slots
1455
;; at assembler generation time.  This is usually done by adding a special print
1456
;; operand to the delayed instruction, and then in the PRINT_OPERAND function
1457
;; calling dbr_sequence_length() to determine how many delay slots were filled.
1458
;; For example:
1459
;;
1460
;; --------------.md-----------------
1461
;; (define_insn "call"
1462
;;  [(call (match_operand 0 "memory_operand" "m")
1463
;;         (match_operand 1 "" ""))]
1464
;;   ""
1465
;;   "call_delayed %0,%1,%2%#"
1466
;;  [(set_attr "length" "4")
1467
;;   (set_attr "type" "call")])
1468
;;
1469
;; -------------.h-------------------
1470
;; #define PRINT_OPERAND_PUNCT_VALID_P(CODE) (CODE == '#')
1471
;;
1472
;;  ------------.c------------------
1473
;; void
1474
;; machine_print_operand (file, x, code)
1475
;;     FILE * file;
1476
;;     rtx    x;
1477
;;     int    code;
1478
;; {
1479
;;   switch (code)
1480
;;   {
1481
;;   case '#':
1482
;;     if (dbr_sequence_length () == 0)
1483
;;       fputs ("\n\tnop", file);
1484
;;     return;
1485
 
1486
;; ::::::::::::::::::::
1487
;; ::
1488
;; :: Notes on Patterns
1489
;; ::
1490
;; ::::::::::::::::::::
1491
 
1492
;; If you need to construct a sequence of assembler instructions in order
1493
;; to implement a pattern be sure to escape any backslashes and double quotes
1494
;; that you use, e.g.:
1495
;;
1496
;; (define_insn "an example"
1497
;;   [(some rtl)]
1498
;;   ""
1499
;;   "*
1500
;;    { static char buffer [100];
1501
;;      sprintf (buffer, \"insn \\t %d\", REGNO (operands[1]));
1502
;;      return buffer;
1503
;;    }"
1504
;; )
1505
;;
1506
;; Also if there is more than one instruction, they can be separated by \\;
1507
;; which is a space saving synonym for \\n\\t:
1508
;;
1509
;; (define_insn "another example"
1510
;;   [(some rtl)]
1511
;;   ""
1512
;;   "*
1513
;;    { static char buffer [100];
1514
;;      sprintf (buffer, \"insn1 \\t %d\\;insn2 \\t %%1\",
1515
;;        REGNO (operands[1]));
1516
;;      return buffer;
1517
;;    }"
1518
;; )
1519
;;
1520
 
1521
(include "predicates.md")
1522
(include "constraints.md")
1523
 
1524
;; ::::::::::::::::::::
1525
;; ::
1526
;; :: Moves
1527
;; ::
1528
;; ::::::::::::::::::::
1529
 
1530
;; Wrap moves in define_expand to prevent memory->memory moves from being
1531
;; generated at the RTL level, which generates better code for most machines
1532
;; which can't do mem->mem moves.
1533
 
1534
;; If operand 0 is a `subreg' with mode M of a register whose own mode is wider
1535
;; than M, the effect of this instruction is to store the specified value in
1536
;; the part of the register that corresponds to mode M.  The effect on the rest
1537
;; of the register is undefined.
1538
 
1539
;; This class of patterns is special in several ways.  First of all, each of
1540
;; these names *must* be defined, because there is no other way to copy a datum
1541
;; from one place to another.
1542
 
1543
;; Second, these patterns are not used solely in the RTL generation pass.  Even
1544
;; the reload pass can generate move insns to copy values from stack slots into
1545
;; temporary registers.  When it does so, one of the operands is a hard
1546
;; register and the other is an operand that can need to be reloaded into a
1547
;; register.
1548
 
1549
;; Therefore, when given such a pair of operands, the pattern must
1550
;; generate RTL which needs no reloading and needs no temporary
1551
;; registers--no registers other than the operands.  For example, if
1552
;; you support the pattern with a `define_expand', then in such a
1553
;; case the `define_expand' mustn't call `force_reg' or any other such
1554
;; function which might generate new pseudo registers.
1555
 
1556
;; This requirement exists even for subword modes on a RISC machine
1557
;; where fetching those modes from memory normally requires several
1558
;; insns and some temporary registers.  Look in `spur.md' to see how
1559
;; the requirement can be satisfied.
1560
 
1561
;; During reload a memory reference with an invalid address may be passed as an
1562
;; operand.  Such an address will be replaced with a valid address later in the
1563
;; reload pass.  In this case, nothing may be done with the address except to
1564
;; use it as it stands.  If it is copied, it will not be replaced with a valid
1565
;; address.  No attempt should be made to make such an address into a valid
1566
;; address and no routine (such as `change_address') that will do so may be
1567
;; called.  Note that `general_operand' will fail when applied to such an
1568
;; address.
1569
;;
1570
;; The global variable `reload_in_progress' (which must be explicitly declared
1571
;; if required) can be used to determine whether such special handling is
1572
;; required.
1573
;;
1574
;; The variety of operands that have reloads depends on the rest of
1575
;; the machine description, but typically on a RISC machine these can
1576
;; only be pseudo registers that did not get hard registers, while on
1577
;; other machines explicit memory references will get optional
1578
;; reloads.
1579
;;
1580
;; If a scratch register is required to move an object to or from memory, it
1581
;; can be allocated using `gen_reg_rtx' prior to reload.  But this is
1582
;; impossible during and after reload.  If there are cases needing scratch
1583
;; registers after reload, you must define `SECONDARY_INPUT_RELOAD_CLASS' and
1584
;; perhaps also `SECONDARY_OUTPUT_RELOAD_CLASS' to detect them, and provide
1585
;; patterns `reload_inM' or `reload_outM' to handle them.
1586
 
1587
;; The constraints on a `moveM' must permit moving any hard register to any
1588
;; other hard register provided that `HARD_REGNO_MODE_OK' permits mode M in
1589
;; both registers and `REGISTER_MOVE_COST' applied to their classes returns a
1590
;; value of 2.
1591
 
1592
;; It is obligatory to support floating point `moveM' instructions
1593
;; into and out of any registers that can hold fixed point values,
1594
;; because unions and structures (which have modes `SImode' or
1595
;; `DImode') can be in those registers and they may have floating
1596
;; point members.
1597
 
1598
;; There may also be a need to support fixed point `moveM' instructions in and
1599
;; out of floating point registers.  Unfortunately, I have forgotten why this
1600
;; was so, and I don't know whether it is still true.  If `HARD_REGNO_MODE_OK'
1601
;; rejects fixed point values in floating point registers, then the constraints
1602
;; of the fixed point `moveM' instructions must be designed to avoid ever
1603
;; trying to reload into a floating point register.
1604
 
1605
(define_expand "movqi"
1606
  [(set (match_operand:QI 0 "general_operand" "")
1607
        (match_operand:QI 1 "general_operand" ""))]
1608
  ""
1609
  "{ frv_emit_move (QImode, operands[0], operands[1]); DONE; }")
1610
 
1611
(define_insn "*movqi_load"
1612
  [(set (match_operand:QI 0 "register_operand" "=d,f")
1613
        (match_operand:QI 1 "frv_load_operand" "m,m"))]
1614
  ""
1615
  "* return output_move_single (operands, insn);"
1616
  [(set_attr "length" "4")
1617
   (set_attr "type" "gload,fload")])
1618
 
1619
(define_insn "*movqi_internal"
1620
  [(set (match_operand:QI 0 "move_destination_operand" "=d,d,m,m,?f,?f,?d,?m,f,d,f")
1621
        (match_operand:QI 1 "move_source_operand"       "L,d,d,O, d, f, f, f,GO,!m,!m"))]
1622
  "register_operand(operands[0], QImode) || reg_or_0_operand (operands[1], QImode)"
1623
  "* return output_move_single (operands, insn);"
1624
  [(set_attr "length" "4")
1625
   (set_attr "type" "int,int,gstore,gstore,movgf,fsconv,movfg,fstore,movgf,gload,fload")])
1626
 
1627
(define_expand "movhi"
1628
  [(set (match_operand:HI 0 "general_operand" "")
1629
        (match_operand:HI 1 "general_operand" ""))]
1630
  ""
1631
  "{ frv_emit_move (HImode, operands[0], operands[1]); DONE; }")
1632
 
1633
(define_insn "*movhi_load"
1634
  [(set (match_operand:HI 0 "register_operand" "=d,f")
1635
        (match_operand:HI 1 "frv_load_operand" "m,m"))]
1636
  ""
1637
  "* return output_move_single (operands, insn);"
1638
  [(set_attr "length" "4")
1639
   (set_attr "type" "gload,fload")])
1640
 
1641
(define_insn "*movhi_internal"
1642
  [(set (match_operand:HI 0 "move_destination_operand" "=d,d,d,m,m,?f,?f,?d,?m,f,d,f")
1643
        (match_operand:HI 1 "move_source_operand"       "L,n,d,d,O, d, f, f, f,GO,!m,!m"))]
1644
  "register_operand(operands[0], HImode) || reg_or_0_operand (operands[1], HImode)"
1645
  "* return output_move_single (operands, insn);"
1646
  [(set_attr "length" "4,8,4,4,4,4,4,4,4,4,4,4")
1647
   (set_attr "type" "int,multi,int,gstore,gstore,movgf,fsconv,movfg,fstore,movgf,gload,fload")])
1648
 
1649
;; Split 2 word load of constants into sethi/setlo instructions
1650
(define_split
1651
  [(set (match_operand:HI 0 "integer_register_operand" "")
1652
        (match_operand:HI 1 "int_2word_operand" ""))]
1653
  "reload_completed"
1654
  [(set (match_dup 0)
1655
        (high:HI (match_dup 1)))
1656
   (set (match_dup 0)
1657
        (lo_sum:HI (match_dup 0)
1658
                (match_dup 1)))]
1659
  "")
1660
 
1661
(define_insn "movhi_high"
1662
  [(set (match_operand:HI 0 "integer_register_operand" "=d")
1663
        (high:HI (match_operand:HI 1 "int_2word_operand" "i")))]
1664
  ""
1665
  "sethi #hi(%1), %0"
1666
  [(set_attr "type" "sethi")
1667
   (set_attr "length" "4")])
1668
 
1669
(define_insn "movhi_lo_sum"
1670
  [(set (match_operand:HI 0 "integer_register_operand" "+d")
1671
        (lo_sum:HI (match_dup 0)
1672
                   (match_operand:HI 1 "int_2word_operand" "i")))]
1673
  ""
1674
  "setlo #lo(%1), %0"
1675
  [(set_attr "type" "setlo")
1676
   (set_attr "length" "4")])
1677
 
1678
(define_expand "movsi"
1679
  [(set (match_operand:SI 0 "move_destination_operand" "")
1680
        (match_operand:SI 1 "move_source_operand" ""))]
1681
  ""
1682
  "{ frv_emit_move (SImode, operands[0], operands[1]); DONE; }")
1683
 
1684
;; Note - it is best to only have one movsi pattern and to handle
1685
;; all the various contingencies by the use of alternatives.  This
1686
;; allows reload the greatest amount of flexibility (since reload will
1687
;; only choose amongst alternatives for a selected insn, it will not
1688
;; replace the insn with another one).
1689
 
1690
;; Unfortunately, we do have to separate out load-type moves from the rest,
1691
;; and only allow memory source operands in the former.  If we do memory and
1692
;; constant loads in a single pattern, reload will be tempted to force
1693
;; constants into memory when the destination is a floating-point register.
1694
;; That may make a function use a PIC pointer when it didn't before, and we
1695
;; cannot change PIC usage (and hence stack layout) so late in the game.
1696
;; The resulting sequences for loading constants into FPRs are preferable
1697
;; even when we're not generating PIC code.
1698
 
1699
;; However, if we don't accept input from memory at all in the generic
1700
;; movsi pattern, reloads for asm instructions that reference pseudos
1701
;; that end up assigned to memory will fail to match, because we
1702
;; recognize them right after they're emitted, and we don't
1703
;; re-recognize them again after the substitution for memory.  So keep
1704
;; a memory constraint available, just make sure reload won't be
1705
;; tempted to use it.
1706
;;
1707
 
1708
 
1709
(define_insn "*movsi_load"
1710
  [(set (match_operand:SI 0 "register_operand" "=d,f")
1711
        (match_operand:SI 1 "frv_load_operand" "m,m"))]
1712
  ""
1713
  "* return output_move_single (operands, insn);"
1714
  [(set_attr "length" "4")
1715
   (set_attr "type" "gload,fload")])
1716
 
1717
(define_insn "*movsi_got"
1718
  [(set (match_operand:SI 0 "integer_register_operand" "=d")
1719
        (match_operand:SI 1 "got12_operand" ""))]
1720
  ""
1721
  "addi gr0, %1, %0"
1722
  [(set_attr "type" "int")
1723
   (set_attr "length" "4")])
1724
 
1725
(define_insn "*movsi_high_got"
1726
  [(set (match_operand:SI 0 "integer_register_operand" "=d")
1727
        (high:SI (match_operand:SI 1 "const_unspec_operand" "")))]
1728
  ""
1729
  "sethi %1, %0"
1730
  [(set_attr "type" "sethi")
1731
   (set_attr "length" "4")])
1732
 
1733
(define_insn "*movsi_lo_sum_got"
1734
  [(set (match_operand:SI 0 "integer_register_operand" "=d")
1735
        (lo_sum:SI (match_operand:SI 1 "integer_register_operand" "0")
1736
                   (match_operand:SI 2 "const_unspec_operand" "")))]
1737
  ""
1738
  "setlo %2, %0"
1739
  [(set_attr "type" "setlo")
1740
   (set_attr "length" "4")])
1741
 
1742
(define_insn "*movsi_internal"
1743
  [(set (match_operand:SI 0 "move_destination_operand" "=d,d,d,m,m,z,d,d,f,f,m,?f,?z,d,f")
1744
        (match_operand:SI 1 "move_source_operand"      "L,n,d,d,O,d,z,f,d,f,f,GO,GO,!m,!m"))]
1745
  "register_operand (operands[0], SImode) || reg_or_0_operand (operands[1], SImode)"
1746
  "* return output_move_single (operands, insn);"
1747
  [(set_attr "length" "4,8,4,4,4,4,4,4,4,4,4,4,4,4,4")
1748
   (set_attr "type" "int,multi,int,gstore,gstore,spr,spr,movfg,movgf,fsconv,fstore,movgf,spr,gload,fload")])
1749
 
1750
;; Split 2 word load of constants into sethi/setlo instructions
1751
(define_insn_and_split "*movsi_2word"
1752
  [(set (match_operand:SI 0 "integer_register_operand" "=d")
1753
        (match_operand:SI 1 "int_2word_operand" "i"))]
1754
  ""
1755
  "#"
1756
  "reload_completed"
1757
  [(set (match_dup 0)
1758
        (high:SI (match_dup 1)))
1759
   (set (match_dup 0)
1760
        (lo_sum:SI (match_dup 0)
1761
                (match_dup 1)))]
1762
  ""
1763
  [(set_attr "length" "8")
1764
   (set_attr "type" "multi")])
1765
 
1766
(define_insn "movsi_high"
1767
  [(set (match_operand:SI 0 "integer_register_operand" "=d")
1768
        (high:SI (match_operand:SI 1 "int_2word_operand" "i")))]
1769
  ""
1770
  "sethi #hi(%1), %0"
1771
  [(set_attr "type" "sethi")
1772
   (set_attr "length" "4")])
1773
 
1774
(define_insn "movsi_lo_sum"
1775
  [(set (match_operand:SI 0 "integer_register_operand" "+d")
1776
        (lo_sum:SI (match_dup 0)
1777
                   (match_operand:SI 1 "int_2word_operand" "i")))]
1778
  ""
1779
  "setlo #lo(%1), %0"
1780
  [(set_attr "type" "setlo")
1781
   (set_attr "length" "4")])
1782
 
1783
(define_expand "movdi"
1784
  [(set (match_operand:DI 0 "nonimmediate_operand" "")
1785
        (match_operand:DI 1 "general_operand" ""))]
1786
  ""
1787
  "{ frv_emit_move (DImode, operands[0], operands[1]); DONE; }")
1788
 
1789
(define_insn "*movdi_double"
1790
  [(set (match_operand:DI 0 "move_destination_operand" "=e,?h,??d,??f,R,?R,??m,??m,e,?h,??d,??f,?e,??d,?h,??f,R,m,e,??d,e,??d,?h,??f")
1791
        (match_operand:DI 1 "move_source_operand"      " e,h,d,f,e,h,d,f,R,R,m,m,h,f,e,d,GO,GO,GO,GO,nF,nF,GO,GO"))]
1792
  "TARGET_DOUBLE
1793
   && (register_operand (operands[0], DImode)
1794
       || reg_or_0_operand (operands[1], DImode))"
1795
  "* return output_move_double (operands, insn);"
1796
  [(set_attr "length" "8,4,8,8,4,4,8,8,4,4,8,8,4,8,4,8,4,8,8,8,16,16,8,8")
1797
   (set_attr "type" "multi,fdconv,multi,multi,gstore,fstore,gstore,fstore,gload,fload,gload,fload,movfg,movfg,movgf,movgf,gstore,gstore,multi,multi,multi,multi,movgf,movgf")])
1798
 
1799
(define_insn "*movdi_nodouble"
1800
  [(set (match_operand:DI 0 "move_destination_operand" "=e,?h,??d,??f,R,?R,??m,??m,e,?h,??d,??f,?e,??d,?h,??f,R,m,e,??d,e,??d,?h,??f")
1801
        (match_operand:DI 1 "move_source_operand"      " e,h,d,f,e,h,d,f,R,R,m,m,h,f,e,d,GO,GO,GO,GO,nF,nF,GO,GO"))]
1802
  "!TARGET_DOUBLE
1803
   && (register_operand (operands[0], DImode)
1804
       || reg_or_0_operand (operands[1], DImode))"
1805
  "* return output_move_double (operands, insn);"
1806
  [(set_attr "length" "8,8,8,8,4,4,8,8,4,4,8,8,8,8,8,8,4,8,8,8,16,16,8,8")
1807
   (set_attr "type" "multi,multi,multi,multi,gstore,fstore,gstore,fstore,gload,fload,gload,fload,movfg,movfg,movgf,movgf,gstore,gstore,multi,multi,multi,multi,movgf,movgf")])
1808
 
1809
(define_split
1810
  [(set (match_operand:DI 0 "register_operand" "")
1811
        (match_operand:DI 1 "dbl_memory_two_insn_operand" ""))]
1812
  "reload_completed"
1813
  [(const_int 0)]
1814
  "frv_split_double_load (operands[0], operands[1]);")
1815
 
1816
(define_split
1817
  [(set (match_operand:DI 0 "odd_reg_operand" "")
1818
        (match_operand:DI 1 "memory_operand" ""))]
1819
  "reload_completed"
1820
  [(const_int 0)]
1821
  "frv_split_double_load (operands[0], operands[1]);")
1822
 
1823
(define_split
1824
  [(set (match_operand:DI 0 "dbl_memory_two_insn_operand" "")
1825
        (match_operand:DI 1 "reg_or_0_operand" ""))]
1826
  "reload_completed"
1827
  [(const_int 0)]
1828
  "frv_split_double_store (operands[0], operands[1]);")
1829
 
1830
(define_split
1831
  [(set (match_operand:DI 0 "memory_operand" "")
1832
        (match_operand:DI 1 "odd_reg_operand" ""))]
1833
  "reload_completed"
1834
  [(const_int 0)]
1835
  "frv_split_double_store (operands[0], operands[1]);")
1836
 
1837
(define_split
1838
  [(set (match_operand:DI 0 "register_operand" "")
1839
        (match_operand:DI 1 "register_operand" ""))]
1840
  "reload_completed
1841
   && (odd_reg_operand (operands[0], DImode)
1842
       || odd_reg_operand (operands[1], DImode)
1843
       || (integer_register_operand (operands[0], DImode)
1844
           && integer_register_operand (operands[1], DImode))
1845
       || (!TARGET_DOUBLE
1846
           && fpr_operand (operands[0], DImode)
1847
           && fpr_operand (operands[1], DImode)))"
1848
  [(set (match_dup 2) (match_dup 4))
1849
   (set (match_dup 3) (match_dup 5))]
1850
  "
1851
{
1852
  rtx op0      = operands[0];
1853
  rtx op0_low  = gen_lowpart (SImode, op0);
1854
  rtx op0_high = gen_highpart (SImode, op0);
1855
  rtx op1      = operands[1];
1856
  rtx op1_low  = gen_lowpart (SImode, op1);
1857
  rtx op1_high = gen_highpart (SImode, op1);
1858
 
1859
  /* We normally copy the low-numbered register first.  However, if the first
1860
     register operand 0 is the same as the second register of operand 1, we
1861
     must copy in the opposite order.  */
1862
 
1863
  if (REGNO (op0_high) == REGNO (op1_low))
1864
    {
1865
      operands[2] = op0_low;
1866
      operands[3] = op0_high;
1867
      operands[4] = op1_low;
1868
      operands[5] = op1_high;
1869
    }
1870
  else
1871
    {
1872
      operands[2] = op0_high;
1873
      operands[3] = op0_low;
1874
      operands[4] = op1_high;
1875
      operands[5] = op1_low;
1876
    }
1877
}")
1878
 
1879
(define_split
1880
  [(set (match_operand:DI 0 "register_operand" "")
1881
        (match_operand:DI 1 "const_int_operand" ""))]
1882
  "reload_completed"
1883
  [(set (match_dup 2) (match_dup 4))
1884
   (set (match_dup 3) (match_dup 5))]
1885
  "
1886
{
1887
  rtx op0 = operands[0];
1888
  rtx op1 = operands[1];
1889
 
1890
  operands[2] = gen_highpart (SImode, op0);
1891
  operands[3] = gen_lowpart (SImode, op0);
1892
  if (HOST_BITS_PER_WIDE_INT <= 32)
1893
    {
1894
      operands[4] = GEN_INT ((INTVAL (op1) < 0) ? -1 : 0);
1895
      operands[5] = op1;
1896
    }
1897
  else
1898
    {
1899
      operands[4] = gen_int_mode ((INTVAL (op1) >> 16) >> 16, SImode);
1900
      operands[5] = gen_int_mode (INTVAL (op1), SImode);
1901
    }
1902
}")
1903
 
1904
(define_split
1905
  [(set (match_operand:DI 0 "register_operand" "")
1906
        (match_operand:DI 1 "const_double_operand" ""))]
1907
  "reload_completed"
1908
  [(set (match_dup 2) (match_dup 4))
1909
   (set (match_dup 3) (match_dup 5))]
1910
  "
1911
{
1912
  rtx op0 = operands[0];
1913
  rtx op1 = operands[1];
1914
 
1915
  operands[2] = gen_highpart (SImode, op0);
1916
  operands[3] = gen_lowpart (SImode, op0);
1917
  operands[4] = GEN_INT (CONST_DOUBLE_HIGH (op1));
1918
  operands[5] = GEN_INT (CONST_DOUBLE_LOW (op1));
1919
}")
1920
 
1921
;; Floating Point Moves
1922
;;
1923
;; Note - Patterns for SF mode moves are compulsory, but
1924
;; patterns for DF are optional, as GCC can synthesize them.
1925
 
1926
(define_expand "movsf"
1927
  [(set (match_operand:SF 0 "general_operand" "")
1928
        (match_operand:SF 1 "general_operand" ""))]
1929
  ""
1930
  "{ frv_emit_move (SFmode, operands[0], operands[1]); DONE; }")
1931
 
1932
(define_split
1933
  [(set (match_operand:SF 0 "integer_register_operand" "")
1934
        (match_operand:SF 1 "int_2word_operand" ""))]
1935
  "reload_completed"
1936
  [(set (match_dup 0)
1937
        (high:SF (match_dup 1)))
1938
   (set (match_dup 0)
1939
        (lo_sum:SF (match_dup 0)
1940
                (match_dup 1)))]
1941
  "")
1942
 
1943
(define_insn "*movsf_load_has_fprs"
1944
  [(set (match_operand:SF 0 "register_operand" "=f,d")
1945
        (match_operand:SF 1 "frv_load_operand" "m,m"))]
1946
  "TARGET_HAS_FPRS"
1947
  "* return output_move_single (operands, insn);"
1948
  [(set_attr "length" "4")
1949
   (set_attr "type" "fload,gload")])
1950
 
1951
(define_insn "*movsf_internal_has_fprs"
1952
  [(set (match_operand:SF 0 "move_destination_operand" "=f,f,m,m,?f,?d,?d,m,?d")
1953
        (match_operand:SF 1 "move_source_operand" "f,OG,f,OG,d,f,d,d,F"))]
1954
  "TARGET_HAS_FPRS
1955
   && (register_operand (operands[0], SFmode) || reg_or_0_operand (operands[1], SFmode))"
1956
  "* return output_move_single (operands, insn);"
1957
  [(set_attr "length" "4,4,4,4,4,4,4,4,8")
1958
   (set_attr "type" "fsconv,movgf,fstore,gstore,movgf,movfg,int,gstore,multi")])
1959
 
1960
;; If we don't support the double instructions, prefer gprs over fprs, since it
1961
;; will all be emulated
1962
(define_insn "*movsf_internal_no_fprs"
1963
  [(set (match_operand:SF 0 "move_destination_operand" "=d,d,m,d,d")
1964
        (match_operand:SF 1 "move_source_operand"      " d,OG,dOG,m,F"))]
1965
  "!TARGET_HAS_FPRS
1966
   && (register_operand (operands[0], SFmode) || reg_or_0_operand (operands[1], SFmode))"
1967
  "* return output_move_single (operands, insn);"
1968
  [(set_attr "length" "4,4,4,4,8")
1969
   (set_attr "type" "int,int,gstore,gload,multi")])
1970
 
1971
(define_insn "movsf_high"
1972
  [(set (match_operand:SF 0 "integer_register_operand" "=d")
1973
        (high:SF (match_operand:SF 1 "int_2word_operand" "i")))]
1974
  ""
1975
  "sethi #hi(%1), %0"
1976
  [(set_attr "type" "sethi")
1977
   (set_attr "length" "4")])
1978
 
1979
(define_insn "movsf_lo_sum"
1980
  [(set (match_operand:SF 0 "integer_register_operand" "+d")
1981
        (lo_sum:SF (match_dup 0)
1982
                   (match_operand:SF 1 "int_2word_operand" "i")))]
1983
  ""
1984
  "setlo #lo(%1), %0"
1985
  [(set_attr "type" "setlo")
1986
   (set_attr "length" "4")])
1987
 
1988
(define_expand "movdf"
1989
  [(set (match_operand:DF 0 "nonimmediate_operand" "")
1990
        (match_operand:DF 1 "general_operand" ""))]
1991
  ""
1992
  "{ frv_emit_move (DFmode, operands[0], operands[1]); DONE; }")
1993
 
1994
(define_insn "*movdf_double"
1995
  [(set (match_operand:DF 0 "move_destination_operand" "=h,?e,??f,??d,R,?R,??m,??m,h,?e,??f,??d,?h,??f,?e,??d,R,m,h,??f,e,??d,e,??d")
1996
        (match_operand:DF 1 "move_source_operand"      " h,e,f,d,h,e,f,d,R,R,m,m,e,d,h,f,GO,GO,GO,GO,GO,GO,F,F"))]
1997
  "TARGET_DOUBLE
1998
   && (register_operand (operands[0], DFmode)
1999
       || reg_or_0_operand (operands[1], DFmode))"
2000
  "* return output_move_double (operands, insn);"
2001
  [(set_attr "length" "4,8,8,8,4,4,8,8,4,4,8,8,4,8,4,8,4,8,8,8,8,8,16,16")
2002
   (set_attr "type" "fdconv,multi,multi,multi,fstore,gstore,fstore,gstore,fload,gload,fload,gload,movgf,movgf,movfg,movfg,gstore,gstore,movgf,movgf,multi,multi,multi,multi")])
2003
 
2004
;; If we don't support the double instructions, prefer gprs over fprs, since it
2005
;; will all be emulated
2006
(define_insn "*movdf_nodouble"
2007
  [(set (match_operand:DF 0 "move_destination_operand" "=e,?h,??d,??f,R,?R,??m,??m,e,?h,??d,??f,?e,??d,?h,??f,R,m,e,??d,e,??d,?h,??f")
2008
        (match_operand:DF 1 "move_source_operand"      " e,h,d,f,e,h,d,f,R,R,m,m,h,f,e,d,GO,GO,GO,GO,nF,nF,GO,GO"))]
2009
  "!TARGET_DOUBLE
2010
   && (register_operand (operands[0], DFmode)
2011
       || reg_or_0_operand (operands[1], DFmode))"
2012
  "* return output_move_double (operands, insn);"
2013
  [(set_attr "length" "8,8,8,8,4,4,8,8,4,4,8,8,8,8,8,8,4,8,8,8,16,16,8,8")
2014
   (set_attr "type" "multi,multi,multi,multi,gstore,fstore,gstore,fstore,gload,fload,gload,fload,movfg,movfg,movgf,movgf,gstore,gstore,multi,multi,multi,multi,movgf,movgf")])
2015
 
2016
(define_split
2017
  [(set (match_operand:DF 0 "register_operand" "")
2018
        (match_operand:DF 1 "dbl_memory_two_insn_operand" ""))]
2019
  "reload_completed"
2020
  [(const_int 0)]
2021
  "frv_split_double_load (operands[0], operands[1]);")
2022
 
2023
(define_split
2024
  [(set (match_operand:DF 0 "odd_reg_operand" "")
2025
        (match_operand:DF 1 "memory_operand" ""))]
2026
  "reload_completed"
2027
  [(const_int 0)]
2028
  "frv_split_double_load (operands[0], operands[1]);")
2029
 
2030
(define_split
2031
  [(set (match_operand:DF 0 "dbl_memory_two_insn_operand" "")
2032
        (match_operand:DF 1 "reg_or_0_operand" ""))]
2033
  "reload_completed"
2034
  [(const_int 0)]
2035
  "frv_split_double_store (operands[0], operands[1]);")
2036
 
2037
(define_split
2038
  [(set (match_operand:DF 0 "memory_operand" "")
2039
        (match_operand:DF 1 "odd_reg_operand" ""))]
2040
  "reload_completed"
2041
  [(const_int 0)]
2042
  "frv_split_double_store (operands[0], operands[1]);")
2043
 
2044
(define_split
2045
  [(set (match_operand:DF 0 "register_operand" "")
2046
        (match_operand:DF 1 "register_operand" ""))]
2047
  "reload_completed
2048
   && (odd_reg_operand (operands[0], DFmode)
2049
       || odd_reg_operand (operands[1], DFmode)
2050
       || (integer_register_operand (operands[0], DFmode)
2051
           && integer_register_operand (operands[1], DFmode))
2052
       || (!TARGET_DOUBLE
2053
           && fpr_operand (operands[0], DFmode)
2054
           && fpr_operand (operands[1], DFmode)))"
2055
  [(set (match_dup 2) (match_dup 4))
2056
   (set (match_dup 3) (match_dup 5))]
2057
  "
2058
{
2059
  rtx op0      = operands[0];
2060
  rtx op0_low  = gen_lowpart (SImode, op0);
2061
  rtx op0_high = gen_highpart (SImode, op0);
2062
  rtx op1      = operands[1];
2063
  rtx op1_low  = gen_lowpart (SImode, op1);
2064
  rtx op1_high = gen_highpart (SImode, op1);
2065
 
2066
  /* We normally copy the low-numbered register first.  However, if the first
2067
     register operand 0 is the same as the second register of operand 1, we
2068
     must copy in the opposite order.  */
2069
 
2070
  if (REGNO (op0_high) == REGNO (op1_low))
2071
    {
2072
      operands[2] = op0_low;
2073
      operands[3] = op0_high;
2074
      operands[4] = op1_low;
2075
      operands[5] = op1_high;
2076
    }
2077
  else
2078
    {
2079
      operands[2] = op0_high;
2080
      operands[3] = op0_low;
2081
      operands[4] = op1_high;
2082
      operands[5] = op1_low;
2083
    }
2084
}")
2085
 
2086
(define_split
2087
  [(set (match_operand:DF 0 "register_operand" "")
2088
        (match_operand:DF 1 "const_int_operand" ""))]
2089
  "reload_completed"
2090
  [(set (match_dup 2) (match_dup 4))
2091
   (set (match_dup 3) (match_dup 5))]
2092
  "
2093
{
2094
  rtx op0 = operands[0];
2095
  rtx op1 = operands[1];
2096
 
2097
  operands[2] = gen_highpart (SImode, op0);
2098
  operands[3] = gen_lowpart (SImode, op0);
2099
  if (HOST_BITS_PER_WIDE_INT <= 32)
2100
    {
2101
      operands[4] = GEN_INT ((INTVAL (op1) < 0) ? -1 : 0);
2102
      operands[5] = op1;
2103
    }
2104
  else
2105
    {
2106
      operands[4] = GEN_INT (((((unsigned HOST_WIDE_INT)INTVAL (op1) >> 16)
2107
                              >> 16) ^ ((unsigned HOST_WIDE_INT)1 << 31))
2108
                             - ((unsigned HOST_WIDE_INT)1 << 31));
2109
      operands[5] = GEN_INT (trunc_int_for_mode (INTVAL (op1), SImode));
2110
    }
2111
}")
2112
 
2113
(define_split
2114
  [(set (match_operand:DF 0 "register_operand" "")
2115
        (match_operand:DF 1 "const_double_operand" ""))]
2116
  "reload_completed"
2117
  [(set (match_dup 2) (match_dup 4))
2118
   (set (match_dup 3) (match_dup 5))]
2119
  "
2120
{
2121
  rtx op0 = operands[0];
2122
  rtx op1 = operands[1];
2123
  REAL_VALUE_TYPE rv;
2124
  long l[2];
2125
 
2126
  REAL_VALUE_FROM_CONST_DOUBLE (rv, op1);
2127
  REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
2128
 
2129
  operands[2] = gen_highpart (SImode, op0);
2130
  operands[3] = gen_lowpart (SImode, op0);
2131
  operands[4] = GEN_INT (l[0]);
2132
  operands[5] = GEN_INT (l[1]);
2133
}")
2134
 
2135
;; String/block move insn.
2136
;; Argument 0 is the destination
2137
;; Argument 1 is the source
2138
;; Argument 2 is the length
2139
;; Argument 3 is the alignment
2140
 
2141
(define_expand "movmemsi"
2142
  [(parallel [(set (match_operand:BLK 0 "" "")
2143
                   (match_operand:BLK 1 "" ""))
2144
              (use (match_operand:SI 2 "" ""))
2145
              (use (match_operand:SI 3 "" ""))])]
2146
  ""
2147
  "
2148
{
2149
  if (frv_expand_block_move (operands))
2150
    DONE;
2151
  else
2152
    FAIL;
2153
}")
2154
 
2155
;; String/block set insn.
2156
;; Argument 0 is the destination
2157
;; Argument 1 is the length
2158
;; Argument 2 is the byte value -- ignore any value but zero
2159
;; Argument 3 is the alignment
2160
 
2161
(define_expand "setmemsi"
2162
  [(parallel [(set (match_operand:BLK 0 "" "")
2163
                   (match_operand 2 "" ""))
2164
              (use (match_operand:SI 1 "" ""))
2165
              (use (match_operand:SI 3 "" ""))])]
2166
  ""
2167
  "
2168
{
2169
  /* If value to set is not zero, use the library routine.  */
2170
  if (operands[2] != const0_rtx)
2171
    FAIL;
2172
 
2173
  if (frv_expand_block_clear (operands))
2174
    DONE;
2175
  else
2176
    FAIL;
2177
}")
2178
 
2179
 
2180
;; The "membar" part of a __builtin_read* or __builtin_write* function.
2181
;; Operand 0 is a volatile reference to the memory that the function reads
2182
;; or writes.  Operand 1 is the address being accessed, or zero if the
2183
;; address isn't a known constant.  Operand 2 describes the __builtin
2184
;; function (either FRV_IO_READ or FRV_IO_WRITE).
2185
(define_insn "optional_membar_"
2186
  [(set (match_operand:IMODE 0 "memory_operand" "=m")
2187
        (unspec:IMODE [(match_operand 1 "const_int_operand" "")
2188
                       (match_operand 2 "const_int_operand" "")]
2189
                      UNSPEC_OPTIONAL_MEMBAR))]
2190
  ""
2191
  "membar"
2192
  [(set_attr "length" "4")])
2193
 
2194
;; ::::::::::::::::::::
2195
;; ::
2196
;; :: Reload CC registers
2197
;; ::
2198
;; ::::::::::::::::::::
2199
 
2200
;; Use as a define_expand so that cse/gcse/combine can't accidentally
2201
;; create movcc insns.
2202
 
2203
(define_expand "movcc"
2204
  [(parallel [(set (match_operand:CC 0 "move_destination_operand" "")
2205
                   (match_operand:CC 1 "move_source_operand" ""))
2206
              (clobber (match_dup 2))])]
2207
  ""
2208
  "
2209
{
2210
 if (! reload_in_progress && ! reload_completed)
2211
    FAIL;
2212
 
2213
 operands[2] = gen_rtx_REG (CC_CCRmode, ICR_TEMP);
2214
}")
2215
 
2216
(define_insn "*internal_movcc"
2217
  [(set (match_operand:CC 0 "move_destination_operand" "=t,d,d,m,d")
2218
        (match_operand:CC 1 "move_source_operand" "d,d,m,d,t"))
2219
   (clobber (match_scratch:CC_CCR 2 "=X,X,X,X,&v"))]
2220
  "reload_in_progress || reload_completed"
2221
  "@
2222
   cmpi %1, #0, %0
2223
   mov %1, %0
2224
   ld%I1%U1 %M1, %0
2225
   st%I0%U0 %1, %M0
2226
   #"
2227
  [(set_attr "length" "4,4,4,4,20")
2228
   (set_attr "type" "int,int,gload,gstore,multi")])
2229
 
2230
;; To move an ICC value to a GPR for a signed comparison, we create a value
2231
;; that when compared to 0, sets the N and Z flags appropriately (we don't care
2232
;; about the V and C flags, since these comparisons are signed).
2233
 
2234
(define_split
2235
  [(set (match_operand:CC 0 "integer_register_operand" "")
2236
        (match_operand:CC 1 "icc_operand" ""))
2237
   (clobber (match_operand:CC_CCR 2 "icr_operand" ""))]
2238
  "reload_in_progress || reload_completed"
2239
  [(match_dup 3)]
2240
  "
2241
{
2242
  rtx dest = simplify_gen_subreg (SImode, operands[0], CCmode, 0);
2243
  rtx icc  = operands[1];
2244
  rtx icr  = operands[2];
2245
 
2246
  start_sequence ();
2247
 
2248
  emit_insn (gen_rtx_SET (VOIDmode, icr,
2249
                          gen_rtx_LT (CC_CCRmode, icc, const0_rtx)));
2250
 
2251
  emit_insn (gen_movsi (dest, const1_rtx));
2252
 
2253
  emit_insn (gen_rtx_COND_EXEC (VOIDmode,
2254
                                gen_rtx_NE (CC_CCRmode, icr, const0_rtx),
2255
                                gen_rtx_SET (VOIDmode, dest,
2256
                                             gen_rtx_NEG (SImode, dest))));
2257
 
2258
  emit_insn (gen_rtx_SET (VOIDmode, icr,
2259
                          gen_rtx_EQ (CC_CCRmode, icc, const0_rtx)));
2260
 
2261
  emit_insn (gen_rtx_COND_EXEC (VOIDmode,
2262
                                gen_rtx_NE (CC_CCRmode, icr, const0_rtx),
2263
                                gen_rtx_SET (VOIDmode, dest, const0_rtx)));
2264
 
2265
  operands[3] = get_insns ();
2266
  end_sequence ();
2267
}")
2268
 
2269
;; Reload CC_UNSmode for unsigned integer comparisons
2270
;; Use define_expand so that cse/gcse/combine can't create movcc_uns insns
2271
 
2272
(define_expand "movcc_uns"
2273
  [(parallel [(set (match_operand:CC_UNS 0 "move_destination_operand" "")
2274
                   (match_operand:CC_UNS 1 "move_source_operand" ""))
2275
              (clobber (match_dup 2))])]
2276
  ""
2277
  "
2278
{
2279
 if (! reload_in_progress && ! reload_completed)
2280
    FAIL;
2281
 operands[2] = gen_rtx_REG (CC_CCRmode, ICR_TEMP);
2282
}")
2283
 
2284
(define_insn "*internal_movcc_uns"
2285
  [(set (match_operand:CC_UNS 0 "move_destination_operand" "=t,d,d,m,d")
2286
        (match_operand:CC_UNS 1 "move_source_operand" "d,d,m,d,t"))
2287
   (clobber (match_scratch:CC_CCR 2 "=X,X,X,X,&v"))]
2288
  "reload_in_progress || reload_completed"
2289
  "@
2290
   cmpi %1, #1, %0
2291
   mov %1, %0
2292
   ld%I1%U1 %M1, %0
2293
   st%I0%U0 %1, %M0
2294
   #"
2295
  [(set_attr "length" "4,4,4,4,20")
2296
   (set_attr "type" "int,int,gload,gstore,multi")])
2297
 
2298
;; To move an ICC value to a GPR for an unsigned comparison, we create a value
2299
;; that when compared to 1, sets the Z, V, and C flags appropriately (we don't
2300
;; care about the N flag, since these comparisons are unsigned).
2301
 
2302
(define_split
2303
  [(set (match_operand:CC_UNS 0 "integer_register_operand" "")
2304
        (match_operand:CC_UNS 1 "icc_operand" ""))
2305
   (clobber (match_operand:CC_CCR 2 "icr_operand" ""))]
2306
  "reload_in_progress || reload_completed"
2307
  [(match_dup 3)]
2308
  "
2309
{
2310
  rtx dest = simplify_gen_subreg (SImode, operands[0], CC_UNSmode, 0);
2311
  rtx icc  = operands[1];
2312
  rtx icr  = operands[2];
2313
 
2314
  start_sequence ();
2315
 
2316
  emit_insn (gen_rtx_SET (VOIDmode, icr,
2317
                          gen_rtx_GTU (CC_CCRmode, icc, const0_rtx)));
2318
 
2319
  emit_insn (gen_movsi (dest, const1_rtx));
2320
 
2321
  emit_insn (gen_rtx_COND_EXEC (VOIDmode,
2322
                                gen_rtx_NE (CC_CCRmode, icr, const0_rtx),
2323
                                gen_addsi3 (dest, dest, dest)));
2324
 
2325
  emit_insn (gen_rtx_SET (VOIDmode, icr,
2326
                          gen_rtx_LTU (CC_CCRmode, icc, const0_rtx)));
2327
 
2328
  emit_insn (gen_rtx_COND_EXEC (VOIDmode,
2329
                                gen_rtx_NE (CC_CCRmode, icr, const0_rtx),
2330
                                gen_rtx_SET (VOIDmode, dest, const0_rtx)));
2331
 
2332
  operands[3] = get_insns ();
2333
  end_sequence ();
2334
}")
2335
 
2336
;; Reload CC_NZmode.  This is mostly the same as the CCmode and CC_UNSmode
2337
;; handling, but it uses different sequences for moving between GPRs and ICCs.
2338
 
2339
(define_expand "movcc_nz"
2340
  [(parallel [(set (match_operand:CC_NZ 0 "move_destination_operand" "")
2341
                   (match_operand:CC_NZ 1 "move_source_operand" ""))
2342
              (clobber (match_dup 2))])]
2343
  ""
2344
  "
2345
{
2346
  if (!reload_in_progress && !reload_completed)
2347
    FAIL;
2348
  operands[2] = gen_rtx_REG (CC_CCRmode, ICR_TEMP);
2349
}")
2350
 
2351
(define_insn "*internal_movcc_nz"
2352
  [(set (match_operand:CC_NZ 0 "move_destination_operand" "=t,d,d,m,d")
2353
        (match_operand:CC_NZ 1 "move_source_operand" "d,d,m,d,t"))
2354
   (clobber (match_scratch:CC_CCR 2 "=X,X,X,X,&v"))]
2355
  "reload_in_progress || reload_completed"
2356
  "@
2357
   cmpi %1, #0, %0
2358
   mov %1, %0
2359
   ld%I1%U1 %M1, %0
2360
   st%I0%U0 %1, %M0
2361
   #"
2362
  [(set_attr "length" "4,4,4,4,20")
2363
   (set_attr "type" "int,int,gload,gstore,multi")])
2364
 
2365
;; Set the destination to a value that, when compared with zero, will
2366
;; restore the value of the Z and N flags.  The values of the other
2367
;; flags don't matter.  The sequence is:
2368
;;
2369
;;     setlos op0,#-1
2370
;;     ckp op1,op2
2371
;;     csub gr0,op0,op0,op2
2372
;;     ckeq op1,op2
2373
;;     cmov gr0,op0,op2
2374
(define_split
2375
  [(set (match_operand:CC_NZ 0 "integer_register_operand" "")
2376
        (match_operand:CC_NZ 1 "icc_operand" ""))
2377
   (clobber (match_operand:CC_CCR 2 "icr_operand" ""))]
2378
  "reload_in_progress || reload_completed"
2379
  [(set (match_dup 3)
2380
        (const_int -1))
2381
   (set (match_dup 2)
2382
        (ge:CC_CCR (match_dup 1)
2383
                   (const_int 0)))
2384
   (cond_exec (ne:CC_CCR (match_dup 2)
2385
                         (const_int 0))
2386
              (set (match_dup 3)
2387
                   (neg:SI (match_dup 3))))
2388
   (set (match_dup 2)
2389
        (eq:CC_CCR (match_dup 1)
2390
                   (const_int 0)))
2391
   (cond_exec (ne:CC_CCR (match_dup 2)
2392
                         (const_int 0))
2393
              (set (match_dup 3) (const_int 0)))]
2394
  "operands[3] = simplify_gen_subreg (SImode, operands[0], CC_NZmode, 0);")
2395
 
2396
;; Reload CC_FPmode for floating point comparisons
2397
;; We use a define_expand here so that cse/gcse/combine can't accidentally
2398
;; create movcc insns.  If this was a named define_insn, we would not be able
2399
;; to make it conditional on reload.
2400
 
2401
(define_expand "movcc_fp"
2402
  [(set (match_operand:CC_FP 0 "movcc_fp_destination_operand" "")
2403
        (match_operand:CC_FP 1 "move_source_operand" ""))]
2404
  "TARGET_HAS_FPRS"
2405
  "
2406
{
2407
 if (! reload_in_progress && ! reload_completed)
2408
    FAIL;
2409
}")
2410
 
2411
(define_insn "*movcc_fp_internal"
2412
  [(set (match_operand:CC_FP 0 "movcc_fp_destination_operand" "=d,d,d,m")
2413
        (match_operand:CC_FP 1 "move_source_operand" "u,d,m,d"))]
2414
  "TARGET_HAS_FPRS && (reload_in_progress || reload_completed)"
2415
  "@
2416
   #
2417
   mov %1, %0
2418
   ld%I1%U1 %M1, %0
2419
   st%I0%U0 %1, %M0"
2420
  [(set_attr "length" "12,4,4,4")
2421
   (set_attr "type" "multi,int,gload,gstore")])
2422
 
2423
 
2424
(define_expand "reload_incc_fp"
2425
  [(match_operand:CC_FP 0 "fcc_operand" "=u")
2426
   (match_operand:CC_FP 1 "gpr_or_memory_operand_with_scratch" "m")
2427
   (match_operand:TI 2 "integer_register_operand" "=&d")]
2428
  "TARGET_HAS_FPRS"
2429
  "
2430
{
2431
  rtx cc_op2 = simplify_gen_subreg (CC_FPmode, operands[2], TImode, 0);
2432
  rtx int_op2 = simplify_gen_subreg (SImode, operands[2], TImode, 0);
2433
  rtx temp1 = simplify_gen_subreg (SImode, operands[2], TImode, 4);
2434
  rtx temp2 = simplify_gen_subreg (SImode, operands[2], TImode, 8);
2435
  int shift = CC_SHIFT_RIGHT (REGNO (operands[0]));
2436
  HOST_WIDE_INT mask;
2437
 
2438
  if (!gpr_or_memory_operand (operands[1], CC_FPmode))
2439
    {
2440
      rtx addr;
2441
      rtx temp3 = simplify_gen_subreg (SImode, operands[2], TImode, 12);
2442
 
2443
      gcc_assert (GET_CODE (operands[1]) == MEM);
2444
 
2445
      addr = XEXP (operands[1], 0);
2446
 
2447
      gcc_assert (GET_CODE (addr) == PLUS);
2448
 
2449
      emit_move_insn (temp3, XEXP (addr, 1));
2450
 
2451
      operands[1] = replace_equiv_address (operands[1],
2452
                                           gen_rtx_PLUS (GET_MODE (addr),
2453
                                                         XEXP (addr, 0),
2454
                                                         temp3));
2455
    }
2456
 
2457
  emit_insn (gen_movcc_fp (cc_op2, operands[1]));
2458
  if (shift)
2459
    emit_insn (gen_ashlsi3 (int_op2, int_op2, GEN_INT (shift)));
2460
 
2461
  mask = ~ ((HOST_WIDE_INT)CC_MASK << shift);
2462
  emit_insn (gen_movsi (temp1, GEN_INT (mask)));
2463
  emit_insn (gen_update_fcc (operands[0], int_op2, temp1, temp2));
2464
  DONE;
2465
}")
2466
 
2467
(define_expand "reload_outcc_fp"
2468
  [(set (match_operand:CC_FP 2 "integer_register_operand" "=&d")
2469
        (match_operand:CC_FP 1 "fcc_operand" "u"))
2470
   (set (match_operand:CC_FP 0 "memory_operand" "=m")
2471
        (match_dup 2))]
2472
  "TARGET_HAS_FPRS"
2473
 "")
2474
 
2475
;; Convert a FCC value to gpr
2476
(define_insn "read_fcc"
2477
  [(set (match_operand:SI 0 "integer_register_operand" "=d")
2478
        (unspec:SI [(match_operand:CC_FP 1 "fcc_operand" "u")]
2479
                   UNSPEC_CC_TO_GPR))]
2480
  "TARGET_HAS_FPRS"
2481
  "movsg ccr, %0"
2482
  [(set_attr "type" "spr")
2483
   (set_attr "length" "4")])
2484
 
2485
(define_split
2486
  [(set (match_operand:CC_FP 0 "integer_register_operand" "")
2487
        (match_operand:CC_FP 1 "fcc_operand" ""))]
2488
  "reload_completed && TARGET_HAS_FPRS"
2489
  [(match_dup 2)]
2490
  "
2491
{
2492
  rtx int_op0 = simplify_gen_subreg (SImode, operands[0], CC_FPmode, 0);
2493
  int shift = CC_SHIFT_RIGHT (REGNO (operands[1]));
2494
 
2495
  start_sequence ();
2496
 
2497
  emit_insn (gen_read_fcc (int_op0, operands[1]));
2498
  if (shift)
2499
    emit_insn (gen_lshrsi3 (int_op0, int_op0, GEN_INT (shift)));
2500
 
2501
  emit_insn (gen_andsi3 (int_op0, int_op0, GEN_INT (CC_MASK)));
2502
 
2503
  operands[2] = get_insns ();
2504
  end_sequence ();
2505
}")
2506
 
2507
;; Move a gpr value to FCC.
2508
;; Operand0 = FCC
2509
;; Operand1 = reloaded value shifted appropriately
2510
;; Operand2 = mask to eliminate current register
2511
;; Operand3 = temporary to load/store ccr
2512
(define_insn "update_fcc"
2513
  [(set (match_operand:CC_FP 0 "fcc_operand" "=u")
2514
        (unspec:CC_FP [(match_operand:SI 1 "integer_register_operand" "d")
2515
                       (match_operand:SI 2 "integer_register_operand" "d")]
2516
                      UNSPEC_GPR_TO_CC))
2517
   (clobber (match_operand:SI 3 "integer_register_operand" "=&d"))]
2518
  "TARGET_HAS_FPRS"
2519
  "movsg ccr, %3\;and %2, %3, %3\;or %1, %3, %3\;movgs %3, ccr"
2520
  [(set_attr "type" "multi")
2521
   (set_attr "length" "16")])
2522
 
2523
;; Reload CC_CCRmode for conditional execution registers
2524
(define_insn "movcc_ccr"
2525
  [(set (match_operand:CC_CCR 0 "move_destination_operand" "=d,d,d,m,v,?w,C,d")
2526
        (match_operand:CC_CCR 1 "move_source_operand" "C,d,m,d,n,n,C,L"))]
2527
  ""
2528
  "@
2529
   #
2530
   mov %1, %0
2531
   ld%I1%U1 %M1, %0
2532
   st%I0%U0 %1, %M0
2533
   #
2534
   #
2535
   orcr %1, %1, %0
2536
   setlos #%1, %0"
2537
  [(set_attr "length" "8,4,4,4,8,12,4,4")
2538
   (set_attr "type" "multi,int,gload,gstore,multi,multi,ccr,int")])
2539
 
2540
(define_expand "reload_incc_ccr"
2541
  [(match_operand:CC_CCR 0 "cr_operand" "=C")
2542
   (match_operand:CC_CCR 1 "memory_operand" "m")
2543
   (match_operand:CC_CCR 2 "integer_register_operand" "=&d")]
2544
  ""
2545
  "
2546
{
2547
  rtx icc = gen_rtx_REG (CCmode, ICC_TEMP);
2548
  rtx int_op2 = simplify_gen_subreg (SImode, operands[2], CC_CCRmode, 0);
2549
  rtx icr = (ICR_P (REGNO (operands[0]))
2550
             ? operands[0] : gen_rtx_REG (CC_CCRmode, ICR_TEMP));
2551
 
2552
  emit_insn (gen_movcc_ccr (operands[2], operands[1]));
2553
  emit_insn (gen_cmpsi_cc (icc, int_op2, const0_rtx));
2554
  emit_insn (gen_movcc_ccr (icr, gen_rtx_NE (CC_CCRmode, icc, const0_rtx)));
2555
 
2556
  if (! ICR_P (REGNO (operands[0])))
2557
    emit_insn (gen_movcc_ccr (operands[0], icr));
2558
 
2559
  DONE;
2560
}")
2561
 
2562
(define_expand "reload_outcc_ccr"
2563
  [(set (match_operand:CC_CCR 2 "integer_register_operand" "=&d")
2564
        (match_operand:CC_CCR 1 "cr_operand" "C"))
2565
   (set (match_operand:CC_CCR 0 "memory_operand" "=m")
2566
        (match_dup 2))]
2567
  ""
2568
  "")
2569
 
2570
(define_split
2571
  [(set (match_operand:CC_CCR 0 "integer_register_operand" "")
2572
        (match_operand:CC_CCR 1 "cr_operand" ""))]
2573
  "reload_completed"
2574
  [(match_dup 2)]
2575
  "
2576
{
2577
  rtx int_op0 = simplify_gen_subreg (SImode, operands[0], CC_CCRmode, 0);
2578
 
2579
  start_sequence ();
2580
  emit_move_insn (operands[0], const1_rtx);
2581
  emit_insn (gen_rtx_COND_EXEC (VOIDmode,
2582
                                gen_rtx_EQ (CC_CCRmode,
2583
                                            operands[1],
2584
                                            const0_rtx),
2585
                                gen_rtx_SET (VOIDmode, int_op0,
2586
                                             const0_rtx)));
2587
 
2588
  operands[2] = get_insns ();
2589
  end_sequence ();
2590
}")
2591
 
2592
(define_split
2593
  [(set (match_operand:CC_CCR 0 "cr_operand" "")
2594
        (match_operand:CC_CCR 1 "const_int_operand" ""))]
2595
  "reload_completed"
2596
  [(match_dup 2)]
2597
  "
2598
{
2599
  rtx icc = gen_rtx_REG (CCmode, ICC_TEMP);
2600
  rtx r0  = gen_rtx_REG (SImode, GPR_FIRST);
2601
  rtx icr = (ICR_P (REGNO (operands[0]))
2602
             ? operands[0] : gen_rtx_REG (CC_CCRmode, ICR_TEMP));
2603
 
2604
  start_sequence ();
2605
 
2606
 emit_insn (gen_cmpsi_cc (icc, r0, const0_rtx));
2607
 
2608
  emit_insn (gen_movcc_ccr (icr,
2609
                            gen_rtx_fmt_ee (((INTVAL (operands[1]) == 0)
2610
                                             ? EQ : NE), CC_CCRmode,
2611
                                            r0, const0_rtx)));
2612
 
2613
  if (! ICR_P (REGNO (operands[0])))
2614
    emit_insn (gen_movcc_ccr (operands[0], icr));
2615
 
2616
  operands[2] = get_insns ();
2617
  end_sequence ();
2618
}")
2619
 
2620
 
2621
;; ::::::::::::::::::::
2622
;; ::
2623
;; :: Conversions
2624
;; ::
2625
;; ::::::::::::::::::::
2626
 
2627
;; Signed conversions from a smaller integer to a larger integer
2628
;;
2629
;; These operations are optional.  If they are not
2630
;; present GCC will synthesize them for itself
2631
;; Even though frv does not provide these instructions, we define them
2632
;; to allow load + sign extend to be collapsed together
2633
(define_insn "extendqihi2"
2634
  [(set (match_operand:HI 0 "integer_register_operand" "=d,d")
2635
        (sign_extend:HI (match_operand:QI 1 "gpr_or_memory_operand" "d,m")))]
2636
  ""
2637
  "@
2638
   #
2639
   ldsb%I1%U1 %M1,%0"
2640
  [(set_attr "length" "8,4")
2641
   (set_attr "type" "multi,gload")])
2642
 
2643
(define_split
2644
  [(set (match_operand:HI 0 "integer_register_operand" "")
2645
        (sign_extend:HI (match_operand:QI 1 "integer_register_operand" "")))]
2646
  "reload_completed"
2647
  [(match_dup 2)
2648
   (match_dup 3)]
2649
  "
2650
{
2651
  rtx op0   = gen_lowpart (SImode, operands[0]);
2652
  rtx op1   = gen_lowpart (SImode, operands[1]);
2653
  rtx shift = GEN_INT (24);
2654
 
2655
  operands[2] = gen_ashlsi3 (op0, op1, shift);
2656
  operands[3] = gen_ashrsi3 (op0, op0, shift);
2657
}")
2658
 
2659
(define_insn "extendqisi2"
2660
  [(set (match_operand:SI 0 "integer_register_operand" "=d,d")
2661
        (sign_extend:SI (match_operand:QI 1 "gpr_or_memory_operand" "d,m")))]
2662
  ""
2663
  "@
2664
   #
2665
   ldsb%I1%U1 %M1,%0"
2666
  [(set_attr "length" "8,4")
2667
   (set_attr "type" "multi,gload")])
2668
 
2669
(define_split
2670
  [(set (match_operand:SI 0 "integer_register_operand" "")
2671
        (sign_extend:SI (match_operand:QI 1 "integer_register_operand" "")))]
2672
  "reload_completed"
2673
  [(match_dup 2)
2674
   (match_dup 3)]
2675
  "
2676
{
2677
  rtx op0   = gen_lowpart (SImode, operands[0]);
2678
  rtx op1   = gen_lowpart (SImode, operands[1]);
2679
  rtx shift = GEN_INT (24);
2680
 
2681
  operands[2] = gen_ashlsi3 (op0, op1, shift);
2682
  operands[3] = gen_ashrsi3 (op0, op0, shift);
2683
}")
2684
 
2685
;;(define_insn "extendqidi2"
2686
;;  [(set (match_operand:DI 0 "register_operand" "=r")
2687
;;      (sign_extend:DI (match_operand:QI 1 "general_operand" "g")))]
2688
;;  ""
2689
;;  "extendqihi2 %0,%1"
2690
;;  [(set_attr "length" "4")])
2691
 
2692
(define_insn "extendhisi2"
2693
  [(set (match_operand:SI 0 "integer_register_operand" "=d,d")
2694
        (sign_extend:SI (match_operand:HI 1 "gpr_or_memory_operand" "d,m")))]
2695
  ""
2696
  "@
2697
   #
2698
   ldsh%I1%U1 %M1,%0"
2699
  [(set_attr "length" "8,4")
2700
   (set_attr "type" "multi,gload")])
2701
 
2702
(define_split
2703
  [(set (match_operand:SI 0 "integer_register_operand" "")
2704
        (sign_extend:SI (match_operand:HI 1 "integer_register_operand" "")))]
2705
  "reload_completed"
2706
  [(match_dup 2)
2707
   (match_dup 3)]
2708
  "
2709
{
2710
  rtx op0   = gen_lowpart (SImode, operands[0]);
2711
  rtx op1   = gen_lowpart (SImode, operands[1]);
2712
  rtx shift = GEN_INT (16);
2713
 
2714
  operands[2] = gen_ashlsi3 (op0, op1, shift);
2715
  operands[3] = gen_ashrsi3 (op0, op0, shift);
2716
}")
2717
 
2718
;;(define_insn "extendhidi2"
2719
;;  [(set (match_operand:DI 0 "register_operand" "=r")
2720
;;      (sign_extend:DI (match_operand:HI 1 "general_operand" "g")))]
2721
;;  ""
2722
;;  "extendhihi2 %0,%1"
2723
;;  [(set_attr "length" "4")])
2724
;;
2725
;;(define_insn "extendsidi2"
2726
;;  [(set (match_operand:DI 0 "register_operand" "=r")
2727
;;      (sign_extend:DI (match_operand:SI 1 "general_operand" "g")))]
2728
;;  ""
2729
;;  "extendsidi2 %0,%1"
2730
;;  [(set_attr "length" "4")])
2731
 
2732
;; Unsigned conversions from a smaller integer to a larger integer
2733
(define_insn "zero_extendqihi2"
2734
  [(set (match_operand:HI 0 "integer_register_operand" "=d,d,d")
2735
        (zero_extend:HI
2736
          (match_operand:QI 1 "gpr_or_memory_operand" "d,L,m")))]
2737
  ""
2738
  "@
2739
   andi %1,#0xff,%0
2740
   setlos %1,%0
2741
   ldub%I1%U1 %M1,%0"
2742
  [(set_attr "length" "4")
2743
   (set_attr "type" "int,int,gload")])
2744
 
2745
(define_insn "zero_extendqisi2"
2746
  [(set (match_operand:SI 0 "integer_register_operand" "=d,d,d")
2747
        (zero_extend:SI
2748
          (match_operand:QI 1 "gpr_or_memory_operand" "d,L,m")))]
2749
  ""
2750
  "@
2751
   andi %1,#0xff,%0
2752
   setlos %1,%0
2753
   ldub%I1%U1 %M1,%0"
2754
  [(set_attr "length" "4")
2755
   (set_attr "type" "int,int,gload")])
2756
 
2757
;;(define_insn "zero_extendqidi2"
2758
;;  [(set (match_operand:DI 0 "register_operand" "=r")
2759
;;      (zero_extend:DI (match_operand:QI 1 "general_operand" "g")))]
2760
;;  ""
2761
;;  "zero_extendqihi2 %0,%1"
2762
;;  [(set_attr "length" "4")])
2763
 
2764
;; Do not set the type for the sethi to "sethi", since the scheduler will think
2765
;; the sethi takes 0 cycles as part of allowing sethi/setlo to be in the same
2766
;; VLIW instruction.
2767
(define_insn "zero_extendhisi2"
2768
  [(set (match_operand:SI 0 "integer_register_operand" "=d,d")
2769
        (zero_extend:SI (match_operand:HI 1 "gpr_or_memory_operand" "0,m")))]
2770
  ""
2771
  "@
2772
    sethi #hi(#0),%0
2773
    lduh%I1%U1 %M1,%0"
2774
  [(set_attr "length" "4")
2775
   (set_attr "type" "int,gload")])
2776
 
2777
;;(define_insn "zero_extendhidi2"
2778
;;  [(set (match_operand:DI 0 "register_operand" "=r")
2779
;;      (zero_extend:DI (match_operand:HI 1 "general_operand" "g")))]
2780
;;  ""
2781
;;  "zero_extendhihi2 %0,%1"
2782
;;  [(set_attr "length" "4")])
2783
;;
2784
;;(define_insn "zero_extendsidi2"
2785
;;  [(set (match_operand:DI 0 "register_operand" "=r")
2786
;;      (zero_extend:DI (match_operand:SI 1 "general_operand" "g")))]
2787
;;  ""
2788
;;  "zero_extendsidi2 %0,%1"
2789
;;  [(set_attr "length" "4")])
2790
;;
2791
;;;; Convert between floating point types of different sizes.
2792
;;
2793
;;(define_insn "extendsfdf2"
2794
;;  [(set (match_operand:DF 0 "register_operand" "=r")
2795
;;      (float_extend:DF (match_operand:SF 1 "register_operand" "r")))]
2796
;;  ""
2797
;;  "extendsfdf2 %0,%1"
2798
;;  [(set_attr "length" "4")])
2799
;;
2800
;;(define_insn "truncdfsf2"
2801
;;  [(set (match_operand:SF 0 "register_operand" "=r")
2802
;;      (float_truncate:SF (match_operand:DF 1 "register_operand" "r")))]
2803
;;  ""
2804
;;  "truncdfsf2 %0,%1"
2805
;;  [(set_attr "length" "4")])
2806
 
2807
;;;; Convert between signed integer types and floating point.
2808
(define_insn "floatsisf2"
2809
  [(set (match_operand:SF 0 "fpr_operand" "=f")
2810
        (float:SF (match_operand:SI 1 "fpr_operand" "f")))]
2811
  "TARGET_HARD_FLOAT"
2812
  "fitos %1,%0"
2813
  [(set_attr "length" "4")
2814
   (set_attr "type" "fsconv")])
2815
 
2816
(define_insn "floatsidf2"
2817
  [(set (match_operand:DF 0 "fpr_operand" "=h")
2818
        (float:DF (match_operand:SI 1 "fpr_operand" "f")))]
2819
  "TARGET_HARD_FLOAT && TARGET_DOUBLE"
2820
  "fitod %1,%0"
2821
  [(set_attr "length" "4")
2822
   (set_attr "type" "fdconv")])
2823
 
2824
;;(define_insn "floatdisf2"
2825
;;  [(set (match_operand:SF 0 "register_operand" "=r")
2826
;;      (float:SF (match_operand:DI 1 "register_operand" "r")))]
2827
;;  ""
2828
;;  "floatdisf2 %0,%1"
2829
;;  [(set_attr "length" "4")])
2830
;;
2831
;;(define_insn "floatdidf2"
2832
;;  [(set (match_operand:DF 0 "register_operand" "=r")
2833
;;      (float:DF (match_operand:DI 1 "register_operand" "r")))]
2834
;;  ""
2835
;;  "floatdidf2 %0,%1"
2836
;;  [(set_attr "length" "4")])
2837
 
2838
(define_insn "fix_truncsfsi2"
2839
  [(set (match_operand:SI 0 "fpr_operand" "=f")
2840
        (fix:SI (match_operand:SF 1 "fpr_operand" "f")))]
2841
  "TARGET_HARD_FLOAT"
2842
  "fstoi %1,%0"
2843
  [(set_attr "length" "4")
2844
   (set_attr "type" "fsconv")])
2845
 
2846
(define_insn "fix_truncdfsi2"
2847
  [(set (match_operand:SI 0 "fpr_operand" "=f")
2848
        (fix:SI (match_operand:DF 1 "fpr_operand" "h")))]
2849
  "TARGET_HARD_FLOAT && TARGET_DOUBLE"
2850
  "fdtoi %1,%0"
2851
  [(set_attr "length" "4")
2852
   (set_attr "type" "fdconv")])
2853
 
2854
;;(define_insn "fix_truncsfdi2"
2855
;;  [(set (match_operand:DI 0 "register_operand" "=r")
2856
;;      (fix:DI (match_operand:SF 1 "register_operand" "r")))]
2857
;;  ""
2858
;;  "fix_truncsfdi2 %0,%1"
2859
;;  [(set_attr "length" "4")])
2860
;;
2861
;;(define_insn "fix_truncdfdi2"
2862
;;  [(set (match_operand:DI 0 "register_operand" "=r")
2863
;;      (fix:DI (match_operand:DF 1 "register_operand" "r")))]
2864
;;  ""
2865
;;  "fix_truncdfdi2 %0,%1"
2866
;;  [(set_attr "length" "4")])
2867
;;
2868
;;;; Convert between unsigned integer types and floating point.
2869
;;
2870
;;(define_insn "floatunssisf2"
2871
;;  [(set (match_operand:SF 0 "register_operand" "=r")
2872
;;      (unsigned_float:SF (match_operand:SI 1 "register_operand" "r")))]
2873
;;  ""
2874
;;  "floatunssisf2 %0,%1"
2875
;;  [(set_attr "length" "4")])
2876
;;
2877
;;(define_insn "floatunssidf2"
2878
;;  [(set (match_operand:DF 0 "register_operand" "=r")
2879
;;      (unsigned_float:DF (match_operand:SI 1 "register_operand" "r")))]
2880
;;  ""
2881
;;  "floatunssidf2 %0,%1"
2882
;;  [(set_attr "length" "4")])
2883
;;
2884
;;(define_insn "floatunsdisf2"
2885
;;  [(set (match_operand:SF 0 "register_operand" "=r")
2886
;;      (unsigned_float:SF (match_operand:DI 1 "register_operand" "r")))]
2887
;;  ""
2888
;;  "floatunsdisf2 %0,%1"
2889
;;  [(set_attr "length" "4")])
2890
;;
2891
;;(define_insn "floatunsdidf2"
2892
;;  [(set (match_operand:DF 0 "register_operand" "=r")
2893
;;      (unsigned_float:DF (match_operand:DI 1 "register_operand" "r")))]
2894
;;  ""
2895
;;  "floatunsdidf2 %0,%1"
2896
;;  [(set_attr "length" "4")])
2897
;;
2898
;;(define_insn "fixuns_truncsfsi2"
2899
;;  [(set (match_operand:SI 0 "register_operand" "=r")
2900
;;      (unsigned_fix:SI (match_operand:SF 1 "register_operand" "r")))]
2901
;;  ""
2902
;;  "fixuns_truncsfsi2 %0,%1"
2903
;;  [(set_attr "length" "4")])
2904
;;
2905
;;(define_insn "fixuns_truncdfsi2"
2906
;;  [(set (match_operand:SI 0 "register_operand" "=r")
2907
;;      (unsigned_fix:SI (match_operand:DF 1 "register_operand" "r")))]
2908
;;  ""
2909
;;  "fixuns_truncdfsi2 %0,%1"
2910
;;  [(set_attr "length" "4")])
2911
;;
2912
;;(define_insn "fixuns_truncsfdi2"
2913
;;  [(set (match_operand:DI 0 "register_operand" "=r")
2914
;;      (unsigned_fix:DI (match_operand:SF 1 "register_operand" "r")))]
2915
;;  ""
2916
;;  "fixuns_truncsfdi2 %0,%1"
2917
;;  [(set_attr "length" "4")])
2918
;;
2919
;;(define_insn "fixuns_truncdfdi2"
2920
;;  [(set (match_operand:DI 0 "register_operand" "=r")
2921
;;      (unsigned_fix:DI (match_operand:DF 1 "register_operand" "r")))]
2922
;;  ""
2923
;;  "fixuns_truncdfdi2 %0,%1"
2924
;;  [(set_attr "length" "4")])
2925
 
2926
 
2927
;; ::::::::::::::::::::
2928
;; ::
2929
;; :: 32-bit Integer arithmetic
2930
;; ::
2931
;; ::::::::::::::::::::
2932
 
2933
;; Addition
2934
(define_insn "addsi3"
2935
  [(set (match_operand:SI 0 "integer_register_operand" "=d")
2936
        (plus:SI (match_operand:SI 1 "integer_register_operand" "%d")
2937
                 (match_operand:SI 2 "gpr_or_int12_operand" "dNOPQ")))]
2938
  ""
2939
  "add%I2 %1,%2,%0"
2940
  [(set_attr "length" "4")
2941
   (set_attr "type" "int")])
2942
 
2943
;; Subtraction.  No need to worry about constants, since the compiler
2944
;; canonicalizes them into addsi3's.  We prevent SUBREG's here to work around a
2945
;; combine bug, that combines the 32x32->upper 32 bit multiply that uses a
2946
;; SUBREG with a minus that shows up in modulus by constants.
2947
(define_insn "subsi3"
2948
  [(set (match_operand:SI 0 "integer_register_operand" "=d")
2949
        (minus:SI (match_operand:SI 1 "gpr_no_subreg_operand" "d")
2950
                  (match_operand:SI 2 "gpr_no_subreg_operand" "d")))]
2951
  ""
2952
  "sub %1,%2,%0"
2953
  [(set_attr "length" "4")
2954
   (set_attr "type" "int")])
2955
 
2956
;; Signed multiplication producing 64-bit results from 32-bit inputs
2957
;; Note, frv doesn't have a 32x32->32 bit multiply, but the compiler
2958
;; will do the 32x32->64 bit multiply and use the bottom word.
2959
(define_expand "mulsidi3"
2960
  [(set (match_operand:DI 0 "integer_register_operand" "")
2961
        (mult:DI (sign_extend:DI (match_operand:SI 1 "integer_register_operand" ""))
2962
                 (sign_extend:DI (match_operand:SI 2 "gpr_or_int12_operand" ""))))]
2963
  ""
2964
  "
2965
{
2966
  if (GET_CODE (operands[2]) == CONST_INT)
2967
    {
2968
      emit_insn (gen_mulsidi3_const (operands[0], operands[1], operands[2]));
2969
      DONE;
2970
    }
2971
}")
2972
 
2973
(define_insn "*mulsidi3_reg"
2974
  [(set (match_operand:DI 0 "even_gpr_operand" "=e")
2975
        (mult:DI (sign_extend:DI (match_operand:SI 1 "integer_register_operand" "%d"))
2976
                 (sign_extend:DI (match_operand:SI 2 "integer_register_operand" "d"))))]
2977
  ""
2978
  "smul %1,%2,%0"
2979
  [(set_attr "length" "4")
2980
   (set_attr "type" "mul")])
2981
 
2982
(define_insn "mulsidi3_const"
2983
  [(set (match_operand:DI 0 "even_gpr_operand" "=e")
2984
        (mult:DI (sign_extend:DI (match_operand:SI 1 "integer_register_operand" "d"))
2985
                 (match_operand:SI 2 "int12_operand" "NOP")))]
2986
  ""
2987
  "smuli %1,%2,%0"
2988
  [(set_attr "length" "4")
2989
   (set_attr "type" "mul")])
2990
 
2991
;; Unsigned multiplication producing 64-bit results from 32-bit inputs
2992
(define_expand "umulsidi3"
2993
  [(set (match_operand:DI 0 "even_gpr_operand" "")
2994
        (mult:DI (zero_extend:DI (match_operand:SI 1 "integer_register_operand" ""))
2995
                 (zero_extend:DI (match_operand:SI 2 "gpr_or_int12_operand" ""))))]
2996
  ""
2997
  "
2998
{
2999
  if (GET_CODE (operands[2]) == CONST_INT)
3000
    {
3001
      emit_insn (gen_umulsidi3_const (operands[0], operands[1], operands[2]));
3002
      DONE;
3003
    }
3004
}")
3005
 
3006
(define_insn "*mulsidi3_reg"
3007
  [(set (match_operand:DI 0 "even_gpr_operand" "=e")
3008
        (mult:DI (zero_extend:DI (match_operand:SI 1 "integer_register_operand" "%d"))
3009
                 (zero_extend:DI (match_operand:SI 2 "integer_register_operand" "d"))))]
3010
  ""
3011
  "umul %1,%2,%0"
3012
  [(set_attr "length" "4")
3013
   (set_attr "type" "mul")])
3014
 
3015
(define_insn "umulsidi3_const"
3016
  [(set (match_operand:DI 0 "even_gpr_operand" "=e")
3017
        (mult:DI (zero_extend:DI (match_operand:SI 1 "integer_register_operand" "d"))
3018
                 (match_operand:SI 2 "int12_operand" "NOP")))]
3019
  ""
3020
  "umuli %1,%2,%0"
3021
  [(set_attr "length" "4")
3022
   (set_attr "type" "mul")])
3023
 
3024
;; Signed Division
3025
(define_insn "divsi3"
3026
  [(set (match_operand:SI 0 "register_operand" "=d,d")
3027
        (div:SI (match_operand:SI 1 "register_operand" "d,d")
3028
                (match_operand:SI 2 "gpr_or_int12_operand" "d,NOP")))]
3029
  ""
3030
  "sdiv%I2 %1,%2,%0"
3031
  [(set_attr "length" "4")
3032
   (set_attr "type" "div")])
3033
 
3034
;; Unsigned Division
3035
(define_insn "udivsi3"
3036
  [(set (match_operand:SI 0 "register_operand" "=d,d")
3037
        (udiv:SI (match_operand:SI 1 "register_operand" "d,d")
3038
                 (match_operand:SI 2 "gpr_or_int12_operand" "d,NOP")))]
3039
  ""
3040
  "udiv%I2 %1,%2,%0"
3041
  [(set_attr "length" "4")
3042
   (set_attr "type" "div")])
3043
 
3044
;; Negation
3045
(define_insn "negsi2"
3046
  [(set (match_operand:SI 0 "integer_register_operand" "=d")
3047
        (neg:SI (match_operand:SI 1 "integer_register_operand" "d")))]
3048
  ""
3049
  "sub %.,%1,%0"
3050
  [(set_attr "length" "4")
3051
   (set_attr "type" "int")])
3052
 
3053
;; Find first one bit
3054
;; (define_insn "ffssi2"
3055
;;   [(set (match_operand:SI 0 "register_operand" "=r")
3056
;;      (ffs:SI (match_operand:SI 1 "register_operand" "r")))]
3057
;;   ""
3058
;;   "ffssi2 %0,%1"
3059
;;   [(set_attr "length" "4")])
3060
 
3061
 
3062
;; ::::::::::::::::::::
3063
;; ::
3064
;; :: 64-bit Integer arithmetic
3065
;; ::
3066
;; ::::::::::::::::::::
3067
 
3068
;; Addition
3069
(define_insn_and_split "adddi3"
3070
  [(set (match_operand:DI 0 "integer_register_operand" "=&e,e")
3071
        (plus:DI (match_operand:DI 1 "integer_register_operand" "%e,0")
3072
                 (match_operand:DI 2 "gpr_or_int10_operand" "eJ,eJ")))
3073
   (clobber (match_scratch:CC 3 "=t,t"))]
3074
  ""
3075
  "#"
3076
  "reload_completed"
3077
  [(match_dup 4)
3078
   (match_dup 5)]
3079
  "
3080
{
3081
  rtx parts[3][2];
3082
  int op, part;
3083
 
3084
  for (op = 0; op < 3; op++)
3085
    for (part = 0; part < 2; part++)
3086
      parts[op][part] = simplify_gen_subreg (SImode, operands[op],
3087
                                             DImode, part * UNITS_PER_WORD);
3088
 
3089
  operands[4] = gen_adddi3_lower (parts[0][1], parts[1][1], parts[2][1],
3090
                                  operands[3]);
3091
  operands[5] = gen_adddi3_upper (parts[0][0], parts[1][0], parts[2][0],
3092
                                  copy_rtx (operands[3]));
3093
}"
3094
  [(set_attr "length" "8")
3095
   (set_attr "type" "multi")])
3096
 
3097
;; Subtraction  No need to worry about constants, since the compiler
3098
;; canonicalizes them into adddi3's.
3099
(define_insn_and_split "subdi3"
3100
  [(set (match_operand:DI 0 "integer_register_operand" "=&e,e,e")
3101
        (minus:DI (match_operand:DI 1 "integer_register_operand" "e,0,e")
3102
                  (match_operand:DI 2 "integer_register_operand" "e,e,0")))
3103
   (clobber (match_scratch:CC 3 "=t,t,t"))]
3104
  ""
3105
  "#"
3106
  "reload_completed"
3107
  [(match_dup 4)
3108
   (match_dup 5)]
3109
  "
3110
{
3111
  rtx op0_high = gen_highpart (SImode, operands[0]);
3112
  rtx op1_high = gen_highpart (SImode, operands[1]);
3113
  rtx op2_high = gen_highpart (SImode, operands[2]);
3114
  rtx op0_low  = gen_lowpart (SImode, operands[0]);
3115
  rtx op1_low  = gen_lowpart (SImode, operands[1]);
3116
  rtx op2_low  = gen_lowpart (SImode, operands[2]);
3117
  rtx op3 = operands[3];
3118
 
3119
  operands[4] = gen_subdi3_lower (op0_low, op1_low, op2_low, op3);
3120
  operands[5] = gen_subdi3_upper (op0_high, op1_high, op2_high, op3);
3121
}"
3122
  [(set_attr "length" "8")
3123
   (set_attr "type" "multi")])
3124
 
3125
;; Patterns for addsi3/subdi3 after splitting
3126
(define_insn "adddi3_lower"
3127
  [(set (match_operand:SI 0 "integer_register_operand" "=d")
3128
        (plus:SI (match_operand:SI 1 "integer_register_operand" "d")
3129
                 (match_operand:SI 2 "gpr_or_int10_operand" "dJ")))
3130
   (set (match_operand:CC 3 "icc_operand" "=t")
3131
        (compare:CC (plus:SI (match_dup 1)
3132
                             (match_dup 2))
3133
                    (const_int 0)))]
3134
  ""
3135
  "add%I2cc %1,%2,%0,%3"
3136
  [(set_attr "length" "4")
3137
   (set_attr "type" "int")])
3138
 
3139
(define_insn "adddi3_upper"
3140
  [(set (match_operand:SI 0 "integer_register_operand" "=d")
3141
        (plus:SI (match_operand:SI 1 "integer_register_operand" "d")
3142
                 (plus:SI (match_operand:SI 2 "gpr_or_int10_operand" "dJ")
3143
                          (match_operand:CC 3 "icc_operand" "t"))))]
3144
  ""
3145
  "addx%I2 %1,%2,%0,%3"
3146
  [(set_attr "length" "4")
3147
   (set_attr "type" "int")])
3148
 
3149
(define_insn "subdi3_lower"
3150
  [(set (match_operand:SI 0 "integer_register_operand" "=d")
3151
        (minus:SI (match_operand:SI 1 "integer_register_operand" "d")
3152
                  (match_operand:SI 2 "integer_register_operand" "d")))
3153
   (set (match_operand:CC 3 "icc_operand" "=t")
3154
        (compare:CC (plus:SI (match_dup 1)
3155
                             (match_dup 2))
3156
                    (const_int 0)))]
3157
  ""
3158
  "subcc %1,%2,%0,%3"
3159
  [(set_attr "length" "4")
3160
   (set_attr "type" "int")])
3161
 
3162
(define_insn "subdi3_upper"
3163
  [(set (match_operand:SI 0 "integer_register_operand" "=d")
3164
        (minus:SI (match_operand:SI 1 "integer_register_operand" "d")
3165
                  (minus:SI (match_operand:SI 2 "integer_register_operand" "d")
3166
                            (match_operand:CC 3 "icc_operand" "t"))))]
3167
  ""
3168
  "subx %1,%2,%0,%3"
3169
  [(set_attr "length" "4")
3170
   (set_attr "type" "int")])
3171
 
3172
(define_insn_and_split "negdi2"
3173
  [(set (match_operand:DI 0 "integer_register_operand" "=&e,e")
3174
        (neg:DI (match_operand:DI 1 "integer_register_operand" "e,0")))
3175
   (clobber (match_scratch:CC 2 "=t,t"))]
3176
  ""
3177
  "#"
3178
  "reload_completed"
3179
  [(match_dup 3)
3180
   (match_dup 4)]
3181
  "
3182
{
3183
  rtx op0_high = gen_highpart (SImode, operands[0]);
3184
  rtx op1_high = gen_rtx_REG (SImode, GPR_FIRST);
3185
  rtx op2_high = gen_highpart (SImode, operands[1]);
3186
  rtx op0_low  = gen_lowpart (SImode, operands[0]);
3187
  rtx op1_low  = op1_high;
3188
  rtx op2_low  = gen_lowpart (SImode, operands[1]);
3189
  rtx op3 = operands[2];
3190
 
3191
  operands[3] = gen_subdi3_lower (op0_low, op1_low, op2_low, op3);
3192
  operands[4] = gen_subdi3_upper (op0_high, op1_high, op2_high, op3);
3193
}"
3194
  [(set_attr "length" "8")
3195
   (set_attr "type" "multi")])
3196
 
3197
;; Multiplication (same size)
3198
;; (define_insn "muldi3"
3199
;;   [(set (match_operand:DI 0 "register_operand" "=r")
3200
;;      (mult:DI (match_operand:DI 1 "register_operand" "%r")
3201
;;               (match_operand:DI 2 "nonmemory_operand" "ri")))]
3202
;;   ""
3203
;;   "muldi3 %0,%1,%2"
3204
;;   [(set_attr "length" "4")])
3205
 
3206
;; Signed Division
3207
;; (define_insn "divdi3"
3208
;;   [(set (match_operand:DI 0 "register_operand" "=r")
3209
;;      (div:DI (match_operand:DI 1 "register_operand" "r")
3210
;;              (match_operand:DI 2 "nonmemory_operand" "ri")))]
3211
;;   ""
3212
;;   "divdi3 %0,%1,%2"
3213
;;   [(set_attr "length" "4")])
3214
 
3215
;; Undsgned Division
3216
;; (define_insn "udivdi3"
3217
;;   [(set (match_operand:DI 0 "register_operand" "=r")
3218
;;      (udiv:DI (match_operand:DI 1 "register_operand" "r")
3219
;;               (match_operand:DI 2 "nonmemory_operand" "ri")))]
3220
;;   ""
3221
;;   "udivdi3 %0,%1,%2"
3222
;;   [(set_attr "length" "4")])
3223
 
3224
;; Negation
3225
;; (define_insn "negdi2"
3226
;;   [(set (match_operand:DI 0 "register_operand" "=r")
3227
;;      (neg:DI (match_operand:DI 1 "register_operand" "r")))]
3228
;;   ""
3229
;;   "negdi2 %0,%1"
3230
;;   [(set_attr "length" "4")])
3231
 
3232
;; Find first one bit
3233
;; (define_insn "ffsdi2"
3234
;;   [(set (match_operand:DI 0 "register_operand" "=r")
3235
;;      (ffs:DI (match_operand:DI 1 "register_operand" "r")))]
3236
;;   ""
3237
;;   "ffsdi2 %0,%1"
3238
;;   [(set_attr "length" "4")])
3239
 
3240
 
3241
;; ::::::::::::::::::::
3242
;; ::
3243
;; :: 32-bit floating point arithmetic
3244
;; ::
3245
;; ::::::::::::::::::::
3246
 
3247
;; Addition
3248
(define_insn "addsf3"
3249
  [(set (match_operand:SF 0 "fpr_operand" "=f")
3250
        (plus:SF (match_operand:SF 1 "fpr_operand" "%f")
3251
                 (match_operand:SF 2 "fpr_operand" "f")))]
3252
  "TARGET_HARD_FLOAT"
3253
  "fadds %1,%2,%0"
3254
  [(set_attr "length" "4")
3255
   (set_attr "type" "fsadd")])
3256
 
3257
;; Subtraction
3258
(define_insn "subsf3"
3259
  [(set (match_operand:SF 0 "fpr_operand" "=f")
3260
        (minus:SF (match_operand:SF 1 "fpr_operand" "f")
3261
                  (match_operand:SF 2 "fpr_operand" "f")))]
3262
  "TARGET_HARD_FLOAT"
3263
  "fsubs %1,%2,%0"
3264
  [(set_attr "length" "4")
3265
   (set_attr "type" "fsadd")])
3266
 
3267
;; Multiplication
3268
(define_insn "mulsf3"
3269
  [(set (match_operand:SF 0 "fpr_operand" "=f")
3270
        (mult:SF (match_operand:SF 1 "fpr_operand" "%f")
3271
                 (match_operand:SF 2 "fpr_operand" "f")))]
3272
  "TARGET_HARD_FLOAT"
3273
  "fmuls %1,%2,%0"
3274
  [(set_attr "length" "4")
3275
   (set_attr "type" "fsmul")])
3276
 
3277
;; Multiplication with addition/subtraction
3278
(define_insn "fmasf4"
3279
  [(set (match_operand:SF 0 "fpr_operand" "=f")
3280
        (fma:SF (match_operand:SF 1 "fpr_operand" "f")
3281
                (match_operand:SF 2 "fpr_operand" "f")
3282
                (match_operand:SF 3 "fpr_operand" "0")))]
3283
  "TARGET_HARD_FLOAT && TARGET_MULADD"
3284
  "fmadds %1,%2,%0"
3285
  [(set_attr "length" "4")
3286
   (set_attr "type" "fsmadd")])
3287
 
3288
(define_insn "fmssf4"
3289
  [(set (match_operand:SF 0 "fpr_operand" "=f")
3290
        (fma:SF (match_operand:SF 1 "fpr_operand" "f")
3291
                (match_operand:SF 2 "fpr_operand" "f")
3292
                (neg:SF (match_operand:SF 3 "fpr_operand" "0"))))]
3293
  "TARGET_HARD_FLOAT && TARGET_MULADD"
3294
  "fmsubs %1,%2,%0"
3295
  [(set_attr "length" "4")
3296
   (set_attr "type" "fsmadd")])
3297
 
3298
;; Division
3299
(define_insn "divsf3"
3300
  [(set (match_operand:SF 0 "fpr_operand" "=f")
3301
        (div:SF (match_operand:SF 1 "fpr_operand" "f")
3302
                (match_operand:SF 2 "fpr_operand" "f")))]
3303
  "TARGET_HARD_FLOAT"
3304
  "fdivs %1,%2,%0"
3305
  [(set_attr "length" "4")
3306
   (set_attr "type" "fsdiv")])
3307
 
3308
;; Negation
3309
(define_insn "negsf2"
3310
  [(set (match_operand:SF 0 "fpr_operand" "=f")
3311
        (neg:SF (match_operand:SF 1 "fpr_operand" "f")))]
3312
  "TARGET_HARD_FLOAT"
3313
  "fnegs %1,%0"
3314
  [(set_attr "length" "4")
3315
   (set_attr "type" "fsconv")])
3316
 
3317
;; Absolute value
3318
(define_insn "abssf2"
3319
  [(set (match_operand:SF 0 "fpr_operand" "=f")
3320
        (abs:SF (match_operand:SF 1 "fpr_operand" "f")))]
3321
  "TARGET_HARD_FLOAT"
3322
  "fabss %1,%0"
3323
  [(set_attr "length" "4")
3324
   (set_attr "type" "fsconv")])
3325
 
3326
;; Square root
3327
(define_insn "sqrtsf2"
3328
  [(set (match_operand:SF 0 "fpr_operand" "=f")
3329
        (sqrt:SF (match_operand:SF 1 "fpr_operand" "f")))]
3330
  "TARGET_HARD_FLOAT"
3331
  "fsqrts %1,%0"
3332
  [(set_attr "length" "4")
3333
   (set_attr "type" "sqrt_single")])
3334
 
3335
 
3336
;; ::::::::::::::::::::
3337
;; ::
3338
;; :: 64-bit floating point arithmetic
3339
;; ::
3340
;; ::::::::::::::::::::
3341
 
3342
;; Addition
3343
(define_insn "adddf3"
3344
  [(set (match_operand:DF 0 "even_fpr_operand" "=h")
3345
        (plus:DF (match_operand:DF 1 "fpr_operand" "%h")
3346
                 (match_operand:DF 2 "fpr_operand" "h")))]
3347
  "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3348
  "faddd %1,%2,%0"
3349
  [(set_attr "length" "4")
3350
   (set_attr "type" "fdadd")])
3351
 
3352
;; Subtraction
3353
(define_insn "subdf3"
3354
  [(set (match_operand:DF 0 "even_fpr_operand" "=h")
3355
        (minus:DF (match_operand:DF 1 "fpr_operand" "h")
3356
                  (match_operand:DF 2 "fpr_operand" "h")))]
3357
  "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3358
  "fsubd %1,%2,%0"
3359
  [(set_attr "length" "4")
3360
   (set_attr "type" "fdadd")])
3361
 
3362
;; Multiplication
3363
(define_insn "muldf3"
3364
  [(set (match_operand:DF 0 "even_fpr_operand" "=h")
3365
        (mult:DF (match_operand:DF 1 "fpr_operand" "%h")
3366
                 (match_operand:DF 2 "fpr_operand" "h")))]
3367
  "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3368
  "fmuld %1,%2,%0"
3369
  [(set_attr "length" "4")
3370
   (set_attr "type" "fdmul")])
3371
 
3372
;; Multiplication with addition/subtraction
3373
(define_insn "*muladddf4"
3374
  [(set (match_operand:DF 0 "fpr_operand" "=f")
3375
        (plus:DF (mult:DF (match_operand:DF 1 "fpr_operand" "%f")
3376
                          (match_operand:DF 2 "fpr_operand" "f"))
3377
                 (match_operand:DF 3 "fpr_operand" "0")))]
3378
  "TARGET_HARD_FLOAT && TARGET_DOUBLE && TARGET_MULADD"
3379
  "fmaddd %1,%2,%0"
3380
  [(set_attr "length" "4")
3381
   (set_attr "type" "fdmadd")])
3382
 
3383
(define_insn "*mulsubdf4"
3384
  [(set (match_operand:DF 0 "fpr_operand" "=f")
3385
        (minus:DF (mult:DF (match_operand:DF 1 "fpr_operand" "%f")
3386
                           (match_operand:DF 2 "fpr_operand" "f"))
3387
                  (match_operand:DF 3 "fpr_operand" "0")))]
3388
  "TARGET_HARD_FLOAT && TARGET_DOUBLE && TARGET_MULADD"
3389
  "fmsubd %1,%2,%0"
3390
  [(set_attr "length" "4")
3391
   (set_attr "type" "fdmadd")])
3392
 
3393
;; Division
3394
(define_insn "divdf3"
3395
  [(set (match_operand:DF 0 "even_fpr_operand" "=h")
3396
        (div:DF (match_operand:DF 1 "fpr_operand" "h")
3397
                (match_operand:DF 2 "fpr_operand" "h")))]
3398
  "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3399
  "fdivd %1,%2,%0"
3400
  [(set_attr "length" "4")
3401
   (set_attr "type" "fddiv")])
3402
 
3403
;; Negation
3404
(define_insn "negdf2"
3405
  [(set (match_operand:DF 0 "even_fpr_operand" "=h")
3406
        (neg:DF (match_operand:DF 1 "fpr_operand" "h")))]
3407
  "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3408
  "fnegd %1,%0"
3409
  [(set_attr "length" "4")
3410
   (set_attr "type" "fdconv")])
3411
 
3412
;; Absolute value
3413
(define_insn "absdf2"
3414
  [(set (match_operand:DF 0 "even_fpr_operand" "=h")
3415
        (abs:DF (match_operand:DF 1 "fpr_operand" "h")))]
3416
  "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3417
  "fabsd %1,%0"
3418
  [(set_attr "length" "4")
3419
   (set_attr "type" "fdconv")])
3420
 
3421
;; Square root
3422
(define_insn "sqrtdf2"
3423
  [(set (match_operand:DF 0 "even_fpr_operand" "=h")
3424
        (sqrt:DF (match_operand:DF 1 "fpr_operand" "h")))]
3425
  "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3426
  "fsqrtd %1,%0"
3427
  [(set_attr "length" "4")
3428
   (set_attr "type" "sqrt_double")])
3429
 
3430
 
3431
;; ::::::::::::::::::::
3432
;; ::
3433
;; :: 32-bit Integer Shifts and Rotates
3434
;; ::
3435
;; ::::::::::::::::::::
3436
 
3437
;; Arithmetic Shift Left
3438
(define_insn "ashlsi3"
3439
  [(set (match_operand:SI 0 "integer_register_operand" "=d,d")
3440
        (ashift:SI (match_operand:SI 1 "integer_register_operand" "d,d")
3441
                   (match_operand:SI 2 "gpr_or_int12_operand" "d,NOP")))]
3442
  ""
3443
  "sll%I2 %1,%2,%0"
3444
  [(set_attr "length" "4")
3445
   (set_attr "type" "int")])
3446
 
3447
;; Arithmetic Shift Right
3448
(define_insn "ashrsi3"
3449
  [(set (match_operand:SI 0 "integer_register_operand" "=d,d")
3450
        (ashiftrt:SI (match_operand:SI 1 "integer_register_operand" "d,d")
3451
                     (match_operand:SI 2 "gpr_or_int12_operand" "d,NOP")))]
3452
  ""
3453
  "sra%I2 %1, %2, %0"
3454
  [(set_attr "length" "4")
3455
   (set_attr "type" "int")])
3456
 
3457
;; Logical Shift Right
3458
(define_insn "lshrsi3"
3459
  [(set (match_operand:SI 0 "integer_register_operand" "=d,d")
3460
        (lshiftrt:SI (match_operand:SI 1 "integer_register_operand" "d,d")
3461
                     (match_operand:SI 2 "gpr_or_int12_operand" "d,NOP")))]
3462
  ""
3463
  "srl%I2 %1, %2, %0"
3464
  [(set_attr "length" "4")
3465
   (set_attr "type" "int")])
3466
 
3467
;; Rotate Left
3468
;; (define_insn "rotlsi3"
3469
;;   [(set (match_operand:SI 0 "register_operand" "=r")
3470
;;      (rotate:SI (match_operand:SI 1 "register_operand" "r")
3471
;;                 (match_operand:SI 2 "nonmemory_operand" "ri")))]
3472
;;   ""
3473
;;   "rotlsi3 %0,%1,%2"
3474
;;   [(set_attr "length" "4")])
3475
 
3476
;; Rotate Right
3477
;; (define_insn "rotrsi3"
3478
;;   [(set (match_operand:SI 0 "register_operand" "=r")
3479
;;      (rotatert:SI (match_operand:SI 1 "register_operand" "r")
3480
;;                   (match_operand:SI 2 "nonmemory_operand" "ri")))]
3481
;;   ""
3482
;;   "rotrsi3 %0,%1,%2"
3483
;;   [(set_attr "length" "4")])
3484
 
3485
 
3486
;; ::::::::::::::::::::
3487
;; ::
3488
;; :: 64-bit Integer Shifts and Rotates
3489
;; ::
3490
;; ::::::::::::::::::::
3491
 
3492
;; Arithmetic Shift Left
3493
;; (define_insn "ashldi3"
3494
;;   [(set (match_operand:DI 0 "register_operand" "=r")
3495
;;      (ashift:DI (match_operand:DI 1 "register_operand" "r")
3496
;;                 (match_operand:SI 2 "nonmemory_operand" "ri")))]
3497
;;   ""
3498
;;   "ashldi3 %0,%1,%2"
3499
;;   [(set_attr "length" "4")])
3500
 
3501
;; Arithmetic Shift Right
3502
;; (define_insn "ashrdi3"
3503
;;   [(set (match_operand:DI 0 "register_operand" "=r")
3504
;;      (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
3505
;;                   (match_operand:SI 2 "nonmemory_operand" "ri")))]
3506
;;   ""
3507
;;   "ashrdi3 %0,%1,%2"
3508
;;   [(set_attr "length" "4")])
3509
 
3510
;; Logical Shift Right
3511
;; (define_insn "lshrdi3"
3512
;;   [(set (match_operand:DI 0 "register_operand" "=r")
3513
;;      (lshiftrt:DI (match_operand:DI 1 "register_operand" "r")
3514
;;                   (match_operand:SI 2 "nonmemory_operand" "ri")))]
3515
;;   ""
3516
;;   "lshrdi3 %0,%1,%2"
3517
;;   [(set_attr "length" "4")])
3518
 
3519
;; Rotate Left
3520
;; (define_insn "rotldi3"
3521
;;   [(set (match_operand:DI 0 "register_operand" "=r")
3522
;;      (rotate:DI (match_operand:DI 1 "register_operand" "r")
3523
;;                 (match_operand:SI 2 "nonmemory_operand" "ri")))]
3524
;;   ""
3525
;;   "rotldi3 %0,%1,%2"
3526
;;   [(set_attr "length" "4")])
3527
 
3528
;; Rotate Right
3529
;; (define_insn "rotrdi3"
3530
;;   [(set (match_operand:DI 0 "register_operand" "=r")
3531
;;      (rotatert:DI (match_operand:DI 1 "register_operand" "r")
3532
;;                   (match_operand:SI 2 "nonmemory_operand" "ri")))]
3533
;;   ""
3534
;;   "rotrdi3 %0,%1,%2"
3535
;;   [(set_attr "length" "4")])
3536
 
3537
 
3538
;; ::::::::::::::::::::
3539
;; ::
3540
;; :: 32-Bit Integer Logical operations
3541
;; ::
3542
;; ::::::::::::::::::::
3543
 
3544
;; Logical AND, 32-bit integers
3545
(define_insn "andsi3_media"
3546
  [(set (match_operand:SI 0 "gpr_or_fpr_operand" "=d,f")
3547
        (and:SI (match_operand:SI 1 "gpr_or_fpr_operand" "%d,f")
3548
                (match_operand:SI 2 "gpr_fpr_or_int12_operand" "dNOP,f")))]
3549
  "TARGET_MEDIA"
3550
  "@
3551
   and%I2 %1, %2, %0
3552
   mand %1, %2, %0"
3553
  [(set_attr "length" "4")
3554
   (set_attr "type" "int,mlogic")])
3555
 
3556
(define_insn "andsi3_nomedia"
3557
  [(set (match_operand:SI 0 "integer_register_operand" "=d")
3558
        (and:SI (match_operand:SI 1 "integer_register_operand" "%d")
3559
                (match_operand:SI 2 "gpr_or_int12_operand" "dNOP")))]
3560
  "!TARGET_MEDIA"
3561
  "and%I2 %1, %2, %0"
3562
  [(set_attr "length" "4")
3563
   (set_attr "type" "int")])
3564
 
3565
(define_expand "andsi3"
3566
  [(set (match_operand:SI 0 "gpr_or_fpr_operand" "")
3567
        (and:SI (match_operand:SI 1 "gpr_or_fpr_operand" "")
3568
                (match_operand:SI 2 "gpr_fpr_or_int12_operand" "")))]
3569
  ""
3570
  "")
3571
 
3572
;; Inclusive OR, 32-bit integers
3573
(define_insn "iorsi3_media"
3574
  [(set (match_operand:SI 0 "gpr_or_fpr_operand" "=d,f")
3575
        (ior:SI (match_operand:SI 1 "gpr_or_fpr_operand" "%d,f")
3576
                (match_operand:SI 2 "gpr_fpr_or_int12_operand" "dNOP,f")))]
3577
  "TARGET_MEDIA"
3578
  "@
3579
   or%I2 %1, %2, %0
3580
   mor %1, %2, %0"
3581
  [(set_attr "length" "4")
3582
   (set_attr "type" "int,mlogic")])
3583
 
3584
(define_insn "iorsi3_nomedia"
3585
  [(set (match_operand:SI 0 "integer_register_operand" "=d")
3586
        (ior:SI (match_operand:SI 1 "integer_register_operand" "%d")
3587
                (match_operand:SI 2 "gpr_or_int12_operand" "dNOP")))]
3588
  "!TARGET_MEDIA"
3589
  "or%I2 %1, %2, %0"
3590
  [(set_attr "length" "4")
3591
   (set_attr "type" "int")])
3592
 
3593
(define_expand "iorsi3"
3594
  [(set (match_operand:SI 0 "gpr_or_fpr_operand" "")
3595
        (ior:SI (match_operand:SI 1 "gpr_or_fpr_operand" "")
3596
                (match_operand:SI 2 "gpr_fpr_or_int12_operand" "")))]
3597
  ""
3598
  "")
3599
 
3600
;; Exclusive OR, 32-bit integers
3601
(define_insn "xorsi3_media"
3602
  [(set (match_operand:SI 0 "gpr_or_fpr_operand" "=d,f")
3603
        (xor:SI (match_operand:SI 1 "gpr_or_fpr_operand" "%d,f")
3604
                (match_operand:SI 2 "gpr_fpr_or_int12_operand" "dNOP,f")))]
3605
  "TARGET_MEDIA"
3606
  "@
3607
   xor%I2 %1, %2, %0
3608
   mxor %1, %2, %0"
3609
  [(set_attr "length" "4")
3610
   (set_attr "type" "int,mlogic")])
3611
 
3612
(define_insn "xorsi3_nomedia"
3613
  [(set (match_operand:SI 0 "integer_register_operand" "=d")
3614
        (xor:SI (match_operand:SI 1 "integer_register_operand" "%d")
3615
                (match_operand:SI 2 "gpr_or_int12_operand" "dNOP")))]
3616
  "!TARGET_MEDIA"
3617
  "xor%I2 %1, %2, %0"
3618
  [(set_attr "length" "4")
3619
   (set_attr "type" "int")])
3620
 
3621
(define_expand "xorsi3"
3622
  [(set (match_operand:SI 0 "gpr_or_fpr_operand" "")
3623
        (xor:SI (match_operand:SI 1 "gpr_or_fpr_operand" "")
3624
                (match_operand:SI 2 "gpr_fpr_or_int12_operand" "")))]
3625
  ""
3626
  "")
3627
 
3628
;; One's complement, 32-bit integers
3629
(define_insn "one_cmplsi2_media"
3630
  [(set (match_operand:SI 0 "gpr_or_fpr_operand" "=d,f")
3631
        (not:SI (match_operand:SI 1 "gpr_or_fpr_operand" "d,f")))]
3632
  "TARGET_MEDIA"
3633
  "@
3634
   not %1, %0
3635
   mnot %1, %0"
3636
  [(set_attr "length" "4")
3637
   (set_attr "type" "int,mlogic")])
3638
 
3639
(define_insn "one_cmplsi2_nomedia"
3640
  [(set (match_operand:SI 0 "integer_register_operand" "=d")
3641
        (not:SI (match_operand:SI 1 "integer_register_operand" "d")))]
3642
  "!TARGET_MEDIA"
3643
  "not %1,%0"
3644
  [(set_attr "length" "4")
3645
   (set_attr "type" "int")])
3646
 
3647
(define_expand "one_cmplsi2"
3648
  [(set (match_operand:SI 0 "gpr_or_fpr_operand" "")
3649
        (not:SI (match_operand:SI 1 "gpr_or_fpr_operand" "")))]
3650
  ""
3651
  "")
3652
 
3653
 
3654
;; ::::::::::::::::::::
3655
;; ::
3656
;; :: 64-Bit Integer Logical operations
3657
;; ::
3658
;; ::::::::::::::::::::
3659
 
3660
;; Logical AND, 64-bit integers
3661
;; (define_insn "anddi3"
3662
;;   [(set (match_operand:DI 0 "register_operand" "=r")
3663
;;      (and:DI (match_operand:DI 1 "register_operand" "%r")
3664
;;              (match_operand:DI 2 "nonmemory_operand" "ri")))]
3665
;;   ""
3666
;;   "anddi3 %0,%1,%2"
3667
;;   [(set_attr "length" "4")])
3668
 
3669
;; Inclusive OR, 64-bit integers
3670
;; (define_insn "iordi3"
3671
;;   [(set (match_operand:DI 0 "register_operand" "=r")
3672
;;      (ior:DI (match_operand:DI 1 "register_operand" "%r")
3673
;;              (match_operand:DI 2 "nonmemory_operand" "ri")))]
3674
;;   ""
3675
;;   "iordi3 %0,%1,%2"
3676
;;   [(set_attr "length" "4")])
3677
 
3678
;; Exclusive OR, 64-bit integers
3679
;; (define_insn "xordi3"
3680
;;   [(set (match_operand:DI 0 "register_operand" "=r")
3681
;;      (xor:DI (match_operand:DI 1 "register_operand" "%r")
3682
;;              (match_operand:DI 2 "nonmemory_operand" "ri")))]
3683
;;   ""
3684
;;   "xordi3 %0,%1,%2"
3685
;;   [(set_attr "length" "4")])
3686
 
3687
;; One's complement, 64-bit integers
3688
;; (define_insn "one_cmpldi2"
3689
;;   [(set (match_operand:DI 0 "register_operand" "=r")
3690
;;      (not:DI (match_operand:DI 1 "register_operand" "r")))]
3691
;;   ""
3692
;;   "notdi3 %0,%1"
3693
;;   [(set_attr "length" "4")])
3694
 
3695
 
3696
;; ::::::::::::::::::::
3697
;; ::
3698
;; :: Combination of integer operation with comparison
3699
;; ::
3700
;; ::::::::::::::::::::
3701
 
3702
(define_insn "*combo_intop_compare1"
3703
  [(set (match_operand:CC_NZ 0 "icc_operand" "=t")
3704
        (compare:CC_NZ
3705
         (match_operator:SI 1 "intop_compare_operator"
3706
                       [(match_operand:SI 2 "integer_register_operand" "d")
3707
                        (match_operand:SI 3 "gpr_or_int10_operand" "dJ")])
3708
         (const_int 0)))]
3709
  ""
3710
  "%O1%I3cc %2, %3, %., %0"
3711
  [(set_attr "type" "int")
3712
   (set_attr "length" "4")])
3713
 
3714
(define_insn "*combo_intop_compare2"
3715
  [(set (match_operand:CC_NZ 0 "icc_operand" "=t")
3716
        (compare:CC_NZ
3717
         (match_operator:SI 1 "intop_compare_operator"
3718
                        [(match_operand:SI 2 "integer_register_operand" "d")
3719
                         (match_operand:SI 3 "gpr_or_int10_operand" "dJ")])
3720
         (const_int 0)))
3721
   (set (match_operand:SI 4 "integer_register_operand" "=d")
3722
        (match_operator:SI 5 "intop_compare_operator"
3723
                           [(match_dup 2)
3724
                            (match_dup 3)]))]
3725
  "GET_CODE (operands[1]) == GET_CODE (operands[5])"
3726
  "%O1%I3cc %2, %3, %4, %0"
3727
  [(set_attr "type" "int")
3728
   (set_attr "length" "4")])
3729
 
3730
;; ::::::::::::::::::::
3731
;; ::
3732
;; :: Comparisons
3733
;; ::
3734
;; ::::::::::::::::::::
3735
 
3736
;; The comparisons are generated by the branch and/or scc operations
3737
 
3738
(define_insn "cmpsi_cc"
3739
  [(set (match_operand:CC 0 "icc_operand" "=t,t")
3740
        (compare:CC (match_operand:SI 1 "integer_register_operand" "d,d")
3741
                    (match_operand:SI 2 "gpr_or_int10_operand" "d,J")))]
3742
  ""
3743
  "cmp%I2 %1,%2,%0"
3744
  [(set_attr "length" "4")
3745
   (set_attr "type" "int")])
3746
 
3747
(define_insn "*cmpsi_cc_uns"
3748
  [(set (match_operand:CC_UNS 0 "icc_operand" "=t,t")
3749
        (compare:CC_UNS (match_operand:SI 1 "integer_register_operand" "d,d")
3750
                        (match_operand:SI 2 "gpr_or_int10_operand" "d,J")))]
3751
  ""
3752
  "cmp%I2 %1,%2,%0"
3753
  [(set_attr "length" "4")
3754
   (set_attr "type" "int")])
3755
 
3756
;; The only requirement for a CC_NZmode GPR or memory value is that
3757
;; comparing it against zero must set the Z and N flags appropriately.
3758
;; The source operand is therefore a valid CC_NZmode value.
3759
(define_insn "*cmpsi_cc_nz"
3760
  [(set (match_operand:CC_NZ 0 "nonimmediate_operand" "=t,d,m")
3761
        (compare:CC_NZ (match_operand:SI 1 "integer_register_operand" "d,d,d")
3762
                       (const_int 0)))]
3763
  ""
3764
  "@
3765
   cmpi %1, #0, %0
3766
   mov %1, %0
3767
   st%I0%U0 %1, %M0"
3768
  [(set_attr "length" "4,4,4")
3769
   (set_attr "type" "int,int,gstore")])
3770
 
3771
(define_insn "*cmpsf_cc_fp"
3772
  [(set (match_operand:CC_FP 0 "fcc_operand" "=u")
3773
        (compare:CC_FP (match_operand:SF 1 "fpr_operand" "f")
3774
                       (match_operand:SF 2 "fpr_operand" "f")))]
3775
  "TARGET_HARD_FLOAT"
3776
  "fcmps %1,%2,%0"
3777
  [(set_attr "length" "4")
3778
   (set_attr "type" "fscmp")])
3779
 
3780
(define_insn "*cmpdf_cc_fp"
3781
  [(set (match_operand:CC_FP 0 "fcc_operand" "=u")
3782
        (compare:CC_FP (match_operand:DF 1 "even_fpr_operand" "h")
3783
                       (match_operand:DF 2 "even_fpr_operand" "h")))]
3784
  "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3785
  "fcmpd %1,%2,%0"
3786
  [(set_attr "length" "4")
3787
   (set_attr "type" "fdcmp")])
3788
 
3789
 
3790
;; ::::::::::::::::::::
3791
;; ::
3792
;; :: Branches
3793
;; ::
3794
;; ::::::::::::::::::::
3795
 
3796
;; Define_expands called by the machine independent part of the compiler
3797
;; to allocate a new comparison register.
3798
 
3799
(define_expand "cbranchdf4"
3800
  [(use (match_operator 0 "ordered_comparison_operator"
3801
         [(match_operand:DF 1 "fpr_operand" "")
3802
          (match_operand:DF 2 "fpr_operand" "")]))
3803
   (use (match_operand 3 ""))]
3804
  "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3805
  { if (frv_emit_cond_branch (operands)) DONE; gcc_unreachable (); })
3806
 
3807
(define_expand "cbranchsf4"
3808
  [(use (match_operator 0 "ordered_comparison_operator"
3809
         [(match_operand:SF 1 "fpr_operand" "")
3810
          (match_operand:SF 2 "fpr_operand" "")]))
3811
   (use (match_operand 3 ""))]
3812
  "TARGET_HARD_FLOAT"
3813
  { if (frv_emit_cond_branch (operands)) DONE; gcc_unreachable (); })
3814
 
3815
(define_expand "cbranchsi4"
3816
  [(use (match_operator 0 "ordered_comparison_operator"
3817
         [(match_operand:SI 1 "integer_register_operand" "")
3818
          (match_operand:SI 2 "gpr_or_int10_operand" "")]))
3819
   (use (match_operand 3 ""))]
3820
  ""
3821
  { if (frv_emit_cond_branch (operands)) DONE; gcc_unreachable (); })
3822
 
3823
;; Actual branches.  We must allow for the (label_ref) and the (pc) to be
3824
;; swapped.  If they are swapped, it reverses the sense of the branch.
3825
;;
3826
;; Note - unlike the define expands above, these patterns can be amalgamated
3827
;; into one pattern for branch-if-true and one for branch-if-false.  This does
3828
;; require an operand operator to select the correct branch mnemonic.
3829
;;
3830
;; If a fixed condition code register is being used, (as opposed to, say,
3831
;; using cc0), then the expands could look like this:
3832
;;
3833
;; (define_insn "*branch_true"
3834
;;   [(set (pc)
3835
;;      (if_then_else (match_operator:CC 0 "comparison_operator"
3836
;;                                       [(reg:CC )
3837
;;                                        (const_int 0)])
3838
;;                    (label_ref (match_operand 1 "" ""))
3839
;;                    (pc)))]
3840
;;   ""
3841
;;   "b%B0 %1"
3842
;;   [(set_attr "length" "4")]
3843
;; )
3844
;;
3845
;; In the above example the %B is a directive to frv_print_operand()
3846
;; to decode and print the correct branch mnemonic.
3847
 
3848
(define_insn "*branch_int_true"
3849
  [(set (pc)
3850
        (if_then_else (match_operator 0 "integer_relational_operator"
3851
                                      [(match_operand 1 "icc_operand" "t")
3852
                                       (const_int 0)])
3853
                      (label_ref (match_operand 2 "" ""))
3854
                      (pc)))]
3855
  ""
3856
  "*
3857
{
3858
  if (get_attr_length (insn) == 4)
3859
    return \"b%c0 %1,%#,%l2\";
3860
  else
3861
    return \"b%C0 %1,%#,1f\;call %l2\\n1:\";
3862
}"
3863
  [(set (attr "length")
3864
        (if_then_else
3865
            (and (ge (minus (match_dup 2) (pc)) (const_int -32768))
3866
                 (le (minus (match_dup 2) (pc)) (const_int 32764)))
3867
            (const_int 4)
3868
            (const_int 8)))
3869
   (set (attr "far_jump")
3870
        (if_then_else
3871
            (eq_attr "length" "4")
3872
            (const_string "no")
3873
            (const_string "yes")))
3874
   (set (attr "type")
3875
        (if_then_else
3876
            (eq_attr "length" "4")
3877
            (const_string "branch")
3878
            (const_string "multi")))])
3879
 
3880
(define_insn "*branch_int_false"
3881
  [(set (pc)
3882
        (if_then_else (match_operator 0 "integer_relational_operator"
3883
                                      [(match_operand 1 "icc_operand" "t")
3884
                                       (const_int 0)])
3885
                      (pc)
3886
                      (label_ref (match_operand 2 "" ""))))]
3887
  ""
3888
  "*
3889
{
3890
  if (get_attr_length (insn) == 4)
3891
    return \"b%C0 %1,%#,%l2\";
3892
  else
3893
    return \"b%c0 %1,%#,1f\;call %l2\\n1:\";
3894
}"
3895
  [(set (attr "length")
3896
        (if_then_else
3897
            (and (ge (minus (match_dup 2) (pc)) (const_int -32768))
3898
                 (le (minus (match_dup 2) (pc)) (const_int 32764)))
3899
            (const_int 4)
3900
            (const_int 8)))
3901
   (set (attr "far_jump")
3902
        (if_then_else
3903
            (eq_attr "length" "4")
3904
            (const_string "no")
3905
            (const_string "yes")))
3906
   (set (attr "type")
3907
        (if_then_else
3908
            (eq_attr "length" "4")
3909
            (const_string "branch")
3910
            (const_string "multi")))])
3911
 
3912
(define_insn "*branch_fp_true"
3913
  [(set (pc)
3914
        (if_then_else (match_operator:CC_FP 0 "float_relational_operator"
3915
                                            [(match_operand 1 "fcc_operand" "u")
3916
                                             (const_int 0)])
3917
                      (label_ref (match_operand 2 "" ""))
3918
                      (pc)))]
3919
  ""
3920
  "*
3921
{
3922
  if (get_attr_length (insn) == 4)
3923
    return \"fb%f0 %1,%#,%l2\";
3924
  else
3925
    return \"fb%F0 %1,%#,1f\;call %l2\\n1:\";
3926
}"
3927
  [(set (attr "length")
3928
        (if_then_else
3929
            (and (ge (minus (match_dup 2) (pc)) (const_int -32768))
3930
                 (le (minus (match_dup 2) (pc)) (const_int 32764)))
3931
            (const_int 4)
3932
            (const_int 8)))
3933
   (set (attr "far_jump")
3934
        (if_then_else
3935
            (eq_attr "length" "4")
3936
            (const_string "no")
3937
            (const_string "yes")))
3938
   (set (attr "type")
3939
        (if_then_else
3940
            (eq_attr "length" "4")
3941
            (const_string "branch")
3942
            (const_string "multi")))])
3943
 
3944
(define_insn "*branch_fp_false"
3945
  [(set (pc)
3946
        (if_then_else (match_operator:CC_FP 0 "float_relational_operator"
3947
                                            [(match_operand 1 "fcc_operand" "u")
3948
                                             (const_int 0)])
3949
                      (pc)
3950
                      (label_ref (match_operand 2 "" ""))))]
3951
  ""
3952
  "*
3953
{
3954
  if (get_attr_length (insn) == 4)
3955
    return \"fb%F0 %1,%#,%l2\";
3956
  else
3957
    return \"fb%f0 %1,%#,1f\;call %l2\\n1:\";
3958
}"
3959
  [(set (attr "length")
3960
        (if_then_else
3961
            (and (ge (minus (match_dup 2) (pc)) (const_int -32768))
3962
                 (le (minus (match_dup 2) (pc)) (const_int 32764)))
3963
            (const_int 4)
3964
            (const_int 8)))
3965
   (set (attr "far_jump")
3966
        (if_then_else
3967
            (eq_attr "length" "4")
3968
            (const_string "no")
3969
            (const_string "yes")))
3970
   (set (attr "type")
3971
        (if_then_else
3972
            (eq_attr "length" "4")
3973
            (const_string "branch")
3974
            (const_string "multi")))])
3975
 
3976
 
3977
;; ::::::::::::::::::::
3978
;; ::
3979
;; :: Set flag operations
3980
;; ::
3981
;; ::::::::::::::::::::
3982
 
3983
;; Define_expands called by the machine independent part of the compiler
3984
;; to allocate a new comparison register
3985
 
3986
(define_expand "cstoredf4"
3987
  [(use (match_operator:SI 1 "ordered_comparison_operator"
3988
         [(match_operand:DF 2 "fpr_operand")
3989
          (match_operand:DF 3 "fpr_operand")]))
3990
   (clobber (match_operand:SI 0 "register_operand"))]
3991
  "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3992
  { if (frv_emit_scc (operands)) DONE; else FAIL; })
3993
 
3994
(define_expand "cstoresf4"
3995
  [(use (match_operator:SI 1 "ordered_comparison_operator"
3996
         [(match_operand:SF 2 "fpr_operand")
3997
          (match_operand:SF 3 "fpr_operand")]))
3998
   (clobber (match_operand:SI 0 "register_operand"))]
3999
  "TARGET_HARD_FLOAT"
4000
  { if (frv_emit_scc (operands)) DONE; else FAIL; })
4001
 
4002
(define_expand "cstoresi4"
4003
  [(use (match_operator:SI 1 "ordered_comparison_operator"
4004
         [(match_operand:SI 2 "integer_register_operand")
4005
          (match_operand:SI 3 "gpr_or_int10_operand")]))
4006
   (clobber (match_operand:SI 0 "register_operand"))]
4007
  ""
4008
  { if (frv_emit_scc (operands)) DONE; else FAIL; })
4009
 
4010
(define_insn "*scc_int"
4011
  [(set (match_operand:SI 0 "integer_register_operand" "=d")
4012
        (match_operator:SI 1 "integer_relational_operator"
4013
                           [(match_operand 2 "icc_operand" "t")
4014
                            (const_int 0)]))
4015
   (clobber (match_operand:CC_CCR 3 "icr_operand" "=v"))]
4016
  ""
4017
  "#"
4018
  [(set_attr "length" "12")
4019
   (set_attr "type" "multi")])
4020
 
4021
(define_insn "*scc_float"
4022
  [(set (match_operand:SI 0 "integer_register_operand" "=d")
4023
        (match_operator:SI 1 "float_relational_operator"
4024
                           [(match_operand:CC_FP 2 "fcc_operand" "u")
4025
                            (const_int 0)]))
4026
   (clobber (match_operand:CC_CCR 3 "fcr_operand" "=w"))]
4027
  ""
4028
  "#"
4029
  [(set_attr "length" "12")
4030
   (set_attr "type" "multi")])
4031
 
4032
;; XXX -- add reload_completed to the splits, because register allocation
4033
;; currently isn't ready to see cond_exec packets.
4034
(define_split
4035
  [(set (match_operand:SI 0 "integer_register_operand" "")
4036
        (match_operator:SI 1 "relational_operator"
4037
                           [(match_operand 2 "cc_operand" "")
4038
                            (const_int 0)]))
4039
   (clobber (match_operand 3 "cr_operand" ""))]
4040
  "reload_completed"
4041
  [(match_dup 4)]
4042
  "operands[4] = frv_split_scc (operands[0], operands[1], operands[2],
4043
                                operands[3], (HOST_WIDE_INT) 1);")
4044
 
4045
(define_insn "*scc_neg1_int"
4046
  [(set (match_operand:SI 0 "integer_register_operand" "=d")
4047
        (neg:SI (match_operator:SI 1 "integer_relational_operator"
4048
                                   [(match_operand 2 "icc_operand" "t")
4049
                                    (const_int 0)])))
4050
   (clobber (match_operand:CC_CCR 3 "icr_operand" "=v"))]
4051
  ""
4052
  "#"
4053
  [(set_attr "length" "12")
4054
   (set_attr "type" "multi")])
4055
 
4056
(define_insn "*scc_neg1_float"
4057
  [(set (match_operand:SI 0 "integer_register_operand" "=d")
4058
        (neg:SI (match_operator:SI 1 "float_relational_operator"
4059
                                   [(match_operand:CC_FP 2 "fcc_operand" "u")
4060
                                    (const_int 0)])))
4061
   (clobber (match_operand:CC_CCR 3 "fcr_operand" "=w"))]
4062
  ""
4063
  "#"
4064
  [(set_attr "length" "12")
4065
   (set_attr "type" "multi")])
4066
 
4067
(define_split
4068
  [(set (match_operand:SI 0 "integer_register_operand" "")
4069
        (neg:SI (match_operator:SI 1 "relational_operator"
4070
                                   [(match_operand 2 "cc_operand" "")
4071
                                    (const_int 0)])))
4072
   (clobber (match_operand 3 "cr_operand" ""))]
4073
  "reload_completed"
4074
  [(match_dup 4)]
4075
  "operands[4] = frv_split_scc (operands[0], operands[1], operands[2],
4076
                                operands[3], (HOST_WIDE_INT) -1);")
4077
 
4078
 
4079
;; ::::::::::::::::::::
4080
;; ::
4081
;; :: Conditionally executed instructions
4082
;; ::
4083
;; ::::::::::::::::::::
4084
 
4085
;; Convert ICC/FCC comparison into CCR bits so we can do conditional execution
4086
(define_insn "*ck_signed"
4087
  [(set (match_operand:CC_CCR 0 "icr_operand" "=v")
4088
        (match_operator:CC_CCR 1 "integer_relational_operator"
4089
                               [(match_operand 2 "icc_operand" "t")
4090
                                (const_int 0)]))]
4091
  ""
4092
  "ck%c1 %2, %0"
4093
  [(set_attr "length" "4")
4094
   (set_attr "type" "ccr")])
4095
 
4096
(define_insn "*fck_float"
4097
  [(set (match_operand:CC_CCR 0 "fcr_operand" "=w")
4098
        (match_operator:CC_CCR 1 "float_relational_operator"
4099
                               [(match_operand:CC_FP 2 "fcc_operand" "u")
4100
                                (const_int 0)]))]
4101
  "TARGET_HAS_FPRS"
4102
  "fck%c1 %2, %0"
4103
  [(set_attr "length" "4")
4104
   (set_attr "type" "ccr")])
4105
 
4106
;; Conditionally convert ICC/FCC comparison into CCR bits to provide && and ||
4107
;; tests in conditional execution
4108
(define_insn "cond_exec_ck"
4109
  [(set (match_operand:CC_CCR 0 "cr_operand" "=v,w")
4110
        (if_then_else:CC_CCR (match_operator 1 "ccr_eqne_operator"
4111
                                             [(match_operand 2 "cr_operand" "C,C")
4112
                                              (const_int 0)])
4113
                             (match_operator 3 "relational_operator"
4114
                                             [(match_operand 4 "cc_operand" "t,u")
4115
                                              (const_int 0)])
4116
                             (const_int 0)))]
4117
  ""
4118
  "@
4119
   cck%c3 %4, %0, %2, %e1
4120
   cfck%f3 %4, %0, %2, %e1"
4121
  [(set_attr "length" "4")
4122
   (set_attr "type" "ccr")])
4123
 
4124
;; Conditionally set a register to either 0 or another register
4125
(define_insn "*cond_exec_movqi"
4126
  [(cond_exec
4127
    (match_operator 0 "ccr_eqne_operator"
4128
                    [(match_operand 1 "cr_operand" "C,C,C,C,C,C")
4129
                     (const_int 0)])
4130
    (set (match_operand:QI 2 "condexec_dest_operand" "=d,d,U,?f,?f,?d")
4131
         (match_operand:QI 3 "condexec_source_operand" "dO,U,dO,f,d,f")))]
4132
  "register_operand(operands[2], QImode) || reg_or_0_operand (operands[3], QImode)"
4133
  "* return output_condmove_single (operands, insn);"
4134
  [(set_attr "length" "4")
4135
   (set_attr "type" "int,gload,gstore,fsconv,movgf,movfg")])
4136
 
4137
(define_insn "*cond_exec_movhi"
4138
  [(cond_exec
4139
    (match_operator 0 "ccr_eqne_operator"
4140
                    [(match_operand 1 "cr_operand" "C,C,C,C,C,C")
4141
                     (const_int 0)])
4142
    (set (match_operand:HI 2 "condexec_dest_operand" "=d,d,U,?f,?f,?d")
4143
         (match_operand:HI 3 "condexec_source_operand" "dO,U,dO,f,d,f")))]
4144
  "register_operand(operands[2], HImode) || reg_or_0_operand (operands[3], HImode)"
4145
  "* return output_condmove_single (operands, insn);"
4146
  [(set_attr "length" "4")
4147
   (set_attr "type" "int,gload,gstore,fsconv,movgf,movfg")])
4148
 
4149
(define_insn "*cond_exec_movsi"
4150
  [(cond_exec
4151
    (match_operator 0 "ccr_eqne_operator"
4152
                    [(match_operand 1 "cr_operand" "C,C,C,C,C,C,C,C")
4153
                     (const_int 0)])
4154
    (set (match_operand:SI 2 "condexec_dest_operand" "=d,d,U,?f,?f,?d,?f,?m")
4155
         (match_operand:SI 3 "condexec_source_operand" "dO,U,dO,f,d,f,m,f")))]
4156
  "register_operand(operands[2], SImode) || reg_or_0_operand (operands[3], SImode)"
4157
  "* return output_condmove_single (operands, insn);"
4158
  [(set_attr "length" "4")
4159
   (set_attr "type" "int,gload,gstore,fsconv,movgf,movfg,fload,fstore")])
4160
 
4161
 
4162
(define_insn "*cond_exec_movsf_has_fprs"
4163
  [(cond_exec
4164
    (match_operator 0 "ccr_eqne_operator"
4165
                    [(match_operand 1 "cr_operand" "C,C,C,C,C,C,C,C,C,C")
4166
                     (const_int 0)])
4167
    (set (match_operand:SF 2 "condexec_dest_operand" "=f,?d,?d,?f,f,f,?d,U,?U,U")
4168
         (match_operand:SF 3 "condexec_source_operand" "f,d,f,d,G,U,U,f,d,G")))]
4169
  "TARGET_HAS_FPRS"
4170
  "* return output_condmove_single (operands, insn);"
4171
  [(set_attr "length" "4")
4172
   (set_attr "type" "fsconv,int,movgf,movfg,movgf,fload,gload,fstore,gstore,gstore")])
4173
 
4174
(define_insn "*cond_exec_movsf_no_fprs"
4175
  [(cond_exec
4176
    (match_operator 0 "ccr_eqne_operator"
4177
                    [(match_operand 1 "cr_operand" "C,C,C")
4178
                     (const_int 0)])
4179
    (set (match_operand:SF 2 "condexec_dest_operand" "=d,d,U")
4180
         (match_operand:SF 3 "condexec_source_operand" "d,U,dG")))]
4181
  "! TARGET_HAS_FPRS"
4182
  "* return output_condmove_single (operands, insn);"
4183
  [(set_attr "length" "4")
4184
   (set_attr "type" "int,gload,gstore")])
4185
 
4186
(define_insn "*cond_exec_si_binary1"
4187
  [(cond_exec
4188
    (match_operator 0 "ccr_eqne_operator"
4189
                    [(match_operand 1 "cr_operand" "C")
4190
                     (const_int 0)])
4191
    (set (match_operand:SI 2 "integer_register_operand" "=d")
4192
         (match_operator:SI 3 "condexec_si_binary_operator"
4193
                            [(match_operand:SI 4 "integer_register_operand" "d")
4194
                             (match_operand:SI 5 "integer_register_operand" "d")])))]
4195
  ""
4196
  "*
4197
{
4198
  switch (GET_CODE (operands[3]))
4199
    {
4200
      case PLUS:     return \"cadd %4, %z5, %2, %1, %e0\";
4201
      case MINUS:    return \"csub %4, %z5, %2, %1, %e0\";
4202
      case AND:      return \"cand %4, %z5, %2, %1, %e0\";
4203
      case IOR:      return \"cor %4, %z5, %2, %1, %e0\";
4204
      case XOR:      return \"cxor %4, %z5, %2, %1, %e0\";
4205
      case ASHIFT:   return \"csll %4, %z5, %2, %1, %e0\";
4206
      case ASHIFTRT: return \"csra %4, %z5, %2, %1, %e0\";
4207
      case LSHIFTRT: return \"csrl %4, %z5, %2, %1, %e0\";
4208
      default:       gcc_unreachable ();
4209
    }
4210
}"
4211
  [(set_attr "length" "4")
4212
   (set_attr "type" "int")])
4213
 
4214
(define_insn "*cond_exec_si_binary2"
4215
  [(cond_exec
4216
    (match_operator 0 "ccr_eqne_operator"
4217
                    [(match_operand 1 "cr_operand" "C")
4218
                     (const_int 0)])
4219
    (set (match_operand:SI 2 "fpr_operand" "=f")
4220
         (match_operator:SI 3 "condexec_si_media_operator"
4221
                            [(match_operand:SI 4 "fpr_operand" "f")
4222
                             (match_operand:SI 5 "fpr_operand" "f")])))]
4223
  "TARGET_MEDIA"
4224
  "*
4225
{
4226
  switch (GET_CODE (operands[3]))
4227
    {
4228
      case AND: return \"cmand %4, %5, %2, %1, %e0\";
4229
      case IOR: return \"cmor %4, %5, %2, %1, %e0\";
4230
      case XOR: return \"cmxor %4, %5, %2, %1, %e0\";
4231
      default:  gcc_unreachable ();
4232
    }
4233
}"
4234
  [(set_attr "length" "4")
4235
   (set_attr "type" "mlogic")])
4236
 
4237
;; Note, flow does not (currently) know how to handle an operation that uses
4238
;; only part of the hard registers allocated for a multiregister value, such as
4239
;; DImode in this case if the user is only interested in the lower 32-bits.  So
4240
;; we emit a USE of the entire register after the csmul instruction so it won't
4241
;; get confused.  See frv_ifcvt_modify_insn for more details.
4242
 
4243
(define_insn "*cond_exec_si_smul"
4244
  [(cond_exec
4245
    (match_operator 0 "ccr_eqne_operator"
4246
                    [(match_operand 1 "cr_operand" "C")
4247
                     (const_int 0)])
4248
    (set (match_operand:DI 2 "even_gpr_operand" "=e")
4249
         (mult:DI (sign_extend:DI (match_operand:SI 3 "integer_register_operand" "%d"))
4250
                  (sign_extend:DI (match_operand:SI 4 "integer_register_operand" "d")))))]
4251
  ""
4252
  "csmul %3, %4, %2, %1, %e0"
4253
  [(set_attr "length" "4")
4254
   (set_attr "type" "mul")])
4255
 
4256
(define_insn "*cond_exec_si_divide"
4257
  [(cond_exec
4258
    (match_operator 0 "ccr_eqne_operator"
4259
                    [(match_operand 1 "cr_operand" "C")
4260
                     (const_int 0)])
4261
    (set (match_operand:SI 2 "integer_register_operand" "=d")
4262
         (match_operator:SI 3 "condexec_si_divide_operator"
4263
                            [(match_operand:SI 4 "integer_register_operand" "d")
4264
                             (match_operand:SI 5 "integer_register_operand" "d")])))]
4265
  ""
4266
  "*
4267
{
4268
  switch (GET_CODE (operands[3]))
4269
    {
4270
      case DIV:  return \"csdiv %4, %z5, %2, %1, %e0\";
4271
      case UDIV: return \"cudiv %4, %z5, %2, %1, %e0\";
4272
      default:   gcc_unreachable ();
4273
    }
4274
}"
4275
  [(set_attr "length" "4")
4276
   (set_attr "type" "div")])
4277
 
4278
(define_insn "*cond_exec_si_unary1"
4279
  [(cond_exec
4280
    (match_operator 0 "ccr_eqne_operator"
4281
                    [(match_operand 1 "cr_operand" "C")
4282
                     (const_int 0)])
4283
    (set (match_operand:SI 2 "integer_register_operand" "=d")
4284
         (match_operator:SI 3 "condexec_si_unary_operator"
4285
                            [(match_operand:SI 4 "integer_register_operand" "d")])))]
4286
  ""
4287
  "*
4288
{
4289
  switch (GET_CODE (operands[3]))
4290
    {
4291
      case NOT: return \"cnot %4, %2, %1, %e0\";
4292
      case NEG: return \"csub %., %4, %2, %1, %e0\";
4293
      default:  gcc_unreachable ();
4294
    }
4295
}"
4296
  [(set_attr "length" "4")
4297
   (set_attr "type" "int")])
4298
 
4299
(define_insn "*cond_exec_si_unary2"
4300
  [(cond_exec
4301
    (match_operator 0 "ccr_eqne_operator"
4302
                    [(match_operand 1 "cr_operand" "C")
4303
                     (const_int 0)])
4304
    (set (match_operand:SI 2 "fpr_operand" "=f")
4305
         (not:SI (match_operand:SI 3 "fpr_operand" "f"))))]
4306
  "TARGET_MEDIA"
4307
  "cmnot %3, %2, %1, %e0"
4308
  [(set_attr "length" "4")
4309
   (set_attr "type" "mlogic")])
4310
 
4311
(define_insn "*cond_exec_cmpsi_cc"
4312
  [(cond_exec
4313
    (match_operator 0 "ccr_eqne_operator"
4314
                    [(match_operand 1 "cr_operand" "C")
4315
                     (const_int 0)])
4316
    (set (match_operand:CC 2 "icc_operand" "=t")
4317
         (compare:CC (match_operand:SI 3 "integer_register_operand" "d")
4318
                     (match_operand:SI 4 "reg_or_0_operand" "dO"))))]
4319
  "reload_completed
4320
   && REGNO (operands[1]) == REGNO (operands[2]) - ICC_FIRST + ICR_FIRST"
4321
  "ccmp %3, %z4, %1, %e0"
4322
  [(set_attr "length" "4")
4323
   (set_attr "type" "int")])
4324
 
4325
(define_insn "*cond_exec_cmpsi_cc_uns"
4326
  [(cond_exec
4327
    (match_operator 0 "ccr_eqne_operator"
4328
                    [(match_operand 1 "cr_operand" "C")
4329
                     (const_int 0)])
4330
    (set (match_operand:CC_UNS 2 "icc_operand" "=t")
4331
         (compare:CC_UNS (match_operand:SI 3 "integer_register_operand" "d")
4332
                         (match_operand:SI 4 "reg_or_0_operand" "dO"))))]
4333
  "reload_completed
4334
   && REGNO (operands[1]) == REGNO (operands[2]) - ICC_FIRST + ICR_FIRST"
4335
  "ccmp %3, %z4, %1, %e0"
4336
  [(set_attr "length" "4")
4337
   (set_attr "type" "int")])
4338
 
4339
(define_insn "*cond_exec_cmpsi_cc_nz"
4340
  [(cond_exec
4341
    (match_operator 0 "ccr_eqne_operator"
4342
                    [(match_operand 1 "cr_operand" "C")
4343
                     (const_int 0)])
4344
    (set (match_operand:CC_NZ 2 "icc_operand" "=t")
4345
         (compare:CC_NZ (match_operand:SI 3 "integer_register_operand" "d")
4346
                        (const_int 0))))]
4347
  "reload_completed
4348
   && REGNO (operands[1]) == REGNO (operands[2]) - ICC_FIRST + ICR_FIRST"
4349
  "ccmp %3, %., %1, %e0"
4350
  [(set_attr "length" "4")
4351
   (set_attr "type" "int")])
4352
 
4353
(define_insn "*cond_exec_sf_conv"
4354
  [(cond_exec
4355
    (match_operator 0 "ccr_eqne_operator"
4356
                    [(match_operand 1 "cr_operand" "C")
4357
                     (const_int 0)])
4358
    (set (match_operand:SF 2 "fpr_operand" "=f")
4359
         (match_operator:SF 3 "condexec_sf_conv_operator"
4360
                            [(match_operand:SF 4 "fpr_operand" "f")])))]
4361
  "TARGET_HARD_FLOAT"
4362
  "*
4363
{
4364
  switch (GET_CODE (operands[3]))
4365
    {
4366
      case ABS: return \"cfabss %4, %2, %1, %e0\";
4367
      case NEG: return \"cfnegs %4, %2, %1, %e0\";
4368
      default:  gcc_unreachable ();
4369
    }
4370
}"
4371
  [(set_attr "length" "4")
4372
   (set_attr "type" "fsconv")])
4373
 
4374
(define_insn "*cond_exec_sf_add"
4375
  [(cond_exec
4376
    (match_operator 0 "ccr_eqne_operator"
4377
                    [(match_operand 1 "cr_operand" "C")
4378
                     (const_int 0)])
4379
    (set (match_operand:SF 2 "fpr_operand" "=f")
4380
         (match_operator:SF 3 "condexec_sf_add_operator"
4381
                            [(match_operand:SF 4 "fpr_operand" "f")
4382
                             (match_operand:SF 5 "fpr_operand" "f")])))]
4383
  "TARGET_HARD_FLOAT"
4384
  "*
4385
{
4386
  switch (GET_CODE (operands[3]))
4387
    {
4388
      case PLUS:  return \"cfadds %4, %5, %2, %1, %e0\";
4389
      case MINUS: return \"cfsubs %4, %5, %2, %1, %e0\";
4390
      default:    gcc_unreachable ();
4391
    }
4392
}"
4393
  [(set_attr "length" "4")
4394
   (set_attr "type" "fsadd")])
4395
 
4396
(define_insn "*cond_exec_sf_mul"
4397
  [(cond_exec
4398
    (match_operator 0 "ccr_eqne_operator"
4399
                    [(match_operand 1 "cr_operand" "C")
4400
                     (const_int 0)])
4401
    (set (match_operand:SF 2 "fpr_operand" "=f")
4402
         (mult:SF (match_operand:SF 3 "fpr_operand" "f")
4403
                  (match_operand:SF 4 "fpr_operand" "f"))))]
4404
  "TARGET_HARD_FLOAT"
4405
  "cfmuls %3, %4, %2, %1, %e0"
4406
  [(set_attr "length" "4")
4407
   (set_attr "type" "fsmul")])
4408
 
4409
(define_insn "*cond_exec_sf_div"
4410
  [(cond_exec
4411
    (match_operator 0 "ccr_eqne_operator"
4412
                    [(match_operand 1 "cr_operand" "C")
4413
                     (const_int 0)])
4414
    (set (match_operand:SF 2 "fpr_operand" "=f")
4415
         (div:SF (match_operand:SF 3 "fpr_operand" "f")
4416
                 (match_operand:SF 4 "fpr_operand" "f"))))]
4417
  "TARGET_HARD_FLOAT"
4418
  "cfdivs %3, %4, %2, %1, %e0"
4419
  [(set_attr "length" "4")
4420
   (set_attr "type" "fsdiv")])
4421
 
4422
(define_insn "*cond_exec_sf_sqrt"
4423
  [(cond_exec
4424
    (match_operator 0 "ccr_eqne_operator"
4425
                    [(match_operand 1 "cr_operand" "C")
4426
                     (const_int 0)])
4427
    (set (match_operand:SF 2 "fpr_operand" "=f")
4428
         (sqrt:SF (match_operand:SF 3 "fpr_operand" "f"))))]
4429
  "TARGET_HARD_FLOAT"
4430
  "cfsqrts %3, %2, %1, %e0"
4431
  [(set_attr "length" "4")
4432
   (set_attr "type" "fsdiv")])
4433
 
4434
(define_insn "*cond_exec_cmpsi_cc_fp"
4435
  [(cond_exec
4436
    (match_operator 0 "ccr_eqne_operator"
4437
                    [(match_operand 1 "cr_operand" "C")
4438
                     (const_int 0)])
4439
    (set (match_operand:CC_FP 2 "fcc_operand" "=u")
4440
         (compare:CC_FP (match_operand:SF 3 "fpr_operand" "f")
4441
                        (match_operand:SF 4 "fpr_operand" "f"))))]
4442
  "reload_completed && TARGET_HARD_FLOAT
4443
   && REGNO (operands[1]) == REGNO (operands[2]) - FCC_FIRST + FCR_FIRST"
4444
  "cfcmps %3, %4, %2, %1, %e0"
4445
  [(set_attr "length" "4")
4446
   (set_attr "type" "fsconv")])
4447
 
4448
 
4449
;; ::::::::::::::::::::
4450
;; ::
4451
;; :: Logical operations on CR registers
4452
;; ::
4453
;; ::::::::::::::::::::
4454
 
4455
;; We use UNSPEC to encode andcr/iorcr/etc. rather than the normal RTL
4456
;; operations, since the RTL operations only have an idea of TRUE and FALSE,
4457
;; while the CRs have TRUE, FALSE, and UNDEFINED.
4458
 
4459
(define_expand "andcr"
4460
  [(set (match_operand:CC_CCR 0 "cr_operand" "")
4461
        (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4462
                        (match_operand:CC_CCR 2 "cr_operand" "")
4463
                        (const_int 0)] UNSPEC_CR_LOGIC))]
4464
  ""
4465
  "")
4466
 
4467
(define_expand "orcr"
4468
  [(set (match_operand:CC_CCR 0 "cr_operand" "")
4469
        (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4470
                        (match_operand:CC_CCR 2 "cr_operand" "")
4471
                        (const_int 1)] UNSPEC_CR_LOGIC))]
4472
  ""
4473
  "")
4474
 
4475
(define_expand "xorcr"
4476
  [(set (match_operand:CC_CCR 0 "cr_operand" "")
4477
        (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4478
                        (match_operand:CC_CCR 2 "cr_operand" "")
4479
                        (const_int 2)] UNSPEC_CR_LOGIC))]
4480
  ""
4481
  "")
4482
 
4483
(define_expand "nandcr"
4484
  [(set (match_operand:CC_CCR 0 "cr_operand" "")
4485
        (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4486
                        (match_operand:CC_CCR 2 "cr_operand" "")
4487
                        (const_int 3)] UNSPEC_CR_LOGIC))]
4488
  ""
4489
  "")
4490
 
4491
(define_expand "norcr"
4492
  [(set (match_operand:CC_CCR 0 "cr_operand" "")
4493
        (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4494
                        (match_operand:CC_CCR 2 "cr_operand" "")
4495
                        (const_int 4)] UNSPEC_CR_LOGIC))]
4496
  ""
4497
  "")
4498
 
4499
(define_expand "andncr"
4500
  [(set (match_operand:CC_CCR 0 "cr_operand" "")
4501
        (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4502
                        (match_operand:CC_CCR 2 "cr_operand" "")
4503
                        (const_int 5)] UNSPEC_CR_LOGIC))]
4504
  ""
4505
  "")
4506
 
4507
(define_expand "orncr"
4508
  [(set (match_operand:CC_CCR 0 "cr_operand" "")
4509
        (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4510
                        (match_operand:CC_CCR 2 "cr_operand" "")
4511
                        (const_int 6)] UNSPEC_CR_LOGIC))]
4512
  ""
4513
  "")
4514
 
4515
(define_expand "nandncr"
4516
  [(set (match_operand:CC_CCR 0 "cr_operand" "")
4517
        (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4518
                        (match_operand:CC_CCR 2 "cr_operand" "")
4519
                        (const_int 7)] UNSPEC_CR_LOGIC))]
4520
  ""
4521
  "")
4522
 
4523
(define_expand "norncr"
4524
  [(set (match_operand:CC_CCR 0 "cr_operand" "")
4525
        (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4526
                        (match_operand:CC_CCR 2 "cr_operand" "")
4527
                        (const_int 8)] UNSPEC_CR_LOGIC))]
4528
  ""
4529
  "")
4530
 
4531
(define_expand "notcr"
4532
  [(set (match_operand:CC_CCR 0 "cr_operand" "")
4533
        (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4534
                        (match_dup 1)
4535
                        (const_int 9)] UNSPEC_CR_LOGIC))]
4536
  ""
4537
  "")
4538
 
4539
(define_insn "*logical_cr"
4540
  [(set (match_operand:CC_CCR 0 "cr_operand" "=C")
4541
        (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "C")
4542
                        (match_operand:CC_CCR 2 "cr_operand" "C")
4543
                        (match_operand:SI 3 "const_int_operand" "n")]
4544
                       UNSPEC_CR_LOGIC))]
4545
  ""
4546
  "*
4547
{
4548
  switch (INTVAL (operands[3]))
4549
  {
4550
  default: break;
4551
  case 0: return \"andcr %1, %2, %0\";
4552
  case 1: return \"orcr %1, %2, %0\";
4553
  case 2: return \"xorcr %1, %2, %0\";
4554
  case 3: return \"nandcr %1, %2, %0\";
4555
  case 4: return \"norcr %1, %2, %0\";
4556
  case 5: return \"andncr %1, %2, %0\";
4557
  case 6: return \"orncr %1, %2, %0\";
4558
  case 7: return \"nandncr %1, %2, %0\";
4559
  case 8: return \"norncr %1, %2, %0\";
4560
  case 9: return \"notcr %1, %0\";
4561
  }
4562
 
4563
  fatal_insn (\"logical_cr\", insn);
4564
}"
4565
  [(set_attr "length" "4")
4566
   (set_attr "type" "ccr")])
4567
 
4568
 
4569
;; ::::::::::::::::::::
4570
;; ::
4571
;; :: Conditional move instructions
4572
;; ::
4573
;; ::::::::::::::::::::
4574
 
4575
 
4576
;; - conditional moves based on floating-point comparisons require
4577
;;   TARGET_HARD_FLOAT, because an FPU is required to do the comparison.
4578
 
4579
;; - conditional moves between FPRs based on integer comparisons
4580
;;   require TARGET_HAS_FPRS.
4581
 
4582
(define_expand "movqicc"
4583
  [(set (match_operand:QI 0 "integer_register_operand" "")
4584
        (if_then_else:QI (match_operand 1 "" "")
4585
                         (match_operand:QI 2 "gpr_or_int_operand" "")
4586
                         (match_operand:QI 3 "gpr_or_int_operand" "")))]
4587
  "TARGET_COND_MOVE"
4588
  "
4589
{
4590
  if (!frv_emit_cond_move (operands[0], operands[1], operands[2], operands[3]))
4591
    FAIL;
4592
 
4593
  DONE;
4594
}")
4595
 
4596
(define_insn "*movqicc_internal1_int"
4597
  [(set (match_operand:QI 0 "integer_register_operand" "=d,d,d")
4598
        (if_then_else:QI (match_operator 1 "integer_relational_operator"
4599
                             [(match_operand 2 "icc_operand" "t,t,t")
4600
                              (const_int 0)])
4601
                         (match_operand:QI 3 "reg_or_0_operand" "0,dO,dO")
4602
                         (match_operand:QI 4 "reg_or_0_operand" "dO,0,dO")))
4603
   (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v"))]
4604
  ""
4605
  "#"
4606
  [(set_attr "length" "8,8,12")
4607
   (set_attr "type" "multi")])
4608
 
4609
(define_insn "*movqicc_internal1_float"
4610
  [(set (match_operand:QI 0 "integer_register_operand" "=d,d,d")
4611
        (if_then_else:QI (match_operator:CC_FP 1 "float_relational_operator"
4612
                             [(match_operand:CC_FP 2 "fcc_operand" "u,u,u")
4613
                              (const_int 0)])
4614
                         (match_operand:QI 3 "reg_or_0_operand" "0,dO,dO")
4615
                         (match_operand:QI 4 "reg_or_0_operand" "dO,0,dO")))
4616
   (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w"))]
4617
  "TARGET_HARD_FLOAT"
4618
  "#"
4619
  [(set_attr "length" "8,8,12")
4620
   (set_attr "type" "multi")])
4621
 
4622
(define_insn "*movqicc_internal2_int"
4623
  [(set (match_operand:QI 0 "integer_register_operand" "=d,d,d,d,d")
4624
        (if_then_else:QI (match_operator 1 "integer_relational_operator"
4625
                             [(match_operand 2 "icc_operand" "t,t,t,t,t")
4626
                              (const_int 0)])
4627
                         (match_operand:QI 3 "const_int_operand" "O,O,L,n,n")
4628
                         (match_operand:QI 4 "const_int_operand" "L,n,O,O,n")))
4629
   (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v"))]
4630
  "(INTVAL (operands[3]) == 0
4631
    || INTVAL (operands[4]) == 0
4632
    || (IN_RANGE (INTVAL (operands[3]), -2048, 2047)
4633
        && IN_RANGE (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
4634
  "#"
4635
  [(set_attr "length" "8,12,8,12,12")
4636
   (set_attr "type" "multi")])
4637
 
4638
(define_insn "*movqicc_internal2_float"
4639
  [(set (match_operand:QI 0 "integer_register_operand" "=d,d,d,d,d")
4640
        (if_then_else:QI (match_operator:CC_FP 1 "float_relational_operator"
4641
                             [(match_operand:CC_FP 2 "fcc_operand" "u,u,u,u,u")
4642
                              (const_int 0)])
4643
                         (match_operand:QI 3 "const_int_operand" "O,O,L,n,n")
4644
                         (match_operand:QI 4 "const_int_operand" "L,n,O,O,n")))
4645
   (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w,w,w"))]
4646
  "TARGET_HARD_FLOAT
4647
   && (INTVAL (operands[3]) == 0
4648
       || INTVAL (operands[4]) == 0
4649
       || (IN_RANGE (INTVAL (operands[3]), -2048, 2047)
4650
           && IN_RANGE (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
4651
  "#"
4652
  [(set_attr "length" "8,12,8,12,12")
4653
   (set_attr "type" "multi")])
4654
 
4655
(define_split
4656
  [(set (match_operand:QI 0 "integer_register_operand" "")
4657
        (if_then_else:QI (match_operator 1 "relational_operator"
4658
                             [(match_operand 2 "cc_operand" "")
4659
                              (const_int 0)])
4660
                         (match_operand:QI 3 "gpr_or_int_operand" "")
4661
                         (match_operand:QI 4 "gpr_or_int_operand" "")))
4662
   (clobber (match_operand:CC_CCR 5 "cr_operand" ""))]
4663
  "reload_completed"
4664
  [(match_dup 6)]
4665
  "operands[6] = frv_split_cond_move (operands);")
4666
 
4667
(define_expand "movhicc"
4668
  [(set (match_operand:HI 0 "integer_register_operand" "")
4669
        (if_then_else:HI (match_operand 1 "" "")
4670
                         (match_operand:HI 2 "gpr_or_int_operand" "")
4671
                         (match_operand:HI 3 "gpr_or_int_operand" "")))]
4672
  "TARGET_COND_MOVE"
4673
  "
4674
{
4675
  if (!frv_emit_cond_move (operands[0], operands[1], operands[2], operands[3]))
4676
    FAIL;
4677
 
4678
  DONE;
4679
}")
4680
 
4681
(define_insn "*movhicc_internal1_int"
4682
  [(set (match_operand:HI 0 "integer_register_operand" "=d,d,d")
4683
        (if_then_else:HI (match_operator 1 "integer_relational_operator"
4684
                             [(match_operand 2 "icc_operand" "t,t,t")
4685
                              (const_int 0)])
4686
                         (match_operand:HI 3 "reg_or_0_operand" "0,dO,dO")
4687
                         (match_operand:HI 4 "reg_or_0_operand" "dO,0,dO")))
4688
   (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v"))]
4689
  ""
4690
  "#"
4691
  [(set_attr "length" "8,8,12")
4692
   (set_attr "type" "multi")])
4693
 
4694
(define_insn "*movhicc_internal1_float"
4695
  [(set (match_operand:HI 0 "integer_register_operand" "=d,d,d")
4696
        (if_then_else:HI (match_operator:CC_FP 1 "float_relational_operator"
4697
                             [(match_operand:CC_FP 2 "fcc_operand" "u,u,u")
4698
                              (const_int 0)])
4699
                         (match_operand:HI 3 "reg_or_0_operand" "0,dO,dO")
4700
                         (match_operand:HI 4 "reg_or_0_operand" "dO,0,dO")))
4701
   (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w"))]
4702
  "TARGET_HARD_FLOAT"
4703
  "#"
4704
  [(set_attr "length" "8,8,12")
4705
   (set_attr "type" "multi")])
4706
 
4707
(define_insn "*movhicc_internal2_int"
4708
  [(set (match_operand:HI 0 "integer_register_operand" "=d,d,d,d,d")
4709
        (if_then_else:HI (match_operator 1 "integer_relational_operator"
4710
                             [(match_operand 2 "icc_operand" "t,t,t,t,t")
4711
                              (const_int 0)])
4712
                         (match_operand:HI 3 "const_int_operand" "O,O,L,n,n")
4713
                         (match_operand:HI 4 "const_int_operand" "L,n,O,O,n")))
4714
   (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v"))]
4715
  "(INTVAL (operands[3]) == 0
4716
    || INTVAL (operands[4]) == 0
4717
    || (IN_RANGE (INTVAL (operands[3]), -2048, 2047)
4718
        && IN_RANGE (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
4719
  "#"
4720
  [(set_attr "length" "8,12,8,12,12")
4721
   (set_attr "type" "multi")])
4722
 
4723
(define_insn "*movhicc_internal2_float"
4724
  [(set (match_operand:HI 0 "integer_register_operand" "=d,d,d,d,d")
4725
        (if_then_else:HI (match_operator:CC_FP 1 "float_relational_operator"
4726
                             [(match_operand:CC_FP 2 "fcc_operand" "u,u,u,u,u")
4727
                              (const_int 0)])
4728
                         (match_operand:HI 3 "const_int_operand" "O,O,L,n,n")
4729
                         (match_operand:HI 4 "const_int_operand" "L,n,O,O,n")))
4730
   (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w,w,w"))]
4731
  "TARGET_HARD_FLOAT
4732
   && (INTVAL (operands[3]) == 0
4733
       || INTVAL (operands[4]) == 0
4734
       || (IN_RANGE (INTVAL (operands[3]), -2048, 2047)
4735
           && IN_RANGE (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
4736
  "#"
4737
  [(set_attr "length" "8,12,8,12,12")
4738
   (set_attr "type" "multi")])
4739
 
4740
(define_split
4741
  [(set (match_operand:HI 0 "integer_register_operand" "")
4742
        (if_then_else:HI (match_operator 1 "relational_operator"
4743
                             [(match_operand 2 "cc_operand" "")
4744
                              (const_int 0)])
4745
                         (match_operand:HI 3 "gpr_or_int_operand" "")
4746
                         (match_operand:HI 4 "gpr_or_int_operand" "")))
4747
   (clobber (match_operand:CC_CCR 5 "cr_operand" ""))]
4748
  "reload_completed"
4749
  [(match_dup 6)]
4750
  "operands[6] = frv_split_cond_move (operands);")
4751
 
4752
(define_expand "movsicc"
4753
  [(set (match_operand:SI 0 "integer_register_operand" "")
4754
        (if_then_else:SI (match_operand 1 "" "")
4755
                         (match_operand:SI 2 "gpr_or_int_operand" "")
4756
                         (match_operand:SI 3 "gpr_or_int_operand" "")))]
4757
  "TARGET_COND_MOVE"
4758
  "
4759
{
4760
  if (!frv_emit_cond_move (operands[0], operands[1], operands[2], operands[3]))
4761
    FAIL;
4762
 
4763
  DONE;
4764
}")
4765
 
4766
(define_insn "*movsicc_internal1_int"
4767
  [(set (match_operand:SI 0 "integer_register_operand" "=d,d,d")
4768
        (if_then_else:SI (match_operator 1 "integer_relational_operator"
4769
                             [(match_operand 2 "icc_operand" "t,t,t")
4770
                              (const_int 0)])
4771
                         (match_operand:SI 3 "reg_or_0_operand" "0,dO,dO")
4772
                         (match_operand:SI 4 "reg_or_0_operand" "dO,0,dO")))
4773
   (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v"))]
4774
  ""
4775
  "#"
4776
  [(set_attr "length" "8,8,12")
4777
   (set_attr "type" "multi")])
4778
 
4779
(define_insn "*movsicc_internal1_float"
4780
  [(set (match_operand:SI 0 "integer_register_operand" "=d,d,d")
4781
        (if_then_else:SI (match_operator:CC_FP 1 "float_relational_operator"
4782
                             [(match_operand:CC_FP 2 "fcc_operand" "u,u,u")
4783
                              (const_int 0)])
4784
                         (match_operand:SI 3 "reg_or_0_operand" "0,dO,dO")
4785
                         (match_operand:SI 4 "reg_or_0_operand" "dO,0,dO")))
4786
   (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w"))]
4787
  "TARGET_HARD_FLOAT"
4788
  "#"
4789
  [(set_attr "length" "8,8,12")
4790
   (set_attr "type" "multi")])
4791
 
4792
(define_insn "*movsicc_internal2_int"
4793
  [(set (match_operand:SI 0 "integer_register_operand" "=d,d,d,d,d")
4794
        (if_then_else:SI (match_operator 1 "integer_relational_operator"
4795
                             [(match_operand 2 "icc_operand" "t,t,t,t,t")
4796
                              (const_int 0)])
4797
                         (match_operand:SI 3 "const_int_operand" "O,O,L,n,n")
4798
                         (match_operand:SI 4 "const_int_operand" "L,n,O,O,n")))
4799
   (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v"))]
4800
  "(INTVAL (operands[3]) == 0
4801
    || INTVAL (operands[4]) == 0
4802
    || (IN_RANGE (INTVAL (operands[3]), -2048, 2047)
4803
        && IN_RANGE (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
4804
  "#"
4805
  [(set_attr "length" "8,12,8,12,12")
4806
   (set_attr "type" "multi")])
4807
 
4808
(define_insn "*movsicc_internal2_float"
4809
  [(set (match_operand:SI 0 "integer_register_operand" "=d,d,d,d,d")
4810
        (if_then_else:SI (match_operator:CC_FP 1 "float_relational_operator"
4811
                             [(match_operand:CC_FP 2 "fcc_operand" "u,u,u,u,u")
4812
                              (const_int 0)])
4813
                         (match_operand:SI 3 "const_int_operand" "O,O,L,n,n")
4814
                         (match_operand:SI 4 "const_int_operand" "L,n,O,O,n")))
4815
   (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w,w,w"))]
4816
  "TARGET_HARD_FLOAT
4817
   && (INTVAL (operands[3]) == 0
4818
       || INTVAL (operands[4]) == 0
4819
       || (IN_RANGE (INTVAL (operands[3]), -2048, 2047)
4820
           && IN_RANGE (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
4821
  "#"
4822
  [(set_attr "length" "8,12,8,12,12")
4823
   (set_attr "type" "multi")])
4824
 
4825
(define_split
4826
  [(set (match_operand:SI 0 "integer_register_operand" "")
4827
        (if_then_else:SI (match_operator 1 "relational_operator"
4828
                             [(match_operand 2 "cc_operand" "")
4829
                              (const_int 0)])
4830
                         (match_operand:SI 3 "gpr_or_int_operand" "")
4831
                         (match_operand:SI 4 "gpr_or_int_operand" "")))
4832
   (clobber (match_operand:CC_CCR 5 "cr_operand" ""))]
4833
  "reload_completed"
4834
  [(match_dup 6)]
4835
  "operands[6] = frv_split_cond_move (operands);")
4836
 
4837
(define_expand "movsfcc"
4838
  [(set (match_operand:SF 0 "register_operand" "")
4839
        (if_then_else:SF (match_operand 1 "" "")
4840
                         (match_operand:SF 2 "register_operand" "")
4841
                         (match_operand:SF 3 "register_operand" "")))]
4842
  "TARGET_COND_MOVE"
4843
  "
4844
{
4845
  if (!frv_emit_cond_move (operands[0], operands[1], operands[2], operands[3]))
4846
    FAIL;
4847
 
4848
  DONE;
4849
}")
4850
 
4851
(define_insn "*movsfcc_has_fprs_int"
4852
  [(set (match_operand:SF 0 "register_operand" "=f,f,f,?f,?f,?d")
4853
        (if_then_else:SF (match_operator 1 "integer_relational_operator"
4854
                             [(match_operand 2 "icc_operand" "t,t,t,t,t,t")
4855
                              (const_int 0)])
4856
                         (match_operand:SF 3 "register_operand" "0,f,f,f,d,fd")
4857
                         (match_operand:SF 4 "register_operand" "f,0,f,d,fd,fd")))
4858
   (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v,v"))]
4859
  "TARGET_HAS_FPRS"
4860
  "#"
4861
  [(set_attr "length" "8,8,12,12,12,12")
4862
   (set_attr "type" "multi")])
4863
 
4864
(define_insn "*movsfcc_hardfloat_float"
4865
  [(set (match_operand:SF 0 "register_operand" "=f,f,f,?f,?f,?d")
4866
        (if_then_else:SF (match_operator:CC_FP 1 "float_relational_operator"
4867
                             [(match_operand:CC_FP 2 "fcc_operand" "u,u,u,u,u,u")
4868
                              (const_int 0)])
4869
                         (match_operand:SF 3 "register_operand" "0,f,f,f,d,fd")
4870
                         (match_operand:SF 4 "register_operand" "f,0,f,d,fd,fd")))
4871
   (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w,w,w,w"))]
4872
  "TARGET_HARD_FLOAT"
4873
  "#"
4874
  [(set_attr "length" "8,8,12,12,12,12")
4875
   (set_attr "type" "multi")])
4876
 
4877
(define_insn "*movsfcc_no_fprs_int"
4878
  [(set (match_operand:SF 0 "integer_register_operand" "=d,d,d")
4879
        (if_then_else:SF (match_operator 1 "integer_relational_operator"
4880
                             [(match_operand 2 "icc_operand" "t,t,t")
4881
                              (const_int 0)])
4882
                         (match_operand:SF 3 "integer_register_operand" "0,d,d")
4883
                         (match_operand:SF 4 "integer_register_operand" "d,0,d")))
4884
   (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v"))]
4885
  "! TARGET_HAS_FPRS"
4886
  "#"
4887
  [(set_attr "length" "8,8,12")
4888
   (set_attr "type" "multi")])
4889
 
4890
(define_split
4891
  [(set (match_operand:SF 0 "register_operand" "")
4892
        (if_then_else:SF (match_operator 1 "relational_operator"
4893
                             [(match_operand 2 "cc_operand" "")
4894
                              (const_int 0)])
4895
                         (match_operand:SF 3 "register_operand" "")
4896
                         (match_operand:SF 4 "register_operand" "")))
4897
   (clobber (match_operand:CC_CCR 5 "cr_operand" ""))]
4898
  "reload_completed"
4899
  [(match_dup 6)]
4900
  "operands[6] = frv_split_cond_move (operands);")
4901
 
4902
 
4903
;; ::::::::::::::::::::
4904
;; ::
4905
;; :: Minimum, maximum, and integer absolute value
4906
;; ::
4907
;; ::::::::::::::::::::
4908
 
4909
;; These 'instructions' are provided to give the compiler a slightly better
4910
;; nudge at register allocation, then it would if it constructed the
4911
;; instructions from basic building blocks (since it indicates it prefers one
4912
;; of the operands to be the same as the destination.  It also helps the
4913
;; earlier passes of the compiler, by not breaking things into small basic
4914
;; blocks.
4915
 
4916
(define_expand "abssi2"
4917
  [(parallel [(set (match_operand:SI 0 "integer_register_operand" "")
4918
                   (abs:SI (match_operand:SI 1 "integer_register_operand" "")))
4919
              (clobber (match_dup 2))
4920
              (clobber (match_dup 3))])]
4921
  "TARGET_COND_MOVE"
4922
  "
4923
{
4924
  operands[2] = gen_reg_rtx (CCmode);
4925
  operands[3] = gen_reg_rtx (CC_CCRmode);
4926
}")
4927
 
4928
(define_insn_and_split "*abssi2_internal"
4929
  [(set (match_operand:SI 0 "integer_register_operand" "=d,d")
4930
        (abs:SI (match_operand:SI 1 "integer_register_operand" "0,d")))
4931
   (clobber (match_operand:CC 2 "icc_operand" "=t,t"))
4932
   (clobber (match_operand:CC_CCR 3 "icr_operand" "=v,v"))]
4933
  "TARGET_COND_MOVE"
4934
  "#"
4935
  "reload_completed"
4936
  [(match_dup 4)]
4937
  "operands[4] = frv_split_abs (operands);"
4938
  [(set_attr "length" "12,16")
4939
   (set_attr "type" "multi")])
4940
 
4941
(define_expand "sminsi3"
4942
  [(parallel [(set (match_operand:SI 0 "integer_register_operand" "")
4943
                   (smin:SI (match_operand:SI 1 "integer_register_operand" "")
4944
                            (match_operand:SI 2 "gpr_or_int10_operand" "")))
4945
              (clobber (match_dup 3))
4946
              (clobber (match_dup 4))])]
4947
  "TARGET_COND_MOVE"
4948
  "
4949
{
4950
  operands[3] = gen_reg_rtx (CCmode);
4951
  operands[4] = gen_reg_rtx (CC_CCRmode);
4952
}")
4953
 
4954
(define_expand "smaxsi3"
4955
  [(parallel [(set (match_operand:SI 0 "integer_register_operand" "")
4956
                   (smax:SI (match_operand:SI 1 "integer_register_operand" "")
4957
                            (match_operand:SI 2 "gpr_or_int10_operand" "")))
4958
              (clobber (match_dup 3))
4959
              (clobber (match_dup 4))])]
4960
  "TARGET_COND_MOVE"
4961
  "
4962
{
4963
  operands[3] = gen_reg_rtx (CCmode);
4964
  operands[4] = gen_reg_rtx (CC_CCRmode);
4965
}")
4966
 
4967
(define_insn_and_split "*minmax_si_signed"
4968
  [(set (match_operand:SI 0 "integer_register_operand" "=d,d,&d")
4969
        (match_operator:SI 1 "minmax_operator"
4970
                           [(match_operand:SI 2 "integer_register_operand" "%0,dO,d")
4971
                            (match_operand:SI 3 "gpr_or_int10_operand" "dO,0,dJ")]))
4972
   (clobber (match_operand:CC 4 "icc_operand" "=t,t,t"))
4973
   (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v"))]
4974
  "TARGET_COND_MOVE"
4975
  "#"
4976
  "reload_completed"
4977
  [(match_dup 6)]
4978
  "operands[6] = frv_split_minmax (operands);"
4979
  [(set_attr "length" "12,12,16")
4980
   (set_attr "type" "multi")])
4981
 
4982
(define_expand "uminsi3"
4983
  [(parallel [(set (match_operand:SI 0 "integer_register_operand" "")
4984
                   (umin:SI (match_operand:SI 1 "integer_register_operand" "")
4985
                            (match_operand:SI 2 "gpr_or_int10_operand" "")))
4986
              (clobber (match_dup 3))
4987
              (clobber (match_dup 4))])]
4988
  "TARGET_COND_MOVE"
4989
  "
4990
{
4991
  operands[3] = gen_reg_rtx (CC_UNSmode);
4992
  operands[4] = gen_reg_rtx (CC_CCRmode);
4993
}")
4994
 
4995
(define_expand "umaxsi3"
4996
  [(parallel [(set (match_operand:SI 0 "integer_register_operand" "")
4997
                   (umax:SI (match_operand:SI 1 "integer_register_operand" "")
4998
                            (match_operand:SI 2 "gpr_or_int10_operand" "")))
4999
              (clobber (match_dup 3))
5000
              (clobber (match_dup 4))])]
5001
  "TARGET_COND_MOVE"
5002
  "
5003
{
5004
  operands[3] = gen_reg_rtx (CC_UNSmode);
5005
  operands[4] = gen_reg_rtx (CC_CCRmode);
5006
}")
5007
 
5008
(define_insn_and_split "*minmax_si_unsigned"
5009
  [(set (match_operand:SI 0 "integer_register_operand" "=d,d,&d")
5010
        (match_operator:SI 1 "minmax_operator"
5011
                           [(match_operand:SI 2 "integer_register_operand" "%0,dO,d")
5012
                            (match_operand:SI 3 "gpr_or_int10_operand" "dO,0,dJ")]))
5013
   (clobber (match_operand:CC_UNS 4 "icc_operand" "=t,t,t"))
5014
   (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v"))]
5015
  "TARGET_COND_MOVE"
5016
  "#"
5017
  "reload_completed"
5018
  [(match_dup 6)]
5019
  "operands[6] = frv_split_minmax (operands);"
5020
  [(set_attr "length" "12,12,16")
5021
   (set_attr "type" "multi")])
5022
 
5023
(define_expand "sminsf3"
5024
  [(parallel [(set (match_operand:SF 0 "fpr_operand" "")
5025
                   (smin:SF (match_operand:SF 1 "fpr_operand" "")
5026
                            (match_operand:SF 2 "fpr_operand" "")))
5027
              (clobber (match_dup 3))
5028
              (clobber (match_dup 4))])]
5029
  "TARGET_COND_MOVE && TARGET_HARD_FLOAT"
5030
  "
5031
{
5032
  operands[3] = gen_reg_rtx (CC_FPmode);
5033
  operands[4] = gen_reg_rtx (CC_CCRmode);
5034
}")
5035
 
5036
(define_expand "smaxsf3"
5037
  [(parallel [(set (match_operand:SF 0 "fpr_operand" "")
5038
                   (smax:SF (match_operand:SF 1 "fpr_operand" "")
5039
                            (match_operand:SF 2 "fpr_operand" "")))
5040
              (clobber (match_dup 3))
5041
              (clobber (match_dup 4))])]
5042
  "TARGET_COND_MOVE && TARGET_HARD_FLOAT"
5043
  "
5044
{
5045
  operands[3] = gen_reg_rtx (CC_FPmode);
5046
  operands[4] = gen_reg_rtx (CC_CCRmode);
5047
}")
5048
 
5049
(define_insn_and_split "*minmax_sf"
5050
  [(set (match_operand:SF 0 "fpr_operand" "=f,f,f")
5051
        (match_operator:SF 1 "minmax_operator"
5052
                           [(match_operand:SF 2 "fpr_operand" "%0,f,f")
5053
                            (match_operand:SF 3 "fpr_operand" "f,0,f")]))
5054
   (clobber (match_operand:CC_FP 4 "fcc_operand" "=u,u,u"))
5055
   (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w"))]
5056
  "TARGET_COND_MOVE && TARGET_HARD_FLOAT"
5057
  "#"
5058
  "reload_completed"
5059
  [(match_dup 6)]
5060
  "operands[6] = frv_split_minmax (operands);"
5061
  [(set_attr "length" "12,12,16")
5062
   (set_attr "type" "multi")])
5063
 
5064
(define_expand "smindf3"
5065
  [(parallel [(set (match_operand:DF 0 "fpr_operand" "")
5066
                   (smin:DF (match_operand:DF 1 "fpr_operand" "")
5067
                            (match_operand:DF 2 "fpr_operand" "")))
5068
              (clobber (match_dup 3))
5069
              (clobber (match_dup 4))])]
5070
  "TARGET_COND_MOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE"
5071
  "
5072
{
5073
  operands[3] = gen_reg_rtx (CC_FPmode);
5074
  operands[4] = gen_reg_rtx (CC_CCRmode);
5075
}")
5076
 
5077
(define_expand "smaxdf3"
5078
  [(parallel [(set (match_operand:DF 0 "fpr_operand" "")
5079
                   (smax:DF (match_operand:DF 1 "fpr_operand" "")
5080
                            (match_operand:DF 2 "fpr_operand" "")))
5081
              (clobber (match_dup 3))
5082
              (clobber (match_dup 4))])]
5083
  "TARGET_COND_MOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE"
5084
  "
5085
{
5086
  operands[3] = gen_reg_rtx (CC_FPmode);
5087
  operands[4] = gen_reg_rtx (CC_CCRmode);
5088
}")
5089
 
5090
(define_insn_and_split "*minmax_df"
5091
  [(set (match_operand:DF 0 "fpr_operand" "=f,f,f")
5092
        (match_operator:DF 1 "minmax_operator"
5093
                           [(match_operand:DF 2 "fpr_operand" "%0,f,f")
5094
                            (match_operand:DF 3 "fpr_operand" "f,0,f")]))
5095
   (clobber (match_operand:CC_FP 4 "fcc_operand" "=u,u,u"))
5096
   (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w"))]
5097
  "TARGET_COND_MOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE"
5098
  "#"
5099
  "reload_completed"
5100
  [(match_dup 6)]
5101
  "operands[6] = frv_split_minmax (operands);"
5102
  [(set_attr "length" "12,12,16")
5103
   (set_attr "type" "multi")])
5104
 
5105
 
5106
;; ::::::::::::::::::::
5107
;; ::
5108
;; :: Call and branch instructions
5109
;; ::
5110
;; ::::::::::::::::::::
5111
 
5112
;; Subroutine call instruction returning no value.  Operand 0 is the function
5113
;; to call; operand 1 is the number of bytes of arguments pushed (in mode
5114
;; `SImode', except it is normally a `const_int'); operand 2 is the number of
5115
;; registers used as operands.
5116
 
5117
;; On most machines, operand 2 is not actually stored into the RTL pattern.  It
5118
;; is supplied for the sake of some RISC machines which need to put this
5119
;; information into the assembler code; they can put it in the RTL instead of
5120
;; operand 1.
5121
 
5122
(define_expand "call"
5123
  [(use (match_operand:QI 0 "" ""))
5124
   (use (match_operand 1 "" ""))
5125
   (use (match_operand 2 "" ""))
5126
   (use (match_operand 3 "" ""))]
5127
  ""
5128
  "
5129
{
5130
  rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
5131
  rtx addr;
5132
 
5133
  gcc_assert (GET_CODE (operands[0]) == MEM);
5134
 
5135
  addr = XEXP (operands[0], 0);
5136
  if (! call_operand (addr, Pmode))
5137
    addr = force_reg (Pmode, addr);
5138
 
5139
  if (! operands[2])
5140
    operands[2] = const0_rtx;
5141
 
5142
  if (TARGET_FDPIC)
5143
    frv_expand_fdpic_call (operands, false, false);
5144
  else
5145
    emit_call_insn (gen_call_internal (addr, operands[1], operands[2], lr));
5146
 
5147
  DONE;
5148
}")
5149
 
5150
(define_insn "call_internal"
5151
  [(call (mem:QI (match_operand:SI 0 "call_operand" "S,dNOP"))
5152
         (match_operand 1 "" ""))
5153
   (use (match_operand 2 "" ""))
5154
   (clobber (match_operand:SI 3 "lr_operand" "=l,l"))]
5155
  "! TARGET_FDPIC"
5156
  "@
5157
   call %0
5158
   call%i0l %M0"
5159
  [(set_attr "length" "4")
5160
   (set_attr "type" "call,jumpl")])
5161
 
5162
;; The odd use of GR0 within the UNSPEC below prevents cseing or
5163
;; hoisting function descriptor loads out of loops.  This is almost
5164
;; never desirable, since if we preserve the function descriptor in a
5165
;; pair of registers, it takes two insns to move it to gr14/gr15, and
5166
;; if it's in the stack, we just waste space with the store, since
5167
;; we'll have to load back from memory anyway.  And, in the worst
5168
;; case, we may end up reusing a function descriptor still pointing at
5169
;; a PLT entry, instead of to the resolved function, which means going
5170
;; through the resolver for every call that uses the outdated value.
5171
;; Bad!
5172
 
5173
;; The explicit MEM inside the SPEC prevents the compiler from moving
5174
;; the load before a branch after a NULL test, or before a store that
5175
;; initializes a function descriptor.
5176
 
5177
(define_insn "movdi_ldd"
5178
  [(set (match_operand:DI 0 "fdpic_fptr_operand" "=e")
5179
        (unspec:DI [(mem:DI (match_operand:SI 1 "ldd_address_operand" "p"))
5180
                    (reg:SI 0)] UNSPEC_LDD))]
5181
  ""
5182
  "ldd%I1 %M1, %0"
5183
  [(set_attr "length" "4")
5184
   (set_attr "type" "gload")])
5185
 
5186
(define_insn "call_fdpicdi"
5187
  [(call (mem:QI (match_operand:DI 0 "fdpic_fptr_operand" "W"))
5188
         (match_operand 1 "" ""))
5189
   (clobber (match_operand:SI 2 "lr_operand" "=l"))]
5190
  "TARGET_FDPIC"
5191
  "call%i0l %M0"
5192
  [(set_attr "length" "4")
5193
   (set_attr "type" "jumpl")])
5194
 
5195
(define_insn "call_fdpicsi"
5196
  [(call (mem:QI (match_operand:SI 0 "call_operand" "S,dNOP"))
5197
         (match_operand 1 "" ""))
5198
   (use (match_operand 2 "" ""))
5199
   (use (match_operand:SI 3 "fdpic_operand" "Z,Z"))
5200
   (clobber (match_operand:SI 4 "lr_operand" "=l,l"))]
5201
  "TARGET_FDPIC"
5202
  "@
5203
   call %0
5204
   call%i0l %M0"
5205
  [(set_attr "length" "4")
5206
   (set_attr "type" "call,jumpl")])
5207
 
5208
(define_expand "sibcall"
5209
  [(use (match_operand:QI 0 "" ""))
5210
   (use (match_operand 1 "" ""))
5211
   (use (match_operand 2 "" ""))
5212
   (use (match_operand 3 "" ""))]
5213
  ""
5214
  "
5215
{
5216
  rtx addr;
5217
 
5218
  gcc_assert (GET_CODE (operands[0]) == MEM);
5219
 
5220
  addr = XEXP (operands[0], 0);
5221
  if (! sibcall_operand (addr, Pmode))
5222
    addr = force_reg (Pmode, addr);
5223
 
5224
  if (! operands[2])
5225
    operands[2] = const0_rtx;
5226
 
5227
  if (TARGET_FDPIC)
5228
    frv_expand_fdpic_call (operands, false, true);
5229
  else
5230
    emit_call_insn (gen_sibcall_internal (addr, operands[1], operands[2]));
5231
 
5232
  DONE;
5233
}")
5234
 
5235
;; It might seem that these sibcall patterns are missing references to
5236
;; LR, but they're not necessary because sibcall_epilogue will make
5237
;; sure LR is restored, and having LR here will set
5238
;; regs_ever_used[REG_LR], forcing it to be saved on the stack, and
5239
;; then restored in sibcalls and regular return code paths, even if
5240
;; the function becomes a leaf function after tail-call elimination.
5241
 
5242
;; We must not use a call-saved register here.  `W' limits ourselves
5243
;; to gr14 or gr15, but since we're almost running out of constraint
5244
;; letters, and most other call-clobbered registers are often used for
5245
;; argument-passing, this will do.
5246
(define_insn "sibcall_internal"
5247
  [(call (mem:QI (match_operand:SI 0 "sibcall_operand" "WNOP"))
5248
         (match_operand 1 "" ""))
5249
   (use (match_operand 2 "" ""))
5250
   (return)]
5251
  "! TARGET_FDPIC"
5252
  "jmp%i0l %M0"
5253
  [(set_attr "length" "4")
5254
   (set_attr "type" "jumpl")])
5255
 
5256
(define_insn "sibcall_fdpicdi"
5257
  [(call (mem:QI (match_operand:DI 0 "fdpic_fptr_operand" "W"))
5258
         (match_operand 1 "" ""))
5259
   (return)]
5260
  "TARGET_FDPIC"
5261
  "jmp%i0l %M0"
5262
  [(set_attr "length" "4")
5263
   (set_attr "type" "jumpl")])
5264
 
5265
 
5266
;; Subroutine call instruction returning a value.  Operand 0 is the hard
5267
;; register in which the value is returned.  There are three more operands, the
5268
;; same as the three operands of the `call' instruction (but with numbers
5269
;; increased by one).
5270
 
5271
;; Subroutines that return `BLKmode' objects use the `call' insn.
5272
 
5273
(define_expand "call_value"
5274
  [(use (match_operand 0 "" ""))
5275
   (use (match_operand:QI 1 "" ""))
5276
   (use (match_operand 2 "" ""))
5277
   (use (match_operand 3 "" ""))
5278
   (use (match_operand 4 "" ""))]
5279
  ""
5280
  "
5281
{
5282
  rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
5283
  rtx addr;
5284
 
5285
  gcc_assert (GET_CODE (operands[1]) == MEM);
5286
 
5287
  addr = XEXP (operands[1], 0);
5288
  if (! call_operand (addr, Pmode))
5289
    addr = force_reg (Pmode, addr);
5290
 
5291
  if (! operands[3])
5292
    operands[3] = const0_rtx;
5293
 
5294
  if (TARGET_FDPIC)
5295
    frv_expand_fdpic_call (operands, true, false);
5296
  else
5297
    emit_call_insn (gen_call_value_internal (operands[0], addr, operands[2],
5298
                                             operands[3], lr));
5299
 
5300
  DONE;
5301
}")
5302
 
5303
(define_insn "call_value_internal"
5304
  [(set (match_operand 0 "register_operand" "=d,d")
5305
        (call (mem:QI (match_operand:SI 1 "call_operand" "S,dNOP"))
5306
                      (match_operand 2 "" "")))
5307
   (use (match_operand 3 "" ""))
5308
   (clobber (match_operand:SI 4 "lr_operand" "=l,l"))]
5309
  "! TARGET_FDPIC"
5310
  "@
5311
   call %1
5312
   call%i1l %M1"
5313
  [(set_attr "length" "4")
5314
   (set_attr "type" "call,jumpl")])
5315
 
5316
(define_insn "call_value_fdpicdi"
5317
  [(set (match_operand 0 "register_operand" "=d")
5318
        (call (mem:QI (match_operand:DI 1 "fdpic_fptr_operand" "W"))
5319
              (match_operand 2 "" "")))
5320
   (clobber (match_operand:SI 3 "lr_operand" "=l"))]
5321
  "TARGET_FDPIC"
5322
  "call%i1l %M1"
5323
  [(set_attr "length" "4")
5324
   (set_attr "type" "jumpl")])
5325
 
5326
(define_insn "call_value_fdpicsi"
5327
  [(set (match_operand 0 "register_operand" "=d,d")
5328
        (call (mem:QI (match_operand:SI 1 "call_operand" "S,dNOP"))
5329
                      (match_operand 2 "" "")))
5330
   (use (match_operand 3 "" ""))
5331
   (use (match_operand:SI 4 "fdpic_operand" "Z,Z"))
5332
   (clobber (match_operand:SI 5 "lr_operand" "=l,l"))]
5333
  "TARGET_FDPIC"
5334
  "@
5335
   call %1
5336
   call%i1l %M1"
5337
  [(set_attr "length" "4")
5338
   (set_attr "type" "call,jumpl")])
5339
 
5340
(define_expand "sibcall_value"
5341
  [(use (match_operand 0 "" ""))
5342
   (use (match_operand:QI 1 "" ""))
5343
   (use (match_operand 2 "" ""))
5344
   (use (match_operand 3 "" ""))
5345
   (use (match_operand 4 "" ""))]
5346
  ""
5347
  "
5348
{
5349
  rtx addr;
5350
 
5351
  gcc_assert (GET_CODE (operands[1]) == MEM);
5352
 
5353
  addr = XEXP (operands[1], 0);
5354
  if (! sibcall_operand (addr, Pmode))
5355
    addr = force_reg (Pmode, addr);
5356
 
5357
  if (! operands[3])
5358
    operands[3] = const0_rtx;
5359
 
5360
  if (TARGET_FDPIC)
5361
    frv_expand_fdpic_call (operands, true, true);
5362
  else
5363
    emit_call_insn (gen_sibcall_value_internal (operands[0], addr, operands[2],
5364
                                                operands[3]));
5365
  DONE;
5366
}")
5367
 
5368
(define_insn "sibcall_value_internal"
5369
  [(set (match_operand 0 "register_operand" "=d")
5370
        (call (mem:QI (match_operand:SI 1 "sibcall_operand" "WNOP"))
5371
                      (match_operand 2 "" "")))
5372
   (use (match_operand 3 "" ""))
5373
   (return)]
5374
  "! TARGET_FDPIC"
5375
  "jmp%i1l %M1"
5376
  [(set_attr "length" "4")
5377
   (set_attr "type" "jumpl")])
5378
 
5379
(define_insn "sibcall_value_fdpicdi"
5380
  [(set (match_operand 0 "register_operand" "=d")
5381
        (call (mem:QI (match_operand:DI 1 "fdpic_fptr_operand" "W"))
5382
              (match_operand 2 "" "")))
5383
   (return)]
5384
  "TARGET_FDPIC"
5385
  "jmp%i1l %M1"
5386
  [(set_attr "length" "4")
5387
   (set_attr "type" "jumpl")])
5388
 
5389
;; return instruction generated instead of jmp to epilog
5390
(define_expand "return"
5391
  [(parallel [(return)
5392
              (use (match_dup 0))
5393
              (use (const_int 1))])]
5394
  "direct_return_p ()"
5395
  "
5396
{
5397
  operands[0] = gen_rtx_REG (Pmode, LR_REGNO);
5398
}")
5399
 
5400
;; return instruction generated by the epilogue
5401
(define_expand "epilogue_return"
5402
  [(parallel [(return)
5403
              (use (match_operand:SI 0 "register_operand" ""))
5404
              (use (const_int 0))])]
5405
  ""
5406
  "")
5407
 
5408
(define_insn "*return_internal"
5409
  [(return)
5410
   (use (match_operand:SI 0 "register_operand" "l,d"))
5411
   (use (match_operand:SI 1 "immediate_operand" "n,n"))]
5412
  ""
5413
  "@
5414
    ret
5415
    jmpl @(%0,%.)"
5416
  [(set_attr "length" "4")
5417
   (set_attr "type" "jump,jumpl")])
5418
 
5419
(define_insn "*return_true"
5420
  [(set (pc)
5421
        (if_then_else (match_operator 0 "integer_relational_operator"
5422
                                      [(match_operand 1 "icc_operand" "t")
5423
                                       (const_int 0)])
5424
                      (return)
5425
                      (pc)))]
5426
  "direct_return_p ()"
5427
  "b%c0lr %1,%#"
5428
  [(set_attr "length" "4")
5429
   (set_attr "type" "jump")])
5430
 
5431
(define_insn "*return_false"
5432
  [(set (pc)
5433
        (if_then_else (match_operator 0 "integer_relational_operator"
5434
                                      [(match_operand 1 "icc_operand" "t")
5435
                                       (const_int 0)])
5436
                      (pc)
5437
                      (return)))]
5438
  "direct_return_p ()"
5439
  "b%C0lr %1,%#"
5440
  [(set_attr "length" "4")
5441
   (set_attr "type" "jump")])
5442
 
5443
;; A version of addsi3 for deallocating stack space at the end of the
5444
;; epilogue.  The addition is done in parallel with an (unspec_volatile),
5445
;; which represents the clobbering of the deallocated space.
5446
(define_insn "stack_adjust"
5447
  [(set (match_operand:SI 0 "register_operand" "=d")
5448
        (plus:SI (match_operand:SI 1 "register_operand" "d")
5449
                 (match_operand:SI 2 "general_operand" "dNOP")))
5450
   (unspec_volatile [(const_int 0)] UNSPEC_STACK_ADJUST)]
5451
  ""
5452
  "add%I2 %1,%2,%0"
5453
  [(set_attr "length" "4")
5454
   (set_attr "type" "int")])
5455
 
5456
;; Normal unconditional jump
5457
 
5458
;; Use the "call" instruction for long branches, but prefer to use "bra" for
5459
;; short ones since it does not force us to save the link register.
5460
 
5461
;; This define_insn uses the branch-shortening code to decide which
5462
;; instruction it emits.  Since the main branch-shortening interface is
5463
;; through get_attr_length(), the two alternatives must be given different
5464
;; lengths.  Here we pretend that the far jump is 8 rather than 4 bytes
5465
;; long, though both alternatives are really the same size.
5466
(define_insn "jump"
5467
  [(set (pc) (label_ref (match_operand 0 "" "")))]
5468
  ""
5469
  "*
5470
{
5471
  if (get_attr_length (insn) == 4)
5472
    return \"bra %l0\";
5473
  else
5474
    return \"call %l0\";
5475
}"
5476
  [(set (attr "length")
5477
        (if_then_else
5478
            (and (ge (minus (match_dup 0) (pc)) (const_int -32768))
5479
                 (le (minus (match_dup 0) (pc)) (const_int 32764)))
5480
            (const_int 4)
5481
            (const_int 8)))
5482
   (set (attr "far_jump")
5483
        (if_then_else
5484
            (eq_attr "length" "4")
5485
            (const_string "no")
5486
            (const_string "yes")))
5487
   (set (attr "type")
5488
        (if_then_else
5489
            (eq_attr "length" "4")
5490
            (const_string "jump")
5491
            (const_string "call")))])
5492
 
5493
;; Indirect jump through a register
5494
(define_insn "indirect_jump"
5495
  [(set (pc) (match_operand:SI 0 "register_operand" "d,l"))]
5496
  ""
5497
  "@
5498
   jmpl @(%0,%.)
5499
   bralr"
5500
  [(set_attr "length" "4")
5501
   (set_attr "type" "jumpl,branch")])
5502
 
5503
;; Instruction to jump to a variable address.  This is a low-level capability
5504
;; which can be used to implement a dispatch table when there is no `casesi'
5505
;; pattern.  Either the 'casesi' pattern or the 'tablejump' pattern, or both,
5506
;; MUST be present in this file.
5507
 
5508
;; This pattern requires two operands: the address or offset, and a label which
5509
;; should immediately precede the jump table.  If the macro
5510
;; `CASE_VECTOR_PC_RELATIVE' is defined then the first operand is an offset
5511
;; which counts from the address of the table; otherwise, it is an absolute
5512
;; address to jump to.  In either case, the first operand has mode `Pmode'.
5513
 
5514
;; The `tablejump' insn is always the last insn before the jump table it uses.
5515
;; Its assembler code normally has no need to use the second operand, but you
5516
;; should incorporate it in the RTL pattern so that the jump optimizer will not
5517
;; delete the table as unreachable code.
5518
 
5519
(define_expand "tablejump"
5520
  [(parallel [(set (pc) (match_operand:SI 0 "address_operand" "p"))
5521
              (use (label_ref (match_operand 1 "" "")))])]
5522
  "!flag_pic"
5523
  "")
5524
 
5525
(define_insn "tablejump_insn"
5526
  [(set (pc) (match_operand:SI 0 "address_operand" "p"))
5527
   (use (label_ref (match_operand 1 "" "")))]
5528
  ""
5529
  "jmp%I0l %M0"
5530
  [(set_attr "length" "4")
5531
   (set_attr "type" "jumpl")])
5532
 
5533
;; Implement switch statements when generating PIC code.  Switches are
5534
;; implemented by `tablejump' when not using -fpic.
5535
 
5536
;; Emit code here to do the range checking and make the index zero based.
5537
;; operand 0 is the index
5538
;; operand 1 is the lower bound
5539
;; operand 2 is the range of indices (highest - lowest + 1)
5540
;; operand 3 is the label that precedes the table itself
5541
;; operand 4 is the fall through label
5542
 
5543
(define_expand "casesi"
5544
  [(use (match_operand:SI 0 "integer_register_operand" ""))
5545
   (use (match_operand:SI 1 "const_int_operand" ""))
5546
   (use (match_operand:SI 2 "const_int_operand" ""))
5547
   (use (match_operand 3 "" ""))
5548
   (use (match_operand 4 "" ""))]
5549
  "flag_pic"
5550
  "
5551
{
5552
  rtx indx;
5553
  rtx scale;
5554
  rtx low = operands[1];
5555
  rtx range = operands[2];
5556
  rtx table = operands[3];
5557
  rtx treg;
5558
  rtx fail = operands[4];
5559
  rtx mem;
5560
  rtx reg2;
5561
  rtx reg3;
5562
 
5563
  gcc_assert (GET_CODE (operands[1]) == CONST_INT);
5564
 
5565
  gcc_assert (GET_CODE (operands[2]) == CONST_INT);
5566
 
5567
  /* If we can't generate an immediate instruction, promote to register.  */
5568
  if (! IN_RANGE (INTVAL (range), -2048, 2047))
5569
    range = force_reg (SImode, range);
5570
 
5571
  /* If low bound is 0, we don't have to subtract it.  */
5572
  if (INTVAL (operands[1]) == 0)
5573
    indx = operands[0];
5574
  else
5575
    {
5576
      indx = gen_reg_rtx (SImode);
5577
      if (IN_RANGE (INTVAL (low), -2047, 2048))
5578
        emit_insn (gen_addsi3 (indx, operands[0], GEN_INT (- INTVAL (low))));
5579
      else
5580
        emit_insn (gen_subsi3 (indx, operands[0], force_reg (SImode, low)));
5581
    }
5582
 
5583
  /* Do an unsigned comparison (in the proper mode) between the index
5584
     expression and the value which represents the length of the range.
5585
     Since we just finished subtracting the lower bound of the range
5586
     from the index expression, this comparison allows us to simultaneously
5587
     check that the original index expression value is both greater than
5588
     or equal to the minimum value of the range and less than or equal to
5589
     the maximum value of the range.  */
5590
 
5591
  emit_cmp_and_jump_insns (indx, range, GTU, NULL_RTX, SImode, 1, fail);
5592
 
5593
  /* Move the table address to a register.  */
5594
  treg = gen_reg_rtx (Pmode);
5595
  emit_insn (gen_movsi (treg, gen_rtx_LABEL_REF (VOIDmode, table)));
5596
 
5597
  /* Scale index-low by wordsize.  */
5598
  scale = gen_reg_rtx (SImode);
5599
  emit_insn (gen_ashlsi3 (scale, indx, const2_rtx));
5600
 
5601
  /* Load the address, add the start of the table back in,
5602
     and jump to it.  */
5603
  mem = gen_rtx_MEM (SImode, gen_rtx_PLUS (Pmode, scale, treg));
5604
  reg2 = gen_reg_rtx (SImode);
5605
  reg3 = gen_reg_rtx (SImode);
5606
  emit_insn (gen_movsi (reg2, mem));
5607
  emit_insn (gen_addsi3 (reg3, reg2, treg));
5608
  emit_jump_insn (gen_tablejump_insn (reg3, table));
5609
  DONE;
5610
}")
5611
 
5612
 
5613
;; ::::::::::::::::::::
5614
;; ::
5615
;; :: Prologue and Epilogue instructions
5616
;; ::
5617
;; ::::::::::::::::::::
5618
 
5619
;; Called after register allocation to add any instructions needed for the
5620
;; prologue.  Using a prologue insn is favored compared to putting all of the
5621
;; instructions in the FUNCTION_PROLOGUE macro, since it allows the scheduler
5622
;; to intermix instructions with the saves of the caller saved registers.  In
5623
;; some cases, it might be necessary to emit a barrier instruction as the last
5624
;; insn to prevent such scheduling.
5625
(define_expand "prologue"
5626
  [(const_int 1)]
5627
  ""
5628
  "
5629
{
5630
  frv_expand_prologue ();
5631
  DONE;
5632
}")
5633
 
5634
;; Called after register allocation to add any instructions needed for the
5635
;; epilogue.  Using an epilogue insn is favored compared to putting all of the
5636
;; instructions in the FUNCTION_EPILOGUE macro, since it allows the scheduler
5637
;; to intermix instructions with the restores of the caller saved registers.
5638
;; In some cases, it might be necessary to emit a barrier instruction as the
5639
;; first insn to prevent such scheduling.
5640
(define_expand "epilogue"
5641
  [(const_int 2)]
5642
  ""
5643
  "
5644
{
5645
  frv_expand_epilogue (true);
5646
  DONE;
5647
}")
5648
 
5649
;; This pattern, if defined, emits RTL for exit from a function without the final
5650
;; branch back to the calling function.  This pattern will be emitted before any
5651
;; sibling call (aka tail call) sites.
5652
;;
5653
;; The sibcall_epilogue pattern must not clobber any arguments used for
5654
;; parameter passing or any stack slots for arguments passed to the current
5655
;; function.
5656
(define_expand "sibcall_epilogue"
5657
  [(const_int 3)]
5658
  ""
5659
  "
5660
{
5661
  frv_expand_epilogue (false);
5662
  DONE;
5663
}")
5664
 
5665
;; Set up the pic register to hold the address of the pic table
5666
(define_insn "pic_prologue"
5667
  [(set (match_operand:SI 0 "integer_register_operand" "=d")
5668
        (unspec_volatile:SI [(const_int 0)] UNSPEC_PIC_PROLOGUE))
5669
   (clobber (match_operand:SI 1 "lr_operand" "=l"))
5670
   (clobber (match_operand:SI 2 "integer_register_operand" "=d"))]
5671
  ""
5672
  "*
5673
{
5674
  static int frv_pic_labelno = 0;
5675
 
5676
  operands[3] = GEN_INT (frv_pic_labelno++);
5677
  return \"call %P3\\n%P3:\;movsg %1, %0\;sethi #gprelhi(%P3), %2\;setlo #gprello(%P3), %2\;sub %0,%2,%0\";
5678
}"
5679
  [(set_attr "length" "16")
5680
   (set_attr "type" "multi")])
5681
 
5682
;; ::::::::::::::::::::
5683
;; ::
5684
;; :: Miscellaneous instructions
5685
;; ::
5686
;; ::::::::::::::::::::
5687
 
5688
;; No operation, needed in case the user uses -g but not -O.
5689
(define_insn "nop"
5690
  [(const_int 0)]
5691
  ""
5692
  "nop"
5693
  [(set_attr "length" "4")
5694
   (set_attr "type" "int")])
5695
 
5696
(define_insn "fnop"
5697
  [(const_int 1)]
5698
  ""
5699
  "fnop"
5700
  [(set_attr "length" "4")
5701
   (set_attr "type" "fnop")])
5702
 
5703
(define_insn "mnop"
5704
  [(const_int 2)]
5705
  ""
5706
  "mnop"
5707
  [(set_attr "length" "4")
5708
   (set_attr "type" "mnop")])
5709
 
5710
;; Pseudo instruction that prevents the scheduler from moving code above this
5711
;; point.  Note, type unknown is used to make sure the VLIW instructions are
5712
;; not continued past this point.
5713
(define_insn "blockage"
5714
  [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
5715
  ""
5716
  "# blockage"
5717
  [(set_attr "length" "0")
5718
   (set_attr "type" "unknown")])
5719
 
5720
;; ::::::::::::::::::::
5721
;; ::
5722
;; :: Media instructions
5723
;; ::
5724
;; ::::::::::::::::::::
5725
 
5726
;; Unimplemented instructions:
5727
;;   - MCMPSH, MCMPUH
5728
 
5729
(define_constants
5730
  [(UNSPEC_MLOGIC               100)
5731
   (UNSPEC_MNOT                 101)
5732
   (UNSPEC_MAVEH                102)
5733
   (UNSPEC_MSATH                103)
5734
   (UNSPEC_MADDH                104)
5735
   (UNSPEC_MQADDH               105)
5736
   (UNSPEC_MPACKH               106)
5737
   (UNSPEC_MUNPACKH             107)
5738
   (UNSPEC_MDPACKH              108)
5739
   (UNSPEC_MBTOH                109)
5740
   (UNSPEC_MHTOB                110)
5741
   (UNSPEC_MROT                 111)
5742
   (UNSPEC_MSHIFT               112)
5743
   (UNSPEC_MEXPDHW              113)
5744
   (UNSPEC_MEXPDHD              114)
5745
   (UNSPEC_MWCUT                115)
5746
   (UNSPEC_MMULH                116)
5747
   (UNSPEC_MMULXH               117)
5748
   (UNSPEC_MMACH                118)
5749
   (UNSPEC_MMRDH                119)
5750
   (UNSPEC_MQMULH               120)
5751
   (UNSPEC_MQMULXH              121)
5752
   (UNSPEC_MQMACH               122)
5753
   (UNSPEC_MCPX                 123)
5754
   (UNSPEC_MQCPX                124)
5755
   (UNSPEC_MCUT                 125)
5756
   (UNSPEC_MRDACC               126)
5757
   (UNSPEC_MRDACCG              127)
5758
   (UNSPEC_MWTACC               128)
5759
   (UNSPEC_MWTACCG              129)
5760
   (UNSPEC_MTRAP                130)
5761
   (UNSPEC_MCLRACC              131)
5762
   (UNSPEC_MCLRACCA             132)
5763
   (UNSPEC_MCOP1                133)
5764
   (UNSPEC_MCOP2                134)
5765
   (UNSPEC_MDUNPACKH            135)
5766
   (UNSPEC_MDUNPACKH_INTERNAL   136)
5767
   (UNSPEC_MBTOHE               137)
5768
   (UNSPEC_MBTOHE_INTERNAL      138)
5769
   (UNSPEC_MBTOHE               137)
5770
   (UNSPEC_MBTOHE_INTERNAL      138)
5771
   (UNSPEC_MQMACH2              139)
5772
   (UNSPEC_MADDACC              140)
5773
   (UNSPEC_MDADDACC             141)
5774
   (UNSPEC_MABSHS               142)
5775
   (UNSPEC_MDROTLI              143)
5776
   (UNSPEC_MCPLHI               144)
5777
   (UNSPEC_MCPLI                145)
5778
   (UNSPEC_MDCUTSSI             146)
5779
   (UNSPEC_MQSATHS              147)
5780
   (UNSPEC_MHSETLOS             148)
5781
   (UNSPEC_MHSETLOH             149)
5782
   (UNSPEC_MHSETHIS             150)
5783
   (UNSPEC_MHSETHIH             151)
5784
   (UNSPEC_MHDSETS              152)
5785
   (UNSPEC_MHDSETH              153)
5786
   (UNSPEC_MQLCLRHS             154)
5787
   (UNSPEC_MQLMTHS              155)
5788
   (UNSPEC_MQSLLHI              156)
5789
   (UNSPEC_MQSRAHI              157)
5790
   (UNSPEC_MASACCS              158)
5791
   (UNSPEC_MDASACCS             159)
5792
])
5793
 
5794
;; Logic operations: type "mlogic"
5795
 
5796
(define_expand "mand"
5797
  [(set (match_operand:SI 0 "fpr_operand" "")
5798
        (unspec:SI [(match_operand:SI 1 "fpr_operand" "")
5799
                    (match_operand:SI 2 "fpr_operand" "")
5800
                    (match_dup 3)]
5801
                   UNSPEC_MLOGIC))]
5802
  "TARGET_MEDIA"
5803
  "operands[3] = GEN_INT (FRV_BUILTIN_MAND);")
5804
 
5805
(define_expand "mor"
5806
  [(set (match_operand:SI 0 "fpr_operand" "")
5807
        (unspec:SI [(match_operand:SI 1 "fpr_operand" "")
5808
                    (match_operand:SI 2 "fpr_operand" "")
5809
                    (match_dup 3)]
5810
                   UNSPEC_MLOGIC))]
5811
  "TARGET_MEDIA"
5812
  "operands[3] = GEN_INT (FRV_BUILTIN_MOR);")
5813
 
5814
(define_expand "mxor"
5815
  [(set (match_operand:SI 0 "fpr_operand" "")
5816
        (unspec:SI [(match_operand:SI 1 "fpr_operand" "")
5817
                    (match_operand:SI 2 "fpr_operand" "")
5818
                    (match_dup 3)]
5819
                   UNSPEC_MLOGIC))]
5820
  "TARGET_MEDIA"
5821
  "operands[3] = GEN_INT (FRV_BUILTIN_MXOR);")
5822
 
5823
(define_insn "*mlogic"
5824
  [(set (match_operand:SI 0 "fpr_operand" "=f")
5825
        (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
5826
                    (match_operand:SI 2 "fpr_operand" "f")
5827
                    (match_operand:SI 3 "const_int_operand" "n")]
5828
                   UNSPEC_MLOGIC))]
5829
  "TARGET_MEDIA"
5830
  "*
5831
{
5832
  switch (INTVAL (operands[3]))
5833
  {
5834
  default:               break;
5835
  case FRV_BUILTIN_MAND: return \"mand %1, %2, %0\";
5836
  case FRV_BUILTIN_MOR:  return \"mor %1, %2, %0\";
5837
  case FRV_BUILTIN_MXOR: return \"mxor %1, %2, %0\";
5838
  }
5839
 
5840
  fatal_insn (\"Bad media insn, mlogic\", insn);
5841
}"
5842
  [(set_attr "length" "4")
5843
   (set_attr "type" "mlogic")])
5844
 
5845
(define_insn "*cond_exec_mlogic"
5846
  [(cond_exec
5847
    (match_operator 0 "ccr_eqne_operator"
5848
                    [(match_operand 1 "cr_operand" "C")
5849
                     (const_int 0)])
5850
    (set (match_operand:SI 2 "fpr_operand" "=f")
5851
         (unspec:SI [(match_operand:SI 3 "fpr_operand" "f")
5852
                     (match_operand:SI 4 "fpr_operand" "f")
5853
                     (match_operand:SI 5 "const_int_operand" "n")]
5854
                    UNSPEC_MLOGIC)))]
5855
  "TARGET_MEDIA"
5856
  "*
5857
{
5858
  switch (INTVAL (operands[5]))
5859
  {
5860
  default:                  break;
5861
  case FRV_BUILTIN_MAND: return \"cmand %3, %4, %2, %1, %e0\";
5862
  case FRV_BUILTIN_MOR:  return \"cmor %3, %4, %2, %1, %e0\";
5863
  case FRV_BUILTIN_MXOR: return \"cmxor %3, %4, %2, %1, %e0\";
5864
  }
5865
 
5866
  fatal_insn (\"Bad media insn, cond_exec_mlogic\", insn);
5867
}"
5868
  [(set_attr "length" "4")
5869
   (set_attr "type" "mlogic")])
5870
 
5871
;; Logical not: type "mlogic"
5872
 
5873
(define_insn "mnot"
5874
  [(set (match_operand:SI 0 "fpr_operand" "=f")
5875
        (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")] UNSPEC_MNOT))]
5876
  "TARGET_MEDIA"
5877
  "mnot %1, %0"
5878
  [(set_attr "length" "4")
5879
   (set_attr "type" "mlogic")])
5880
 
5881
(define_insn "*cond_exec_mnot"
5882
  [(cond_exec
5883
    (match_operator 0 "ccr_eqne_operator"
5884
                    [(match_operand 1 "cr_operand" "C")
5885
                     (const_int 0)])
5886
    (set (match_operand:SI 2 "fpr_operand" "=f")
5887
         (unspec:SI [(match_operand:SI 3 "fpr_operand" "f")] UNSPEC_MNOT)))]
5888
  "TARGET_MEDIA"
5889
  "cmnot %3, %2, %1, %e0"
5890
  [(set_attr "length" "4")
5891
   (set_attr "type" "mlogic")])
5892
 
5893
;; Dual average (halfword): type "maveh"
5894
 
5895
(define_insn "maveh"
5896
  [(set (match_operand:SI 0 "fpr_operand" "=f")
5897
        (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
5898
                    (match_operand:SI 2 "fpr_operand" "f")]
5899
                   UNSPEC_MAVEH))]
5900
  "TARGET_MEDIA"
5901
  "maveh %1, %2, %0"
5902
  [(set_attr "length" "4")
5903
   (set_attr "type" "maveh")])
5904
 
5905
;; Dual saturation (halfword): type "msath"
5906
 
5907
(define_expand "msaths"
5908
  [(set (match_operand:SI 0 "fpr_operand" "=f")
5909
        (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
5910
                    (match_operand:SI 2 "fpr_operand" "f")
5911
                    (match_dup 3)]
5912
                   UNSPEC_MSATH))]
5913
  "TARGET_MEDIA"
5914
  "operands[3] = GEN_INT (FRV_BUILTIN_MSATHS);")
5915
 
5916
(define_expand "msathu"
5917
  [(set (match_operand:SI 0 "fpr_operand" "=f")
5918
        (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
5919
                    (match_operand:SI 2 "fpr_operand" "f")
5920
                    (match_dup 3)]
5921
                   UNSPEC_MSATH))]
5922
  "TARGET_MEDIA"
5923
  "operands[3] = GEN_INT (FRV_BUILTIN_MSATHU);")
5924
 
5925
(define_insn "*msath"
5926
  [(set (match_operand:SI 0 "fpr_operand" "=f")
5927
        (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
5928
                    (match_operand:SI 2 "fpr_operand" "f")
5929
                    (match_operand:SI 3 "const_int_operand" "n")]
5930
                   UNSPEC_MSATH))]
5931
  "TARGET_MEDIA"
5932
  "*
5933
{
5934
  switch (INTVAL (operands[3]))
5935
  {
5936
  default:                  break;
5937
  case FRV_BUILTIN_MSATHS:  return \"msaths %1, %2, %0\";
5938
  case FRV_BUILTIN_MSATHU:  return \"msathu %1, %2, %0\";
5939
  }
5940
 
5941
  fatal_insn (\"Bad media insn, msath\", insn);
5942
}"
5943
  [(set_attr "length" "4")
5944
   (set_attr "type" "msath")])
5945
 
5946
;; Dual addition/subtraction with saturation (halfword): type "maddh"
5947
 
5948
(define_expand "maddhss"
5949
  [(set (match_operand:SI 0 "fpr_operand" "=f")
5950
        (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
5951
                    (match_operand:SI 2 "fpr_operand" "f")
5952
                    (match_dup 3)]
5953
                   UNSPEC_MADDH))]
5954
  "TARGET_MEDIA"
5955
  "operands[3] = GEN_INT (FRV_BUILTIN_MADDHSS);")
5956
 
5957
(define_expand "maddhus"
5958
  [(set (match_operand:SI 0 "fpr_operand" "=f")
5959
        (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
5960
                    (match_operand:SI 2 "fpr_operand" "f")
5961
                    (match_dup 3)]
5962
                   UNSPEC_MADDH))]
5963
  "TARGET_MEDIA"
5964
  "operands[3] = GEN_INT (FRV_BUILTIN_MADDHUS);")
5965
 
5966
(define_expand "msubhss"
5967
  [(set (match_operand:SI 0 "fpr_operand" "=f")
5968
        (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
5969
                    (match_operand:SI 2 "fpr_operand" "f")
5970
                    (match_dup 3)]
5971
                   UNSPEC_MADDH))]
5972
  "TARGET_MEDIA"
5973
  "operands[3] = GEN_INT (FRV_BUILTIN_MSUBHSS);")
5974
 
5975
(define_expand "msubhus"
5976
  [(set (match_operand:SI 0 "fpr_operand" "=f")
5977
        (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
5978
                    (match_operand:SI 2 "fpr_operand" "f")
5979
                    (match_dup 3)]
5980
                   UNSPEC_MADDH))]
5981
  "TARGET_MEDIA"
5982
  "operands[3] = GEN_INT (FRV_BUILTIN_MSUBHUS);")
5983
 
5984
(define_insn "*maddh"
5985
  [(set (match_operand:SI 0 "fpr_operand" "=f")
5986
        (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
5987
                    (match_operand:SI 2 "fpr_operand" "f")
5988
                    (match_operand:SI 3 "const_int_operand" "n")]
5989
                   UNSPEC_MADDH))]
5990
  "TARGET_MEDIA"
5991
  "*
5992
{
5993
  switch (INTVAL (operands[3]))
5994
  {
5995
  default:                  break;
5996
  case FRV_BUILTIN_MADDHSS: return \"maddhss %1, %2, %0\";
5997
  case FRV_BUILTIN_MADDHUS: return \"maddhus %1, %2, %0\";
5998
  case FRV_BUILTIN_MSUBHSS: return \"msubhss %1, %2, %0\";
5999
  case FRV_BUILTIN_MSUBHUS: return \"msubhus %1, %2, %0\";
6000
  }
6001
 
6002
  fatal_insn (\"Bad media insn, maddh\", insn);
6003
}"
6004
  [(set_attr "length" "4")
6005
   (set_attr "type" "maddh")])
6006
 
6007
(define_insn "*cond_exec_maddh"
6008
  [(cond_exec
6009
    (match_operator 0 "ccr_eqne_operator"
6010
                    [(match_operand 1 "cr_operand" "C")
6011
                     (const_int 0)])
6012
    (set (match_operand:SI 2 "fpr_operand" "=f")
6013
         (unspec:SI [(match_operand:SI 3 "fpr_operand" "f")
6014
                     (match_operand:SI 4 "fpr_operand" "f")
6015
                     (match_operand:SI 5 "const_int_operand" "n")]
6016
                    UNSPEC_MADDH)))]
6017
  "TARGET_MEDIA"
6018
  "*
6019
{
6020
  switch (INTVAL (operands[5]))
6021
  {
6022
  default:                  break;
6023
  case FRV_BUILTIN_MADDHSS: return \"cmaddhss %3, %4, %2, %1, %e0\";
6024
  case FRV_BUILTIN_MADDHUS: return \"cmaddhus %3, %4, %2, %1, %e0\";
6025
  case FRV_BUILTIN_MSUBHSS: return \"cmsubhss %3, %4, %2, %1, %e0\";
6026
  case FRV_BUILTIN_MSUBHUS: return \"cmsubhus %3, %4, %2, %1, %e0\";
6027
  }
6028
 
6029
  fatal_insn (\"Bad media insn, cond_exec_maddh\", insn);
6030
}"
6031
  [(set_attr "length" "4")
6032
   (set_attr "type" "maddh")])
6033
 
6034
;; Quad addition/subtraction with saturation (halfword): type "mqaddh"
6035
 
6036
(define_expand "mqaddhss"
6037
  [(set (match_operand:DI 0 "even_fpr_operand" "=h")
6038
        (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
6039
                    (match_operand:DI 2 "even_fpr_operand" "h")
6040
                    (match_dup 3)]
6041
                   UNSPEC_MQADDH))]
6042
  "TARGET_MEDIA"
6043
  "operands[3] = GEN_INT (FRV_BUILTIN_MQADDHSS);")
6044
 
6045
(define_expand "mqaddhus"
6046
  [(set (match_operand:DI 0 "even_fpr_operand" "=h")
6047
        (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
6048
                    (match_operand:DI 2 "even_fpr_operand" "h")
6049
                    (match_dup 3)]
6050
                   UNSPEC_MQADDH))]
6051
  "TARGET_MEDIA"
6052
  "operands[3] = GEN_INT (FRV_BUILTIN_MQADDHUS);")
6053
 
6054
(define_expand "mqsubhss"
6055
  [(set (match_operand:DI 0 "even_fpr_operand" "=h")
6056
        (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
6057
                    (match_operand:DI 2 "even_fpr_operand" "h")
6058
                    (match_dup 3)]
6059
                   UNSPEC_MQADDH))]
6060
  "TARGET_MEDIA"
6061
  "operands[3] = GEN_INT (FRV_BUILTIN_MQSUBHSS);")
6062
 
6063
(define_expand "mqsubhus"
6064
  [(set (match_operand:DI 0 "even_fpr_operand" "=h")
6065
        (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
6066
                    (match_operand:DI 2 "even_fpr_operand" "h")
6067
                    (match_dup 3)]
6068
                   UNSPEC_MQADDH))]
6069
  "TARGET_MEDIA"
6070
  "operands[3] = GEN_INT (FRV_BUILTIN_MQSUBHUS);")
6071
 
6072
(define_insn "*mqaddh"
6073
  [(set (match_operand:DI 0 "even_fpr_operand" "=h")
6074
        (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
6075
                    (match_operand:DI 2 "even_fpr_operand" "h")
6076
                    (match_operand:SI 3 "const_int_operand" "n")]
6077
                   UNSPEC_MQADDH))]
6078
  "TARGET_MEDIA"
6079
  "*
6080
{
6081
  switch (INTVAL (operands[3]))
6082
  {
6083
  default:                   break;
6084
  case FRV_BUILTIN_MQADDHSS: return \"mqaddhss %1, %2, %0\";
6085
  case FRV_BUILTIN_MQADDHUS: return \"mqaddhus %1, %2, %0\";
6086
  case FRV_BUILTIN_MQSUBHSS: return \"mqsubhss %1, %2, %0\";
6087
  case FRV_BUILTIN_MQSUBHUS: return \"mqsubhus %1, %2, %0\";
6088
  }
6089
 
6090
  fatal_insn (\"Bad media insn, mqaddh\", insn);
6091
}"
6092
  [(set_attr "length" "4")
6093
   (set_attr "type" "mqaddh")])
6094
 
6095
(define_insn "*cond_exec_mqaddh"
6096
  [(cond_exec
6097
    (match_operator 0 "ccr_eqne_operator"
6098
                    [(match_operand 1 "cr_operand" "C")
6099
                     (const_int 0)])
6100
    (set (match_operand:DI 2 "even_fpr_operand" "=h")
6101
         (unspec:DI [(match_operand:DI 3 "even_fpr_operand" "h")
6102
                     (match_operand:DI 4 "even_fpr_operand" "h")
6103
                     (match_operand:SI 5 "const_int_operand" "n")]
6104
                    UNSPEC_MQADDH)))]
6105
  "TARGET_MEDIA"
6106
  "*
6107
{
6108
  switch (INTVAL (operands[5]))
6109
  {
6110
  default:                   break;
6111
  case FRV_BUILTIN_MQADDHSS: return \"cmqaddhss %3, %4, %2, %1, %e0\";
6112
  case FRV_BUILTIN_MQADDHUS: return \"cmqaddhus %3, %4, %2, %1, %e0\";
6113
  case FRV_BUILTIN_MQSUBHSS: return \"cmqsubhss %3, %4, %2, %1, %e0\";
6114
  case FRV_BUILTIN_MQSUBHUS: return \"cmqsubhus %3, %4, %2, %1, %e0\";
6115
  }
6116
 
6117
  fatal_insn (\"Bad media insn, cond_exec_mqaddh\", insn);
6118
}"
6119
  [(set_attr "length" "4")
6120
   (set_attr "type" "mqaddh")])
6121
 
6122
;; Pack halfword: type "mpackh"
6123
 
6124
(define_insn "mpackh"
6125
  [(set (match_operand:SI 0 "fpr_operand" "=f")
6126
        (unspec:SI [(match_operand:HI 1 "fpr_operand" "f")
6127
                    (match_operand:HI 2 "fpr_operand" "f")]
6128
                   UNSPEC_MPACKH))]
6129
  "TARGET_MEDIA"
6130
  "mpackh %1, %2, %0"
6131
  [(set_attr "length" "4")
6132
   (set_attr "type" "mpackh")])
6133
 
6134
;; Unpack halfword: type "mpackh"
6135
 
6136
(define_insn "munpackh"
6137
  [(set (match_operand:DI 0 "even_fpr_operand" "=h")
6138
        (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")]
6139
                   UNSPEC_MUNPACKH))]
6140
  "TARGET_MEDIA"
6141
  "munpackh %1, %0"
6142
  [(set_attr "length" "4")
6143
   (set_attr "type" "munpackh")])
6144
 
6145
;; Dual pack halfword: type "mdpackh"
6146
 
6147
(define_insn "mdpackh"
6148
    [(set (match_operand:DI 0 "even_fpr_operand" "=h")
6149
          (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
6150
                      (match_operand:DI 2 "even_fpr_operand" "h")]
6151
                     UNSPEC_MDPACKH))]
6152
  "TARGET_MEDIA"
6153
  "mdpackh %1, %2, %0"
6154
  [(set_attr "length" "4")
6155
   (set_attr "type" "mdpackh")])
6156
 
6157
;; Byte-halfword conversion: type "mbhconv"
6158
 
6159
(define_insn "mbtoh"
6160
  [(set (match_operand:DI 0 "even_fpr_operand" "=h")
6161
        (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")]
6162
                   UNSPEC_MBTOH))]
6163
  "TARGET_MEDIA"
6164
  "mbtoh %1, %0"
6165
  [(set_attr "length" "4")
6166
   (set_attr "type" "mbhconv")])
6167
 
6168
(define_insn "*cond_exec_mbtoh"
6169
  [(cond_exec
6170
    (match_operator 0 "ccr_eqne_operator"
6171
                    [(match_operand 1 "cr_operand" "C")
6172
                     (const_int 0)])
6173
    (set (match_operand:DI 2 "even_fpr_operand" "=h")
6174
         (unspec:DI [(match_operand:SI 3 "fpr_operand" "f")]
6175
                    UNSPEC_MBTOH)))]
6176
  "TARGET_MEDIA"
6177
  "cmbtoh %3, %2, %1, %e0"
6178
  [(set_attr "length" "4")
6179
   (set_attr "type" "mbhconv")])
6180
 
6181
(define_insn "mhtob"
6182
  [(set (match_operand:SI 0 "fpr_operand" "=f")
6183
        (unspec:SI [(match_operand:DI 1 "even_fpr_operand" "h")]
6184
                   UNSPEC_MHTOB))]
6185
  "TARGET_MEDIA"
6186
  "mhtob %1, %0"
6187
  [(set_attr "length" "4")
6188
   (set_attr "type" "mbhconv")])
6189
 
6190
(define_insn "*cond_exec_mhtob"
6191
  [(cond_exec
6192
    (match_operator 0 "ccr_eqne_operator"
6193
                    [(match_operand 1 "cr_operand" "C")
6194
                     (const_int 0)])
6195
    (set (match_operand:SI 2 "fpr_operand" "=f")
6196
         (unspec:SI [(match_operand:DI 3 "even_fpr_operand" "h")]
6197
                    UNSPEC_MHTOB)))]
6198
  "TARGET_MEDIA"
6199
  "cmhtob %3, %2, %1, %e0"
6200
  [(set_attr "length" "4")
6201
   (set_attr "type" "mbhconv")])
6202
 
6203
;; Rotate: type "mrot"
6204
 
6205
(define_expand "mrotli"
6206
  [(set (match_operand:SI 0 "fpr_operand" "")
6207
        (unspec:SI [(match_operand:SI 1 "fpr_operand" "")
6208
                    (match_operand:SI 2 "uint5_operand" "")
6209
                    (match_dup 3)]
6210
                   UNSPEC_MROT))]
6211
  "TARGET_MEDIA"
6212
  "operands[3] = GEN_INT (FRV_BUILTIN_MROTLI);")
6213
 
6214
(define_expand "mrotri"
6215
  [(set (match_operand:SI 0 "fpr_operand" "")
6216
        (unspec:SI [(match_operand:SI 1 "fpr_operand" "")
6217
                    (match_operand:SI 2 "uint5_operand" "")
6218
                    (match_dup 3)]
6219
                   UNSPEC_MROT))]
6220
  "TARGET_MEDIA"
6221
  "operands[3] = GEN_INT (FRV_BUILTIN_MROTRI);")
6222
 
6223
(define_insn "*mrot"
6224
  [(set (match_operand:SI 0 "fpr_operand" "=f")
6225
        (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6226
                    (match_operand:SI 2 "uint5_operand" "I")
6227
                    (match_operand:SI 3 "const_int_operand" "n")]
6228
                   UNSPEC_MROT))]
6229
  "TARGET_MEDIA"
6230
  "*
6231
{
6232
  switch (INTVAL (operands[3]))
6233
  {
6234
  default:                 break;
6235
  case FRV_BUILTIN_MROTLI: return \"mrotli %1, %2, %0\";
6236
  case FRV_BUILTIN_MROTRI: return \"mrotri %1, %2, %0\";
6237
  }
6238
 
6239
  fatal_insn (\"Bad media insn, mrot\", insn);
6240
}"
6241
  [(set_attr "length" "4")
6242
   (set_attr "type" "mrot")])
6243
 
6244
;; Dual shift halfword: type "msh"
6245
 
6246
(define_expand "msllhi"
6247
  [(set (match_operand:SI 0 "fpr_operand" "")
6248
        (unspec:SI [(match_operand:SI 1 "fpr_operand" "")
6249
                    (match_operand:SI 2 "uint4_operand" "")
6250
                    (match_dup 3)]
6251
                   UNSPEC_MSHIFT))]
6252
  "TARGET_MEDIA"
6253
  "operands[3] = GEN_INT (FRV_BUILTIN_MSLLHI);")
6254
 
6255
(define_expand "msrlhi"
6256
  [(set (match_operand:SI 0 "fpr_operand" "")
6257
        (unspec:SI [(match_operand:SI 1 "fpr_operand" "")
6258
                    (match_operand:SI 2 "uint4_operand" "")
6259
                    (match_dup 3)]
6260
                   UNSPEC_MSHIFT))]
6261
  "TARGET_MEDIA"
6262
  "operands[3] = GEN_INT (FRV_BUILTIN_MSRLHI);")
6263
 
6264
(define_expand "msrahi"
6265
  [(set (match_operand:SI 0 "fpr_operand" "")
6266
        (unspec:SI [(match_operand:SI 1 "fpr_operand" "")
6267
                    (match_operand:SI 2 "uint4_operand" "")
6268
                    (match_dup 3)]
6269
                   UNSPEC_MSHIFT))]
6270
  "TARGET_MEDIA"
6271
  "operands[3] = GEN_INT (FRV_BUILTIN_MSRAHI);")
6272
 
6273
(define_insn "*mshift"
6274
  [(set (match_operand:SI 0 "fpr_operand" "=f")
6275
        (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6276
                    (match_operand:SI 2 "uint4_operand" "I")
6277
                    (match_operand:SI 3 "const_int_operand" "n")]
6278
                   UNSPEC_MSHIFT))]
6279
  "TARGET_MEDIA"
6280
  "*
6281
{
6282
  switch (INTVAL (operands[3]))
6283
  {
6284
  default:                 break;
6285
  case FRV_BUILTIN_MSLLHI: return \"msllhi %1, %2, %0\";
6286
  case FRV_BUILTIN_MSRLHI: return \"msrlhi %1, %2, %0\";
6287
  case FRV_BUILTIN_MSRAHI: return \"msrahi %1, %2, %0\";
6288
  }
6289
 
6290
  fatal_insn (\"Bad media insn, mshift\", insn);
6291
}"
6292
  [(set_attr "length" "4")
6293
   (set_attr "type" "mshift")])
6294
 
6295
;; Expand halfword to word: type "mexpdhw"
6296
 
6297
(define_insn "mexpdhw"
6298
  [(set (match_operand:SI 0 "fpr_operand" "=f")
6299
        (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6300
                    (match_operand:SI 2 "uint1_operand" "I")]
6301
                   UNSPEC_MEXPDHW))]
6302
  "TARGET_MEDIA"
6303
  "mexpdhw %1, %2, %0"
6304
  [(set_attr "length" "4")
6305
   (set_attr "type" "mexpdhw")])
6306
 
6307
(define_insn "*cond_exec_mexpdhw"
6308
  [(cond_exec
6309
    (match_operator 0 "ccr_eqne_operator"
6310
                    [(match_operand 1 "cr_operand" "C")
6311
                     (const_int 0)])
6312
    (set (match_operand:SI 2 "fpr_operand" "=f")
6313
         (unspec:SI [(match_operand:SI 3 "fpr_operand" "f")
6314
                     (match_operand:SI 4 "uint1_operand" "I")]
6315
                    UNSPEC_MEXPDHW)))]
6316
  "TARGET_MEDIA"
6317
  "cmexpdhw %3, %4, %2, %1, %e0"
6318
  [(set_attr "length" "4")
6319
   (set_attr "type" "mexpdhw")])
6320
 
6321
;; Expand halfword to double: type "mexpdhd"
6322
 
6323
(define_insn "mexpdhd"
6324
  [(set (match_operand:DI 0 "even_fpr_operand" "=h")
6325
        (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")
6326
                    (match_operand:SI 2 "uint1_operand" "I")]
6327
                   UNSPEC_MEXPDHD))]
6328
  "TARGET_MEDIA"
6329
  "mexpdhd %1, %2, %0"
6330
  [(set_attr "length" "4")
6331
   (set_attr "type" "mexpdhd")])
6332
 
6333
(define_insn "*cond_exec_mexpdhd"
6334
  [(cond_exec
6335
    (match_operator 0 "ccr_eqne_operator"
6336
                    [(match_operand 1 "cr_operand" "C")
6337
                     (const_int 0)])
6338
    (set (match_operand:DI 2 "even_fpr_operand" "=h")
6339
         (unspec:DI [(match_operand:SI 3 "fpr_operand" "f")
6340
                     (match_operand:SI 4 "uint1_operand" "I")]
6341
                    UNSPEC_MEXPDHD)))]
6342
  "TARGET_MEDIA"
6343
  "cmexpdhd %3, %4, %2, %1, %e0"
6344
  [(set_attr "length" "4")
6345
   (set_attr "type" "mexpdhd")])
6346
 
6347
;; FR cut: type "mwcut"
6348
 
6349
(define_insn "mwcut"
6350
  [(set (match_operand:SI 0 "fpr_operand" "=f")
6351
        (unspec:SI [(match_operand:DI 1 "fpr_operand" "f")
6352
                    (match_operand:SI 2 "fpr_or_int6_operand" "fI")]
6353
                   UNSPEC_MWCUT))]
6354
  "TARGET_MEDIA"
6355
  "mwcut%i2 %1, %2, %0"
6356
  [(set_attr "length" "4")
6357
   (set_attr "type" "mwcut")])
6358
 
6359
;; Dual multiplication (halfword): type "mmulh"
6360
 
6361
(define_expand "mmulhs"
6362
  [(parallel [(set (match_operand:DI 0 "even_acc_operand" "=b")
6363
                   (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")
6364
                               (match_operand:SI 2 "fpr_operand" "f")
6365
                               (match_dup 4)]
6366
                              UNSPEC_MMULH))
6367
              (set (match_operand:HI 3 "accg_operand" "=B")
6368
                   (unspec:HI [(const_int 0)] UNSPEC_MMULH))])]
6369
  "TARGET_MEDIA"
6370
  "operands[4] = GEN_INT (FRV_BUILTIN_MMULHS);")
6371
 
6372
(define_expand "mmulhu"
6373
  [(parallel [(set (match_operand:DI 0 "even_acc_operand" "=b")
6374
                   (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")
6375
                               (match_operand:SI 2 "fpr_operand" "f")
6376
                               (match_dup 4)]
6377
                              UNSPEC_MMULH))
6378
              (set (match_operand:HI 3 "accg_operand" "=B")
6379
                   (unspec:HI [(const_int 0)] UNSPEC_MMULH))])]
6380
  "TARGET_MEDIA"
6381
  "operands[4] = GEN_INT (FRV_BUILTIN_MMULHU);")
6382
 
6383
(define_insn "*mmulh"
6384
  [(set (match_operand:DI 0 "even_acc_operand" "=b")
6385
        (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")
6386
                    (match_operand:SI 2 "fpr_operand" "f")
6387
                    (match_operand:SI 3 "const_int_operand" "n")]
6388
                   UNSPEC_MMULH))
6389
   (set (match_operand:HI 4 "accg_operand" "=B")
6390
        (unspec:HI [(const_int 0)] UNSPEC_MMULH))]
6391
  "TARGET_MEDIA"
6392
  "*
6393
{
6394
  switch (INTVAL (operands[3]))
6395
  {
6396
  default:                  break;
6397
  case FRV_BUILTIN_MMULHS:  return \"mmulhs %1, %2, %0\";
6398
  case FRV_BUILTIN_MMULHU:  return \"mmulhu %1, %2, %0\";
6399
  }
6400
 
6401
  fatal_insn (\"Bad media insn, mmulh\", insn);
6402
}"
6403
  [(set_attr "length" "4")
6404
   (set_attr "type" "mmulh")])
6405
 
6406
(define_insn "*cond_exec_mmulh"
6407
  [(cond_exec
6408
    (match_operator 0 "ccr_eqne_operator"
6409
                    [(match_operand 1 "cr_operand" "C")
6410
                     (const_int 0)])
6411
    (parallel [(set (match_operand:DI 2 "even_acc_operand" "=b")
6412
                    (unspec:DI [(match_operand:SI 3 "fpr_operand" "f")
6413
                                (match_operand:SI 4 "fpr_operand" "f")
6414
                                (match_operand:SI 5 "const_int_operand" "n")]
6415
                               UNSPEC_MMULH))
6416
               (set (match_operand:HI 6 "accg_operand" "=B")
6417
                    (unspec:HI [(const_int 0)] UNSPEC_MMULH))]))]
6418
  "TARGET_MEDIA"
6419
  "*
6420
{
6421
  switch (INTVAL (operands[5]))
6422
  {
6423
  default:                  break;
6424
  case FRV_BUILTIN_MMULHS:  return \"cmmulhs %3, %4, %2, %1, %e0\";
6425
  case FRV_BUILTIN_MMULHU:  return \"cmmulhu %3, %4, %2, %1, %e0\";
6426
  }
6427
 
6428
  fatal_insn (\"Bad media insn, cond_exec_mmulh\", insn);
6429
}"
6430
  [(set_attr "length" "4")
6431
   (set_attr "type" "mmulh")])
6432
 
6433
;; Dual cross multiplication (halfword): type "mmulxh"
6434
 
6435
(define_expand "mmulxhs"
6436
  [(parallel [(set (match_operand:DI 0 "even_acc_operand" "=b")
6437
                   (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")
6438
                               (match_operand:SI 2 "fpr_operand" "f")
6439
                               (match_dup 4)]
6440
                              UNSPEC_MMULXH))
6441
              (set (match_operand:HI 3 "accg_operand" "=B")
6442
                   (unspec:HI [(const_int 0)] UNSPEC_MMULXH))])]
6443
  "TARGET_MEDIA"
6444
  "operands[4] = GEN_INT (FRV_BUILTIN_MMULXHS);")
6445
 
6446
(define_expand "mmulxhu"
6447
  [(parallel [(set (match_operand:DI 0 "even_acc_operand" "=b")
6448
                   (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")
6449
                               (match_operand:SI 2 "fpr_operand" "f")
6450
                               (match_dup 4)]
6451
                              UNSPEC_MMULXH))
6452
              (set (match_operand:HI 3 "accg_operand" "=B")
6453
                   (unspec:HI [(const_int 0)] UNSPEC_MMULXH))])]
6454
  "TARGET_MEDIA"
6455
  "operands[4] = GEN_INT (FRV_BUILTIN_MMULXHU);")
6456
 
6457
(define_insn "*mmulxh"
6458
  [(set (match_operand:DI 0 "even_acc_operand" "=b")
6459
        (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")
6460
                    (match_operand:SI 2 "fpr_operand" "f")
6461
                    (match_operand:SI 3 "const_int_operand" "n")]
6462
                   UNSPEC_MMULXH))
6463
   (set (match_operand:HI 4 "accg_operand" "=B")
6464
        (unspec:HI [(const_int 0)] UNSPEC_MMULXH))]
6465
  "TARGET_MEDIA"
6466
  "*
6467
{
6468
  switch (INTVAL (operands[3]))
6469
  {
6470
  default:                  break;
6471
  case FRV_BUILTIN_MMULXHS: return \"mmulxhs %1, %2, %0\";
6472
  case FRV_BUILTIN_MMULXHU: return \"mmulxhu %1, %2, %0\";
6473
  }
6474
 
6475
  fatal_insn (\"Bad media insn, mmulxh\", insn);
6476
}"
6477
  [(set_attr "length" "4")
6478
   (set_attr "type" "mmulxh")])
6479
 
6480
;; Dual product-sum (halfword): type "mmach"
6481
 
6482
(define_expand "mmachs"
6483
  [(parallel [(set (match_operand:DI 0 "even_acc_operand" "+b")
6484
                   (unspec:DI [(match_dup 0)
6485
                               (match_operand:SI 1 "fpr_operand" "f")
6486
                               (match_operand:SI 2 "fpr_operand" "f")
6487
                               (match_operand:HI 3 "accg_operand" "+B")
6488
                               (match_dup 4)]
6489
                              UNSPEC_MMACH))
6490
              (set (match_dup 3)
6491
                   (unspec:HI [(const_int 0)] UNSPEC_MMACH))])]
6492
  "TARGET_MEDIA"
6493
  "operands[4] = GEN_INT (FRV_BUILTIN_MMACHS);")
6494
 
6495
(define_expand "mmachu"
6496
  [(parallel [(set (match_operand:DI 0 "even_acc_operand" "+b")
6497
                   (unspec:DI [(match_dup 0)
6498
                               (match_operand:SI 1 "fpr_operand" "f")
6499
                               (match_operand:SI 2 "fpr_operand" "f")
6500
                               (match_operand:HI 3 "accg_operand" "+B")
6501
                               (match_dup 4)]
6502
                              UNSPEC_MMACH))
6503
              (set (match_dup 3)
6504
                   (unspec:HI [(const_int 0)] UNSPEC_MMACH))])]
6505
  "TARGET_MEDIA"
6506
  "operands[4] = GEN_INT (FRV_BUILTIN_MMACHU);")
6507
 
6508
(define_insn "*mmach"
6509
  [(set (match_operand:DI 0 "even_acc_operand" "+b")
6510
        (unspec:DI [(match_dup 0)
6511
                    (match_operand:SI 1 "fpr_operand" "f")
6512
                    (match_operand:SI 2 "fpr_operand" "f")
6513
                    (match_operand:HI 3 "accg_operand" "+B")
6514
                    (match_operand:SI 4 "const_int_operand" "n")]
6515
                   UNSPEC_MMACH))
6516
   (set (match_dup 3) (unspec:HI [(const_int 0)] UNSPEC_MMACH))]
6517
  "TARGET_MEDIA"
6518
  "*
6519
{
6520
  switch (INTVAL (operands[4]))
6521
  {
6522
  default:                 break;
6523
  case FRV_BUILTIN_MMACHS: return \"mmachs %1, %2, %0\";
6524
  case FRV_BUILTIN_MMACHU: return \"mmachu %1, %2, %0\";
6525
  }
6526
 
6527
  fatal_insn (\"Bad media insn, mmach\", insn);
6528
}"
6529
  [(set_attr "length" "4")
6530
   (set_attr "type" "mmach")])
6531
 
6532
(define_insn "*cond_exec_mmach"
6533
  [(cond_exec
6534
    (match_operator 0 "ccr_eqne_operator"
6535
                    [(match_operand 1 "cr_operand" "C")
6536
                     (const_int 0)])
6537
    (parallel [(set (match_operand:DI 2 "even_acc_operand" "+b")
6538
                    (unspec:DI [(match_dup 2)
6539
                                (match_operand:SI 3 "fpr_operand" "f")
6540
                                (match_operand:SI 4 "fpr_operand" "f")
6541
                                (match_operand:HI 5 "accg_operand" "+B")
6542
                                (match_operand:SI 6 "const_int_operand" "n")]
6543
                               UNSPEC_MMACH))
6544
               (set (match_dup 5)
6545
                    (unspec:HI [(const_int 0)] UNSPEC_MMACH))]))]
6546
  "TARGET_MEDIA"
6547
  "*
6548
{
6549
  switch (INTVAL (operands[6]))
6550
  {
6551
  default:                 break;
6552
  case FRV_BUILTIN_MMACHS: return \"cmmachs %3, %4, %2, %1, %e0\";
6553
  case FRV_BUILTIN_MMACHU: return \"cmmachu %3, %4, %2, %1, %e0\";
6554
  }
6555
 
6556
  fatal_insn (\"Bad media insn, cond_exec_mmach\", insn);
6557
}"
6558
  [(set_attr "length" "4")
6559
   (set_attr "type" "mmach")])
6560
 
6561
;; Dual product-difference: type "mmrdh"
6562
 
6563
(define_expand "mmrdhs"
6564
  [(parallel [(set (match_operand:DI 0 "even_acc_operand" "+b")
6565
                   (unspec:DI [(match_dup 0)
6566
                               (match_operand:SI 1 "fpr_operand" "f")
6567
                               (match_operand:SI 2 "fpr_operand" "f")
6568
                               (match_operand:HI 3 "accg_operand" "+B")
6569
                               (match_dup 4)]
6570
                              UNSPEC_MMRDH))
6571
              (set (match_dup 3)
6572
                   (unspec:HI [(const_int 0)] UNSPEC_MMRDH))])]
6573
  "TARGET_MEDIA"
6574
  "operands[4] = GEN_INT (FRV_BUILTIN_MMRDHS);")
6575
 
6576
(define_expand "mmrdhu"
6577
  [(parallel [(set (match_operand:DI 0 "even_acc_operand" "+b")
6578
                   (unspec:DI [(match_dup 0)
6579
                               (match_operand:SI 1 "fpr_operand" "f")
6580
                               (match_operand:SI 2 "fpr_operand" "f")
6581
                               (match_operand:HI 3 "accg_operand" "+B")
6582
                               (match_dup 4)]
6583
                              UNSPEC_MMRDH))
6584
              (set (match_dup 3)
6585
                   (unspec:HI [(const_int 0)] UNSPEC_MMRDH))])]
6586
  "TARGET_MEDIA"
6587
  "operands[4] = GEN_INT (FRV_BUILTIN_MMRDHU);")
6588
 
6589
(define_insn "*mmrdh"
6590
  [(set (match_operand:DI 0 "even_acc_operand" "+b")
6591
        (unspec:DI [(match_dup 0)
6592
                    (match_operand:SI 1 "fpr_operand" "f")
6593
                    (match_operand:SI 2 "fpr_operand" "f")
6594
                    (match_operand:HI 3 "accg_operand" "+B")
6595
                    (match_operand:SI 4 "const_int_operand" "n")]
6596
                   UNSPEC_MMRDH))
6597
   (set (match_dup 3)
6598
        (unspec:HI [(const_int 0)] UNSPEC_MMRDH))]
6599
  "TARGET_MEDIA"
6600
  "*
6601
{
6602
  switch (INTVAL (operands[4]))
6603
  {
6604
  default:                 break;
6605
  case FRV_BUILTIN_MMRDHS: return \"mmrdhs %1, %2, %0\";
6606
  case FRV_BUILTIN_MMRDHU: return \"mmrdhu %1, %2, %0\";
6607
  }
6608
 
6609
  fatal_insn (\"Bad media insn, mrdh\", insn);
6610
}"
6611
  [(set_attr "length" "4")
6612
   (set_attr "type" "mmrdh")])
6613
 
6614
;; Quad multiply (halfword): type "mqmulh"
6615
 
6616
(define_expand "mqmulhs"
6617
  [(parallel [(set (match_operand:V4SI 0 "quad_acc_operand" "=A")
6618
                   (unspec:V4SI [(match_operand:DI 1 "even_fpr_operand" "h")
6619
                                 (match_operand:DI 2 "even_fpr_operand" "h")
6620
                                 (match_dup 4)]
6621
                                UNSPEC_MQMULH))
6622
              (set (match_operand:V4QI 3 "accg_operand" "=B")
6623
                   (unspec:V4QI [(const_int 0)] UNSPEC_MQMULH))])]
6624
  "TARGET_MEDIA"
6625
  "operands[4] = GEN_INT (FRV_BUILTIN_MQMULHS);")
6626
 
6627
(define_expand "mqmulhu"
6628
  [(parallel [(set (match_operand:V4SI 0 "quad_acc_operand" "=A")
6629
                   (unspec:V4SI [(match_operand:DI 1 "even_fpr_operand" "h")
6630
                                 (match_operand:DI 2 "even_fpr_operand" "h")
6631
                                 (match_dup 4)]
6632
                                UNSPEC_MQMULH))
6633
              (set (match_operand:V4QI 3 "accg_operand" "=B")
6634
                   (unspec:V4QI [(const_int 0)] UNSPEC_MQMULH))])]
6635
  "TARGET_MEDIA"
6636
  "operands[4] = GEN_INT (FRV_BUILTIN_MQMULHU);")
6637
 
6638
(define_insn "*mqmulh"
6639
  [(set (match_operand:V4SI 0 "quad_acc_operand" "=A")
6640
        (unspec:V4SI [(match_operand:DI 1 "even_fpr_operand" "h")
6641
                      (match_operand:DI 2 "even_fpr_operand" "h")
6642
                      (match_operand:SI 3 "const_int_operand" "n")]
6643
                     UNSPEC_MQMULH))
6644
   (set (match_operand:V4QI 4 "accg_operand" "=B")
6645
        (unspec:V4QI [(const_int 0)] UNSPEC_MQMULH))]
6646
  "TARGET_MEDIA"
6647
  "*
6648
{
6649
  switch (INTVAL (operands[3]))
6650
  {
6651
  default:                   break;
6652
  case FRV_BUILTIN_MQMULHS:  return \"mqmulhs %1, %2, %0\";
6653
  case FRV_BUILTIN_MQMULHU:  return \"mqmulhu %1, %2, %0\";
6654
  }
6655
 
6656
  fatal_insn (\"Bad media insn, mqmulh\", insn);
6657
}"
6658
  [(set_attr "length" "4")
6659
   (set_attr "type" "mqmulh")])
6660
 
6661
(define_insn "*cond_exec_mqmulh"
6662
  [(cond_exec
6663
    (match_operator 0 "ccr_eqne_operator"
6664
                    [(match_operand 1 "cr_operand" "C")
6665
                     (const_int 0)])
6666
    (parallel [(set (match_operand:V4SI 2 "quad_acc_operand" "=A")
6667
                    (unspec:V4SI [(match_operand:DI 3 "even_fpr_operand" "h")
6668
                                  (match_operand:DI 4 "even_fpr_operand" "h")
6669
                                  (match_operand:SI 5 "const_int_operand" "n")]
6670
                                 UNSPEC_MQMULH))
6671
               (set (match_operand:V4QI 6 "accg_operand" "=B")
6672
                    (unspec:V4QI [(const_int 0)] UNSPEC_MQMULH))]))]
6673
  "TARGET_MEDIA"
6674
  "*
6675
{
6676
  switch (INTVAL (operands[5]))
6677
  {
6678
  default:                   break;
6679
  case FRV_BUILTIN_MQMULHS:  return \"cmqmulhs %3, %4, %2, %1, %e0\";
6680
  case FRV_BUILTIN_MQMULHU:  return \"cmqmulhu %3, %4, %2, %1, %e0\";
6681
  }
6682
 
6683
  fatal_insn (\"Bad media insn, cond_exec_mqmulh\", insn);
6684
}"
6685
  [(set_attr "length" "4")
6686
   (set_attr "type" "mqmulh")])
6687
 
6688
;; Quad cross multiply (halfword): type "mqmulxh"
6689
 
6690
(define_expand "mqmulxhs"
6691
  [(parallel [(set (match_operand:V4SI 0 "quad_acc_operand" "=A")
6692
                   (unspec:V4SI [(match_operand:DI 1 "even_fpr_operand" "h")
6693
                                 (match_operand:DI 2 "even_fpr_operand" "h")
6694
                                 (match_dup 4)]
6695
                                UNSPEC_MQMULXH))
6696
              (set (match_operand:V4QI 3 "accg_operand" "=B")
6697
                   (unspec:V4QI [(const_int 0)] UNSPEC_MQMULXH))])]
6698
  "TARGET_MEDIA"
6699
  "operands[4] = GEN_INT (FRV_BUILTIN_MQMULXHS);")
6700
 
6701
(define_expand "mqmulxhu"
6702
  [(parallel [(set (match_operand:V4SI 0 "quad_acc_operand" "=A")
6703
                   (unspec:V4SI [(match_operand:DI 1 "even_fpr_operand" "h")
6704
                                 (match_operand:DI 2 "even_fpr_operand" "h")
6705
                                 (match_dup 4)]
6706
                                UNSPEC_MQMULXH))
6707
              (set (match_operand:V4QI 3 "accg_operand" "=B")
6708
                   (unspec:V4QI [(const_int 0)] UNSPEC_MQMULXH))])]
6709
  "TARGET_MEDIA"
6710
  "operands[4] = GEN_INT (FRV_BUILTIN_MQMULXHU);")
6711
 
6712
(define_insn "*mqmulxh"
6713
  [(set (match_operand:V4SI 0 "quad_acc_operand" "=A")
6714
        (unspec:V4SI [(match_operand:DI 1 "even_fpr_operand" "h")
6715
                      (match_operand:DI 2 "even_fpr_operand" "h")
6716
                      (match_operand:SI 3 "const_int_operand" "n")]
6717
                     UNSPEC_MQMULXH))
6718
   (set (match_operand:V4QI 4 "accg_operand" "=B")
6719
        (unspec:V4QI [(const_int 0)] UNSPEC_MQMULXH))]
6720
  "TARGET_MEDIA"
6721
  "*
6722
{
6723
  switch (INTVAL (operands[3]))
6724
  {
6725
  default:                   break;
6726
  case FRV_BUILTIN_MQMULXHS: return \"mqmulxhs %1, %2, %0\";
6727
  case FRV_BUILTIN_MQMULXHU: return \"mqmulxhu %1, %2, %0\";
6728
  }
6729
 
6730
  fatal_insn (\"Bad media insn, mqmulxh\", insn);
6731
}"
6732
  [(set_attr "length" "4")
6733
   (set_attr "type" "mqmulxh")])
6734
 
6735
;; Quad product-sum (halfword): type "mqmach"
6736
 
6737
(define_expand "mqmachs"
6738
  [(parallel [(set (match_operand:V4SI 0 "even_acc_operand" "+A")
6739
                   (unspec:V4SI [(match_dup 0)
6740
                                 (match_operand:DI 1 "even_fpr_operand" "h")
6741
                                 (match_operand:DI 2 "even_fpr_operand" "h")
6742
                                 (match_operand:V4QI 3 "accg_operand" "+B")
6743
                                 (match_dup 4)]
6744
                                UNSPEC_MQMACH))
6745
              (set (match_dup 3)
6746
                   (unspec:V4QI [(const_int 0)] UNSPEC_MQMACH))])]
6747
  "TARGET_MEDIA"
6748
  "operands[4] = GEN_INT (FRV_BUILTIN_MQMACHS);")
6749
 
6750
(define_expand "mqmachu"
6751
  [(parallel [(set (match_operand:V4SI 0 "even_acc_operand" "+A")
6752
                   (unspec:V4SI [(match_dup 0)
6753
                                 (match_operand:DI 1 "even_fpr_operand" "h")
6754
                                 (match_operand:DI 2 "even_fpr_operand" "h")
6755
                                 (match_operand:V4QI 3 "accg_operand" "+B")
6756
                                 (match_dup 4)]
6757
                                UNSPEC_MQMACH))
6758
              (set (match_dup 3)
6759
                   (unspec:V4QI [(const_int 0)] UNSPEC_MQMACH))])]
6760
  "TARGET_MEDIA"
6761
  "operands[4] = GEN_INT (FRV_BUILTIN_MQMACHU);")
6762
 
6763
(define_insn "*mqmach"
6764
  [(set (match_operand:V4SI 0 "even_acc_operand" "+A")
6765
        (unspec:V4SI [(match_dup 0)
6766
                      (match_operand:DI 1 "even_fpr_operand" "h")
6767
                      (match_operand:DI 2 "even_fpr_operand" "h")
6768
                      (match_operand:V4QI 3 "accg_operand" "+B")
6769
                      (match_operand:SI 4 "const_int_operand" "n")]
6770
                     UNSPEC_MQMACH))
6771
   (set (match_dup 3)
6772
        (unspec:V4QI [(const_int 0)] UNSPEC_MQMACH))]
6773
  "TARGET_MEDIA"
6774
  "*
6775
{
6776
  switch (INTVAL (operands[4]))
6777
  {
6778
  default:                  break;
6779
  case FRV_BUILTIN_MQMACHS: return \"mqmachs %1, %2, %0\";
6780
  case FRV_BUILTIN_MQMACHU: return \"mqmachu %1, %2, %0\";
6781
  }
6782
 
6783
  fatal_insn (\"Bad media insn, mqmach\", insn);
6784
}"
6785
  [(set_attr "length" "4")
6786
   (set_attr "type" "mqmach")])
6787
 
6788
(define_insn "*cond_exec_mqmach"
6789
  [(cond_exec
6790
    (match_operator 0 "ccr_eqne_operator"
6791
                    [(match_operand 1 "cr_operand" "C")
6792
                     (const_int 0)])
6793
    (parallel [(set (match_operand:V4SI 2 "even_acc_operand" "+A")
6794
                    (unspec:V4SI [(match_dup 2)
6795
                                  (match_operand:DI 3 "even_fpr_operand" "h")
6796
                                  (match_operand:DI 4 "even_fpr_operand" "h")
6797
                                  (match_operand:V4QI 5 "accg_operand" "+B")
6798
                                  (match_operand:SI 6 "const_int_operand" "n")]
6799
                                 UNSPEC_MQMACH))
6800
               (set (match_dup 5)
6801
                    (unspec:V4QI [(const_int 0)] UNSPEC_MQMACH))]))]
6802
  "TARGET_MEDIA"
6803
  "*
6804
{
6805
  switch (INTVAL (operands[6]))
6806
  {
6807
  default:                  break;
6808
  case FRV_BUILTIN_MQMACHS: return \"cmqmachs %3, %4, %2, %1, %e0\";
6809
  case FRV_BUILTIN_MQMACHU: return \"cmqmachu %3, %4, %2, %1, %e0\";
6810
  }
6811
 
6812
  fatal_insn (\"Bad media insn, cond_exec_mqmach\", insn);
6813
}"
6814
  [(set_attr "length" "4")
6815
   (set_attr "type" "mqmach")])
6816
 
6817
;; Dual complex number product-sum (halfword)
6818
 
6819
(define_expand "mcpxrs"
6820
  [(parallel [(set (match_operand:SI 0 "acc_operand" "=a")
6821
                   (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6822
                               (match_operand:SI 2 "fpr_operand" "f")
6823
                               (match_dup 4)]
6824
                              UNSPEC_MCPX))
6825
              (set (match_operand:QI 3 "accg_operand" "=B")
6826
                   (unspec:QI [(const_int 0)] UNSPEC_MCPX))])]
6827
  "TARGET_MEDIA"
6828
  "operands[4] = GEN_INT (FRV_BUILTIN_MCPXRS);")
6829
 
6830
(define_expand "mcpxru"
6831
  [(parallel [(set (match_operand:SI 0 "acc_operand" "=a")
6832
                   (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6833
                               (match_operand:SI 2 "fpr_operand" "f")
6834
                               (match_dup 4)]
6835
                              UNSPEC_MCPX))
6836
              (set (match_operand:QI 3 "accg_operand" "=B")
6837
                   (unspec:QI [(const_int 0)] UNSPEC_MCPX))])]
6838
  "TARGET_MEDIA"
6839
  "operands[4] = GEN_INT (FRV_BUILTIN_MCPXRU);")
6840
 
6841
(define_expand "mcpxis"
6842
  [(parallel [(set (match_operand:SI 0 "acc_operand" "=a")
6843
                   (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6844
                               (match_operand:SI 2 "fpr_operand" "f")
6845
                               (match_dup 4)]
6846
                              UNSPEC_MCPX))
6847
              (set (match_operand:QI 3 "accg_operand" "=B")
6848
                   (unspec:QI [(const_int 0)] UNSPEC_MCPX))])]
6849
  "TARGET_MEDIA"
6850
  "operands[4] = GEN_INT (FRV_BUILTIN_MCPXIS);")
6851
 
6852
(define_expand "mcpxiu"
6853
  [(parallel [(set (match_operand:SI 0 "acc_operand" "=a")
6854
                   (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6855
                               (match_operand:SI 2 "fpr_operand" "f")
6856
                               (match_dup 4)]
6857
                              UNSPEC_MCPX))
6858
              (set (match_operand:QI 3 "accg_operand" "=B")
6859
                   (unspec:QI [(const_int 0)] UNSPEC_MCPX))])]
6860
  "TARGET_MEDIA"
6861
  "operands[4] = GEN_INT (FRV_BUILTIN_MCPXIU);")
6862
 
6863
(define_insn "*mcpx"
6864
  [(parallel [(set (match_operand:SI 0 "acc_operand" "=a")
6865
                   (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6866
                               (match_operand:SI 2 "fpr_operand" "f")
6867
                               (match_operand:SI 3 "const_int_operand" "n")]
6868
                              UNSPEC_MCPX))
6869
              (set (match_operand:QI 4 "accg_operand" "=B")
6870
                   (unspec:QI [(const_int 0)] UNSPEC_MCPX))])]
6871
  "TARGET_MEDIA"
6872
  "*
6873
{
6874
  switch (INTVAL (operands[3]))
6875
  {
6876
  default:                 break;
6877
  case FRV_BUILTIN_MCPXRS: return \"mcpxrs %1, %2, %0\";
6878
  case FRV_BUILTIN_MCPXRU: return \"mcpxru %1, %2, %0\";
6879
  case FRV_BUILTIN_MCPXIS: return \"mcpxis %1, %2, %0\";
6880
  case FRV_BUILTIN_MCPXIU: return \"mcpxiu %1, %2, %0\";
6881
  }
6882
 
6883
  fatal_insn (\"Bad media insn, mcpx\", insn);
6884
}"
6885
  [(set_attr "length" "4")
6886
   (set_attr "type" "mcpx")])
6887
 
6888
(define_insn "*cond_exec_mcpx"
6889
  [(cond_exec
6890
    (match_operator 0 "ccr_eqne_operator"
6891
                    [(match_operand 1 "cr_operand" "C")
6892
                     (const_int 0)])
6893
    (parallel [(set (match_operand:SI 2 "acc_operand" "=a")
6894
                    (unspec:SI [(match_operand:SI 3 "fpr_operand" "f")
6895
                                (match_operand:SI 4 "fpr_operand" "f")
6896
                                (match_operand:SI 5 "const_int_operand" "n")]
6897
                               UNSPEC_MCPX))
6898
               (set (match_operand:QI 6 "accg_operand" "=B")
6899
                    (unspec:QI [(const_int 0)] UNSPEC_MCPX))]))]
6900
  "TARGET_MEDIA"
6901
  "*
6902
{
6903
  switch (INTVAL (operands[5]))
6904
  {
6905
  default:                 break;
6906
  case FRV_BUILTIN_MCPXRS: return \"cmcpxrs %3, %4, %2, %1, %e0\";
6907
  case FRV_BUILTIN_MCPXRU: return \"cmcpxru %3, %4, %2, %1, %e0\";
6908
  case FRV_BUILTIN_MCPXIS: return \"cmcpxis %3, %4, %2, %1, %e0\";
6909
  case FRV_BUILTIN_MCPXIU: return \"cmcpxiu %3, %4, %2, %1, %e0\";
6910
  }
6911
 
6912
  fatal_insn (\"Bad media insn, cond_exec_mcpx\", insn);
6913
}"
6914
  [(set_attr "length" "4")
6915
   (set_attr "type" "mcpx")])
6916
 
6917
;; Quad complex number product-sum (halfword): type "mqcpx"
6918
 
6919
(define_expand "mqcpxrs"
6920
  [(parallel [(set (match_operand:DI 0 "even_acc_operand" "=b")
6921
                   (unspec:DI [(match_operand:DI 1 "fpr_operand" "f")
6922
                               (match_operand:DI 2 "fpr_operand" "f")
6923
                               (match_dup 4)]
6924
                              UNSPEC_MQCPX))
6925
              (set (match_operand:HI 3 "accg_operand" "=B")
6926
                   (unspec:HI [(const_int 0)] UNSPEC_MQCPX))])]
6927
  "TARGET_MEDIA"
6928
  "operands[4] = GEN_INT (FRV_BUILTIN_MQCPXRS);")
6929
 
6930
(define_expand "mqcpxru"
6931
  [(parallel [(set (match_operand:DI 0 "even_acc_operand" "=b")
6932
                   (unspec:DI [(match_operand:DI 1 "fpr_operand" "f")
6933
                               (match_operand:DI 2 "fpr_operand" "f")
6934
                               (match_dup 4)]
6935
                              UNSPEC_MQCPX))
6936
              (set (match_operand:HI 3 "accg_operand" "=B")
6937
                   (unspec:HI [(const_int 0)] UNSPEC_MQCPX))])]
6938
  "TARGET_MEDIA"
6939
  "operands[4] = GEN_INT (FRV_BUILTIN_MQCPXRU);")
6940
 
6941
(define_expand "mqcpxis"
6942
  [(parallel [(set (match_operand:DI 0 "even_acc_operand" "=b")
6943
                   (unspec:DI [(match_operand:DI 1 "fpr_operand" "f")
6944
                               (match_operand:DI 2 "fpr_operand" "f")
6945
                               (match_dup 4)]
6946
                              UNSPEC_MQCPX))
6947
              (set (match_operand:HI 3 "accg_operand" "=B")
6948
                   (unspec:HI [(const_int 0)] UNSPEC_MQCPX))])]
6949
  "TARGET_MEDIA"
6950
  "operands[4] = GEN_INT (FRV_BUILTIN_MQCPXIS);")
6951
 
6952
(define_expand "mqcpxiu"
6953
  [(parallel [(set (match_operand:DI 0 "even_acc_operand" "=b")
6954
                   (unspec:DI [(match_operand:DI 1 "fpr_operand" "f")
6955
                               (match_operand:DI 2 "fpr_operand" "f")
6956
                               (match_dup 4)]
6957
                              UNSPEC_MQCPX))
6958
              (set (match_operand:HI 3 "accg_operand" "=B")
6959
                   (unspec:HI [(const_int 0)] UNSPEC_MQCPX))])]
6960
  "TARGET_MEDIA"
6961
  "operands[4] = GEN_INT (FRV_BUILTIN_MQCPXIU);")
6962
 
6963
(define_insn "*mqcpx"
6964
  [(set (match_operand:DI 0 "even_acc_operand" "=b")
6965
        (unspec:DI [(match_operand:DI 1 "fpr_operand" "f")
6966
                    (match_operand:DI 2 "fpr_operand" "f")
6967
                    (match_operand:SI 3 "const_int_operand" "n")]
6968
                   UNSPEC_MQCPX))
6969
   (set (match_operand:HI 4 "accg_operand" "=B")
6970
        (unspec:HI [(const_int 0)] UNSPEC_MQCPX))]
6971
  "TARGET_MEDIA"
6972
  "*
6973
{
6974
  switch (INTVAL (operands[3]))
6975
  {
6976
  default:                  break;
6977
  case FRV_BUILTIN_MQCPXRS: return \"mqcpxrs %1, %2, %0\";
6978
  case FRV_BUILTIN_MQCPXRU: return \"mqcpxru %1, %2, %0\";
6979
  case FRV_BUILTIN_MQCPXIS: return \"mqcpxis %1, %2, %0\";
6980
  case FRV_BUILTIN_MQCPXIU: return \"mqcpxiu %1, %2, %0\";
6981
  }
6982
 
6983
  fatal_insn (\"Bad media insn, mqcpx\", insn);
6984
}"
6985
  [(set_attr "length" "4")
6986
   (set_attr "type" "mqcpx")])
6987
 
6988
;; Cut: type "mcut"
6989
 
6990
(define_expand "mcut"
6991
  [(set (match_operand:SI 0 "fpr_operand" "=f")
6992
        (unspec:SI [(match_operand:SI 1 "acc_operand" "a")
6993
                    (match_operand:SI 2 "fpr_or_int6_operand" "fI")
6994
                    (match_operand:QI 3 "accg_operand" "B")
6995
                    (match_dup 4)]
6996
                   UNSPEC_MCUT))]
6997
  "TARGET_MEDIA"
6998
  "operands[4] = GEN_INT (FRV_BUILTIN_MCUT);")
6999
 
7000
(define_expand "mcutss"
7001
  [(set (match_operand:SI 0 "fpr_operand" "=f")
7002
        (unspec:SI [(match_operand:SI 1 "acc_operand" "a")
7003
                    (match_operand:SI 2 "fpr_or_int6_operand" "fI")
7004
                    (match_operand:QI 3 "accg_operand" "B")
7005
                    (match_dup 4)]
7006
                   UNSPEC_MCUT))]
7007
  "TARGET_MEDIA"
7008
  "operands[4] = GEN_INT (FRV_BUILTIN_MCUTSS);")
7009
 
7010
(define_insn "*mcut"
7011
  [(set (match_operand:SI 0 "fpr_operand" "=f")
7012
        (unspec:SI [(match_operand:SI 1 "acc_operand" "a")
7013
                    (match_operand:SI 2 "fpr_or_int6_operand" "fI")
7014
                    (match_operand:QI 3 "accg_operand" "B")
7015
                    (match_operand:SI 4 "const_int_operand" "n")]
7016
                   UNSPEC_MCUT))]
7017
  "TARGET_MEDIA"
7018
  "*
7019
{
7020
  switch (INTVAL (operands[4]))
7021
  {
7022
  default:                 break;
7023
  case FRV_BUILTIN_MCUT:   return \"mcut%i2 %1, %2, %0\";
7024
  case FRV_BUILTIN_MCUTSS: return \"mcutss%i2 %1, %2, %0\";
7025
  }
7026
 
7027
  fatal_insn (\"Bad media insn, mcut\", insn);
7028
}"
7029
  [(set_attr "length" "4")
7030
   (set_attr "type" "mcut")])
7031
 
7032
;; Accumulator read: type "mrdacc"
7033
 
7034
(define_insn "mrdacc"
7035
  [(set (match_operand:SI 0 "fpr_operand" "=f")
7036
        (unspec:SI [(match_operand:SI 1 "acc_operand" "a")] UNSPEC_MRDACC))]
7037
  "TARGET_MEDIA"
7038
  "mrdacc %1, %0"
7039
  [(set_attr "length" "4")
7040
   (set_attr "type" "mrdacc")])
7041
 
7042
(define_insn "mrdaccg"
7043
  [(set (match_operand:SI 0 "fpr_operand" "=f")
7044
        (unspec:SI [(match_operand:QI 1 "accg_operand" "B")] UNSPEC_MRDACCG))]
7045
  "TARGET_MEDIA"
7046
  "mrdaccg %1, %0"
7047
  [(set_attr "length" "4")
7048
   (set_attr "type" "mrdacc")])
7049
 
7050
;; Accumulator write: type "mwtacc"
7051
 
7052
(define_insn "mwtacc"
7053
  [(set (match_operand:SI 0 "acc_operand" "=a")
7054
        (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")] UNSPEC_MWTACC))]
7055
  "TARGET_MEDIA"
7056
  "mwtacc %1, %0"
7057
  [(set_attr "length" "4")
7058
   (set_attr "type" "mwtacc")])
7059
 
7060
(define_insn "mwtaccg"
7061
  [(set (match_operand:QI 0 "accg_operand" "=B")
7062
        (unspec:QI [(match_operand:SI 1 "fpr_operand" "f")] UNSPEC_MWTACCG))]
7063
  "TARGET_MEDIA"
7064
  "mwtaccg %1, %0"
7065
  [(set_attr "length" "4")
7066
   (set_attr "type" "mwtacc")])
7067
 
7068
;; Trap: This one executes on the control unit, not the media units.
7069
 
7070
(define_insn "mtrap"
7071
  [(unspec_volatile [(const_int 0)] UNSPEC_MTRAP)]
7072
  "TARGET_MEDIA"
7073
  "mtrap"
7074
  [(set_attr "length" "4")
7075
   (set_attr "type" "trap")])
7076
 
7077
;; Clear single accumulator: type "mclracc"
7078
 
7079
(define_insn "mclracc_internal"
7080
  [(set (match_operand:SI 0 "acc_operand" "=a")
7081
        (unspec:SI [(const_int 0)] UNSPEC_MCLRACC))
7082
   (set (match_operand:QI 1 "accg_operand" "=B")
7083
        (unspec:QI [(const_int 0)] UNSPEC_MCLRACC))]
7084
  "TARGET_MEDIA"
7085
  "mclracc %0,#0"
7086
  [(set_attr "length" "4")
7087
   (set_attr "type" "mclracc")])
7088
 
7089
(define_expand "mclracc"
7090
  [(parallel [(set (match_operand:SI 0 "acc_operand" "=a")
7091
                   (unspec:SI [(const_int 0)] UNSPEC_MCLRACC))
7092
              (set (match_dup 1)
7093
                   (unspec:QI [(const_int 0)] UNSPEC_MCLRACC))])]
7094
  "TARGET_MEDIA"
7095
  "
7096
{
7097
  if (GET_CODE (operands[0]) != REG || !ACC_P (REGNO (operands[0])))
7098
    FAIL;
7099
 
7100
  operands[1] = frv_matching_accg_for_acc (operands[0]);
7101
}")
7102
 
7103
;; Clear all accumulators: type "mclracca"
7104
 
7105
(define_insn "mclracca8_internal"
7106
  [(set (match_operand:V4SI 0 "quad_acc_operand" "=b")
7107
        (unspec:V4SI [(const_int 0)] UNSPEC_MCLRACCA))
7108
   (set (match_operand:V4SI 1 "quad_acc_operand" "=b")
7109
        (unspec:V4SI [(const_int 0)] UNSPEC_MCLRACCA))
7110
   (set (match_operand:V4QI 2 "accg_operand" "=B")
7111
        (unspec:V4QI [(const_int 0)] UNSPEC_MCLRACCA))
7112
   (set (match_operand:V4QI 3 "accg_operand" "=B")
7113
        (unspec:V4QI [(const_int 0)] UNSPEC_MCLRACCA))]
7114
  "TARGET_MEDIA && TARGET_ACC_8"
7115
  "mclracc acc0,#1"
7116
  [(set_attr "length" "4")
7117
   (set_attr "type" "mclracca")])
7118
 
7119
(define_insn "mclracca4_internal"
7120
  [(set (match_operand:V4SI 0 "quad_acc_operand" "=b")
7121
        (unspec:V4SI [(const_int 0)] UNSPEC_MCLRACCA))
7122
   (set (match_operand:V4QI 1 "accg_operand" "=B")
7123
        (unspec:V4QI [(const_int 0)] UNSPEC_MCLRACCA))]
7124
  "TARGET_MEDIA && TARGET_ACC_4"
7125
  "mclracc acc0,#1"
7126
  [(set_attr "length" "4")
7127
   (set_attr "type" "mclracca")])
7128
 
7129
(define_expand "mclracca8"
7130
  [(parallel [(set (match_dup 0) (unspec:V4SI [(const_int 0)] UNSPEC_MCLRACCA))
7131
              (set (match_dup 1) (unspec:V4SI [(const_int 0)] UNSPEC_MCLRACCA))
7132
              (set (match_dup 2) (unspec:V4QI [(const_int 0)] UNSPEC_MCLRACCA))
7133
              (set (match_dup 3) (unspec:V4QI [(const_int 0)] UNSPEC_MCLRACCA))])]
7134
  "TARGET_MEDIA && TARGET_ACC_8"
7135
  "
7136
{
7137
  operands[0] = gen_rtx_REG (V4SImode, ACC_FIRST);
7138
  operands[1] = gen_rtx_REG (V4SImode, ACC_FIRST + (~3 & ACC_MASK));
7139
  operands[2] = gen_rtx_REG (V4QImode, ACCG_FIRST);
7140
  operands[3] = gen_rtx_REG (V4QImode, ACCG_FIRST + (~3 & ACC_MASK));
7141
}")
7142
 
7143
(define_expand "mclracca4"
7144
  [(parallel [(set (match_dup 0) (unspec:V4SI [(const_int 0)] UNSPEC_MCLRACCA))
7145
              (set (match_dup 1) (unspec:V4QI [(const_int 0)] UNSPEC_MCLRACCA))])]
7146
  "TARGET_MEDIA && TARGET_ACC_4"
7147
  "
7148
{
7149
  operands[0] = gen_rtx_REG (V4SImode, ACC_FIRST);
7150
  operands[1] = gen_rtx_REG (V4QImode, ACCG_FIRST);
7151
}")
7152
 
7153
(define_insn "mcop1"
7154
  [(set (match_operand:SI 0 "fpr_operand" "=f")
7155
        (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
7156
                    (match_operand:SI 2 "fpr_operand" "f")] UNSPEC_MCOP1))]
7157
  "TARGET_MEDIA_REV1"
7158
  "mcop1 %1, %2, %0"
7159
  [(set_attr "length" "4")
7160
;; What is the class of the insn ???
7161
   (set_attr "type" "multi")])
7162
 
7163
(define_insn "mcop2"
7164
  [(set (match_operand:SI 0 "fpr_operand" "=f")
7165
        (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
7166
                    (match_operand:SI 2 "fpr_operand" "f")] UNSPEC_MCOP2))]
7167
  "TARGET_MEDIA_REV1"
7168
  "mcop2 %1, %2, %0"
7169
  [(set_attr "length" "4")
7170
;; What is the class of the insn ???
7171
   (set_attr "type" "multi")])
7172
 
7173
(define_insn "*mdunpackh_internal"
7174
  [(set (match_operand:V4SI 0 "quad_fpr_operand" "=x")
7175
        (unspec:V4SI [(match_operand:DI 1 "even_fpr_operand" "h")]
7176
                     UNSPEC_MDUNPACKH_INTERNAL))]
7177
  "TARGET_MEDIA_REV1"
7178
  "mdunpackh %1, %0"
7179
  [(set_attr "length" "4")
7180
   (set_attr "type" "mdunpackh")])
7181
 
7182
(define_insn_and_split "mdunpackh"
7183
  [(set (match_operand:V4SI 0 "memory_operand" "=o")
7184
        (unspec:V4SI [(match_operand:DI 1 "even_fpr_operand" "h")]
7185
                     UNSPEC_MDUNPACKH))
7186
   (clobber (match_scratch:V4SI 2 "=x"))]
7187
  "TARGET_MEDIA_REV1"
7188
  "#"
7189
  "reload_completed"
7190
  [(set (match_dup 2)
7191
        (unspec:V4SI [(match_dup 1)] UNSPEC_MDUNPACKH_INTERNAL))
7192
   (set (match_dup 3)
7193
        (match_dup 4))
7194
   (set (match_dup 5)
7195
        (match_dup 6))]
7196
  "
7197
{
7198
  operands[3] = change_address (operands[0], DImode, NULL_RTX);
7199
  operands[4] = gen_rtx_REG (DImode, REGNO (operands[2]));
7200
  operands[5] = frv_index_memory (operands[0], DImode, 1);
7201
  operands[6] = gen_rtx_REG (DImode, REGNO (operands[2])+2);
7202
}"
7203
  [(set_attr "length" "20")
7204
   (set_attr "type" "multi")])
7205
 
7206
(define_insn "*mbtohe_internal"
7207
  [(set (match_operand:V4SI 0 "quad_fpr_operand" "=x")
7208
        (unspec:V4SI [(match_operand:SI 1 "fpr_operand" "f")]
7209
                     UNSPEC_MBTOHE_INTERNAL))]
7210
  "TARGET_MEDIA_REV1"
7211
  "mbtohe %1, %0"
7212
  [(set_attr "length" "4")
7213
   (set_attr "type" "mbhconve")])
7214
 
7215
(define_insn_and_split "mbtohe"
7216
  [(set (match_operand:V4SI 0 "memory_operand" "=o")
7217
        (unspec:V4SI [(match_operand:SI 1 "fpr_operand" "f")]
7218
                     UNSPEC_MBTOHE))
7219
   (clobber (match_scratch:V4SI 2 "=x"))]
7220
  "TARGET_MEDIA_REV1"
7221
  "#"
7222
  "reload_completed"
7223
  [(set (match_dup 2)
7224
        (unspec:V4SI [(match_dup 1)] UNSPEC_MBTOHE_INTERNAL))
7225
   (set (match_dup 3)
7226
        (match_dup 4))
7227
   (set (match_dup 5)
7228
        (match_dup 6))]
7229
  "
7230
{
7231
  operands[3] = change_address (operands[0], DImode, NULL_RTX);
7232
  operands[4] = gen_rtx_REG (DImode, REGNO (operands[2]));
7233
  operands[5] = frv_index_memory (operands[0], DImode, 1);
7234
  operands[6] = gen_rtx_REG (DImode, REGNO (operands[2])+2);
7235
}"
7236
  [(set_attr "length" "20")
7237
   (set_attr "type" "multi")])
7238
 
7239
;; Quad product-sum (halfword) instructions only found on the FR400.
7240
;; type "mqmach"
7241
 
7242
(define_expand "mqxmachs"
7243
  [(parallel [(set (match_operand:V4SI 0 "quad_acc_operand" "")
7244
                   (unspec:V4SI [(match_dup 0)
7245
                                 (match_operand:DI 1 "even_fpr_operand" "")
7246
                                 (match_operand:DI 2 "even_fpr_operand" "")
7247
                                 (match_operand:V4QI 3 "accg_operand" "")
7248
                                 (match_dup 4)]
7249
                                UNSPEC_MQMACH2))
7250
                (set (match_dup 3)
7251
                     (unspec:V4QI [(const_int 0)] UNSPEC_MQMACH2))])]
7252
  "TARGET_MEDIA_REV2"
7253
  "operands[4] = GEN_INT (FRV_BUILTIN_MQXMACHS);")
7254
 
7255
(define_expand "mqxmacxhs"
7256
  [(parallel [(set (match_operand:V4SI 0 "quad_acc_operand" "")
7257
                   (unspec:V4SI [(match_dup 0)
7258
                                 (match_operand:DI 1 "even_fpr_operand" "")
7259
                                 (match_operand:DI 2 "even_fpr_operand" "")
7260
                                 (match_operand:V4QI 3 "accg_operand" "")
7261
                                 (match_dup 4)]
7262
                                UNSPEC_MQMACH2))
7263
              (set (match_dup 3)
7264
                   (unspec:V4QI [(const_int 0)] UNSPEC_MQMACH2))])]
7265
  "TARGET_MEDIA_REV2"
7266
  "operands[4] = GEN_INT (FRV_BUILTIN_MQXMACXHS);")
7267
 
7268
(define_expand "mqmacxhs"
7269
  [(parallel [(set (match_operand:V4SI 0 "quad_acc_operand" "")
7270
                   (unspec:V4SI [(match_dup 0)
7271
                                 (match_operand:DI 1 "even_fpr_operand" "")
7272
                                 (match_operand:DI 2 "even_fpr_operand" "")
7273
                                 (match_operand:V4QI 3 "accg_operand" "")
7274
                                 (match_dup 4)]
7275
                                UNSPEC_MQMACH2))
7276
              (set (match_dup 3)
7277
                   (unspec:V4QI [(const_int 0)] UNSPEC_MQMACH2))])]
7278
  "TARGET_MEDIA_REV2"
7279
  "operands[4] = GEN_INT (FRV_BUILTIN_MQMACXHS);")
7280
 
7281
(define_insn "*mqmach2"
7282
  [(set (match_operand:V4SI 0 "quad_acc_operand" "+A")
7283
        (unspec:V4SI [(match_dup 0)
7284
                      (match_operand:DI 1 "even_fpr_operand" "h")
7285
                      (match_operand:DI 2 "even_fpr_operand" "h")
7286
                      (match_operand:V4QI 3 "accg_operand" "+B")
7287
                      (match_operand:SI 4 "const_int_operand" "n")]
7288
                     UNSPEC_MQMACH2))
7289
   (set (match_dup 3)
7290
        (unspec:V4QI [(const_int 0)] UNSPEC_MQMACH2))]
7291
  "TARGET_MEDIA_REV2"
7292
  "*
7293
{
7294
  switch (INTVAL (operands[4]))
7295
  {
7296
  default:                    break;
7297
  case FRV_BUILTIN_MQXMACHS:  return \"mqxmachs %1, %2, %0\";
7298
  case FRV_BUILTIN_MQXMACXHS: return \"mqxmacxhs %1, %2, %0\";
7299
  case FRV_BUILTIN_MQMACXHS:  return \"mqmacxhs %1, %2, %0\";
7300
  }
7301
 
7302
  fatal_insn (\"Bad media insn, mqmach2\", insn);
7303
}"
7304
  [(set_attr "length" "4")
7305
   (set_attr "type" "mqmach")])
7306
 
7307
;; Accumulator addition/subtraction: type "maddacc"
7308
 
7309
(define_expand "maddaccs"
7310
  [(parallel [(set (match_operand:SI 0 "acc_operand" "")
7311
                   (unspec:SI [(match_operand:DI 1 "even_acc_operand" "")]
7312
                              UNSPEC_MADDACC))
7313
              (set (match_operand:QI 2 "accg_operand" "")
7314
                   (unspec:QI [(match_operand:HI 3 "accg_operand" "")
7315
                               (match_dup 4)]
7316
                              UNSPEC_MADDACC))])]
7317
  "TARGET_MEDIA_REV2"
7318
  "operands[4] = GEN_INT (FRV_BUILTIN_MADDACCS);")
7319
 
7320
(define_expand "msubaccs"
7321
  [(parallel [(set (match_operand:SI 0 "acc_operand" "")
7322
                   (unspec:SI [(match_operand:DI 1 "even_acc_operand" "")]
7323
                              UNSPEC_MADDACC))
7324
              (set (match_operand:QI 2 "accg_operand" "")
7325
                   (unspec:QI [(match_operand:HI 3 "accg_operand" "")
7326
                               (match_dup 4)]
7327
                              UNSPEC_MADDACC))])]
7328
  "TARGET_MEDIA_REV2"
7329
  "operands[4] = GEN_INT (FRV_BUILTIN_MSUBACCS);")
7330
 
7331
(define_insn "masaccs"
7332
  [(set (match_operand:DI 0 "even_acc_operand" "=b")
7333
        (unspec:DI [(match_operand:DI 1 "even_acc_operand" "b")]
7334
                   UNSPEC_MASACCS))
7335
   (set (match_operand:HI 2 "accg_operand" "=B")
7336
        (unspec:HI [(match_operand:HI 3 "accg_operand" "B")]
7337
                   UNSPEC_MASACCS))]
7338
  "TARGET_MEDIA_REV2"
7339
  "masaccs %1, %0"
7340
  [(set_attr "length" "4")
7341
   (set_attr "type" "maddacc")])
7342
 
7343
(define_insn "*maddacc"
7344
  [(set (match_operand:SI 0 "acc_operand" "=a")
7345
        (unspec:SI [(match_operand:DI 1 "even_acc_operand" "b")]
7346
                   UNSPEC_MADDACC))
7347
   (set (match_operand:QI 2 "accg_operand" "=B")
7348
        (unspec:QI [(match_operand:HI 3 "accg_operand" "B")
7349
                    (match_operand:SI 4 "const_int_operand" "n")]
7350
                   UNSPEC_MADDACC))]
7351
  "TARGET_MEDIA_REV2"
7352
  "*
7353
{
7354
  switch (INTVAL (operands[4]))
7355
  {
7356
  default:                   break;
7357
  case FRV_BUILTIN_MADDACCS: return \"maddaccs %1, %0\";
7358
  case FRV_BUILTIN_MSUBACCS: return \"msubaccs %1, %0\";
7359
  }
7360
 
7361
  fatal_insn (\"Bad media insn, maddacc\", insn);
7362
}"
7363
  [(set_attr "length" "4")
7364
   (set_attr "type" "maddacc")])
7365
 
7366
;; Dual accumulator addition/subtraction: type "mdaddacc"
7367
 
7368
(define_expand "mdaddaccs"
7369
  [(parallel [(set (match_operand:DI 0 "even_acc_operand" "")
7370
                   (unspec:DI [(match_operand:V4SI 1 "quad_acc_operand" "")]
7371
                              UNSPEC_MDADDACC))
7372
              (set (match_operand:HI 2 "accg_operand" "")
7373
                   (unspec:HI [(match_operand:V4QI 3 "accg_operand" "")
7374
                               (match_dup 4)]
7375
                              UNSPEC_MDADDACC))])]
7376
  "TARGET_MEDIA_REV2"
7377
  "operands[4] = GEN_INT (FRV_BUILTIN_MDADDACCS);")
7378
 
7379
(define_expand "mdsubaccs"
7380
  [(parallel [(set (match_operand:DI 0 "even_acc_operand" "")
7381
                   (unspec:DI [(match_operand:V4SI 1 "quad_acc_operand" "")]
7382
                              UNSPEC_MDADDACC))
7383
              (set (match_operand:HI 2 "accg_operand" "")
7384
                   (unspec:HI [(match_operand:V4QI 3 "accg_operand" "")
7385
                               (match_dup 4)]
7386
                              UNSPEC_MDADDACC))])]
7387
  "TARGET_MEDIA_REV2"
7388
  "operands[4] = GEN_INT (FRV_BUILTIN_MDSUBACCS);")
7389
 
7390
(define_insn "mdasaccs"
7391
  [(set (match_operand:V4SI 0 "quad_acc_operand" "=A")
7392
        (unspec:V4SI [(match_operand:V4SI 1 "quad_acc_operand" "A")]
7393
                     UNSPEC_MDASACCS))
7394
   (set (match_operand:V4QI 2 "accg_operand" "=B")
7395
        (unspec:V4QI [(match_operand:V4QI 3 "accg_operand" "B")]
7396
                     UNSPEC_MDASACCS))]
7397
  "TARGET_MEDIA_REV2"
7398
  "mdasaccs %1, %0"
7399
  [(set_attr "length" "4")
7400
   (set_attr "type" "mdaddacc")])
7401
 
7402
(define_insn "*mdaddacc"
7403
  [(set (match_operand:DI 0 "even_acc_operand" "=b")
7404
        (unspec:DI [(match_operand:V4SI 1 "quad_acc_operand" "A")]
7405
                   UNSPEC_MDADDACC))
7406
   (set (match_operand:HI 2 "accg_operand" "=B")
7407
        (unspec:HI [(match_operand:V4QI 3 "accg_operand" "B")
7408
                    (match_operand:SI 4 "const_int_operand" "n")]
7409
                   UNSPEC_MDADDACC))]
7410
  "TARGET_MEDIA_REV2"
7411
  "*
7412
{
7413
  switch (INTVAL (operands[4]))
7414
  {
7415
  default:                    break;
7416
  case FRV_BUILTIN_MDADDACCS: return \"mdaddaccs %1, %0\";
7417
  case FRV_BUILTIN_MDSUBACCS: return \"mdsubaccs %1, %0\";
7418
  }
7419
 
7420
  fatal_insn (\"Bad media insn, mdaddacc\", insn);
7421
}"
7422
  [(set_attr "length" "4")
7423
   (set_attr "type" "mdaddacc")])
7424
 
7425
;; Dual absolute (halfword): type "mabsh"
7426
 
7427
(define_insn "mabshs"
7428
  [(set (match_operand:SI 0 "fpr_operand" "=f")
7429
        (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")] UNSPEC_MABSHS))]
7430
  "TARGET_MEDIA_REV2"
7431
  "mabshs %1, %0"
7432
  [(set_attr "length" "4")
7433
   (set_attr "type" "mabsh")])
7434
 
7435
;; Dual rotate: type "mdrot"
7436
 
7437
(define_insn "mdrotli"
7438
  [(set (match_operand:DI 0 "even_fpr_operand" "=h")
7439
        (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
7440
                    (match_operand:SI 2 "uint5_operand" "I")]
7441
                   UNSPEC_MDROTLI))]
7442
  "TARGET_MEDIA_REV2"
7443
  "mdrotli %1, %2, %0"
7444
  [(set_attr "length" "4")
7445
   (set_attr "type" "mdrot")])
7446
 
7447
;; Dual coupling (concatenation): type "mcpl"
7448
 
7449
(define_insn "mcplhi"
7450
  [(set (match_operand:SI 0 "fpr_operand" "=f")
7451
        (unspec:SI [(match_operand:DI 1 "fpr_operand" "h")
7452
                    (match_operand:SI 2 "uint4_operand" "I")]
7453
                   UNSPEC_MCPLHI))]
7454
  "TARGET_MEDIA_REV2"
7455
  "mcplhi %1, %2, %0"
7456
  [(set_attr "length" "4")
7457
   (set_attr "type" "mcpl")])
7458
 
7459
(define_insn "mcpli"
7460
  [(set (match_operand:SI 0 "fpr_operand" "=f")
7461
        (unspec:SI [(match_operand:DI 1 "fpr_operand" "h")
7462
                    (match_operand:SI 2 "uint5_operand" "I")]
7463
                   UNSPEC_MCPLI))]
7464
  "TARGET_MEDIA_REV2"
7465
  "mcpli %1, %2, %0"
7466
  [(set_attr "length" "4")
7467
   (set_attr "type" "mcpl")])
7468
 
7469
;; Dual cut: type "mdcut"
7470
 
7471
(define_insn "mdcutssi"
7472
  [(set (match_operand:DI 0 "even_fpr_operand" "=h")
7473
        (unspec:DI [(match_operand:DI 1 "even_acc_operand" "b")
7474
                    (match_operand:SI 2 "int6_operand" "I")
7475
                    (match_operand:HI 3 "accg_operand" "B")]
7476
                   UNSPEC_MDCUTSSI))]
7477
  "TARGET_MEDIA_REV2"
7478
  "mdcutssi %1, %2, %0"
7479
  [(set_attr "length" "4")
7480
   (set_attr "type" "mdcut")])
7481
 
7482
;; Quad saturate (halfword): type "mqsath"
7483
 
7484
(define_insn "mqsaths"
7485
  [(set (match_operand:DI 0 "even_fpr_operand" "=h")
7486
        (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
7487
                    (match_operand:DI 2 "even_fpr_operand" "h")]
7488
                   UNSPEC_MQSATHS))]
7489
  "TARGET_MEDIA_REV2"
7490
  "mqsaths %1, %2, %0"
7491
  [(set_attr "length" "4")
7492
   (set_attr "type" "mqsath")])
7493
 
7494
;; Quad limit instructions: type "mqlimh"
7495
 
7496
(define_insn "mqlclrhs"
7497
  [(set (match_operand:DI 0 "even_fpr_operand" "=h")
7498
        (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
7499
                    (match_operand:DI 2 "even_fpr_operand" "h")]
7500
                   UNSPEC_MQLCLRHS))]
7501
  "TARGET_MEDIA_FR450"
7502
  "mqlclrhs %1, %2, %0"
7503
  [(set_attr "length" "4")
7504
   (set_attr "type" "mqlimh")])
7505
 
7506
(define_insn "mqlmths"
7507
  [(set (match_operand:DI 0 "even_fpr_operand" "=h")
7508
        (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
7509
                    (match_operand:DI 2 "even_fpr_operand" "h")]
7510
                   UNSPEC_MQLMTHS))]
7511
  "TARGET_MEDIA_FR450"
7512
  "mqlmths %1, %2, %0"
7513
  [(set_attr "length" "4")
7514
   (set_attr "type" "mqlimh")])
7515
 
7516
(define_insn "mqsllhi"
7517
  [(set (match_operand:DI 0 "even_fpr_operand" "=h")
7518
        (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
7519
                    (match_operand:SI 2 "int6_operand" "I")]
7520
                   UNSPEC_MQSLLHI))]
7521
  "TARGET_MEDIA_FR450"
7522
  "mqsllhi %1, %2, %0"
7523
  [(set_attr "length" "4")
7524
   (set_attr "type" "mqshift")])
7525
 
7526
(define_insn "mqsrahi"
7527
  [(set (match_operand:DI 0 "even_fpr_operand" "=h")
7528
        (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
7529
                    (match_operand:SI 2 "int6_operand" "I")]
7530
                   UNSPEC_MQSRAHI))]
7531
  "TARGET_MEDIA_FR450"
7532
  "mqsrahi %1, %2, %0"
7533
  [(set_attr "length" "4")
7534
   (set_attr "type" "mqshift")])
7535
 
7536
;; Set hi/lo instructions: type "mset"
7537
 
7538
(define_insn "mhsetlos"
7539
  [(set (match_operand:SI 0 "fpr_operand" "=f")
7540
        (unspec:SI [(match_operand:SI 1 "fpr_operand" "0")
7541
                    (match_operand:SI 2 "int12_operand" "NOP")]
7542
                   UNSPEC_MHSETLOS))]
7543
  "TARGET_MEDIA_REV2"
7544
  "mhsetlos %2, %0"
7545
  [(set_attr "length" "4")
7546
   (set_attr "type" "mset")])
7547
 
7548
(define_insn "mhsetloh"
7549
  [(set (match_operand:SI 0 "fpr_operand" "=f")
7550
        (unspec:SI [(match_operand:SI 1 "fpr_operand" "0")
7551
                    (match_operand:SI 2 "int5_operand" "I")]
7552
                   UNSPEC_MHSETLOH))]
7553
  "TARGET_MEDIA_REV2"
7554
  "mhsetloh %2, %0"
7555
  [(set_attr "length" "4")
7556
   (set_attr "type" "mset")])
7557
 
7558
(define_insn "mhsethis"
7559
  [(set (match_operand:SI 0 "fpr_operand" "=f")
7560
        (unspec:SI [(match_operand:SI 1 "fpr_operand" "0")
7561
                    (match_operand:SI 2 "int12_operand" "NOP")]
7562
                   UNSPEC_MHSETHIS))]
7563
  "TARGET_MEDIA_REV2"
7564
  "mhsethis %2, %0"
7565
  [(set_attr "length" "4")
7566
   (set_attr "type" "mset")])
7567
 
7568
(define_insn "mhsethih"
7569
  [(set (match_operand:SI 0 "fpr_operand" "=f")
7570
        (unspec:SI [(match_operand:SI 1 "fpr_operand" "0")
7571
                    (match_operand:SI 2 "int5_operand" "I")]
7572
                   UNSPEC_MHSETHIH))]
7573
  "TARGET_MEDIA_REV2"
7574
  "mhsethih %2, %0"
7575
  [(set_attr "length" "4")
7576
   (set_attr "type" "mset")])
7577
 
7578
(define_insn "mhdsets"
7579
  [(set (match_operand:SI 0 "fpr_operand" "=f")
7580
        (unspec:SI [(match_operand:SI 1 "int12_operand" "NOP")]
7581
                   UNSPEC_MHDSETS))]
7582
  "TARGET_MEDIA_REV2"
7583
  "mhdsets %1, %0"
7584
  [(set_attr "length" "4")
7585
   (set_attr "type" "mset")])
7586
 
7587
(define_insn "mhdseth"
7588
  [(set (match_operand:SI 0 "fpr_operand" "=f")
7589
        (unspec:SI [(match_operand:SI 1 "fpr_operand" "0")
7590
                    (match_operand:SI 2 "int5_operand" "I")]
7591
                   UNSPEC_MHDSETH))]
7592
  "TARGET_MEDIA_REV2"
7593
  "mhdseth %2, %0"
7594
  [(set_attr "length" "4")
7595
   (set_attr "type" "mset")])
7596
 
7597
;;-----------------------------------------------------------------------------
7598
 
7599
(define_expand "symGOT2reg"
7600
  [(match_operand:SI 0 "" "")
7601
   (match_operand:SI 1 "" "")
7602
   (match_operand:SI 2 "" "")
7603
   (match_operand:SI 3 "" "")]
7604
  ""
7605
  "
7606
{
7607
  rtx insn;
7608
 
7609
  insn = emit_insn (gen_symGOT2reg_i (operands[0], operands[1], operands[2], operands[3]));
7610
 
7611
  MEM_READONLY_P (SET_SRC (PATTERN (insn))) = 1;
7612
 
7613
  set_unique_reg_note (insn, REG_EQUAL, operands[1]);
7614
 
7615
  DONE;
7616
}")
7617
 
7618
(define_expand "symGOT2reg_i"
7619
  [(set (match_operand:SI 0 "" "")
7620
        (mem:SI (plus:SI (match_operand:SI 2 "" "")
7621
                         (const:SI (unspec:SI [(match_operand:SI 1 "" "")
7622
                                               (match_operand:SI 3 "" "")]
7623
                                              UNSPEC_GOT)))))]
7624
  ""
7625
  "")
7626
 
7627
(define_expand "symGOT2reg_hilo"
7628
  [(set (match_dup 6)
7629
        (high:SI (const:SI (unspec:SI [(match_operand:SI 1 "" "")
7630
                                       (match_dup 4)] UNSPEC_GOT))))
7631
   (set (match_dup 5)
7632
        (lo_sum:SI (match_dup 6)
7633
                   (const:SI (unspec:SI [(match_dup 1)
7634
                                         (match_operand:SI 3 "" "")]
7635
                                        UNSPEC_GOT))))
7636
   (set (match_operand:SI 0 "" "")
7637
        (mem:SI (plus:SI (match_dup 5)
7638
                         (match_operand:SI 2 "" ""))))
7639
   ]
7640
  ""
7641
  "
7642
{
7643
  if (!can_create_pseudo_p ())
7644
    operands[6] = operands[5] = operands[0];
7645
  else
7646
    {
7647
      operands[6] = gen_reg_rtx (SImode);
7648
      operands[5] = gen_reg_rtx (SImode);
7649
    }
7650
 
7651
  operands[4] = GEN_INT (INTVAL (operands[3]) + 1);
7652
  operands[3] = GEN_INT (INTVAL (operands[3]) + 2);
7653
}")
7654
 
7655
(define_expand "symGOTOFF2reg_hilo"
7656
  [(set (match_dup 6)
7657
        (high:SI (const:SI (unspec:SI [(match_operand:SI 1 "" "")
7658
                                       (match_dup 4)] UNSPEC_GOT))))
7659
   (set (match_dup 5)
7660
        (lo_sum:SI (match_dup 6)
7661
                   (const:SI (unspec:SI [(match_dup 1)
7662
                                         (match_operand:SI 3 "" "")]
7663
                                        UNSPEC_GOT))))
7664
   (set (match_operand:SI 0 "" "")
7665
        (plus:SI (match_dup 5)
7666
                 (match_operand:SI 2 "" "")))
7667
   ]
7668
  ""
7669
  "
7670
{
7671
  if (!can_create_pseudo_p ())
7672
    operands[6] = operands[5] = operands[0];
7673
  else
7674
    {
7675
      operands[6] = gen_reg_rtx (SImode);
7676
      operands[5] = gen_reg_rtx (SImode);
7677
    }
7678
 
7679
  operands[4] = GEN_INT (INTVAL (operands[3]) + 1);
7680
  operands[3] = GEN_INT (INTVAL (operands[3]) + 2);
7681
}")
7682
 
7683
(define_expand "symGOTOFF2reg"
7684
  [(match_operand:SI 0 "" "")
7685
   (match_operand:SI 1 "" "")
7686
   (match_operand:SI 2 "" "")
7687
   (match_operand:SI 3 "" "")]
7688
  ""
7689
  "
7690
{
7691
  rtx insn = emit_insn (gen_symGOTOFF2reg_i (operands[0], operands[1], operands[2], operands[3]));
7692
 
7693
  set_unique_reg_note (insn, REG_EQUAL, operands[1]);
7694
 
7695
  DONE;
7696
}")
7697
 
7698
(define_expand "symGOTOFF2reg_i"
7699
  [(set (match_operand:SI 0 "" "")
7700
        (plus:SI (match_operand:SI 2 "" "")
7701
                 (const:SI
7702
                  (unspec:SI [(match_operand:SI 1 "" "")
7703
                             (match_operand:SI 3 "" "")]
7704
                             UNSPEC_GOT))))]
7705
  ""
7706
  "")
7707
 
7708
(define_expand "symGPREL2reg"
7709
  [(match_operand:SI 0 "" "")
7710
   (match_operand:SI 1 "" "")
7711
   (match_operand:SI 2 "" "")
7712
   (match_operand:SI 3 "" "")
7713
   (match_dup 4)]
7714
  ""
7715
  "
7716
{
7717
  rtx insn;
7718
 
7719
  if (!can_create_pseudo_p ())
7720
    operands[4] = operands[0];
7721
  else
7722
    operands[4] = gen_reg_rtx (SImode);
7723
 
7724
  emit_insn (frv_gen_GPsym2reg (operands[4], operands[2]));
7725
 
7726
  insn = emit_insn (gen_symGOTOFF2reg_i (operands[0], operands[1],
7727
                                         operands[4], operands[3]));
7728
 
7729
  set_unique_reg_note (insn, REG_EQUAL, operands[1]);
7730
 
7731
  DONE;
7732
}")
7733
 
7734
(define_expand "symGPREL2reg_hilo"
7735
  [(match_operand:SI 0 "" "")
7736
   (match_operand:SI 1 "" "")
7737
   (match_operand:SI 2 "" "")
7738
   (match_operand:SI 3 "" "")
7739
   (match_dup 4)]
7740
  ""
7741
  "
7742
{
7743
  rtx insn;
7744
 
7745
  if (!can_create_pseudo_p ())
7746
    {
7747
      emit_insn (gen_symGOT2reg (operands[0], operands[1], operands[2],
7748
                                 GEN_INT (R_FRV_GOT12)));
7749
      DONE;
7750
    }
7751
 
7752
  operands[4] = gen_reg_rtx (SImode);
7753
 
7754
  emit_insn (frv_gen_GPsym2reg (operands[4], operands[2]));
7755
 
7756
  insn = emit_insn (gen_symGOTOFF2reg_hilo (operands[0], operands[1],
7757
                                            operands[4], operands[3]));
7758
 
7759
  set_unique_reg_note (insn, REG_EQUAL, operands[1]);
7760
 
7761
  DONE;
7762
}")
7763
 
7764
(define_constants
7765
  [
7766
   (UNSPEC_SMUL                 154)
7767
   (UNSPEC_UMUL                 155)
7768
   (UNSPEC_SMU                  156)
7769
   (UNSPEC_ADDSS                157)
7770
   (UNSPEC_SUBSS                158)
7771
   (UNSPEC_SLASS                159)
7772
   (UNSPEC_SCAN                 160)
7773
   (UNSPEC_INTSS                161)
7774
   (UNSPEC_SCUTSS               162)
7775
   (UNSPEC_PREFETCH0            163)
7776
   (UNSPEC_PREFETCH             164)
7777
   (UNSPEC_IACCreadll           165)
7778
   (UNSPEC_IACCreadl            166)
7779
   (UNSPEC_IACCsetll            167)
7780
   (UNSPEC_IACCsetl             168)
7781
   (UNSPEC_SMASS                169)
7782
   (UNSPEC_SMSSS                170)
7783
   (UNSPEC_IMUL                 171)
7784
 
7785
   (IACC0_REG                   171)
7786
])
7787
 
7788
(define_insn "smul"
7789
  [(set (match_operand:DI 0 "integer_register_operand" "=d")
7790
        (unspec:DI [(match_operand:SI 1 "integer_register_operand" "d")
7791
                    (match_operand:SI 2 "integer_register_operand" "d")]
7792
                   UNSPEC_SMUL))]
7793
  ""
7794
  "smul %1, %2, %0"
7795
  [(set_attr "length" "4")
7796
   (set_attr "type" "mul")])
7797
 
7798
(define_insn "umul"
7799
  [(set (match_operand:DI 0 "integer_register_operand" "=d")
7800
        (unspec:DI [(match_operand:SI 1 "integer_register_operand" "d")
7801
                    (match_operand:SI 2 "integer_register_operand" "d")]
7802
                   UNSPEC_UMUL))]
7803
  ""
7804
  "umul %1, %2, %0"
7805
  [(set_attr "length" "4")
7806
   (set_attr "type" "mul")])
7807
 
7808
(define_insn "smass"
7809
  [(set (reg:DI IACC0_REG)
7810
        (unspec:DI [(match_operand:SI 0 "integer_register_operand" "d")
7811
                    (match_operand:SI 1 "integer_register_operand" "d")
7812
                    (reg:DI IACC0_REG)]
7813
                   UNSPEC_SMASS))]
7814
  "TARGET_FR405_BUILTINS"
7815
  "smass %1, %0"
7816
  [(set_attr "length" "4")
7817
   (set_attr "type" "macc")])
7818
 
7819
(define_insn "smsss"
7820
  [(set (reg:DI IACC0_REG)
7821
        (unspec:DI [(match_operand:SI 0 "integer_register_operand" "d")
7822
                    (match_operand:SI 1 "integer_register_operand" "d")
7823
                    (reg:DI IACC0_REG)]
7824
                   UNSPEC_SMSSS))]
7825
  "TARGET_FR405_BUILTINS"
7826
  "smsss %1, %0"
7827
  [(set_attr "length" "4")
7828
   (set_attr "type" "macc")])
7829
 
7830
(define_insn "smu"
7831
  [(set (reg:DI IACC0_REG)
7832
        (unspec:DI [(match_operand:SI 0 "integer_register_operand" "d")
7833
                    (match_operand:SI 1 "integer_register_operand" "d")]
7834
                   UNSPEC_SMU))]
7835
  "TARGET_FR405_BUILTINS"
7836
  "smu %1, %0"
7837
  [(set_attr "length" "4")
7838
   (set_attr "type" "macc")])
7839
 
7840
(define_insn "addss"
7841
  [(set (match_operand:SI 0 "integer_register_operand" "=d")
7842
        (unspec:SI [(match_operand:SI 1 "integer_register_operand" "d")
7843
                    (match_operand:SI 2 "integer_register_operand" "d")]
7844
                   UNSPEC_ADDSS))]
7845
  "TARGET_FR405_BUILTINS"
7846
  "addss %1, %2, %0"
7847
  [(set_attr "length" "4")
7848
   (set_attr "type" "int")])
7849
 
7850
(define_insn "subss"
7851
  [(set (match_operand:SI 0 "integer_register_operand" "=d")
7852
        (unspec:SI [(match_operand:SI 1 "integer_register_operand" "d")
7853
                    (match_operand:SI 2 "integer_register_operand" "d")]
7854
                   UNSPEC_SUBSS))]
7855
  "TARGET_FR405_BUILTINS"
7856
  "subss %1, %2, %0"
7857
  [(set_attr "length" "4")
7858
   (set_attr "type" "int")])
7859
 
7860
(define_insn "slass"
7861
  [(set (match_operand:SI 0 "integer_register_operand" "=d")
7862
        (unspec:SI [(match_operand:SI 1 "integer_register_operand" "d")
7863
                    (match_operand:SI 2 "integer_register_operand" "d")]
7864
                   UNSPEC_SLASS))]
7865
  "TARGET_FR405_BUILTINS"
7866
  "slass %1, %2, %0"
7867
  [(set_attr "length" "4")
7868
   (set_attr "type" "int")])
7869
 
7870
(define_insn "scan"
7871
  [(set (match_operand:SI 0 "integer_register_operand" "=d")
7872
        (unspec:SI [(match_operand:SI 1 "integer_register_operand" "d")
7873
                    (match_operand:SI 2 "integer_register_operand" "d")]
7874
                   UNSPEC_SCAN))]
7875
  ""
7876
  "scan %1, %2, %0"
7877
  [(set_attr "length" "4")
7878
   (set_attr "type" "scan")])
7879
 
7880
(define_insn "scutss"
7881
  [(set (match_operand:SI 0 "integer_register_operand" "=d")
7882
        (unspec:SI [(match_operand:SI 1 "integer_register_operand" "d")
7883
                    (reg:DI IACC0_REG)]
7884
                   UNSPEC_SCUTSS))]
7885
  "TARGET_FR405_BUILTINS"
7886
  "scutss %1,%0"
7887
  [(set_attr "length" "4")
7888
   (set_attr "type" "cut")])
7889
 
7890
(define_insn "frv_prefetch0"
7891
  [(prefetch (unspec:SI [(match_operand:SI 0 "register_operand" "r")]
7892
                        UNSPEC_PREFETCH0)
7893
             (const_int 0)
7894
             (const_int 0))]
7895
  ""
7896
  "dcpl %0, gr0, #0"
7897
  [(set_attr "length" "4")])
7898
 
7899
(define_insn "frv_prefetch"
7900
  [(prefetch (unspec:SI [(match_operand:SI 0 "register_operand" "r")]
7901
                        UNSPEC_PREFETCH)
7902
             (const_int 0)
7903
             (const_int 0))]
7904
  "TARGET_FR500_FR550_BUILTINS"
7905
  "nop.p\\n\\tnldub @(%0, gr0), gr0"
7906
  [(set_attr "length" "8")])
7907
 
7908
;; TLS patterns
7909
 
7910
(define_insn "call_gettlsoff"
7911
  [(set (match_operand:SI 0 "register_operand" "=D09")
7912
        (unspec:SI
7913
         [(match_operand:SI 1 "symbolic_operand" "")]
7914
         UNSPEC_GETTLSOFF))
7915
   (clobber (reg:SI GR8_REG))
7916
   (clobber (reg:SI LRREG))
7917
   (use (match_operand:SI 2 "register_operand" "D15"))]
7918
  "HAVE_AS_TLS"
7919
  "call #gettlsoff(%a1)"
7920
  [(set_attr "length" "4")
7921
   (set_attr "type" "load_or_call")])
7922
 
7923
;; We have to expand this like a libcall (it sort of actually is)
7924
;; because otherwise sched may move, for example, an insn that sets up
7925
;; GR8 for a subsequence call before the *tls_indirect_call insn, and
7926
;; then reload won't be able to fix things up.
7927
(define_expand "tls_indirect_call"
7928
  [(set (reg:DI GR8_REG)
7929
        (match_operand:DI 2 "register_operand" ""))
7930
   (parallel
7931
    [(set (reg:SI GR9_REG)
7932
          (unspec:SI
7933
           [(match_operand:SI 1 "symbolic_operand" "")
7934
           (reg:DI GR8_REG)]
7935
           UNSPEC_TLS_INDIRECT_CALL))
7936
    (clobber (reg:SI GR8_REG))
7937
    (clobber (reg:SI LRREG))
7938
    (use (match_operand:SI 3 "register_operand" ""))])
7939
   (set (match_operand:SI 0 "register_operand" "")
7940
        (reg:SI GR9_REG))]
7941
  "HAVE_AS_TLS")
7942
 
7943
(define_insn "*tls_indirect_call"
7944
  [(set (reg:SI GR9_REG)
7945
        (unspec:SI
7946
         [(match_operand:SI 0 "symbolic_operand" "")
7947
          (reg:DI GR8_REG)]
7948
         UNSPEC_TLS_INDIRECT_CALL))
7949
   (clobber (reg:SI GR8_REG))
7950
   (clobber (reg:SI LRREG))
7951
   ;; If there was a way to represent the fact that we don't need GR9
7952
   ;; or GR15 to be set before this instruction (it could be in
7953
   ;; parallel), we could use it here.  This change wouldn't apply to
7954
   ;; call_gettlsoff, thought, since the linker may turn the latter
7955
   ;; into ldi @(gr15,offset),gr9.
7956
   (use (match_operand:SI 1 "register_operand" "D15"))]
7957
  "HAVE_AS_TLS"
7958
  "calll #gettlsoff(%a0)@(gr8,gr0)"
7959
  [(set_attr "length" "4")
7960
   (set_attr "type" "jumpl")])
7961
 
7962
(define_insn "tls_load_gottlsoff12"
7963
  [(set (match_operand:SI 0 "register_operand" "=r")
7964
        (unspec:SI
7965
         [(match_operand:SI 1 "symbolic_operand" "")
7966
          (match_operand:SI 2 "register_operand" "r")]
7967
         UNSPEC_TLS_LOAD_GOTTLSOFF12))]
7968
  "HAVE_AS_TLS"
7969
  "ldi @(%2, #gottlsoff12(%1)), %0"
7970
  [(set_attr "length" "4")])
7971
 
7972
(define_expand "tlsoff_hilo"
7973
  [(set (match_operand:SI 0 "register_operand" "=r")
7974
        (high:SI (const:SI (unspec:SI
7975
                            [(match_operand:SI 1 "symbolic_operand" "")
7976
                             (match_operand:SI 2 "immediate_operand" "n")]
7977
                            UNSPEC_GOT))))
7978
   (set (match_dup 0)
7979
        (lo_sum:SI (match_dup 0)
7980
                   (const:SI (unspec:SI [(match_dup 1)
7981
                                         (match_dup 3)] UNSPEC_GOT))))]
7982
  ""
7983
  "
7984
{
7985
  operands[3] = GEN_INT (INTVAL (operands[2]) + 1);
7986
}")
7987
 
7988
;; Just like movdi_ldd, but with relaxation annotations.
7989
(define_insn "tls_tlsdesc_ldd"
7990
  [(set (match_operand:DI 0 "register_operand" "=r")
7991
        (unspec:DI [(mem:DI (unspec:SI
7992
                             [(match_operand:SI 1 "register_operand" "r")
7993
                              (match_operand:SI 2 "register_operand" "r")
7994
                              (match_operand:SI 3 "symbolic_operand" "")]
7995
                             UNSPEC_TLS_TLSDESC_LDD_AUX))]
7996
                   UNSPEC_TLS_TLSDESC_LDD))]
7997
  ""
7998
  "ldd #tlsdesc(%a3)@(%1,%2), %0"
7999
  [(set_attr "length" "4")
8000
   (set_attr "type" "gload")])
8001
 
8002
(define_insn "tls_tlsoff_ld"
8003
  [(set (match_operand:SI 0 "register_operand" "=r")
8004
        (mem:SI (unspec:SI
8005
                 [(match_operand:SI 1 "register_operand" "r")
8006
                  (match_operand:SI 2 "register_operand" "r")
8007
                  (match_operand:SI 3 "symbolic_operand" "")]
8008
                 UNSPEC_TLS_TLSOFF_LD)))]
8009
  ""
8010
  "ld #tlsoff(%a3)@(%1,%2), %0"
8011
  [(set_attr "length" "4")
8012
   (set_attr "type" "gload")])
8013
 
8014
(define_insn "tls_lddi"
8015
  [(set (match_operand:DI 0 "register_operand" "=r")
8016
        (unspec:DI [(match_operand:SI 1 "symbolic_operand" "")
8017
                    (match_operand:SI 2 "register_operand" "d")]
8018
                   UNSPEC_TLS_LDDI))]
8019
  ""
8020
  "lddi @(%2, #gottlsdesc12(%a1)), %0"
8021
  [(set_attr "length" "4")
8022
   (set_attr "type" "gload")])

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