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[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [config/] [h8300/] [h8300.c] - Blame information for rev 709

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1 709 jeremybenn
/* Subroutines for insn-output.c for Renesas H8/300.
2
   Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3
   2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4
   Free Software Foundation, Inc.
5
   Contributed by Steve Chamberlain (sac@cygnus.com),
6
   Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
7
 
8
This file is part of GCC.
9
 
10
GCC is free software; you can redistribute it and/or modify
11
it under the terms of the GNU General Public License as published by
12
the Free Software Foundation; either version 3, or (at your option)
13
any later version.
14
 
15
GCC is distributed in the hope that it will be useful,
16
but WITHOUT ANY WARRANTY; without even the implied warranty of
17
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18
GNU General Public License for more details.
19
 
20
You should have received a copy of the GNU General Public License
21
along with GCC; see the file COPYING3.  If not see
22
<http://www.gnu.org/licenses/>.  */
23
 
24
#include "config.h"
25
#include "system.h"
26
#include "coretypes.h"
27
#include "tm.h"
28
#include "rtl.h"
29
#include "tree.h"
30
#include "regs.h"
31
#include "hard-reg-set.h"
32
#include "insn-config.h"
33
#include "conditions.h"
34
#include "output.h"
35
#include "insn-attr.h"
36
#include "flags.h"
37
#include "recog.h"
38
#include "expr.h"
39
#include "function.h"
40
#include "optabs.h"
41
#include "diagnostic-core.h"
42
#include "c-family/c-pragma.h"  /* ??? */
43
#include "tm_p.h"
44
#include "tm-constrs.h"
45
#include "ggc.h"
46
#include "target.h"
47
#include "target-def.h"
48
#include "df.h"
49
 
50
/* Classifies a h8300_src_operand or h8300_dst_operand.
51
 
52
   H8OP_IMMEDIATE
53
        A constant operand of some sort.
54
 
55
   H8OP_REGISTER
56
        An ordinary register.
57
 
58
   H8OP_MEM_ABSOLUTE
59
        A memory reference with a constant address.
60
 
61
   H8OP_MEM_BASE
62
        A memory reference with a register as its address.
63
 
64
   H8OP_MEM_COMPLEX
65
        Some other kind of memory reference.  */
66
enum h8300_operand_class
67
{
68
  H8OP_IMMEDIATE,
69
  H8OP_REGISTER,
70
  H8OP_MEM_ABSOLUTE,
71
  H8OP_MEM_BASE,
72
  H8OP_MEM_COMPLEX,
73
  NUM_H8OPS
74
};
75
 
76
/* For a general two-operand instruction, element [X][Y] gives
77
   the length of the opcode fields when the first operand has class
78
   (X + 1) and the second has class Y.  */
79
typedef unsigned char h8300_length_table[NUM_H8OPS - 1][NUM_H8OPS];
80
 
81
/* Forward declarations.  */
82
static const char *byte_reg (rtx, int);
83
static int h8300_interrupt_function_p (tree);
84
static int h8300_saveall_function_p (tree);
85
static int h8300_monitor_function_p (tree);
86
static int h8300_os_task_function_p (tree);
87
static void h8300_emit_stack_adjustment (int, HOST_WIDE_INT, bool);
88
static HOST_WIDE_INT round_frame_size (HOST_WIDE_INT);
89
static unsigned int compute_saved_regs (void);
90
static const char *cond_string (enum rtx_code);
91
static unsigned int h8300_asm_insn_count (const char *);
92
static tree h8300_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
93
static tree h8300_handle_eightbit_data_attribute (tree *, tree, tree, int, bool *);
94
static tree h8300_handle_tiny_data_attribute (tree *, tree, tree, int, bool *);
95
static void h8300_print_operand_address (FILE *, rtx);
96
static void h8300_print_operand (FILE *, rtx, int);
97
static bool h8300_print_operand_punct_valid_p (unsigned char code);
98
#ifndef OBJECT_FORMAT_ELF
99
static void h8300_asm_named_section (const char *, unsigned int, tree);
100
#endif
101
static int h8300_register_move_cost (enum machine_mode, reg_class_t, reg_class_t);
102
static int h8300_and_costs (rtx);
103
static int h8300_shift_costs (rtx);
104
static void          h8300_push_pop               (int, int, bool, bool);
105
static int           h8300_stack_offset_p         (rtx, int);
106
static int           h8300_ldm_stm_regno          (rtx, int, int, int);
107
static void          h8300_reorg                  (void);
108
static unsigned int  h8300_constant_length        (rtx);
109
static unsigned int  h8300_displacement_length    (rtx, int);
110
static unsigned int  h8300_classify_operand       (rtx, int, enum h8300_operand_class *);
111
static unsigned int  h8300_length_from_table      (rtx, rtx, const h8300_length_table *);
112
static unsigned int  h8300_unary_length           (rtx);
113
static unsigned int  h8300_short_immediate_length (rtx);
114
static unsigned int  h8300_bitfield_length        (rtx, rtx);
115
static unsigned int  h8300_binary_length          (rtx, const h8300_length_table *);
116
static bool          h8300_short_move_mem_p       (rtx, enum rtx_code);
117
static unsigned int  h8300_move_length            (rtx *, const h8300_length_table *);
118
static bool          h8300_hard_regno_scratch_ok  (unsigned int);
119
static rtx           h8300_get_index (rtx, enum machine_mode mode, int *);
120
 
121
/* CPU_TYPE, says what cpu we're compiling for.  */
122
int cpu_type;
123
 
124
/* True if a #pragma interrupt has been seen for the current function.  */
125
static int pragma_interrupt;
126
 
127
/* True if a #pragma saveall has been seen for the current function.  */
128
static int pragma_saveall;
129
 
130
static const char *const names_big[] =
131
{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
132
 
133
static const char *const names_extended[] =
134
{ "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
135
 
136
static const char *const names_upper_extended[] =
137
{ "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
138
 
139
/* Points to one of the above.  */
140
/* ??? The above could be put in an array indexed by CPU_TYPE.  */
141
const char * const *h8_reg_names;
142
 
143
/* Various operations needed by the following, indexed by CPU_TYPE.  */
144
 
145
const char *h8_push_op, *h8_pop_op, *h8_mov_op;
146
 
147
/* Value of MOVE_RATIO.  */
148
int h8300_move_ratio;
149
 
150
/* See below where shifts are handled for explanation of this enum.  */
151
 
152
enum shift_alg
153
{
154
  SHIFT_INLINE,
155
  SHIFT_ROT_AND,
156
  SHIFT_SPECIAL,
157
  SHIFT_LOOP
158
};
159
 
160
/* Symbols of the various shifts which can be used as indices.  */
161
 
162
enum shift_type
163
{
164
  SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
165
};
166
 
167
/* Macros to keep the shift algorithm tables small.  */
168
#define INL SHIFT_INLINE
169
#define ROT SHIFT_ROT_AND
170
#define LOP SHIFT_LOOP
171
#define SPC SHIFT_SPECIAL
172
 
173
/* The shift algorithms for each machine, mode, shift type, and shift
174
   count are defined below.  The three tables below correspond to
175
   QImode, HImode, and SImode, respectively.  Each table is organized
176
   by, in the order of indices, machine, shift type, and shift count.  */
177
 
178
static enum shift_alg shift_alg_qi[3][3][8] = {
179
  {
180
    /* TARGET_H8300  */
181
    /* 0    1    2    3    4    5    6    7  */
182
    { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT   */
183
    { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
184
    { INL, INL, INL, INL, INL, LOP, LOP, SPC }  /* SHIFT_ASHIFTRT */
185
  },
186
  {
187
    /* TARGET_H8300H  */
188
    /* 0    1    2    3    4    5    6    7  */
189
    { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT   */
190
    { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
191
    { INL, INL, INL, INL, INL, LOP, LOP, SPC }  /* SHIFT_ASHIFTRT */
192
  },
193
  {
194
    /* TARGET_H8300S  */
195
    /*  0    1    2    3    4    5    6    7  */
196
    { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT   */
197
    { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */
198
    { INL, INL, INL, INL, INL, INL, INL, SPC }  /* SHIFT_ASHIFTRT */
199
  }
200
};
201
 
202
static enum shift_alg shift_alg_hi[3][3][16] = {
203
  {
204
    /* TARGET_H8300  */
205
    /*  0    1    2    3    4    5    6    7  */
206
    /*  8    9   10   11   12   13   14   15  */
207
    { INL, INL, INL, INL, INL, INL, INL, SPC,
208
      SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT   */
209
    { INL, INL, INL, INL, INL, LOP, LOP, SPC,
210
      SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
211
    { INL, INL, INL, INL, INL, LOP, LOP, SPC,
212
      SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
213
  },
214
  {
215
    /* TARGET_H8300H  */
216
    /*  0    1    2    3    4    5    6    7  */
217
    /*  8    9   10   11   12   13   14   15  */
218
    { INL, INL, INL, INL, INL, INL, INL, SPC,
219
      SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT   */
220
    { INL, INL, INL, INL, INL, INL, INL, SPC,
221
      SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
222
    { INL, INL, INL, INL, INL, INL, INL, SPC,
223
      SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
224
  },
225
  {
226
    /* TARGET_H8300S  */
227
    /*  0    1    2    3    4    5    6    7  */
228
    /*  8    9   10   11   12   13   14   15  */
229
    { INL, INL, INL, INL, INL, INL, INL, INL,
230
      SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT   */
231
    { INL, INL, INL, INL, INL, INL, INL, INL,
232
      SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
233
    { INL, INL, INL, INL, INL, INL, INL, INL,
234
      SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
235
  }
236
};
237
 
238
static enum shift_alg shift_alg_si[3][3][32] = {
239
  {
240
    /* TARGET_H8300  */
241
    /*  0    1    2    3    4    5    6    7  */
242
    /*  8    9   10   11   12   13   14   15  */
243
    /* 16   17   18   19   20   21   22   23  */
244
    /* 24   25   26   27   28   29   30   31  */
245
    { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
246
      SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
247
      SPC, SPC, SPC, SPC, SPC, LOP, LOP, LOP,
248
      SPC, SPC, SPC, SPC, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFT   */
249
    { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
250
      SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC,
251
      SPC, SPC, SPC, LOP, LOP, LOP, LOP, LOP,
252
      SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_LSHIFTRT */
253
    { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
254
      SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
255
      SPC, SPC, LOP, LOP, LOP, LOP, LOP, LOP,
256
      SPC, SPC, SPC, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
257
  },
258
  {
259
    /* TARGET_H8300H  */
260
    /*  0    1    2    3    4    5    6    7  */
261
    /*  8    9   10   11   12   13   14   15  */
262
    /* 16   17   18   19   20   21   22   23  */
263
    /* 24   25   26   27   28   29   30   31  */
264
    { INL, INL, INL, INL, INL, LOP, LOP, LOP,
265
      SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
266
      SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
267
      SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT   */
268
    { INL, INL, INL, INL, INL, LOP, LOP, LOP,
269
      SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
270
      SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
271
      SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
272
    { INL, INL, INL, INL, INL, LOP, LOP, LOP,
273
      SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
274
      SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
275
      SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
276
  },
277
  {
278
    /* TARGET_H8300S  */
279
    /*  0    1    2    3    4    5    6    7  */
280
    /*  8    9   10   11   12   13   14   15  */
281
    /* 16   17   18   19   20   21   22   23  */
282
    /* 24   25   26   27   28   29   30   31  */
283
    { INL, INL, INL, INL, INL, INL, INL, INL,
284
      INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
285
      SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
286
      SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT   */
287
    { INL, INL, INL, INL, INL, INL, INL, INL,
288
      INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
289
      SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
290
      SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
291
    { INL, INL, INL, INL, INL, INL, INL, INL,
292
      INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
293
      SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
294
      SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
295
  }
296
};
297
 
298
#undef INL
299
#undef ROT
300
#undef LOP
301
#undef SPC
302
 
303
enum h8_cpu
304
{
305
  H8_300,
306
  H8_300H,
307
  H8_S
308
};
309
 
310
/* Initialize various cpu specific globals at start up.  */
311
 
312
static void
313
h8300_option_override (void)
314
{
315
  static const char *const h8_push_ops[2] = { "push" , "push.l" };
316
  static const char *const h8_pop_ops[2]  = { "pop"  , "pop.l"  };
317
  static const char *const h8_mov_ops[2]  = { "mov.w", "mov.l"  };
318
 
319
  if (TARGET_H8300)
320
    {
321
      cpu_type = (int) CPU_H8300;
322
      h8_reg_names = names_big;
323
    }
324
  else
325
    {
326
      /* For this we treat the H8/300H and H8S the same.  */
327
      cpu_type = (int) CPU_H8300H;
328
      h8_reg_names = names_extended;
329
    }
330
  h8_push_op = h8_push_ops[cpu_type];
331
  h8_pop_op = h8_pop_ops[cpu_type];
332
  h8_mov_op = h8_mov_ops[cpu_type];
333
 
334
  if (!TARGET_H8300S && TARGET_MAC)
335
    {
336
      error ("-ms2600 is used without -ms");
337
      target_flags |= MASK_H8300S_1;
338
    }
339
 
340
  if (TARGET_H8300 && TARGET_NORMAL_MODE)
341
    {
342
      error ("-mn is used without -mh or -ms");
343
      target_flags ^= MASK_NORMAL_MODE;
344
    }
345
 
346
  /* Some of the shifts are optimized for speed by default.
347
     See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
348
     If optimizing for size, change shift_alg for those shift to
349
     SHIFT_LOOP.  */
350
  if (optimize_size)
351
    {
352
      /* H8/300 */
353
      shift_alg_hi[H8_300][SHIFT_ASHIFT][5] = SHIFT_LOOP;
354
      shift_alg_hi[H8_300][SHIFT_ASHIFT][6] = SHIFT_LOOP;
355
      shift_alg_hi[H8_300][SHIFT_ASHIFT][13] = SHIFT_LOOP;
356
      shift_alg_hi[H8_300][SHIFT_ASHIFT][14] = SHIFT_LOOP;
357
 
358
      shift_alg_hi[H8_300][SHIFT_LSHIFTRT][13] = SHIFT_LOOP;
359
      shift_alg_hi[H8_300][SHIFT_LSHIFTRT][14] = SHIFT_LOOP;
360
 
361
      shift_alg_hi[H8_300][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
362
      shift_alg_hi[H8_300][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
363
 
364
      /* H8/300H */
365
      shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP;
366
      shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP;
367
 
368
      shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP;
369
      shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP;
370
 
371
      shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP;
372
      shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP;
373
      shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
374
      shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
375
 
376
      /* H8S */
377
      shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
378
    }
379
 
380
  /* Work out a value for MOVE_RATIO.  */
381
  if (!TARGET_H8300SX)
382
    {
383
      /* Memory-memory moves are quite expensive without the
384
         h8sx instructions.  */
385
      h8300_move_ratio = 3;
386
    }
387
  else if (flag_omit_frame_pointer)
388
    {
389
      /* movmd sequences are fairly cheap when er6 isn't fixed.  They can
390
         sometimes be as short as two individual memory-to-memory moves,
391
         but since they use all the call-saved registers, it seems better
392
         to allow up to three moves here.  */
393
      h8300_move_ratio = 4;
394
    }
395
  else if (optimize_size)
396
    {
397
      /* In this case we don't use movmd sequences since they tend
398
         to be longer than calls to memcpy().  Memory-to-memory
399
         moves are cheaper than for !TARGET_H8300SX, so it makes
400
         sense to have a slightly higher threshold.  */
401
      h8300_move_ratio = 4;
402
    }
403
  else
404
    {
405
      /* We use movmd sequences for some moves since it can be quicker
406
         than calling memcpy().  The sequences will need to save and
407
         restore er6 though, so bump up the cost.  */
408
      h8300_move_ratio = 6;
409
    }
410
 
411
  /* This target defaults to strict volatile bitfields.  */
412
  if (flag_strict_volatile_bitfields < 0 && abi_version_at_least(2))
413
    flag_strict_volatile_bitfields = 1;
414
}
415
 
416
/* Return the byte register name for a register rtx X.  B should be 0
417
   if you want a lower byte register.  B should be 1 if you want an
418
   upper byte register.  */
419
 
420
static const char *
421
byte_reg (rtx x, int b)
422
{
423
  static const char *const names_small[] = {
424
    "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
425
    "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
426
  };
427
 
428
  gcc_assert (REG_P (x));
429
 
430
  return names_small[REGNO (x) * 2 + b];
431
}
432
 
433
/* REGNO must be saved/restored across calls if this macro is true.  */
434
 
435
#define WORD_REG_USED(regno)                                            \
436
  (regno < SP_REG                                                       \
437
   /* No need to save registers if this function will not return.  */   \
438
   && ! TREE_THIS_VOLATILE (current_function_decl)                      \
439
   && (h8300_saveall_function_p (current_function_decl)                 \
440
       /* Save any call saved register that was used.  */               \
441
       || (df_regs_ever_live_p (regno) && !call_used_regs[regno])       \
442
       /* Save the frame pointer if it was used.  */                    \
443
       || (regno == HARD_FRAME_POINTER_REGNUM && df_regs_ever_live_p (regno)) \
444
       /* Save any register used in an interrupt handler.  */           \
445
       || (h8300_current_function_interrupt_function_p ()               \
446
           && df_regs_ever_live_p (regno))                              \
447
       /* Save call clobbered registers in non-leaf interrupt           \
448
          handlers.  */                                                 \
449
       || (h8300_current_function_interrupt_function_p ()               \
450
           && call_used_regs[regno]                                     \
451
           && !current_function_is_leaf)))
452
 
453
/* We use this to wrap all emitted insns in the prologue.  */
454
static rtx
455
F (rtx x, bool set_it)
456
{
457
  if (set_it)
458
    RTX_FRAME_RELATED_P (x) = 1;
459
  return x;
460
}
461
 
462
/* Mark all the subexpressions of the PARALLEL rtx PAR as
463
   frame-related.  Return PAR.
464
 
465
   dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
466
   PARALLEL rtx other than the first if they do not have the
467
   FRAME_RELATED flag set on them.  */
468
static rtx
469
Fpa (rtx par)
470
{
471
  int len = XVECLEN (par, 0);
472
  int i;
473
 
474
  for (i = 0; i < len; i++)
475
    F (XVECEXP (par, 0, i), true);
476
 
477
  return par;
478
}
479
 
480
/* Output assembly language to FILE for the operation OP with operand size
481
   SIZE to adjust the stack pointer.  */
482
 
483
static void
484
h8300_emit_stack_adjustment (int sign, HOST_WIDE_INT size, bool in_prologue)
485
{
486
  /* If the frame size is 0, we don't have anything to do.  */
487
  if (size == 0)
488
    return;
489
 
490
  /* H8/300 cannot add/subtract a large constant with a single
491
     instruction.  If a temporary register is available, load the
492
     constant to it and then do the addition.  */
493
  if (TARGET_H8300
494
      && size > 4
495
      && !h8300_current_function_interrupt_function_p ()
496
      && !(cfun->static_chain_decl != NULL && sign < 0))
497
    {
498
      rtx r3 = gen_rtx_REG (Pmode, 3);
499
      F (emit_insn (gen_movhi (r3, GEN_INT (sign * size))), in_prologue);
500
      F (emit_insn (gen_addhi3 (stack_pointer_rtx,
501
                                stack_pointer_rtx, r3)), in_prologue);
502
    }
503
  else
504
    {
505
      /* The stack adjustment made here is further optimized by the
506
         splitter.  In case of H8/300, the splitter always splits the
507
         addition emitted here to make the adjustment interrupt-safe.
508
         FIXME: We don't always tag those, because we don't know what
509
         the splitter will do.  */
510
      if (Pmode == HImode)
511
        {
512
          rtx x = emit_insn (gen_addhi3 (stack_pointer_rtx,
513
                                         stack_pointer_rtx, GEN_INT (sign * size)));
514
          if (size < 4)
515
            F (x, in_prologue);
516
        }
517
      else
518
        F (emit_insn (gen_addsi3 (stack_pointer_rtx,
519
                                  stack_pointer_rtx, GEN_INT (sign * size))), in_prologue);
520
    }
521
}
522
 
523
/* Round up frame size SIZE.  */
524
 
525
static HOST_WIDE_INT
526
round_frame_size (HOST_WIDE_INT size)
527
{
528
  return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1)
529
          & -STACK_BOUNDARY / BITS_PER_UNIT);
530
}
531
 
532
/* Compute which registers to push/pop.
533
   Return a bit vector of registers.  */
534
 
535
static unsigned int
536
compute_saved_regs (void)
537
{
538
  unsigned int saved_regs = 0;
539
  int regno;
540
 
541
  /* Construct a bit vector of registers to be pushed/popped.  */
542
  for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
543
    {
544
      if (WORD_REG_USED (regno))
545
        saved_regs |= 1 << regno;
546
    }
547
 
548
  /* Don't push/pop the frame pointer as it is treated separately.  */
549
  if (frame_pointer_needed)
550
    saved_regs &= ~(1 << HARD_FRAME_POINTER_REGNUM);
551
 
552
  return saved_regs;
553
}
554
 
555
/* Emit an insn to push register RN.  */
556
 
557
static rtx
558
push (int rn)
559
{
560
  rtx reg = gen_rtx_REG (word_mode, rn);
561
  rtx x;
562
 
563
  if (TARGET_H8300)
564
    x = gen_push_h8300 (reg);
565
  else if (!TARGET_NORMAL_MODE)
566
    x = gen_push_h8300hs_advanced (reg);
567
  else
568
    x = gen_push_h8300hs_normal (reg);
569
  x = F (emit_insn (x), true);
570
  add_reg_note (x, REG_INC, stack_pointer_rtx);
571
  return x;
572
}
573
 
574
/* Emit an insn to pop register RN.  */
575
 
576
static rtx
577
pop (int rn)
578
{
579
  rtx reg = gen_rtx_REG (word_mode, rn);
580
  rtx x;
581
 
582
  if (TARGET_H8300)
583
    x = gen_pop_h8300 (reg);
584
  else if (!TARGET_NORMAL_MODE)
585
    x = gen_pop_h8300hs_advanced (reg);
586
  else
587
    x = gen_pop_h8300hs_normal (reg);
588
  x = emit_insn (x);
589
  add_reg_note (x, REG_INC, stack_pointer_rtx);
590
  return x;
591
}
592
 
593
/* Emit an instruction to push or pop NREGS consecutive registers
594
   starting at register REGNO.  POP_P selects a pop rather than a
595
   push and RETURN_P is true if the instruction should return.
596
 
597
   It must be possible to do the requested operation in a single
598
   instruction.  If NREGS == 1 && !RETURN_P, use a normal push
599
   or pop insn.  Otherwise emit a parallel of the form:
600
 
601
     (parallel
602
       [(return)  ;; if RETURN_P
603
        (save or restore REGNO)
604
        (save or restore REGNO + 1)
605
        ...
606
        (save or restore REGNO + NREGS - 1)
607
        (set sp (plus sp (const_int adjust)))]  */
608
 
609
static void
610
h8300_push_pop (int regno, int nregs, bool pop_p, bool return_p)
611
{
612
  int i, j;
613
  rtvec vec;
614
  rtx sp, offset, x;
615
 
616
  /* See whether we can use a simple push or pop.  */
617
  if (!return_p && nregs == 1)
618
    {
619
      if (pop_p)
620
        pop (regno);
621
      else
622
        push (regno);
623
      return;
624
    }
625
 
626
  /* We need one element for the return insn, if present, one for each
627
     register, and one for stack adjustment.  */
628
  vec = rtvec_alloc ((return_p ? 1 : 0) + nregs + 1);
629
  sp = stack_pointer_rtx;
630
  i = 0;
631
 
632
  /* Add the return instruction.  */
633
  if (return_p)
634
    {
635
      RTVEC_ELT (vec, i) = ret_rtx;
636
      i++;
637
    }
638
 
639
  /* Add the register moves.  */
640
  for (j = 0; j < nregs; j++)
641
    {
642
      rtx lhs, rhs;
643
 
644
      if (pop_p)
645
        {
646
          /* Register REGNO + NREGS - 1 is popped first.  Before the
647
             stack adjustment, its slot is at address @sp.  */
648
          lhs = gen_rtx_REG (SImode, regno + j);
649
          rhs = gen_rtx_MEM (SImode, plus_constant (sp, (nregs - j - 1) * 4));
650
        }
651
      else
652
        {
653
          /* Register REGNO is pushed first and will be stored at @(-4,sp).  */
654
          lhs = gen_rtx_MEM (SImode, plus_constant (sp, (j + 1) * -4));
655
          rhs = gen_rtx_REG (SImode, regno + j);
656
        }
657
      RTVEC_ELT (vec, i + j) = gen_rtx_SET (VOIDmode, lhs, rhs);
658
    }
659
 
660
  /* Add the stack adjustment.  */
661
  offset = GEN_INT ((pop_p ? nregs : -nregs) * 4);
662
  RTVEC_ELT (vec, i + j) = gen_rtx_SET (VOIDmode, sp,
663
                                        gen_rtx_PLUS (Pmode, sp, offset));
664
 
665
  x = gen_rtx_PARALLEL (VOIDmode, vec);
666
  if (!pop_p)
667
    x = Fpa (x);
668
 
669
  if (return_p)
670
    emit_jump_insn (x);
671
  else
672
    emit_insn (x);
673
}
674
 
675
/* Return true if X has the value sp + OFFSET.  */
676
 
677
static int
678
h8300_stack_offset_p (rtx x, int offset)
679
{
680
  if (offset == 0)
681
    return x == stack_pointer_rtx;
682
 
683
  return (GET_CODE (x) == PLUS
684
          && XEXP (x, 0) == stack_pointer_rtx
685
          && GET_CODE (XEXP (x, 1)) == CONST_INT
686
          && INTVAL (XEXP (x, 1)) == offset);
687
}
688
 
689
/* A subroutine of h8300_ldm_stm_parallel.  X is one pattern in
690
   something that may be an ldm or stm instruction.  If it fits
691
   the required template, return the register it loads or stores,
692
   otherwise return -1.
693
 
694
   LOAD_P is true if X should be a load, false if it should be a store.
695
   NREGS is the number of registers that the whole instruction is expected
696
   to load or store.  INDEX is the index of the register that X should
697
   load or store, relative to the lowest-numbered register.  */
698
 
699
static int
700
h8300_ldm_stm_regno (rtx x, int load_p, int index, int nregs)
701
{
702
  int regindex, memindex, offset;
703
 
704
  if (load_p)
705
    regindex = 0, memindex = 1, offset = (nregs - index - 1) * 4;
706
  else
707
    memindex = 0, regindex = 1, offset = (index + 1) * -4;
708
 
709
  if (GET_CODE (x) == SET
710
      && GET_CODE (XEXP (x, regindex)) == REG
711
      && GET_CODE (XEXP (x, memindex)) == MEM
712
      && h8300_stack_offset_p (XEXP (XEXP (x, memindex), 0), offset))
713
    return REGNO (XEXP (x, regindex));
714
 
715
  return -1;
716
}
717
 
718
/* Return true if the elements of VEC starting at FIRST describe an
719
   ldm or stm instruction (LOAD_P says which).  */
720
 
721
int
722
h8300_ldm_stm_parallel (rtvec vec, int load_p, int first)
723
{
724
  rtx last;
725
  int nregs, i, regno, adjust;
726
 
727
  /* There must be a stack adjustment, a register move, and at least one
728
     other operation (a return or another register move).  */
729
  if (GET_NUM_ELEM (vec) < 3)
730
    return false;
731
 
732
  /* Get the range of registers to be pushed or popped.  */
733
  nregs = GET_NUM_ELEM (vec) - first - 1;
734
  regno = h8300_ldm_stm_regno (RTVEC_ELT (vec, first), load_p, 0, nregs);
735
 
736
  /* Check that the call to h8300_ldm_stm_regno succeeded and
737
     that we're only dealing with GPRs.  */
738
  if (regno < 0 || regno + nregs > 8)
739
    return false;
740
 
741
  /* 2-register h8s instructions must start with an even-numbered register.
742
     3- and 4-register instructions must start with er0 or er4.  */
743
  if (!TARGET_H8300SX)
744
    {
745
      if ((regno & 1) != 0)
746
        return false;
747
      if (nregs > 2 && (regno & 3) != 0)
748
        return false;
749
    }
750
 
751
  /* Check the other loads or stores.  */
752
  for (i = 1; i < nregs; i++)
753
    if (h8300_ldm_stm_regno (RTVEC_ELT (vec, first + i), load_p, i, nregs)
754
        != regno + i)
755
      return false;
756
 
757
  /* Check the stack adjustment.  */
758
  last = RTVEC_ELT (vec, first + nregs);
759
  adjust = (load_p ? nregs : -nregs) * 4;
760
  return (GET_CODE (last) == SET
761
          && SET_DEST (last) == stack_pointer_rtx
762
          && h8300_stack_offset_p (SET_SRC (last), adjust));
763
}
764
 
765
/* This is what the stack looks like after the prolog of
766
   a function with a frame has been set up:
767
 
768
   <args>
769
   PC
770
   FP                   <- fp
771
   <locals>
772
   <saved registers>    <- sp
773
 
774
   This is what the stack looks like after the prolog of
775
   a function which doesn't have a frame:
776
 
777
   <args>
778
   PC
779
   <locals>
780
   <saved registers>    <- sp
781
*/
782
 
783
/* Generate RTL code for the function prologue.  */
784
 
785
void
786
h8300_expand_prologue (void)
787
{
788
  int regno;
789
  int saved_regs;
790
  int n_regs;
791
 
792
  /* If the current function has the OS_Task attribute set, then
793
     we have a naked prologue.  */
794
  if (h8300_os_task_function_p (current_function_decl))
795
    return;
796
 
797
  if (h8300_monitor_function_p (current_function_decl))
798
    /* My understanding of monitor functions is they act just like
799
       interrupt functions, except the prologue must mask
800
       interrupts.  */
801
    emit_insn (gen_monitor_prologue ());
802
 
803
  if (frame_pointer_needed)
804
    {
805
      /* Push fp.  */
806
      push (HARD_FRAME_POINTER_REGNUM);
807
      F (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx), true);
808
    }
809
 
810
  /* Push the rest of the registers in ascending order.  */
811
  saved_regs = compute_saved_regs ();
812
  for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs)
813
    {
814
      n_regs = 1;
815
      if (saved_regs & (1 << regno))
816
        {
817
          if (TARGET_H8300S)
818
            {
819
              /* See how many registers we can push at the same time.  */
820
              if ((!TARGET_H8300SX || (regno & 3) == 0)
821
                  && ((saved_regs >> regno) & 0x0f) == 0x0f)
822
                n_regs = 4;
823
 
824
              else if ((!TARGET_H8300SX || (regno & 3) == 0)
825
                       && ((saved_regs >> regno) & 0x07) == 0x07)
826
                n_regs = 3;
827
 
828
              else if ((!TARGET_H8300SX || (regno & 1) == 0)
829
                       && ((saved_regs >> regno) & 0x03) == 0x03)
830
                n_regs = 2;
831
            }
832
 
833
          h8300_push_pop (regno, n_regs, false, false);
834
        }
835
    }
836
 
837
  /* Leave room for locals.  */
838
  h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()), true);
839
}
840
 
841
/* Return nonzero if we can use "rts" for the function currently being
842
   compiled.  */
843
 
844
int
845
h8300_can_use_return_insn_p (void)
846
{
847
  return (reload_completed
848
          && !frame_pointer_needed
849
          && get_frame_size () == 0
850
          && compute_saved_regs () == 0);
851
}
852
 
853
/* Generate RTL code for the function epilogue.  */
854
 
855
void
856
h8300_expand_epilogue (void)
857
{
858
  int regno;
859
  int saved_regs;
860
  int n_regs;
861
  HOST_WIDE_INT frame_size;
862
  bool returned_p;
863
 
864
  if (h8300_os_task_function_p (current_function_decl))
865
    /* OS_Task epilogues are nearly naked -- they just have an
866
       rts instruction.  */
867
    return;
868
 
869
  frame_size = round_frame_size (get_frame_size ());
870
  returned_p = false;
871
 
872
  /* Deallocate locals.  */
873
  h8300_emit_stack_adjustment (1, frame_size, false);
874
 
875
  /* Pop the saved registers in descending order.  */
876
  saved_regs = compute_saved_regs ();
877
  for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs)
878
    {
879
      n_regs = 1;
880
      if (saved_regs & (1 << regno))
881
        {
882
          if (TARGET_H8300S)
883
            {
884
              /* See how many registers we can pop at the same time.  */
885
              if ((TARGET_H8300SX || (regno & 3) == 3)
886
                  && ((saved_regs << 3 >> regno) & 0x0f) == 0x0f)
887
                n_regs = 4;
888
 
889
              else if ((TARGET_H8300SX || (regno & 3) == 2)
890
                       && ((saved_regs << 2 >> regno) & 0x07) == 0x07)
891
                n_regs = 3;
892
 
893
              else if ((TARGET_H8300SX || (regno & 1) == 1)
894
                       && ((saved_regs << 1 >> regno) & 0x03) == 0x03)
895
                n_regs = 2;
896
            }
897
 
898
          /* See if this pop would be the last insn before the return.
899
             If so, use rte/l or rts/l instead of pop or ldm.l.  */
900
          if (TARGET_H8300SX
901
              && !frame_pointer_needed
902
              && frame_size == 0
903
              && (saved_regs & ((1 << (regno - n_regs + 1)) - 1)) == 0)
904
            returned_p = true;
905
 
906
          h8300_push_pop (regno - n_regs + 1, n_regs, true, returned_p);
907
        }
908
    }
909
 
910
  /* Pop frame pointer if we had one.  */
911
  if (frame_pointer_needed)
912
    {
913
      if (TARGET_H8300SX)
914
        returned_p = true;
915
      h8300_push_pop (HARD_FRAME_POINTER_REGNUM, 1, true, returned_p);
916
    }
917
 
918
  if (!returned_p)
919
    emit_jump_insn (ret_rtx);
920
}
921
 
922
/* Return nonzero if the current function is an interrupt
923
   function.  */
924
 
925
int
926
h8300_current_function_interrupt_function_p (void)
927
{
928
  return (h8300_interrupt_function_p (current_function_decl)
929
          || h8300_monitor_function_p (current_function_decl));
930
}
931
 
932
/* Output assembly code for the start of the file.  */
933
 
934
static void
935
h8300_file_start (void)
936
{
937
  default_file_start ();
938
 
939
  if (TARGET_H8300H)
940
    fputs (TARGET_NORMAL_MODE ? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file);
941
  else if (TARGET_H8300SX)
942
    fputs (TARGET_NORMAL_MODE ? "\t.h8300sxn\n" : "\t.h8300sx\n", asm_out_file);
943
  else if (TARGET_H8300S)
944
    fputs (TARGET_NORMAL_MODE ? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file);
945
}
946
 
947
/* Output assembly language code for the end of file.  */
948
 
949
static void
950
h8300_file_end (void)
951
{
952
  fputs ("\t.end\n", asm_out_file);
953
}
954
 
955
/* Split an add of a small constant into two adds/subs insns.
956
 
957
   If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
958
   instead of adds/subs.  */
959
 
960
void
961
split_adds_subs (enum machine_mode mode, rtx *operands)
962
{
963
  HOST_WIDE_INT val = INTVAL (operands[1]);
964
  rtx reg = operands[0];
965
  HOST_WIDE_INT sign = 1;
966
  HOST_WIDE_INT amount;
967
  rtx (*gen_add) (rtx, rtx, rtx);
968
 
969
  /* Force VAL to be positive so that we do not have to consider the
970
     sign.  */
971
  if (val < 0)
972
    {
973
      val = -val;
974
      sign = -1;
975
    }
976
 
977
  switch (mode)
978
    {
979
    case HImode:
980
      gen_add = gen_addhi3;
981
      break;
982
 
983
    case SImode:
984
      gen_add = gen_addsi3;
985
      break;
986
 
987
    default:
988
      gcc_unreachable ();
989
    }
990
 
991
  /* Try different amounts in descending order.  */
992
  for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
993
       amount > 0;
994
       amount /= 2)
995
    {
996
      for (; val >= amount; val -= amount)
997
        emit_insn (gen_add (reg, reg, GEN_INT (sign * amount)));
998
    }
999
 
1000
  return;
1001
}
1002
 
1003
/* Handle machine specific pragmas for compatibility with existing
1004
   compilers for the H8/300.
1005
 
1006
   pragma saveall generates prologue/epilogue code which saves and
1007
   restores all the registers on function entry.
1008
 
1009
   pragma interrupt saves and restores all registers, and exits with
1010
   an rte instruction rather than an rts.  A pointer to a function
1011
   with this attribute may be safely used in an interrupt vector.  */
1012
 
1013
void
1014
h8300_pr_interrupt (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
1015
{
1016
  pragma_interrupt = 1;
1017
}
1018
 
1019
void
1020
h8300_pr_saveall (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
1021
{
1022
  pragma_saveall = 1;
1023
}
1024
 
1025
/* If the next function argument with MODE and TYPE is to be passed in
1026
   a register, return a reg RTX for the hard register in which to pass
1027
   the argument.  CUM represents the state after the last argument.
1028
   If the argument is to be pushed, NULL_RTX is returned.
1029
 
1030
   On the H8/300 all normal args are pushed, unless -mquickcall in which
1031
   case the first 3 arguments are passed in registers.  */
1032
 
1033
static rtx
1034
h8300_function_arg (cumulative_args_t cum_v, enum machine_mode mode,
1035
                    const_tree type, bool named)
1036
{
1037
  CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1038
 
1039
  static const char *const hand_list[] = {
1040
    "__main",
1041
    "__cmpsi2",
1042
    "__divhi3",
1043
    "__modhi3",
1044
    "__udivhi3",
1045
    "__umodhi3",
1046
    "__divsi3",
1047
    "__modsi3",
1048
    "__udivsi3",
1049
    "__umodsi3",
1050
    "__mulhi3",
1051
    "__mulsi3",
1052
    "__reg_memcpy",
1053
    "__reg_memset",
1054
    "__ucmpsi2",
1055
    0,
1056
  };
1057
 
1058
  rtx result = NULL_RTX;
1059
  const char *fname;
1060
  int regpass = 0;
1061
 
1062
  /* Never pass unnamed arguments in registers.  */
1063
  if (!named)
1064
    return NULL_RTX;
1065
 
1066
  /* Pass 3 regs worth of data in regs when user asked on the command line.  */
1067
  if (TARGET_QUICKCALL)
1068
    regpass = 3;
1069
 
1070
  /* If calling hand written assembler, use 4 regs of args.  */
1071
  if (cum->libcall)
1072
    {
1073
      const char * const *p;
1074
 
1075
      fname = XSTR (cum->libcall, 0);
1076
 
1077
      /* See if this libcall is one of the hand coded ones.  */
1078
      for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
1079
        ;
1080
 
1081
      if (*p)
1082
        regpass = 4;
1083
    }
1084
 
1085
  if (regpass)
1086
    {
1087
      int size;
1088
 
1089
      if (mode == BLKmode)
1090
        size = int_size_in_bytes (type);
1091
      else
1092
        size = GET_MODE_SIZE (mode);
1093
 
1094
      if (size + cum->nbytes <= regpass * UNITS_PER_WORD
1095
          && cum->nbytes / UNITS_PER_WORD <= 3)
1096
        result = gen_rtx_REG (mode, cum->nbytes / UNITS_PER_WORD);
1097
    }
1098
 
1099
  return result;
1100
}
1101
 
1102
/* Update the data in CUM to advance over an argument
1103
   of mode MODE and data type TYPE.
1104
   (TYPE is null for libcalls where that information may not be available.)  */
1105
 
1106
static void
1107
h8300_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
1108
                            const_tree type, bool named ATTRIBUTE_UNUSED)
1109
{
1110
  CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1111
 
1112
  cum->nbytes += (mode != BLKmode
1113
                  ? (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD
1114
                  : (int_size_in_bytes (type) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD);
1115
}
1116
 
1117
 
1118
/* Implements TARGET_REGISTER_MOVE_COST.
1119
 
1120
   Any SI register-to-register move may need to be reloaded,
1121
   so inmplement h8300_register_move_cost to return > 2 so that reload never
1122
   shortcuts.  */
1123
 
1124
static int
1125
h8300_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
1126
                         reg_class_t from, reg_class_t to)
1127
{
1128
  if (from == MAC_REGS || to == MAC_REG)
1129
    return 6;
1130
  else
1131
    return 3;
1132
}
1133
 
1134
/* Compute the cost of an and insn.  */
1135
 
1136
static int
1137
h8300_and_costs (rtx x)
1138
{
1139
  rtx operands[4];
1140
 
1141
  if (GET_MODE (x) == QImode)
1142
    return 1;
1143
 
1144
  if (GET_MODE (x) != HImode
1145
      && GET_MODE (x) != SImode)
1146
    return 100;
1147
 
1148
  operands[0] = NULL;
1149
  operands[1] = XEXP (x, 0);
1150
  operands[2] = XEXP (x, 1);
1151
  operands[3] = x;
1152
  return compute_logical_op_length (GET_MODE (x), operands) / 2;
1153
}
1154
 
1155
/* Compute the cost of a shift insn.  */
1156
 
1157
static int
1158
h8300_shift_costs (rtx x)
1159
{
1160
  rtx operands[4];
1161
 
1162
  if (GET_MODE (x) != QImode
1163
      && GET_MODE (x) != HImode
1164
      && GET_MODE (x) != SImode)
1165
    return 100;
1166
 
1167
  operands[0] = NULL;
1168
  operands[1] = NULL;
1169
  operands[2] = XEXP (x, 1);
1170
  operands[3] = x;
1171
  return compute_a_shift_length (NULL, operands) / 2;
1172
}
1173
 
1174
/* Worker function for TARGET_RTX_COSTS.  */
1175
 
1176
static bool
1177
h8300_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
1178
                 int *total, bool speed)
1179
{
1180
  if (TARGET_H8300SX && outer_code == MEM)
1181
    {
1182
      /* Estimate the number of execution states needed to calculate
1183
         the address.  */
1184
      if (register_operand (x, VOIDmode)
1185
          || GET_CODE (x) == POST_INC
1186
          || GET_CODE (x) == POST_DEC
1187
          || CONSTANT_P (x))
1188
        *total = 0;
1189
      else
1190
        *total = COSTS_N_INSNS (1);
1191
      return true;
1192
    }
1193
 
1194
  switch (code)
1195
    {
1196
    case CONST_INT:
1197
      {
1198
        HOST_WIDE_INT n = INTVAL (x);
1199
 
1200
        if (TARGET_H8300SX)
1201
          {
1202
            /* Constant operands need the same number of processor
1203
               states as register operands.  Although we could try to
1204
               use a size-based cost for !speed, the lack of
1205
               of a mode makes the results very unpredictable.  */
1206
            *total = 0;
1207
            return true;
1208
          }
1209
        if (-4 <= n || n <= 4)
1210
          {
1211
            switch ((int) n)
1212
              {
1213
              case 0:
1214
                *total = 0;
1215
                return true;
1216
              case 1:
1217
              case 2:
1218
              case -1:
1219
              case -2:
1220
                *total = 0 + (outer_code == SET);
1221
                return true;
1222
              case 4:
1223
              case -4:
1224
                if (TARGET_H8300H || TARGET_H8300S)
1225
                  *total = 0 + (outer_code == SET);
1226
                else
1227
                  *total = 1;
1228
                return true;
1229
              }
1230
          }
1231
        *total = 1;
1232
        return true;
1233
      }
1234
 
1235
    case CONST:
1236
    case LABEL_REF:
1237
    case SYMBOL_REF:
1238
      if (TARGET_H8300SX)
1239
        {
1240
          /* See comment for CONST_INT.  */
1241
          *total = 0;
1242
          return true;
1243
        }
1244
      *total = 3;
1245
      return true;
1246
 
1247
    case CONST_DOUBLE:
1248
      *total = 20;
1249
      return true;
1250
 
1251
    case COMPARE:
1252
      if (XEXP (x, 1) == const0_rtx)
1253
        *total = 0;
1254
      return false;
1255
 
1256
    case AND:
1257
      if (!h8300_dst_operand (XEXP (x, 0), VOIDmode)
1258
          || !h8300_src_operand (XEXP (x, 1), VOIDmode))
1259
        return false;
1260
      *total = COSTS_N_INSNS (h8300_and_costs (x));
1261
      return true;
1262
 
1263
    /* We say that MOD and DIV are so expensive because otherwise we'll
1264
       generate some really horrible code for division of a power of two.  */
1265
    case MOD:
1266
    case DIV:
1267
    case UMOD:
1268
    case UDIV:
1269
      if (TARGET_H8300SX)
1270
        switch (GET_MODE (x))
1271
          {
1272
          case QImode:
1273
          case HImode:
1274
            *total = COSTS_N_INSNS (!speed ? 4 : 10);
1275
            return false;
1276
 
1277
          case SImode:
1278
            *total = COSTS_N_INSNS (!speed ? 4 : 18);
1279
            return false;
1280
 
1281
          default:
1282
            break;
1283
          }
1284
      *total = COSTS_N_INSNS (12);
1285
      return true;
1286
 
1287
    case MULT:
1288
      if (TARGET_H8300SX)
1289
        switch (GET_MODE (x))
1290
          {
1291
          case QImode:
1292
          case HImode:
1293
            *total = COSTS_N_INSNS (2);
1294
            return false;
1295
 
1296
          case SImode:
1297
            *total = COSTS_N_INSNS (5);
1298
            return false;
1299
 
1300
          default:
1301
            break;
1302
          }
1303
      *total = COSTS_N_INSNS (4);
1304
      return true;
1305
 
1306
    case ASHIFT:
1307
    case ASHIFTRT:
1308
    case LSHIFTRT:
1309
      if (h8sx_binary_shift_operator (x, VOIDmode))
1310
        {
1311
          *total = COSTS_N_INSNS (2);
1312
          return false;
1313
        }
1314
      else if (h8sx_unary_shift_operator (x, VOIDmode))
1315
        {
1316
          *total = COSTS_N_INSNS (1);
1317
          return false;
1318
        }
1319
      *total = COSTS_N_INSNS (h8300_shift_costs (x));
1320
      return true;
1321
 
1322
    case ROTATE:
1323
    case ROTATERT:
1324
      if (GET_MODE (x) == HImode)
1325
        *total = 2;
1326
      else
1327
        *total = 8;
1328
      return true;
1329
 
1330
    default:
1331
      *total = COSTS_N_INSNS (1);
1332
      return false;
1333
    }
1334
}
1335
 
1336
/* Documentation for the machine specific operand escapes:
1337
 
1338
   'E' like s but negative.
1339
   'F' like t but negative.
1340
   'G' constant just the negative
1341
   'R' print operand as a byte:8 address if appropriate, else fall back to
1342
       'X' handling.
1343
   'S' print operand as a long word
1344
   'T' print operand as a word
1345
   'V' find the set bit, and print its number.
1346
   'W' find the clear bit, and print its number.
1347
   'X' print operand as a byte
1348
   'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1349
       If this operand isn't a register, fall back to 'R' handling.
1350
   'Z' print int & 7.
1351
   'c' print the opcode corresponding to rtl
1352
   'e' first word of 32-bit value - if reg, then least reg. if mem
1353
       then least. if const then most sig word
1354
   'f' second word of 32-bit value - if reg, then biggest reg. if mem
1355
       then +2. if const then least sig word
1356
   'j' print operand as condition code.
1357
   'k' print operand as reverse condition code.
1358
   'm' convert an integer operand to a size suffix (.b, .w or .l)
1359
   'o' print an integer without a leading '#'
1360
   's' print as low byte of 16-bit value
1361
   't' print as high byte of 16-bit value
1362
   'w' print as low byte of 32-bit value
1363
   'x' print as 2nd byte of 32-bit value
1364
   'y' print as 3rd byte of 32-bit value
1365
   'z' print as msb of 32-bit value
1366
*/
1367
 
1368
/* Return assembly language string which identifies a comparison type.  */
1369
 
1370
static const char *
1371
cond_string (enum rtx_code code)
1372
{
1373
  switch (code)
1374
    {
1375
    case NE:
1376
      return "ne";
1377
    case EQ:
1378
      return "eq";
1379
    case GE:
1380
      return "ge";
1381
    case GT:
1382
      return "gt";
1383
    case LE:
1384
      return "le";
1385
    case LT:
1386
      return "lt";
1387
    case GEU:
1388
      return "hs";
1389
    case GTU:
1390
      return "hi";
1391
    case LEU:
1392
      return "ls";
1393
    case LTU:
1394
      return "lo";
1395
    default:
1396
      gcc_unreachable ();
1397
    }
1398
}
1399
 
1400
/* Print operand X using operand code CODE to assembly language output file
1401
   FILE.  */
1402
 
1403
static void
1404
h8300_print_operand (FILE *file, rtx x, int code)
1405
{
1406
  /* This is used for communication between codes V,W,Z and Y.  */
1407
  static int bitint;
1408
 
1409
  switch (code)
1410
    {
1411
    case 'E':
1412
      switch (GET_CODE (x))
1413
        {
1414
        case REG:
1415
          fprintf (file, "%sl", names_big[REGNO (x)]);
1416
          break;
1417
        case CONST_INT:
1418
          fprintf (file, "#%ld", (-INTVAL (x)) & 0xff);
1419
          break;
1420
        default:
1421
          gcc_unreachable ();
1422
        }
1423
      break;
1424
    case 'F':
1425
      switch (GET_CODE (x))
1426
        {
1427
        case REG:
1428
          fprintf (file, "%sh", names_big[REGNO (x)]);
1429
          break;
1430
        case CONST_INT:
1431
          fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8);
1432
          break;
1433
        default:
1434
          gcc_unreachable ();
1435
        }
1436
      break;
1437
    case 'G':
1438
      gcc_assert (GET_CODE (x) == CONST_INT);
1439
      fprintf (file, "#%ld", 0xff & (-INTVAL (x)));
1440
      break;
1441
    case 'S':
1442
      if (GET_CODE (x) == REG)
1443
        fprintf (file, "%s", names_extended[REGNO (x)]);
1444
      else
1445
        goto def;
1446
      break;
1447
    case 'T':
1448
      if (GET_CODE (x) == REG)
1449
        fprintf (file, "%s", names_big[REGNO (x)]);
1450
      else
1451
        goto def;
1452
      break;
1453
    case 'V':
1454
      bitint = (INTVAL (x) & 0xffff);
1455
      if ((exact_log2 ((bitint >> 8) & 0xff)) == -1)
1456
        bitint = exact_log2 (bitint & 0xff);
1457
      else
1458
        bitint = exact_log2 ((bitint >> 8) & 0xff);
1459
      gcc_assert (bitint >= 0);
1460
      fprintf (file, "#%d", bitint);
1461
      break;
1462
    case 'W':
1463
      bitint = ((~INTVAL (x)) & 0xffff);
1464
      if ((exact_log2 ((bitint >> 8) & 0xff)) == -1 )
1465
        bitint = exact_log2 (bitint & 0xff);
1466
      else
1467
        bitint = (exact_log2 ((bitint >> 8) & 0xff));
1468
      gcc_assert (bitint >= 0);
1469
      fprintf (file, "#%d", bitint);
1470
      break;
1471
    case 'R':
1472
    case 'X':
1473
      if (GET_CODE (x) == REG)
1474
        fprintf (file, "%s", byte_reg (x, 0));
1475
      else
1476
        goto def;
1477
      break;
1478
    case 'Y':
1479
      gcc_assert (bitint >= 0);
1480
      if (GET_CODE (x) == REG)
1481
        fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1482
      else
1483
        h8300_print_operand (file, x, 'R');
1484
      bitint = -1;
1485
      break;
1486
    case 'Z':
1487
      bitint = INTVAL (x);
1488
      fprintf (file, "#%d", bitint & 7);
1489
      break;
1490
    case 'c':
1491
      switch (GET_CODE (x))
1492
        {
1493
        case IOR:
1494
          fprintf (file, "or");
1495
          break;
1496
        case XOR:
1497
          fprintf (file, "xor");
1498
          break;
1499
        case AND:
1500
          fprintf (file, "and");
1501
          break;
1502
        default:
1503
          break;
1504
        }
1505
      break;
1506
    case 'e':
1507
      switch (GET_CODE (x))
1508
        {
1509
        case REG:
1510
          if (TARGET_H8300)
1511
            fprintf (file, "%s", names_big[REGNO (x)]);
1512
          else
1513
            fprintf (file, "%s", names_upper_extended[REGNO (x)]);
1514
          break;
1515
        case MEM:
1516
          h8300_print_operand (file, x, 0);
1517
          break;
1518
        case CONST_INT:
1519
          fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff));
1520
          break;
1521
        case CONST_DOUBLE:
1522
          {
1523
            long val;
1524
            REAL_VALUE_TYPE rv;
1525
            REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1526
            REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1527
            fprintf (file, "#%ld", ((val >> 16) & 0xffff));
1528
            break;
1529
          }
1530
        default:
1531
          gcc_unreachable ();
1532
          break;
1533
        }
1534
      break;
1535
    case 'f':
1536
      switch (GET_CODE (x))
1537
        {
1538
        case REG:
1539
          if (TARGET_H8300)
1540
            fprintf (file, "%s", names_big[REGNO (x) + 1]);
1541
          else
1542
            fprintf (file, "%s", names_big[REGNO (x)]);
1543
          break;
1544
        case MEM:
1545
          x = adjust_address (x, HImode, 2);
1546
          h8300_print_operand (file, x, 0);
1547
          break;
1548
        case CONST_INT:
1549
          fprintf (file, "#%ld", INTVAL (x) & 0xffff);
1550
          break;
1551
        case CONST_DOUBLE:
1552
          {
1553
            long val;
1554
            REAL_VALUE_TYPE rv;
1555
            REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1556
            REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1557
            fprintf (file, "#%ld", (val & 0xffff));
1558
            break;
1559
          }
1560
        default:
1561
          gcc_unreachable ();
1562
        }
1563
      break;
1564
    case 'j':
1565
      fputs (cond_string (GET_CODE (x)), file);
1566
      break;
1567
    case 'k':
1568
      fputs (cond_string (reverse_condition (GET_CODE (x))), file);
1569
      break;
1570
    case 'm':
1571
      gcc_assert (GET_CODE (x) == CONST_INT);
1572
      switch (INTVAL (x))
1573
        {
1574
        case 1:
1575
          fputs (".b", file);
1576
          break;
1577
 
1578
        case 2:
1579
          fputs (".w", file);
1580
          break;
1581
 
1582
        case 4:
1583
          fputs (".l", file);
1584
          break;
1585
 
1586
        default:
1587
          gcc_unreachable ();
1588
        }
1589
      break;
1590
    case 'o':
1591
      h8300_print_operand_address (file, x);
1592
      break;
1593
    case 's':
1594
      if (GET_CODE (x) == CONST_INT)
1595
        fprintf (file, "#%ld", (INTVAL (x)) & 0xff);
1596
      else
1597
        fprintf (file, "%s", byte_reg (x, 0));
1598
      break;
1599
    case 't':
1600
      if (GET_CODE (x) == CONST_INT)
1601
        fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1602
      else
1603
        fprintf (file, "%s", byte_reg (x, 1));
1604
      break;
1605
    case 'w':
1606
      if (GET_CODE (x) == CONST_INT)
1607
        fprintf (file, "#%ld", INTVAL (x) & 0xff);
1608
      else
1609
        fprintf (file, "%s",
1610
                 byte_reg (x, TARGET_H8300 ? 2 : 0));
1611
      break;
1612
    case 'x':
1613
      if (GET_CODE (x) == CONST_INT)
1614
        fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1615
      else
1616
        fprintf (file, "%s",
1617
                 byte_reg (x, TARGET_H8300 ? 3 : 1));
1618
      break;
1619
    case 'y':
1620
      if (GET_CODE (x) == CONST_INT)
1621
        fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff);
1622
      else
1623
        fprintf (file, "%s", byte_reg (x, 0));
1624
      break;
1625
    case 'z':
1626
      if (GET_CODE (x) == CONST_INT)
1627
        fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff);
1628
      else
1629
        fprintf (file, "%s", byte_reg (x, 1));
1630
      break;
1631
 
1632
    default:
1633
    def:
1634
      switch (GET_CODE (x))
1635
        {
1636
        case REG:
1637
          switch (GET_MODE (x))
1638
            {
1639
            case QImode:
1640
#if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1641
              fprintf (file, "%s", byte_reg (x, 0));
1642
#else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1643
              fprintf (file, "%s", names_big[REGNO (x)]);
1644
#endif
1645
              break;
1646
            case HImode:
1647
              fprintf (file, "%s", names_big[REGNO (x)]);
1648
              break;
1649
            case SImode:
1650
            case SFmode:
1651
              fprintf (file, "%s", names_extended[REGNO (x)]);
1652
              break;
1653
            default:
1654
              gcc_unreachable ();
1655
            }
1656
          break;
1657
 
1658
        case MEM:
1659
          {
1660
            rtx addr = XEXP (x, 0);
1661
 
1662
            fprintf (file, "@");
1663
            output_address (addr);
1664
 
1665
            /* Add a length suffix to constant addresses.  Although this
1666
               is often unnecessary, it helps to avoid ambiguity in the
1667
               syntax of mova.  If we wrote an insn like:
1668
 
1669
                    mova/w.l @(1,@foo.b),er0
1670
 
1671
               then .b would be considered part of the symbol name.
1672
               Adding a length after foo will avoid this.  */
1673
            if (CONSTANT_P (addr))
1674
              switch (code)
1675
                {
1676
                case 'R':
1677
                  /* Used for mov.b and bit operations.  */
1678
                  if (h8300_eightbit_constant_address_p (addr))
1679
                    {
1680
                      fprintf (file, ":8");
1681
                      break;
1682
                    }
1683
 
1684
                  /* Fall through.  We should not get here if we are
1685
                     processing bit operations on H8/300 or H8/300H
1686
                     because 'U' constraint does not allow bit
1687
                     operations on the tiny area on these machines.  */
1688
 
1689
                case 'X':
1690
                case 'T':
1691
                case 'S':
1692
                  if (h8300_constant_length (addr) == 2)
1693
                    fprintf (file, ":16");
1694
                  else
1695
                    fprintf (file, ":32");
1696
                  break;
1697
                default:
1698
                  break;
1699
                }
1700
          }
1701
          break;
1702
 
1703
        case CONST_INT:
1704
        case SYMBOL_REF:
1705
        case CONST:
1706
        case LABEL_REF:
1707
          fprintf (file, "#");
1708
          h8300_print_operand_address (file, x);
1709
          break;
1710
        case CONST_DOUBLE:
1711
          {
1712
            long val;
1713
            REAL_VALUE_TYPE rv;
1714
            REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1715
            REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1716
            fprintf (file, "#%ld", val);
1717
            break;
1718
          }
1719
        default:
1720
          break;
1721
        }
1722
    }
1723
}
1724
 
1725
/* Implements TARGET_PRINT_OPERAND_PUNCT_VALID_P.  */
1726
 
1727
static bool
1728
h8300_print_operand_punct_valid_p (unsigned char code)
1729
{
1730
  return (code == '#');
1731
}
1732
 
1733
/* Output assembly language output for the address ADDR to FILE.  */
1734
 
1735
static void
1736
h8300_print_operand_address (FILE *file, rtx addr)
1737
{
1738
  rtx index;
1739
  int size;
1740
 
1741
  switch (GET_CODE (addr))
1742
    {
1743
    case REG:
1744
      fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
1745
      break;
1746
 
1747
    case PRE_DEC:
1748
      fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1749
      break;
1750
 
1751
    case POST_INC:
1752
      fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
1753
      break;
1754
 
1755
    case PRE_INC:
1756
      fprintf (file, "+%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1757
      break;
1758
 
1759
    case POST_DEC:
1760
      fprintf (file, "%s-", h8_reg_names[REGNO (XEXP (addr, 0))]);
1761
      break;
1762
 
1763
    case PLUS:
1764
      fprintf (file, "(");
1765
 
1766
      index = h8300_get_index (XEXP (addr, 0), VOIDmode, &size);
1767
      if (GET_CODE (index) == REG)
1768
        {
1769
          /* reg,foo */
1770
          h8300_print_operand_address (file, XEXP (addr, 1));
1771
          fprintf (file, ",");
1772
          switch (size)
1773
            {
1774
            case 0:
1775
              h8300_print_operand_address (file, index);
1776
              break;
1777
 
1778
            case 1:
1779
              h8300_print_operand (file, index, 'X');
1780
              fputs (".b", file);
1781
              break;
1782
 
1783
            case 2:
1784
              h8300_print_operand (file, index, 'T');
1785
              fputs (".w", file);
1786
              break;
1787
 
1788
            case 4:
1789
              h8300_print_operand (file, index, 'S');
1790
              fputs (".l", file);
1791
              break;
1792
            }
1793
          /* h8300_print_operand_address (file, XEXP (addr, 0)); */
1794
        }
1795
      else
1796
        {
1797
          /* foo+k */
1798
          h8300_print_operand_address (file, XEXP (addr, 0));
1799
          fprintf (file, "+");
1800
          h8300_print_operand_address (file, XEXP (addr, 1));
1801
        }
1802
      fprintf (file, ")");
1803
      break;
1804
 
1805
    case CONST_INT:
1806
      {
1807
        /* Since the H8/300 only has 16-bit pointers, negative values are also
1808
           those >= 32768.  This happens for example with pointer minus a
1809
           constant.  We don't want to turn (char *p - 2) into
1810
           (char *p + 65534) because loop unrolling can build upon this
1811
           (IE: char *p + 131068).  */
1812
        int n = INTVAL (addr);
1813
        if (TARGET_H8300)
1814
          n = (int) (short) n;
1815
        fprintf (file, "%d", n);
1816
        break;
1817
      }
1818
 
1819
    default:
1820
      output_addr_const (file, addr);
1821
      break;
1822
    }
1823
}
1824
 
1825
/* Output all insn addresses and their sizes into the assembly language
1826
   output file.  This is helpful for debugging whether the length attributes
1827
   in the md file are correct.  This is not meant to be a user selectable
1828
   option.  */
1829
 
1830
void
1831
final_prescan_insn (rtx insn, rtx *operand ATTRIBUTE_UNUSED,
1832
                    int num_operands ATTRIBUTE_UNUSED)
1833
{
1834
  /* This holds the last insn address.  */
1835
  static int last_insn_address = 0;
1836
 
1837
  const int uid = INSN_UID (insn);
1838
 
1839
  if (TARGET_ADDRESSES)
1840
    {
1841
      fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid),
1842
               INSN_ADDRESSES (uid) - last_insn_address);
1843
      last_insn_address = INSN_ADDRESSES (uid);
1844
    }
1845
}
1846
 
1847
/* Prepare for an SI sized move.  */
1848
 
1849
int
1850
h8300_expand_movsi (rtx operands[])
1851
{
1852
  rtx src = operands[1];
1853
  rtx dst = operands[0];
1854
  if (!reload_in_progress && !reload_completed)
1855
    {
1856
      if (!register_operand (dst, GET_MODE (dst)))
1857
        {
1858
          rtx tmp = gen_reg_rtx (GET_MODE (dst));
1859
          emit_move_insn (tmp, src);
1860
          operands[1] = tmp;
1861
        }
1862
    }
1863
  return 0;
1864
}
1865
 
1866
/* Given FROM and TO register numbers, say whether this elimination is allowed.
1867
   Frame pointer elimination is automatically handled.
1868
 
1869
   For the h8300, if frame pointer elimination is being done, we would like to
1870
   convert ap and rp into sp, not fp.
1871
 
1872
   All other eliminations are valid.  */
1873
 
1874
static bool
1875
h8300_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
1876
{
1877
  return (to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true);
1878
}
1879
 
1880
/* Conditionally modify register usage based on target flags.  */
1881
 
1882
static void
1883
h8300_conditional_register_usage (void)
1884
{
1885
  if (!TARGET_MAC)
1886
    fixed_regs[MAC_REG] = call_used_regs[MAC_REG] = 1;
1887
}
1888
 
1889
/* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1890
   Define the offset between two registers, one to be eliminated, and
1891
   the other its replacement, at the start of a routine.  */
1892
 
1893
int
1894
h8300_initial_elimination_offset (int from, int to)
1895
{
1896
  /* The number of bytes that the return address takes on the stack.  */
1897
  int pc_size = POINTER_SIZE / BITS_PER_UNIT;
1898
 
1899
  /* The number of bytes that the saved frame pointer takes on the stack.  */
1900
  int fp_size = frame_pointer_needed * UNITS_PER_WORD;
1901
 
1902
  /* The number of bytes that the saved registers, excluding the frame
1903
     pointer, take on the stack.  */
1904
  int saved_regs_size = 0;
1905
 
1906
  /* The number of bytes that the locals takes on the stack.  */
1907
  int frame_size = round_frame_size (get_frame_size ());
1908
 
1909
  int regno;
1910
 
1911
  for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
1912
    if (WORD_REG_USED (regno))
1913
      saved_regs_size += UNITS_PER_WORD;
1914
 
1915
  /* Adjust saved_regs_size because the above loop took the frame
1916
     pointer int account.  */
1917
  saved_regs_size -= fp_size;
1918
 
1919
  switch (to)
1920
    {
1921
    case HARD_FRAME_POINTER_REGNUM:
1922
      switch (from)
1923
        {
1924
        case ARG_POINTER_REGNUM:
1925
          return pc_size + fp_size;
1926
        case RETURN_ADDRESS_POINTER_REGNUM:
1927
          return fp_size;
1928
        case FRAME_POINTER_REGNUM:
1929
          return -saved_regs_size;
1930
        default:
1931
          gcc_unreachable ();
1932
        }
1933
      break;
1934
    case STACK_POINTER_REGNUM:
1935
      switch (from)
1936
        {
1937
        case ARG_POINTER_REGNUM:
1938
          return pc_size + saved_regs_size + frame_size;
1939
        case RETURN_ADDRESS_POINTER_REGNUM:
1940
          return saved_regs_size + frame_size;
1941
        case FRAME_POINTER_REGNUM:
1942
          return frame_size;
1943
        default:
1944
          gcc_unreachable ();
1945
        }
1946
      break;
1947
    default:
1948
      gcc_unreachable ();
1949
    }
1950
  gcc_unreachable ();
1951
}
1952
 
1953
/* Worker function for RETURN_ADDR_RTX.  */
1954
 
1955
rtx
1956
h8300_return_addr_rtx (int count, rtx frame)
1957
{
1958
  rtx ret;
1959
 
1960
  if (count == 0)
1961
    ret = gen_rtx_MEM (Pmode,
1962
                       gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM));
1963
  else if (flag_omit_frame_pointer)
1964
    return (rtx) 0;
1965
  else
1966
    ret = gen_rtx_MEM (Pmode,
1967
                       memory_address (Pmode,
1968
                                       plus_constant (frame, UNITS_PER_WORD)));
1969
  set_mem_alias_set (ret, get_frame_alias_set ());
1970
  return ret;
1971
}
1972
 
1973
/* Update the condition code from the insn.  */
1974
 
1975
void
1976
notice_update_cc (rtx body, rtx insn)
1977
{
1978
  rtx set;
1979
 
1980
  switch (get_attr_cc (insn))
1981
    {
1982
    case CC_NONE:
1983
      /* Insn does not affect CC at all.  */
1984
      break;
1985
 
1986
    case CC_NONE_0HIT:
1987
      /* Insn does not change CC, but the 0'th operand has been changed.  */
1988
      if (cc_status.value1 != 0
1989
          && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
1990
        cc_status.value1 = 0;
1991
      if (cc_status.value2 != 0
1992
          && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value2))
1993
        cc_status.value2 = 0;
1994
      break;
1995
 
1996
    case CC_SET_ZN:
1997
      /* Insn sets the Z,N flags of CC to recog_data.operand[0].
1998
         The V flag is unusable.  The C flag may or may not be known but
1999
         that's ok because alter_cond will change tests to use EQ/NE.  */
2000
      CC_STATUS_INIT;
2001
      cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
2002
      set = single_set (insn);
2003
      cc_status.value1 = SET_SRC (set);
2004
      if (SET_DEST (set) != cc0_rtx)
2005
        cc_status.value2 = SET_DEST (set);
2006
      break;
2007
 
2008
    case CC_SET_ZNV:
2009
      /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
2010
         The C flag may or may not be known but that's ok because
2011
         alter_cond will change tests to use EQ/NE.  */
2012
      CC_STATUS_INIT;
2013
      cc_status.flags |= CC_NO_CARRY;
2014
      set = single_set (insn);
2015
      cc_status.value1 = SET_SRC (set);
2016
      if (SET_DEST (set) != cc0_rtx)
2017
        {
2018
          /* If the destination is STRICT_LOW_PART, strip off
2019
             STRICT_LOW_PART.  */
2020
          if (GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
2021
            cc_status.value2 = XEXP (SET_DEST (set), 0);
2022
          else
2023
            cc_status.value2 = SET_DEST (set);
2024
        }
2025
      break;
2026
 
2027
    case CC_COMPARE:
2028
      /* The insn is a compare instruction.  */
2029
      CC_STATUS_INIT;
2030
      cc_status.value1 = SET_SRC (body);
2031
      break;
2032
 
2033
    case CC_CLOBBER:
2034
      /* Insn doesn't leave CC in a usable state.  */
2035
      CC_STATUS_INIT;
2036
      break;
2037
    }
2038
}
2039
 
2040
/* Given that X occurs in an address of the form (plus X constant),
2041
   return the part of X that is expected to be a register.  There are
2042
   four kinds of addressing mode to recognize:
2043
 
2044
        @(dd,Rn)
2045
        @(dd,RnL.b)
2046
        @(dd,Rn.w)
2047
        @(dd,ERn.l)
2048
 
2049
   If SIZE is nonnull, and the address is one of the last three forms,
2050
   set *SIZE to the index multiplication factor.  Set it to 0 for
2051
   plain @(dd,Rn) addresses.
2052
 
2053
   MODE is the mode of the value being accessed.  It can be VOIDmode
2054
   if the address is known to be valid, but its mode is unknown.  */
2055
 
2056
static rtx
2057
h8300_get_index (rtx x, enum machine_mode mode, int *size)
2058
{
2059
  int dummy, factor;
2060
 
2061
  if (size == 0)
2062
    size = &dummy;
2063
 
2064
  factor = (mode == VOIDmode ? 0 : GET_MODE_SIZE (mode));
2065
  if (TARGET_H8300SX
2066
      && factor <= 4
2067
      && (mode == VOIDmode
2068
          || GET_MODE_CLASS (mode) == MODE_INT
2069
          || GET_MODE_CLASS (mode) == MODE_FLOAT))
2070
    {
2071
      if (factor <= 1 && GET_CODE (x) == ZERO_EXTEND)
2072
        {
2073
          /* When accessing byte-sized values, the index can be
2074
             a zero-extended QImode or HImode register.  */
2075
          *size = GET_MODE_SIZE (GET_MODE (XEXP (x, 0)));
2076
          return XEXP (x, 0);
2077
        }
2078
      else
2079
        {
2080
          /* We're looking for addresses of the form:
2081
 
2082
                 (mult X I)
2083
              or (mult (zero_extend X) I)
2084
 
2085
             where I is the size of the operand being accessed.
2086
             The canonical form of the second expression is:
2087
 
2088
                 (and (mult (subreg X) I) J)
2089
 
2090
             where J == GET_MODE_MASK (GET_MODE (X)) * I.  */
2091
          rtx index;
2092
 
2093
          if (GET_CODE (x) == AND
2094
              && GET_CODE (XEXP (x, 1)) == CONST_INT
2095
              && (factor == 0
2096
                  || INTVAL (XEXP (x, 1)) == 0xff * factor
2097
                  || INTVAL (XEXP (x, 1)) == 0xffff * factor))
2098
            {
2099
              index = XEXP (x, 0);
2100
              *size = (INTVAL (XEXP (x, 1)) >= 0xffff ? 2 : 1);
2101
            }
2102
          else
2103
            {
2104
              index = x;
2105
              *size = 4;
2106
            }
2107
 
2108
          if (GET_CODE (index) == MULT
2109
              && GET_CODE (XEXP (index, 1)) == CONST_INT
2110
              && (factor == 0 || factor == INTVAL (XEXP (index, 1))))
2111
            return XEXP (index, 0);
2112
        }
2113
    }
2114
  *size = 0;
2115
  return x;
2116
}
2117
 
2118
/* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P.
2119
 
2120
   On the H8/300, the predecrement and postincrement address depend thus
2121
   (the amount of decrement or increment being the length of the operand).  */
2122
 
2123
static bool
2124
h8300_mode_dependent_address_p (const_rtx addr)
2125
{
2126
  if (GET_CODE (addr) == PLUS
2127
      && h8300_get_index (XEXP (addr, 0), VOIDmode, 0) != XEXP (addr, 0))
2128
    return true;
2129
 
2130
  return false;
2131
}
2132
 
2133
static const h8300_length_table addb_length_table =
2134
{
2135
  /* #xx  Rs   @aa  @Rs  @xx  */
2136
  {  2,   2,   4,   4,   4  }, /* add.b xx,Rd  */
2137
  {  4,   4,   4,   4,   6  }, /* add.b xx,@aa */
2138
  {  4,   4,   4,   4,   6  }, /* add.b xx,@Rd */
2139
  {  6,   4,   4,   4,   6  }  /* add.b xx,@xx */
2140
};
2141
 
2142
static const h8300_length_table addw_length_table =
2143
{
2144
  /* #xx  Rs   @aa  @Rs  @xx  */
2145
  {  2,   2,   4,   4,   4  }, /* add.w xx,Rd  */
2146
  {  4,   4,   4,   4,   6  }, /* add.w xx,@aa */
2147
  {  4,   4,   4,   4,   6  }, /* add.w xx,@Rd */
2148
  {  4,   4,   4,   4,   6  }  /* add.w xx,@xx */
2149
};
2150
 
2151
static const h8300_length_table addl_length_table =
2152
{
2153
  /* #xx  Rs   @aa  @Rs  @xx  */
2154
  {  2,   2,   4,   4,   4  }, /* add.l xx,Rd  */
2155
  {  4,   4,   6,   6,   6  }, /* add.l xx,@aa */
2156
  {  4,   4,   6,   6,   6  }, /* add.l xx,@Rd */
2157
  {  4,   4,   6,   6,   6  }  /* add.l xx,@xx */
2158
};
2159
 
2160
#define logicb_length_table addb_length_table
2161
#define logicw_length_table addw_length_table
2162
 
2163
static const h8300_length_table logicl_length_table =
2164
{
2165
  /* #xx  Rs   @aa  @Rs  @xx  */
2166
  {  2,   4,   4,   4,   4  }, /* and.l xx,Rd  */
2167
  {  4,   4,   6,   6,   6  }, /* and.l xx,@aa */
2168
  {  4,   4,   6,   6,   6  }, /* and.l xx,@Rd */
2169
  {  4,   4,   6,   6,   6  }  /* and.l xx,@xx */
2170
};
2171
 
2172
static const h8300_length_table movb_length_table =
2173
{
2174
  /* #xx  Rs   @aa  @Rs  @xx  */
2175
  {  2,   2,   2,   2,   4  }, /* mov.b xx,Rd  */
2176
  {  4,   2,   4,   4,   4  }, /* mov.b xx,@aa */
2177
  {  4,   2,   4,   4,   4  }, /* mov.b xx,@Rd */
2178
  {  4,   4,   4,   4,   4  }  /* mov.b xx,@xx */
2179
};
2180
 
2181
#define movw_length_table movb_length_table
2182
 
2183
static const h8300_length_table movl_length_table =
2184
{
2185
  /* #xx  Rs   @aa  @Rs  @xx  */
2186
  {  2,   2,   4,   4,   4  }, /* mov.l xx,Rd  */
2187
  {  4,   4,   4,   4,   4  }, /* mov.l xx,@aa */
2188
  {  4,   4,   4,   4,   4  }, /* mov.l xx,@Rd */
2189
  {  4,   4,   4,   4,   4  }  /* mov.l xx,@xx */
2190
};
2191
 
2192
/* Return the size of the given address or displacement constant.  */
2193
 
2194
static unsigned int
2195
h8300_constant_length (rtx constant)
2196
{
2197
  /* Check for (@d:16,Reg).  */
2198
  if (GET_CODE (constant) == CONST_INT
2199
      && IN_RANGE (INTVAL (constant), -0x8000, 0x7fff))
2200
    return 2;
2201
 
2202
  /* Check for (@d:16,Reg) in cases where the displacement is
2203
     an absolute address.  */
2204
  if (Pmode == HImode || h8300_tiny_constant_address_p (constant))
2205
    return 2;
2206
 
2207
  return 4;
2208
}
2209
 
2210
/* Return the size of a displacement field in address ADDR, which should
2211
   have the form (plus X constant).  SIZE is the number of bytes being
2212
   accessed.  */
2213
 
2214
static unsigned int
2215
h8300_displacement_length (rtx addr, int size)
2216
{
2217
  rtx offset;
2218
 
2219
  offset = XEXP (addr, 1);
2220
 
2221
  /* Check for @(d:2,Reg).  */
2222
  if (register_operand (XEXP (addr, 0), VOIDmode)
2223
      && GET_CODE (offset) == CONST_INT
2224
      && (INTVAL (offset) == size
2225
          || INTVAL (offset) == size * 2
2226
          || INTVAL (offset) == size * 3))
2227
    return 0;
2228
 
2229
  return h8300_constant_length (offset);
2230
}
2231
 
2232
/* Store the class of operand OP in *OPCLASS and return the length of any
2233
   extra operand fields.  SIZE is the number of bytes in OP.  OPCLASS
2234
   can be null if only the length is needed.  */
2235
 
2236
static unsigned int
2237
h8300_classify_operand (rtx op, int size, enum h8300_operand_class *opclass)
2238
{
2239
  enum h8300_operand_class dummy;
2240
 
2241
  if (opclass == 0)
2242
    opclass = &dummy;
2243
 
2244
  if (CONSTANT_P (op))
2245
    {
2246
      *opclass = H8OP_IMMEDIATE;
2247
 
2248
      /* Byte-sized immediates are stored in the opcode fields.  */
2249
      if (size == 1)
2250
        return 0;
2251
 
2252
      /* If this is a 32-bit instruction, see whether the constant
2253
         will fit into a 16-bit immediate field.  */
2254
      if (TARGET_H8300SX
2255
          && size == 4
2256
          && GET_CODE (op) == CONST_INT
2257
          && IN_RANGE (INTVAL (op), 0, 0xffff))
2258
        return 2;
2259
 
2260
      return size;
2261
    }
2262
  else if (GET_CODE (op) == MEM)
2263
    {
2264
      op = XEXP (op, 0);
2265
      if (CONSTANT_P (op))
2266
        {
2267
          *opclass = H8OP_MEM_ABSOLUTE;
2268
          return h8300_constant_length (op);
2269
        }
2270
      else if (GET_CODE (op) == PLUS && CONSTANT_P (XEXP (op, 1)))
2271
        {
2272
          *opclass = H8OP_MEM_COMPLEX;
2273
          return h8300_displacement_length (op, size);
2274
        }
2275
      else if (GET_RTX_CLASS (GET_CODE (op)) == RTX_AUTOINC)
2276
        {
2277
          *opclass = H8OP_MEM_COMPLEX;
2278
          return 0;
2279
        }
2280
      else if (register_operand (op, VOIDmode))
2281
        {
2282
          *opclass = H8OP_MEM_BASE;
2283
          return 0;
2284
        }
2285
    }
2286
  gcc_assert (register_operand (op, VOIDmode));
2287
  *opclass = H8OP_REGISTER;
2288
  return 0;
2289
}
2290
 
2291
/* Return the length of the instruction described by TABLE given that
2292
   its operands are OP1 and OP2.  OP1 must be an h8300_dst_operand
2293
   and OP2 must be an h8300_src_operand.  */
2294
 
2295
static unsigned int
2296
h8300_length_from_table (rtx op1, rtx op2, const h8300_length_table *table)
2297
{
2298
  enum h8300_operand_class op1_class, op2_class;
2299
  unsigned int size, immediate_length;
2300
 
2301
  size = GET_MODE_SIZE (GET_MODE (op1));
2302
  immediate_length = (h8300_classify_operand (op1, size, &op1_class)
2303
                      + h8300_classify_operand (op2, size, &op2_class));
2304
  return immediate_length + (*table)[op1_class - 1][op2_class];
2305
}
2306
 
2307
/* Return the length of a unary instruction such as neg or not given that
2308
   its operand is OP.  */
2309
 
2310
unsigned int
2311
h8300_unary_length (rtx op)
2312
{
2313
  enum h8300_operand_class opclass;
2314
  unsigned int size, operand_length;
2315
 
2316
  size = GET_MODE_SIZE (GET_MODE (op));
2317
  operand_length = h8300_classify_operand (op, size, &opclass);
2318
  switch (opclass)
2319
    {
2320
    case H8OP_REGISTER:
2321
      return 2;
2322
 
2323
    case H8OP_MEM_BASE:
2324
      return (size == 4 ? 6 : 4);
2325
 
2326
    case H8OP_MEM_ABSOLUTE:
2327
      return operand_length + (size == 4 ? 6 : 4);
2328
 
2329
    case H8OP_MEM_COMPLEX:
2330
      return operand_length + 6;
2331
 
2332
    default:
2333
      gcc_unreachable ();
2334
    }
2335
}
2336
 
2337
/* Likewise short immediate instructions such as add.w #xx:3,OP.  */
2338
 
2339
static unsigned int
2340
h8300_short_immediate_length (rtx op)
2341
{
2342
  enum h8300_operand_class opclass;
2343
  unsigned int size, operand_length;
2344
 
2345
  size = GET_MODE_SIZE (GET_MODE (op));
2346
  operand_length = h8300_classify_operand (op, size, &opclass);
2347
 
2348
  switch (opclass)
2349
    {
2350
    case H8OP_REGISTER:
2351
      return 2;
2352
 
2353
    case H8OP_MEM_BASE:
2354
    case H8OP_MEM_ABSOLUTE:
2355
    case H8OP_MEM_COMPLEX:
2356
      return 4 + operand_length;
2357
 
2358
    default:
2359
      gcc_unreachable ();
2360
    }
2361
}
2362
 
2363
/* Likewise bitfield load and store instructions.  */
2364
 
2365
static unsigned int
2366
h8300_bitfield_length (rtx op, rtx op2)
2367
{
2368
  enum h8300_operand_class opclass;
2369
  unsigned int size, operand_length;
2370
 
2371
  if (GET_CODE (op) == REG)
2372
    op = op2;
2373
  gcc_assert (GET_CODE (op) != REG);
2374
 
2375
  size = GET_MODE_SIZE (GET_MODE (op));
2376
  operand_length = h8300_classify_operand (op, size, &opclass);
2377
 
2378
  switch (opclass)
2379
    {
2380
    case H8OP_MEM_BASE:
2381
    case H8OP_MEM_ABSOLUTE:
2382
    case H8OP_MEM_COMPLEX:
2383
      return 4 + operand_length;
2384
 
2385
    default:
2386
      gcc_unreachable ();
2387
    }
2388
}
2389
 
2390
/* Calculate the length of general binary instruction INSN using TABLE.  */
2391
 
2392
static unsigned int
2393
h8300_binary_length (rtx insn, const h8300_length_table *table)
2394
{
2395
  rtx set;
2396
 
2397
  set = single_set (insn);
2398
  gcc_assert (set);
2399
 
2400
  if (BINARY_P (SET_SRC (set)))
2401
    return h8300_length_from_table (XEXP (SET_SRC (set), 0),
2402
                                    XEXP (SET_SRC (set), 1), table);
2403
  else
2404
    {
2405
      gcc_assert (GET_RTX_CLASS (GET_CODE (SET_SRC (set))) == RTX_TERNARY);
2406
      return h8300_length_from_table (XEXP (XEXP (SET_SRC (set), 1), 0),
2407
                                      XEXP (XEXP (SET_SRC (set), 1), 1),
2408
                                      table);
2409
    }
2410
}
2411
 
2412
/* Subroutine of h8300_move_length.  Return true if OP is 1- or 2-byte
2413
   memory reference and either (1) it has the form @(d:16,Rn) or
2414
   (2) its address has the code given by INC_CODE.  */
2415
 
2416
static bool
2417
h8300_short_move_mem_p (rtx op, enum rtx_code inc_code)
2418
{
2419
  rtx addr;
2420
  unsigned int size;
2421
 
2422
  if (GET_CODE (op) != MEM)
2423
    return false;
2424
 
2425
  addr = XEXP (op, 0);
2426
  size = GET_MODE_SIZE (GET_MODE (op));
2427
  if (size != 1 && size != 2)
2428
    return false;
2429
 
2430
  return (GET_CODE (addr) == inc_code
2431
          || (GET_CODE (addr) == PLUS
2432
              && GET_CODE (XEXP (addr, 0)) == REG
2433
              && h8300_displacement_length (addr, size) == 2));
2434
}
2435
 
2436
/* Calculate the length of move instruction INSN using the given length
2437
   table.  Although the tables are correct for most cases, there is some
2438
   irregularity in the length of mov.b and mov.w.  The following forms:
2439
 
2440
        mov @ERs+, Rd
2441
        mov @(d:16,ERs), Rd
2442
        mov Rs, @-ERd
2443
        mov Rs, @(d:16,ERd)
2444
 
2445
   are two bytes shorter than most other "mov Rs, @complex" or
2446
   "mov @complex,Rd" combinations.  */
2447
 
2448
static unsigned int
2449
h8300_move_length (rtx *operands, const h8300_length_table *table)
2450
{
2451
  unsigned int size;
2452
 
2453
  size = h8300_length_from_table (operands[0], operands[1], table);
2454
  if (REG_P (operands[0]) && h8300_short_move_mem_p (operands[1], POST_INC))
2455
    size -= 2;
2456
  if (REG_P (operands[1]) && h8300_short_move_mem_p (operands[0], PRE_DEC))
2457
    size -= 2;
2458
  return size;
2459
}
2460
 
2461
/* Return the length of a mova instruction with the given operands.
2462
   DEST is the register destination, SRC is the source address and
2463
   OFFSET is the 16-bit or 32-bit displacement.  */
2464
 
2465
static unsigned int
2466
h8300_mova_length (rtx dest, rtx src, rtx offset)
2467
{
2468
  unsigned int size;
2469
 
2470
  size = (2
2471
          + h8300_constant_length (offset)
2472
          + h8300_classify_operand (src, GET_MODE_SIZE (GET_MODE (src)), 0));
2473
  if (!REG_P (dest) || !REG_P (src) || REGNO (src) != REGNO (dest))
2474
    size += 2;
2475
  return size;
2476
}
2477
 
2478
/* Compute the length of INSN based on its length_table attribute.
2479
   OPERANDS is the array of its operands.  */
2480
 
2481
unsigned int
2482
h8300_insn_length_from_table (rtx insn, rtx * operands)
2483
{
2484
  switch (get_attr_length_table (insn))
2485
    {
2486
    case LENGTH_TABLE_NONE:
2487
      gcc_unreachable ();
2488
 
2489
    case LENGTH_TABLE_ADDB:
2490
      return h8300_binary_length (insn, &addb_length_table);
2491
 
2492
    case LENGTH_TABLE_ADDW:
2493
      return h8300_binary_length (insn, &addw_length_table);
2494
 
2495
    case LENGTH_TABLE_ADDL:
2496
      return h8300_binary_length (insn, &addl_length_table);
2497
 
2498
    case LENGTH_TABLE_LOGICB:
2499
      return h8300_binary_length (insn, &logicb_length_table);
2500
 
2501
    case LENGTH_TABLE_MOVB:
2502
      return h8300_move_length (operands, &movb_length_table);
2503
 
2504
    case LENGTH_TABLE_MOVW:
2505
      return h8300_move_length (operands, &movw_length_table);
2506
 
2507
    case LENGTH_TABLE_MOVL:
2508
      return h8300_move_length (operands, &movl_length_table);
2509
 
2510
    case LENGTH_TABLE_MOVA:
2511
      return h8300_mova_length (operands[0], operands[1], operands[2]);
2512
 
2513
    case LENGTH_TABLE_MOVA_ZERO:
2514
      return h8300_mova_length (operands[0], operands[1], const0_rtx);
2515
 
2516
    case LENGTH_TABLE_UNARY:
2517
      return h8300_unary_length (operands[0]);
2518
 
2519
    case LENGTH_TABLE_MOV_IMM4:
2520
      return 2 + h8300_classify_operand (operands[0], 0, 0);
2521
 
2522
    case LENGTH_TABLE_SHORT_IMMEDIATE:
2523
      return h8300_short_immediate_length (operands[0]);
2524
 
2525
    case LENGTH_TABLE_BITFIELD:
2526
      return h8300_bitfield_length (operands[0], operands[1]);
2527
 
2528
    case LENGTH_TABLE_BITBRANCH:
2529
      return h8300_bitfield_length (operands[1], operands[2]) - 2;
2530
 
2531
    default:
2532
      gcc_unreachable ();
2533
    }
2534
}
2535
 
2536
/* Return true if LHS and RHS are memory references that can be mapped
2537
   to the same h8sx assembly operand.  LHS appears as the destination of
2538
   an instruction and RHS appears as a source.
2539
 
2540
   Three cases are allowed:
2541
 
2542
        - RHS is @+Rn or @-Rn, LHS is @Rn
2543
        - RHS is @Rn, LHS is @Rn+ or @Rn-
2544
        - RHS and LHS have the same address and neither has side effects.  */
2545
 
2546
bool
2547
h8sx_mergeable_memrefs_p (rtx lhs, rtx rhs)
2548
{
2549
  if (GET_CODE (rhs) == MEM && GET_CODE (lhs) == MEM)
2550
    {
2551
      rhs = XEXP (rhs, 0);
2552
      lhs = XEXP (lhs, 0);
2553
 
2554
      if (GET_CODE (rhs) == PRE_INC || GET_CODE (rhs) == PRE_DEC)
2555
        return rtx_equal_p (XEXP (rhs, 0), lhs);
2556
 
2557
      if (GET_CODE (lhs) == POST_INC || GET_CODE (lhs) == POST_DEC)
2558
        return rtx_equal_p (rhs, XEXP (lhs, 0));
2559
 
2560
      if (rtx_equal_p (rhs, lhs))
2561
        return true;
2562
    }
2563
  return false;
2564
}
2565
 
2566
/* Return true if OPERANDS[1] can be mapped to the same assembly
2567
   operand as OPERANDS[0].  */
2568
 
2569
bool
2570
h8300_operands_match_p (rtx *operands)
2571
{
2572
  if (register_operand (operands[0], VOIDmode)
2573
      && register_operand (operands[1], VOIDmode))
2574
    return true;
2575
 
2576
  if (h8sx_mergeable_memrefs_p (operands[0], operands[1]))
2577
    return true;
2578
 
2579
  return false;
2580
}
2581
 
2582
/* Try using movmd to move LENGTH bytes from memory region SRC to memory
2583
   region DEST.  The two regions do not overlap and have the common
2584
   alignment given by ALIGNMENT.  Return true on success.
2585
 
2586
   Using movmd for variable-length moves seems to involve some
2587
   complex trade-offs.  For instance:
2588
 
2589
      - Preparing for a movmd instruction is similar to preparing
2590
        for a memcpy.  The main difference is that the arguments
2591
        are moved into er4, er5 and er6 rather than er0, er1 and er2.
2592
 
2593
      - Since movmd clobbers the frame pointer, we need to save
2594
        and restore it somehow when frame_pointer_needed.  This can
2595
        sometimes make movmd sequences longer than calls to memcpy().
2596
 
2597
      - The counter register is 16 bits, so the instruction is only
2598
        suitable for variable-length moves when sizeof (size_t) == 2.
2599
        That's only true in normal mode.
2600
 
2601
      - We will often lack static alignment information.  Falling back
2602
        on movmd.b would likely be slower than calling memcpy(), at least
2603
        for big moves.
2604
 
2605
   This function therefore only uses movmd when the length is a
2606
   known constant, and only then if -fomit-frame-pointer is in
2607
   effect or if we're not optimizing for size.
2608
 
2609
   At the moment the function uses movmd for all in-range constants,
2610
   but it might be better to fall back on memcpy() for large moves
2611
   if ALIGNMENT == 1.  */
2612
 
2613
bool
2614
h8sx_emit_movmd (rtx dest, rtx src, rtx length,
2615
                 HOST_WIDE_INT alignment)
2616
{
2617
  if (!flag_omit_frame_pointer && optimize_size)
2618
    return false;
2619
 
2620
  if (GET_CODE (length) == CONST_INT)
2621
    {
2622
      rtx dest_reg, src_reg, first_dest, first_src;
2623
      HOST_WIDE_INT n;
2624
      int factor;
2625
 
2626
      /* Use movmd.l if the alignment allows it, otherwise fall back
2627
         on movmd.b.  */
2628
      factor = (alignment >= 2 ? 4 : 1);
2629
 
2630
      /* Make sure the length is within range.  We can handle counter
2631
         values up to 65536, although HImode truncation will make
2632
         the count appear negative in rtl dumps.  */
2633
      n = INTVAL (length);
2634
      if (n <= 0 || n / factor > 65536)
2635
        return false;
2636
 
2637
      /* Create temporary registers for the source and destination
2638
         pointers.  Initialize them to the start of each region.  */
2639
      dest_reg = copy_addr_to_reg (XEXP (dest, 0));
2640
      src_reg = copy_addr_to_reg (XEXP (src, 0));
2641
 
2642
      /* Create references to the movmd source and destination blocks.  */
2643
      first_dest = replace_equiv_address (dest, dest_reg);
2644
      first_src = replace_equiv_address (src, src_reg);
2645
 
2646
      set_mem_size (first_dest, n & -factor);
2647
      set_mem_size (first_src, n & -factor);
2648
 
2649
      length = copy_to_mode_reg (HImode, gen_int_mode (n / factor, HImode));
2650
      emit_insn (gen_movmd (first_dest, first_src, length, GEN_INT (factor)));
2651
 
2652
      if ((n & -factor) != n)
2653
        {
2654
          /* Move SRC and DEST past the region we just copied.
2655
             This is done to update the memory attributes.  */
2656
          dest = adjust_address (dest, BLKmode, n & -factor);
2657
          src = adjust_address (src, BLKmode, n & -factor);
2658
 
2659
          /* Replace the addresses with the source and destination
2660
             registers, which movmd has left with the right values.  */
2661
          dest = replace_equiv_address (dest, dest_reg);
2662
          src = replace_equiv_address (src, src_reg);
2663
 
2664
          /* Mop up the left-over bytes.  */
2665
          if (n & 2)
2666
            emit_move_insn (adjust_address (dest, HImode, 0),
2667
                            adjust_address (src, HImode, 0));
2668
          if (n & 1)
2669
            emit_move_insn (adjust_address (dest, QImode, n & 2),
2670
                            adjust_address (src, QImode, n & 2));
2671
        }
2672
      return true;
2673
    }
2674
  return false;
2675
}
2676
 
2677
/* Move ADDR into er6 after pushing its old value onto the stack.  */
2678
 
2679
void
2680
h8300_swap_into_er6 (rtx addr)
2681
{
2682
  rtx insn = push (HARD_FRAME_POINTER_REGNUM);
2683
  if (frame_pointer_needed)
2684
    add_reg_note (insn, REG_CFA_DEF_CFA,
2685
                  plus_constant (gen_rtx_MEM (Pmode, stack_pointer_rtx),
2686
                                 2 * UNITS_PER_WORD));
2687
  else
2688
    add_reg_note (insn, REG_CFA_ADJUST_CFA,
2689
                  gen_rtx_SET (VOIDmode, stack_pointer_rtx,
2690
                               plus_constant (stack_pointer_rtx, 4)));
2691
 
2692
  emit_move_insn (hard_frame_pointer_rtx, addr);
2693
  if (REGNO (addr) == SP_REG)
2694
    emit_move_insn (hard_frame_pointer_rtx,
2695
                    plus_constant (hard_frame_pointer_rtx,
2696
                                   GET_MODE_SIZE (word_mode)));
2697
}
2698
 
2699
/* Move the current value of er6 into ADDR and pop its old value
2700
   from the stack.  */
2701
 
2702
void
2703
h8300_swap_out_of_er6 (rtx addr)
2704
{
2705
  rtx insn;
2706
 
2707
  if (REGNO (addr) != SP_REG)
2708
    emit_move_insn (addr, hard_frame_pointer_rtx);
2709
 
2710
  insn = pop (HARD_FRAME_POINTER_REGNUM);
2711
  RTX_FRAME_RELATED_P (insn) = 1;
2712
  if (frame_pointer_needed)
2713
    add_reg_note (insn, REG_CFA_DEF_CFA,
2714
                  plus_constant (hard_frame_pointer_rtx, 2 * UNITS_PER_WORD));
2715
  else
2716
    add_reg_note (insn, REG_CFA_ADJUST_CFA,
2717
                  gen_rtx_SET (VOIDmode, stack_pointer_rtx,
2718
                               plus_constant (stack_pointer_rtx, -4)));
2719
}
2720
 
2721
/* Return the length of mov instruction.  */
2722
 
2723
unsigned int
2724
compute_mov_length (rtx *operands)
2725
{
2726
  /* If the mov instruction involves a memory operand, we compute the
2727
     length, assuming the largest addressing mode is used, and then
2728
     adjust later in the function.  Otherwise, we compute and return
2729
     the exact length in one step.  */
2730
  enum machine_mode mode = GET_MODE (operands[0]);
2731
  rtx dest = operands[0];
2732
  rtx src = operands[1];
2733
  rtx addr;
2734
 
2735
  if (GET_CODE (src) == MEM)
2736
    addr = XEXP (src, 0);
2737
  else if (GET_CODE (dest) == MEM)
2738
    addr = XEXP (dest, 0);
2739
  else
2740
    addr = NULL_RTX;
2741
 
2742
  if (TARGET_H8300)
2743
    {
2744
      unsigned int base_length;
2745
 
2746
      switch (mode)
2747
        {
2748
        case QImode:
2749
          if (addr == NULL_RTX)
2750
            return 2;
2751
 
2752
          /* The eightbit addressing is available only in QImode, so
2753
             go ahead and take care of it.  */
2754
          if (h8300_eightbit_constant_address_p (addr))
2755
            return 2;
2756
 
2757
          base_length = 4;
2758
          break;
2759
 
2760
        case HImode:
2761
          if (addr == NULL_RTX)
2762
            {
2763
              if (REG_P (src))
2764
                return 2;
2765
 
2766
              if (src == const0_rtx)
2767
                return 2;
2768
 
2769
              return 4;
2770
            }
2771
 
2772
          base_length = 4;
2773
          break;
2774
 
2775
        case SImode:
2776
          if (addr == NULL_RTX)
2777
            {
2778
              if (REG_P (src))
2779
                return 4;
2780
 
2781
              if (GET_CODE (src) == CONST_INT)
2782
                {
2783
                  if (src == const0_rtx)
2784
                    return 4;
2785
 
2786
                  if ((INTVAL (src) & 0xffff) == 0)
2787
                    return 6;
2788
 
2789
                  if ((INTVAL (src) & 0xffff) == 0)
2790
                    return 6;
2791
 
2792
                  if ((INTVAL (src) & 0xffff)
2793
                      == ((INTVAL (src) >> 16) & 0xffff))
2794
                    return 6;
2795
                }
2796
              return 8;
2797
            }
2798
 
2799
          base_length = 8;
2800
          break;
2801
 
2802
        case SFmode:
2803
          if (addr == NULL_RTX)
2804
            {
2805
              if (REG_P (src))
2806
                return 4;
2807
 
2808
              if (satisfies_constraint_G (src))
2809
                return 4;
2810
 
2811
              return 8;
2812
            }
2813
 
2814
          base_length = 8;
2815
          break;
2816
 
2817
        default:
2818
          gcc_unreachable ();
2819
        }
2820
 
2821
      /* Adjust the length based on the addressing mode used.
2822
         Specifically, we subtract the difference between the actual
2823
         length and the longest one, which is @(d:16,Rs).  For SImode
2824
         and SFmode, we double the adjustment because two mov.w are
2825
         used to do the job.  */
2826
 
2827
      /* @Rs+ and @-Rd are 2 bytes shorter than the longest.  */
2828
      if (GET_CODE (addr) == PRE_DEC
2829
          || GET_CODE (addr) == POST_INC)
2830
        {
2831
          if (mode == QImode || mode == HImode)
2832
            return base_length - 2;
2833
          else
2834
            /* In SImode and SFmode, we use two mov.w instructions, so
2835
               double the adjustment.  */
2836
            return base_length - 4;
2837
        }
2838
 
2839
      /* @Rs and @Rd are 2 bytes shorter than the longest.  Note that
2840
         in SImode and SFmode, the second mov.w involves an address
2841
         with displacement, namely @(2,Rs) or @(2,Rd), so we subtract
2842
         only 2 bytes.  */
2843
      if (GET_CODE (addr) == REG)
2844
        return base_length - 2;
2845
 
2846
      return base_length;
2847
    }
2848
  else
2849
    {
2850
      unsigned int base_length;
2851
 
2852
      switch (mode)
2853
        {
2854
        case QImode:
2855
          if (addr == NULL_RTX)
2856
            return 2;
2857
 
2858
          /* The eightbit addressing is available only in QImode, so
2859
             go ahead and take care of it.  */
2860
          if (h8300_eightbit_constant_address_p (addr))
2861
            return 2;
2862
 
2863
          base_length = 8;
2864
          break;
2865
 
2866
        case HImode:
2867
          if (addr == NULL_RTX)
2868
            {
2869
              if (REG_P (src))
2870
                return 2;
2871
 
2872
              if (src == const0_rtx)
2873
                return 2;
2874
 
2875
              return 4;
2876
            }
2877
 
2878
          base_length = 8;
2879
          break;
2880
 
2881
        case SImode:
2882
          if (addr == NULL_RTX)
2883
            {
2884
              if (REG_P (src))
2885
                {
2886
                  if (REGNO (src) == MAC_REG || REGNO (dest) == MAC_REG)
2887
                    return 4;
2888
                  else
2889
                    return 2;
2890
                }
2891
 
2892
              if (GET_CODE (src) == CONST_INT)
2893
                {
2894
                  int val = INTVAL (src);
2895
 
2896
                  if (val == 0)
2897
                    return 2;
2898
 
2899
                  if (val == (val & 0x00ff) || val == (val & 0xff00))
2900
                    return 4;
2901
 
2902
                  switch (val & 0xffffffff)
2903
                    {
2904
                    case 0xffffffff:
2905
                    case 0xfffffffe:
2906
                    case 0xfffffffc:
2907
                    case 0x0000ffff:
2908
                    case 0x0000fffe:
2909
                    case 0xffff0000:
2910
                    case 0xfffe0000:
2911
                    case 0x00010000:
2912
                    case 0x00020000:
2913
                      return 4;
2914
                    }
2915
                }
2916
              return 6;
2917
            }
2918
 
2919
          base_length = 10;
2920
          break;
2921
 
2922
        case SFmode:
2923
          if (addr == NULL_RTX)
2924
            {
2925
              if (REG_P (src))
2926
                return 2;
2927
 
2928
              if (satisfies_constraint_G (src))
2929
                return 2;
2930
 
2931
              return 6;
2932
            }
2933
 
2934
          base_length = 10;
2935
          break;
2936
 
2937
        default:
2938
          gcc_unreachable ();
2939
        }
2940
 
2941
      /* Adjust the length based on the addressing mode used.
2942
         Specifically, we subtract the difference between the actual
2943
         length and the longest one, which is @(d:24,ERs).  */
2944
 
2945
      /* @ERs+ and @-ERd are 6 bytes shorter than the longest.  */
2946
      if (GET_CODE (addr) == PRE_DEC
2947
          || GET_CODE (addr) == POST_INC)
2948
        return base_length - 6;
2949
 
2950
      /* @ERs and @ERd are 6 bytes shorter than the longest.  */
2951
      if (GET_CODE (addr) == REG)
2952
        return base_length - 6;
2953
 
2954
      /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
2955
         longest.  */
2956
      if (GET_CODE (addr) == PLUS
2957
          && GET_CODE (XEXP (addr, 0)) == REG
2958
          && GET_CODE (XEXP (addr, 1)) == CONST_INT
2959
          && INTVAL (XEXP (addr, 1)) > -32768
2960
          && INTVAL (XEXP (addr, 1)) < 32767)
2961
        return base_length - 4;
2962
 
2963
      /* @aa:16 is 4 bytes shorter than the longest.  */
2964
      if (h8300_tiny_constant_address_p (addr))
2965
        return base_length - 4;
2966
 
2967
      /* @aa:24 is 2 bytes shorter than the longest.  */
2968
      if (CONSTANT_P (addr))
2969
        return base_length - 2;
2970
 
2971
      return base_length;
2972
    }
2973
}
2974
 
2975
/* Output an addition insn.  */
2976
 
2977
const char *
2978
output_plussi (rtx *operands)
2979
{
2980
  enum machine_mode mode = GET_MODE (operands[0]);
2981
 
2982
  gcc_assert (mode == SImode);
2983
 
2984
  if (TARGET_H8300)
2985
    {
2986
      if (GET_CODE (operands[2]) == REG)
2987
        return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2988
 
2989
      if (GET_CODE (operands[2]) == CONST_INT)
2990
        {
2991
          HOST_WIDE_INT n = INTVAL (operands[2]);
2992
 
2993
          if ((n & 0xffffff) == 0)
2994
            return "add\t%z2,%z0";
2995
          if ((n & 0xffff) == 0)
2996
            return "add\t%y2,%y0\n\taddx\t%z2,%z0";
2997
          if ((n & 0xff) == 0)
2998
            return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2999
        }
3000
 
3001
      return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3002
    }
3003
  else
3004
    {
3005
      if (GET_CODE (operands[2]) == CONST_INT
3006
          && register_operand (operands[1], VOIDmode))
3007
        {
3008
          HOST_WIDE_INT intval = INTVAL (operands[2]);
3009
 
3010
          if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3011
            return "add.l\t%S2,%S0";
3012
          if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3013
            return "sub.l\t%G2,%S0";
3014
 
3015
          /* See if we can finish with 2 bytes.  */
3016
 
3017
          switch ((unsigned int) intval & 0xffffffff)
3018
            {
3019
            case 0x00000001:
3020
            case 0x00000002:
3021
            case 0x00000004:
3022
              return "adds\t%2,%S0";
3023
 
3024
            case 0xffffffff:
3025
            case 0xfffffffe:
3026
            case 0xfffffffc:
3027
              return "subs\t%G2,%S0";
3028
 
3029
            case 0x00010000:
3030
            case 0x00020000:
3031
              operands[2] = GEN_INT (intval >> 16);
3032
              return "inc.w\t%2,%e0";
3033
 
3034
            case 0xffff0000:
3035
            case 0xfffe0000:
3036
              operands[2] = GEN_INT (intval >> 16);
3037
              return "dec.w\t%G2,%e0";
3038
            }
3039
 
3040
          /* See if we can finish with 4 bytes.  */
3041
          if ((intval & 0xffff) == 0)
3042
            {
3043
              operands[2] = GEN_INT (intval >> 16);
3044
              return "add.w\t%2,%e0";
3045
            }
3046
        }
3047
 
3048
      if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
3049
        {
3050
          operands[2] = GEN_INT (-INTVAL (operands[2]));
3051
          return "sub.l\t%S2,%S0";
3052
        }
3053
      return "add.l\t%S2,%S0";
3054
    }
3055
}
3056
 
3057
/* ??? It would be much easier to add the h8sx stuff if a single function
3058
   classified the addition as either inc/dec, adds/subs, add.w or add.l.  */
3059
/* Compute the length of an addition insn.  */
3060
 
3061
unsigned int
3062
compute_plussi_length (rtx *operands)
3063
{
3064
  enum machine_mode mode = GET_MODE (operands[0]);
3065
 
3066
  gcc_assert (mode == SImode);
3067
 
3068
  if (TARGET_H8300)
3069
    {
3070
      if (GET_CODE (operands[2]) == REG)
3071
        return 6;
3072
 
3073
      if (GET_CODE (operands[2]) == CONST_INT)
3074
        {
3075
          HOST_WIDE_INT n = INTVAL (operands[2]);
3076
 
3077
          if ((n & 0xffffff) == 0)
3078
            return 2;
3079
          if ((n & 0xffff) == 0)
3080
            return 4;
3081
          if ((n & 0xff) == 0)
3082
            return 6;
3083
        }
3084
 
3085
      return 8;
3086
    }
3087
  else
3088
    {
3089
      if (GET_CODE (operands[2]) == CONST_INT
3090
          && register_operand (operands[1], VOIDmode))
3091
        {
3092
          HOST_WIDE_INT intval = INTVAL (operands[2]);
3093
 
3094
          if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3095
            return 2;
3096
          if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3097
            return 2;
3098
 
3099
          /* See if we can finish with 2 bytes.  */
3100
 
3101
          switch ((unsigned int) intval & 0xffffffff)
3102
            {
3103
            case 0x00000001:
3104
            case 0x00000002:
3105
            case 0x00000004:
3106
              return 2;
3107
 
3108
            case 0xffffffff:
3109
            case 0xfffffffe:
3110
            case 0xfffffffc:
3111
              return 2;
3112
 
3113
            case 0x00010000:
3114
            case 0x00020000:
3115
              return 2;
3116
 
3117
            case 0xffff0000:
3118
            case 0xfffe0000:
3119
              return 2;
3120
            }
3121
 
3122
          /* See if we can finish with 4 bytes.  */
3123
          if ((intval & 0xffff) == 0)
3124
            return 4;
3125
        }
3126
 
3127
      if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
3128
        return h8300_length_from_table (operands[0],
3129
                                        GEN_INT (-INTVAL (operands[2])),
3130
                                        &addl_length_table);
3131
      else
3132
        return h8300_length_from_table (operands[0], operands[2],
3133
                                        &addl_length_table);
3134
      return 6;
3135
    }
3136
}
3137
 
3138
/* Compute which flag bits are valid after an addition insn.  */
3139
 
3140
enum attr_cc
3141
compute_plussi_cc (rtx *operands)
3142
{
3143
  enum machine_mode mode = GET_MODE (operands[0]);
3144
 
3145
  gcc_assert (mode == SImode);
3146
 
3147
  if (TARGET_H8300)
3148
    {
3149
      return CC_CLOBBER;
3150
    }
3151
  else
3152
    {
3153
      if (GET_CODE (operands[2]) == CONST_INT
3154
          && register_operand (operands[1], VOIDmode))
3155
        {
3156
          HOST_WIDE_INT intval = INTVAL (operands[2]);
3157
 
3158
          if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3159
            return CC_SET_ZN;
3160
          if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3161
            return CC_SET_ZN;
3162
 
3163
          /* See if we can finish with 2 bytes.  */
3164
 
3165
          switch ((unsigned int) intval & 0xffffffff)
3166
            {
3167
            case 0x00000001:
3168
            case 0x00000002:
3169
            case 0x00000004:
3170
              return CC_NONE_0HIT;
3171
 
3172
            case 0xffffffff:
3173
            case 0xfffffffe:
3174
            case 0xfffffffc:
3175
              return CC_NONE_0HIT;
3176
 
3177
            case 0x00010000:
3178
            case 0x00020000:
3179
              return CC_CLOBBER;
3180
 
3181
            case 0xffff0000:
3182
            case 0xfffe0000:
3183
              return CC_CLOBBER;
3184
            }
3185
 
3186
          /* See if we can finish with 4 bytes.  */
3187
          if ((intval & 0xffff) == 0)
3188
            return CC_CLOBBER;
3189
        }
3190
 
3191
      return CC_SET_ZN;
3192
    }
3193
}
3194
 
3195
/* Output a logical insn.  */
3196
 
3197
const char *
3198
output_logical_op (enum machine_mode mode, rtx *operands)
3199
{
3200
  /* Figure out the logical op that we need to perform.  */
3201
  enum rtx_code code = GET_CODE (operands[3]);
3202
  /* Pretend that every byte is affected if both operands are registers.  */
3203
  const unsigned HOST_WIDE_INT intval =
3204
    (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
3205
                              /* Always use the full instruction if the
3206
                                 first operand is in memory.  It is better
3207
                                 to use define_splits to generate the shorter
3208
                                 sequence where valid.  */
3209
                              && register_operand (operands[1], VOIDmode)
3210
                              ? INTVAL (operands[2]) : 0x55555555);
3211
  /* The determinant of the algorithm.  If we perform an AND, 0
3212
     affects a bit.  Otherwise, 1 affects a bit.  */
3213
  const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
3214
  /* Break up DET into pieces.  */
3215
  const unsigned HOST_WIDE_INT b0 = (det >>  0) & 0xff;
3216
  const unsigned HOST_WIDE_INT b1 = (det >>  8) & 0xff;
3217
  const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
3218
  const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
3219
  const unsigned HOST_WIDE_INT w0 = (det >>  0) & 0xffff;
3220
  const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3221
  int lower_half_easy_p = 0;
3222
  int upper_half_easy_p = 0;
3223
  /* The name of an insn.  */
3224
  const char *opname;
3225
  char insn_buf[100];
3226
 
3227
  switch (code)
3228
    {
3229
    case AND:
3230
      opname = "and";
3231
      break;
3232
    case IOR:
3233
      opname = "or";
3234
      break;
3235
    case XOR:
3236
      opname = "xor";
3237
      break;
3238
    default:
3239
      gcc_unreachable ();
3240
    }
3241
 
3242
  switch (mode)
3243
    {
3244
    case HImode:
3245
      /* First, see if we can finish with one insn.  */
3246
      if ((TARGET_H8300H || TARGET_H8300S)
3247
          && b0 != 0
3248
          && b1 != 0)
3249
        {
3250
          sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname);
3251
          output_asm_insn (insn_buf, operands);
3252
        }
3253
      else
3254
        {
3255
          /* Take care of the lower byte.  */
3256
          if (b0 != 0)
3257
            {
3258
              sprintf (insn_buf, "%s\t%%s2,%%s0", opname);
3259
              output_asm_insn (insn_buf, operands);
3260
            }
3261
          /* Take care of the upper byte.  */
3262
          if (b1 != 0)
3263
            {
3264
              sprintf (insn_buf, "%s\t%%t2,%%t0", opname);
3265
              output_asm_insn (insn_buf, operands);
3266
            }
3267
        }
3268
      break;
3269
    case SImode:
3270
      if (TARGET_H8300H || TARGET_H8300S)
3271
        {
3272
          /* Determine if the lower half can be taken care of in no more
3273
             than two bytes.  */
3274
          lower_half_easy_p = (b0 == 0
3275
                               || b1 == 0
3276
                               || (code != IOR && w0 == 0xffff));
3277
 
3278
          /* Determine if the upper half can be taken care of in no more
3279
             than two bytes.  */
3280
          upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3281
                               || (code == AND && w1 == 0xff00));
3282
        }
3283
 
3284
      /* Check if doing everything with one insn is no worse than
3285
         using multiple insns.  */
3286
      if ((TARGET_H8300H || TARGET_H8300S)
3287
          && w0 != 0 && w1 != 0
3288
          && !(lower_half_easy_p && upper_half_easy_p)
3289
          && !(code == IOR && w1 == 0xffff
3290
               && (w0 & 0x8000) != 0 && lower_half_easy_p))
3291
        {
3292
          sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname);
3293
          output_asm_insn (insn_buf, operands);
3294
        }
3295
      else
3296
        {
3297
          /* Take care of the lower and upper words individually.  For
3298
             each word, we try different methods in the order of
3299
 
3300
             1) the special insn (in case of AND or XOR),
3301
             2) the word-wise insn, and
3302
             3) The byte-wise insn.  */
3303
          if (w0 == 0xffff
3304
              && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3305
            output_asm_insn ((code == AND)
3306
                             ? "sub.w\t%f0,%f0" : "not.w\t%f0",
3307
                             operands);
3308
          else if ((TARGET_H8300H || TARGET_H8300S)
3309
                   && (b0 != 0)
3310
                   && (b1 != 0))
3311
            {
3312
              sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname);
3313
              output_asm_insn (insn_buf, operands);
3314
            }
3315
          else
3316
            {
3317
              if (b0 != 0)
3318
                {
3319
                  sprintf (insn_buf, "%s\t%%w2,%%w0", opname);
3320
                  output_asm_insn (insn_buf, operands);
3321
                }
3322
              if (b1 != 0)
3323
                {
3324
                  sprintf (insn_buf, "%s\t%%x2,%%x0", opname);
3325
                  output_asm_insn (insn_buf, operands);
3326
                }
3327
            }
3328
 
3329
          if ((w1 == 0xffff)
3330
              && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3331
            output_asm_insn ((code == AND)
3332
                             ? "sub.w\t%e0,%e0" : "not.w\t%e0",
3333
                             operands);
3334
          else if ((TARGET_H8300H || TARGET_H8300S)
3335
                   && code == IOR
3336
                   && w1 == 0xffff
3337
                   && (w0 & 0x8000) != 0)
3338
            {
3339
              output_asm_insn ("exts.l\t%S0", operands);
3340
            }
3341
          else if ((TARGET_H8300H || TARGET_H8300S)
3342
                   && code == AND
3343
                   && w1 == 0xff00)
3344
            {
3345
              output_asm_insn ("extu.w\t%e0", operands);
3346
            }
3347
          else if (TARGET_H8300H || TARGET_H8300S)
3348
            {
3349
              if (w1 != 0)
3350
                {
3351
                  sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname);
3352
                  output_asm_insn (insn_buf, operands);
3353
                }
3354
            }
3355
          else
3356
            {
3357
              if (b2 != 0)
3358
                {
3359
                  sprintf (insn_buf, "%s\t%%y2,%%y0", opname);
3360
                  output_asm_insn (insn_buf, operands);
3361
                }
3362
              if (b3 != 0)
3363
                {
3364
                  sprintf (insn_buf, "%s\t%%z2,%%z0", opname);
3365
                  output_asm_insn (insn_buf, operands);
3366
                }
3367
            }
3368
        }
3369
      break;
3370
    default:
3371
      gcc_unreachable ();
3372
    }
3373
  return "";
3374
}
3375
 
3376
/* Compute the length of a logical insn.  */
3377
 
3378
unsigned int
3379
compute_logical_op_length (enum machine_mode mode, rtx *operands)
3380
{
3381
  /* Figure out the logical op that we need to perform.  */
3382
  enum rtx_code code = GET_CODE (operands[3]);
3383
  /* Pretend that every byte is affected if both operands are registers.  */
3384
  const unsigned HOST_WIDE_INT intval =
3385
    (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
3386
                              /* Always use the full instruction if the
3387
                                 first operand is in memory.  It is better
3388
                                 to use define_splits to generate the shorter
3389
                                 sequence where valid.  */
3390
                              && register_operand (operands[1], VOIDmode)
3391
                              ? INTVAL (operands[2]) : 0x55555555);
3392
  /* The determinant of the algorithm.  If we perform an AND, 0
3393
     affects a bit.  Otherwise, 1 affects a bit.  */
3394
  const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
3395
  /* Break up DET into pieces.  */
3396
  const unsigned HOST_WIDE_INT b0 = (det >>  0) & 0xff;
3397
  const unsigned HOST_WIDE_INT b1 = (det >>  8) & 0xff;
3398
  const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
3399
  const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
3400
  const unsigned HOST_WIDE_INT w0 = (det >>  0) & 0xffff;
3401
  const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3402
  int lower_half_easy_p = 0;
3403
  int upper_half_easy_p = 0;
3404
  /* Insn length.  */
3405
  unsigned int length = 0;
3406
 
3407
  switch (mode)
3408
    {
3409
    case HImode:
3410
      /* First, see if we can finish with one insn.  */
3411
      if ((TARGET_H8300H || TARGET_H8300S)
3412
          && b0 != 0
3413
          && b1 != 0)
3414
        {
3415
          length = h8300_length_from_table (operands[1], operands[2],
3416
                                            &logicw_length_table);
3417
        }
3418
      else
3419
        {
3420
          /* Take care of the lower byte.  */
3421
          if (b0 != 0)
3422
            length += 2;
3423
 
3424
          /* Take care of the upper byte.  */
3425
          if (b1 != 0)
3426
            length += 2;
3427
        }
3428
      break;
3429
    case SImode:
3430
      if (TARGET_H8300H || TARGET_H8300S)
3431
        {
3432
          /* Determine if the lower half can be taken care of in no more
3433
             than two bytes.  */
3434
          lower_half_easy_p = (b0 == 0
3435
                               || b1 == 0
3436
                               || (code != IOR && w0 == 0xffff));
3437
 
3438
          /* Determine if the upper half can be taken care of in no more
3439
             than two bytes.  */
3440
          upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3441
                               || (code == AND && w1 == 0xff00));
3442
        }
3443
 
3444
      /* Check if doing everything with one insn is no worse than
3445
         using multiple insns.  */
3446
      if ((TARGET_H8300H || TARGET_H8300S)
3447
          && w0 != 0 && w1 != 0
3448
          && !(lower_half_easy_p && upper_half_easy_p)
3449
          && !(code == IOR && w1 == 0xffff
3450
               && (w0 & 0x8000) != 0 && lower_half_easy_p))
3451
        {
3452
          length = h8300_length_from_table (operands[1], operands[2],
3453
                                            &logicl_length_table);
3454
        }
3455
      else
3456
        {
3457
          /* Take care of the lower and upper words individually.  For
3458
             each word, we try different methods in the order of
3459
 
3460
             1) the special insn (in case of AND or XOR),
3461
             2) the word-wise insn, and
3462
             3) The byte-wise insn.  */
3463
          if (w0 == 0xffff
3464
              && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3465
            {
3466
              length += 2;
3467
            }
3468
          else if ((TARGET_H8300H || TARGET_H8300S)
3469
                   && (b0 != 0)
3470
                   && (b1 != 0))
3471
            {
3472
              length += 4;
3473
            }
3474
          else
3475
            {
3476
              if (b0 != 0)
3477
                length += 2;
3478
 
3479
              if (b1 != 0)
3480
                length += 2;
3481
            }
3482
 
3483
          if (w1 == 0xffff
3484
              && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3485
            {
3486
              length += 2;
3487
            }
3488
          else if ((TARGET_H8300H || TARGET_H8300S)
3489
                   && code == IOR
3490
                   && w1 == 0xffff
3491
                   && (w0 & 0x8000) != 0)
3492
            {
3493
              length += 2;
3494
            }
3495
          else if ((TARGET_H8300H || TARGET_H8300S)
3496
                   && code == AND
3497
                   && w1 == 0xff00)
3498
            {
3499
              length += 2;
3500
            }
3501
          else if (TARGET_H8300H || TARGET_H8300S)
3502
            {
3503
              if (w1 != 0)
3504
                length += 4;
3505
            }
3506
          else
3507
            {
3508
              if (b2 != 0)
3509
                length += 2;
3510
 
3511
              if (b3 != 0)
3512
                length += 2;
3513
            }
3514
        }
3515
      break;
3516
    default:
3517
      gcc_unreachable ();
3518
    }
3519
  return length;
3520
}
3521
 
3522
/* Compute which flag bits are valid after a logical insn.  */
3523
 
3524
enum attr_cc
3525
compute_logical_op_cc (enum machine_mode mode, rtx *operands)
3526
{
3527
  /* Figure out the logical op that we need to perform.  */
3528
  enum rtx_code code = GET_CODE (operands[3]);
3529
  /* Pretend that every byte is affected if both operands are registers.  */
3530
  const unsigned HOST_WIDE_INT intval =
3531
    (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
3532
                              /* Always use the full instruction if the
3533
                                 first operand is in memory.  It is better
3534
                                 to use define_splits to generate the shorter
3535
                                 sequence where valid.  */
3536
                              && register_operand (operands[1], VOIDmode)
3537
                              ? INTVAL (operands[2]) : 0x55555555);
3538
  /* The determinant of the algorithm.  If we perform an AND, 0
3539
     affects a bit.  Otherwise, 1 affects a bit.  */
3540
  const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
3541
  /* Break up DET into pieces.  */
3542
  const unsigned HOST_WIDE_INT b0 = (det >>  0) & 0xff;
3543
  const unsigned HOST_WIDE_INT b1 = (det >>  8) & 0xff;
3544
  const unsigned HOST_WIDE_INT w0 = (det >>  0) & 0xffff;
3545
  const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3546
  int lower_half_easy_p = 0;
3547
  int upper_half_easy_p = 0;
3548
  /* Condition code.  */
3549
  enum attr_cc cc = CC_CLOBBER;
3550
 
3551
  switch (mode)
3552
    {
3553
    case HImode:
3554
      /* First, see if we can finish with one insn.  */
3555
      if ((TARGET_H8300H || TARGET_H8300S)
3556
          && b0 != 0
3557
          && b1 != 0)
3558
        {
3559
          cc = CC_SET_ZNV;
3560
        }
3561
      break;
3562
    case SImode:
3563
      if (TARGET_H8300H || TARGET_H8300S)
3564
        {
3565
          /* Determine if the lower half can be taken care of in no more
3566
             than two bytes.  */
3567
          lower_half_easy_p = (b0 == 0
3568
                               || b1 == 0
3569
                               || (code != IOR && w0 == 0xffff));
3570
 
3571
          /* Determine if the upper half can be taken care of in no more
3572
             than two bytes.  */
3573
          upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3574
                               || (code == AND && w1 == 0xff00));
3575
        }
3576
 
3577
      /* Check if doing everything with one insn is no worse than
3578
         using multiple insns.  */
3579
      if ((TARGET_H8300H || TARGET_H8300S)
3580
          && w0 != 0 && w1 != 0
3581
          && !(lower_half_easy_p && upper_half_easy_p)
3582
          && !(code == IOR && w1 == 0xffff
3583
               && (w0 & 0x8000) != 0 && lower_half_easy_p))
3584
        {
3585
          cc = CC_SET_ZNV;
3586
        }
3587
      else
3588
        {
3589
          if ((TARGET_H8300H || TARGET_H8300S)
3590
              && code == IOR
3591
              && w1 == 0xffff
3592
              && (w0 & 0x8000) != 0)
3593
            {
3594
              cc = CC_SET_ZNV;
3595
            }
3596
        }
3597
      break;
3598
    default:
3599
      gcc_unreachable ();
3600
    }
3601
  return cc;
3602
}
3603
 
3604
/* Expand a conditional branch.  */
3605
 
3606
void
3607
h8300_expand_branch (rtx operands[])
3608
{
3609
  enum rtx_code code = GET_CODE (operands[0]);
3610
  rtx op0 = operands[1];
3611
  rtx op1 = operands[2];
3612
  rtx label = operands[3];
3613
  rtx tmp;
3614
 
3615
  tmp = gen_rtx_COMPARE (VOIDmode, op0, op1);
3616
  emit_insn (gen_rtx_SET (VOIDmode, cc0_rtx, tmp));
3617
 
3618
  tmp = gen_rtx_fmt_ee (code, VOIDmode, cc0_rtx, const0_rtx);
3619
  tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
3620
                              gen_rtx_LABEL_REF (VOIDmode, label),
3621
                              pc_rtx);
3622
  emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
3623
}
3624
 
3625
 
3626
/* Expand a conditional store.  */
3627
 
3628
void
3629
h8300_expand_store (rtx operands[])
3630
{
3631
  rtx dest = operands[0];
3632
  enum rtx_code code = GET_CODE (operands[1]);
3633
  rtx op0 = operands[2];
3634
  rtx op1 = operands[3];
3635
  rtx tmp;
3636
 
3637
  tmp = gen_rtx_COMPARE (VOIDmode, op0, op1);
3638
  emit_insn (gen_rtx_SET (VOIDmode, cc0_rtx, tmp));
3639
 
3640
  tmp = gen_rtx_fmt_ee (code, GET_MODE (dest), cc0_rtx, const0_rtx);
3641
  emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
3642
}
3643
 
3644
/* Shifts.
3645
 
3646
   We devote a fair bit of code to getting efficient shifts since we
3647
   can only shift one bit at a time on the H8/300 and H8/300H and only
3648
   one or two bits at a time on the H8S.
3649
 
3650
   All shift code falls into one of the following ways of
3651
   implementation:
3652
 
3653
   o SHIFT_INLINE: Emit straight line code for the shift; this is used
3654
     when a straight line shift is about the same size or smaller than
3655
     a loop.
3656
 
3657
   o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
3658
     off the bits we don't need.  This is used when only a few of the
3659
     bits in the original value will survive in the shifted value.
3660
 
3661
   o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
3662
     simulate a shift by 8, 16, or 24 bits.  Once moved, a few inline
3663
     shifts can be added if the shift count is slightly more than 8 or
3664
     16.  This case also includes other oddballs that are not worth
3665
     explaining here.
3666
 
3667
   o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
3668
 
3669
   For each shift count, we try to use code that has no trade-off
3670
   between code size and speed whenever possible.
3671
 
3672
   If the trade-off is unavoidable, we try to be reasonable.
3673
   Specifically, the fastest version is one instruction longer than
3674
   the shortest version, we take the fastest version.  We also provide
3675
   the use a way to switch back to the shortest version with -Os.
3676
 
3677
   For the details of the shift algorithms for various shift counts,
3678
   refer to shift_alg_[qhs]i.  */
3679
 
3680
/* Classify a shift with the given mode and code.  OP is the shift amount.  */
3681
 
3682
enum h8sx_shift_type
3683
h8sx_classify_shift (enum machine_mode mode, enum rtx_code code, rtx op)
3684
{
3685
  if (!TARGET_H8300SX)
3686
    return H8SX_SHIFT_NONE;
3687
 
3688
  switch (code)
3689
    {
3690
    case ASHIFT:
3691
    case LSHIFTRT:
3692
      /* Check for variable shifts (shll Rs,Rd and shlr Rs,Rd).  */
3693
      if (GET_CODE (op) != CONST_INT)
3694
        return H8SX_SHIFT_BINARY;
3695
 
3696
      /* Reject out-of-range shift amounts.  */
3697
      if (INTVAL (op) <= 0 || INTVAL (op) >= GET_MODE_BITSIZE (mode))
3698
        return H8SX_SHIFT_NONE;
3699
 
3700
      /* Power-of-2 shifts are effectively unary operations.  */
3701
      if (exact_log2 (INTVAL (op)) >= 0)
3702
        return H8SX_SHIFT_UNARY;
3703
 
3704
      return H8SX_SHIFT_BINARY;
3705
 
3706
    case ASHIFTRT:
3707
      if (op == const1_rtx || op == const2_rtx)
3708
        return H8SX_SHIFT_UNARY;
3709
      return H8SX_SHIFT_NONE;
3710
 
3711
    case ROTATE:
3712
      if (GET_CODE (op) == CONST_INT
3713
          && (INTVAL (op) == 1
3714
              || INTVAL (op) == 2
3715
              || INTVAL (op) == GET_MODE_BITSIZE (mode) - 2
3716
              || INTVAL (op) == GET_MODE_BITSIZE (mode) - 1))
3717
        return H8SX_SHIFT_UNARY;
3718
      return H8SX_SHIFT_NONE;
3719
 
3720
    default:
3721
      return H8SX_SHIFT_NONE;
3722
    }
3723
}
3724
 
3725
/* Return the asm template for a single h8sx shift instruction.
3726
   OPERANDS[0] and OPERANDS[1] are the destination, OPERANDS[2]
3727
   is the source and OPERANDS[3] is the shift.  SUFFIX is the
3728
   size suffix ('b', 'w' or 'l') and OPTYPE is the h8300_print_operand
3729
   prefix for the destination operand.  */
3730
 
3731
const char *
3732
output_h8sx_shift (rtx *operands, int suffix, int optype)
3733
{
3734
  static char buffer[16];
3735
  const char *stem;
3736
 
3737
  switch (GET_CODE (operands[3]))
3738
    {
3739
    case ASHIFT:
3740
      stem = "shll";
3741
      break;
3742
 
3743
    case ASHIFTRT:
3744
      stem = "shar";
3745
      break;
3746
 
3747
    case LSHIFTRT:
3748
      stem = "shlr";
3749
      break;
3750
 
3751
    case ROTATE:
3752
      stem = "rotl";
3753
      if (INTVAL (operands[2]) > 2)
3754
        {
3755
          /* This is really a right rotate.  */
3756
          operands[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands[0]))
3757
                                 - INTVAL (operands[2]));
3758
          stem = "rotr";
3759
        }
3760
      break;
3761
 
3762
    default:
3763
      gcc_unreachable ();
3764
    }
3765
  if (operands[2] == const1_rtx)
3766
    sprintf (buffer, "%s.%c\t%%%c0", stem, suffix, optype);
3767
  else
3768
    sprintf (buffer, "%s.%c\t%%X2,%%%c0", stem, suffix, optype);
3769
  return buffer;
3770
}
3771
 
3772
/* Emit code to do shifts.  */
3773
 
3774
bool
3775
expand_a_shift (enum machine_mode mode, enum rtx_code code, rtx operands[])
3776
{
3777
  switch (h8sx_classify_shift (mode, code, operands[2]))
3778
    {
3779
    case H8SX_SHIFT_BINARY:
3780
      operands[1] = force_reg (mode, operands[1]);
3781
      return false;
3782
 
3783
    case H8SX_SHIFT_UNARY:
3784
      return false;
3785
 
3786
    case H8SX_SHIFT_NONE:
3787
      break;
3788
    }
3789
 
3790
  emit_move_insn (copy_rtx (operands[0]), operands[1]);
3791
 
3792
  /* Need a loop to get all the bits we want  - we generate the
3793
     code at emit time, but need to allocate a scratch reg now.  */
3794
 
3795
  emit_insn (gen_rtx_PARALLEL
3796
             (VOIDmode,
3797
              gen_rtvec (2,
3798
                         gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
3799
                                      gen_rtx_fmt_ee (code, mode,
3800
                                                      copy_rtx (operands[0]), operands[2])),
3801
                         gen_rtx_CLOBBER (VOIDmode,
3802
                                          gen_rtx_SCRATCH (QImode)))));
3803
  return true;
3804
}
3805
 
3806
/* Symbols of the various modes which can be used as indices.  */
3807
 
3808
enum shift_mode
3809
{
3810
  QIshift, HIshift, SIshift
3811
};
3812
 
3813
/* For single bit shift insns, record assembler and what bits of the
3814
   condition code are valid afterwards (represented as various CC_FOO
3815
   bits, 0 means CC isn't left in a usable state).  */
3816
 
3817
struct shift_insn
3818
{
3819
  const char *const assembler;
3820
  const enum attr_cc cc_valid;
3821
};
3822
 
3823
/* Assembler instruction shift table.
3824
 
3825
   These tables are used to look up the basic shifts.
3826
   They are indexed by cpu, shift_type, and mode.  */
3827
 
3828
static const struct shift_insn shift_one[2][3][3] =
3829
{
3830
/* H8/300 */
3831
  {
3832
/* SHIFT_ASHIFT */
3833
    {
3834
      { "shll\t%X0", CC_SET_ZNV },
3835
      { "add.w\t%T0,%T0", CC_SET_ZN },
3836
      { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER }
3837
    },
3838
/* SHIFT_LSHIFTRT */
3839
    {
3840
      { "shlr\t%X0", CC_SET_ZNV },
3841
      { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER },
3842
      { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
3843
    },
3844
/* SHIFT_ASHIFTRT */
3845
    {
3846
      { "shar\t%X0", CC_SET_ZNV },
3847
      { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER },
3848
      { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
3849
    }
3850
  },
3851
/* H8/300H */
3852
  {
3853
/* SHIFT_ASHIFT */
3854
    {
3855
      { "shll.b\t%X0", CC_SET_ZNV },
3856
      { "shll.w\t%T0", CC_SET_ZNV },
3857
      { "shll.l\t%S0", CC_SET_ZNV }
3858
    },
3859
/* SHIFT_LSHIFTRT */
3860
    {
3861
      { "shlr.b\t%X0", CC_SET_ZNV },
3862
      { "shlr.w\t%T0", CC_SET_ZNV },
3863
      { "shlr.l\t%S0", CC_SET_ZNV }
3864
    },
3865
/* SHIFT_ASHIFTRT */
3866
    {
3867
      { "shar.b\t%X0", CC_SET_ZNV },
3868
      { "shar.w\t%T0", CC_SET_ZNV },
3869
      { "shar.l\t%S0", CC_SET_ZNV }
3870
    }
3871
  }
3872
};
3873
 
3874
static const struct shift_insn shift_two[3][3] =
3875
{
3876
/* SHIFT_ASHIFT */
3877
    {
3878
      { "shll.b\t#2,%X0", CC_SET_ZNV },
3879
      { "shll.w\t#2,%T0", CC_SET_ZNV },
3880
      { "shll.l\t#2,%S0", CC_SET_ZNV }
3881
    },
3882
/* SHIFT_LSHIFTRT */
3883
    {
3884
      { "shlr.b\t#2,%X0", CC_SET_ZNV },
3885
      { "shlr.w\t#2,%T0", CC_SET_ZNV },
3886
      { "shlr.l\t#2,%S0", CC_SET_ZNV }
3887
    },
3888
/* SHIFT_ASHIFTRT */
3889
    {
3890
      { "shar.b\t#2,%X0", CC_SET_ZNV },
3891
      { "shar.w\t#2,%T0", CC_SET_ZNV },
3892
      { "shar.l\t#2,%S0", CC_SET_ZNV }
3893
    }
3894
};
3895
 
3896
/* Rotates are organized by which shift they'll be used in implementing.
3897
   There's no need to record whether the cc is valid afterwards because
3898
   it is the AND insn that will decide this.  */
3899
 
3900
static const char *const rotate_one[2][3][3] =
3901
{
3902
/* H8/300 */
3903
  {
3904
/* SHIFT_ASHIFT */
3905
    {
3906
      "rotr\t%X0",
3907
      "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
3908
 
3909
    },
3910
/* SHIFT_LSHIFTRT */
3911
    {
3912
      "rotl\t%X0",
3913
      "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3914
 
3915
    },
3916
/* SHIFT_ASHIFTRT */
3917
    {
3918
      "rotl\t%X0",
3919
      "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3920
 
3921
    }
3922
  },
3923
/* H8/300H */
3924
  {
3925
/* SHIFT_ASHIFT */
3926
    {
3927
      "rotr.b\t%X0",
3928
      "rotr.w\t%T0",
3929
      "rotr.l\t%S0"
3930
    },
3931
/* SHIFT_LSHIFTRT */
3932
    {
3933
      "rotl.b\t%X0",
3934
      "rotl.w\t%T0",
3935
      "rotl.l\t%S0"
3936
    },
3937
/* SHIFT_ASHIFTRT */
3938
    {
3939
      "rotl.b\t%X0",
3940
      "rotl.w\t%T0",
3941
      "rotl.l\t%S0"
3942
    }
3943
  }
3944
};
3945
 
3946
static const char *const rotate_two[3][3] =
3947
{
3948
/* SHIFT_ASHIFT */
3949
    {
3950
      "rotr.b\t#2,%X0",
3951
      "rotr.w\t#2,%T0",
3952
      "rotr.l\t#2,%S0"
3953
    },
3954
/* SHIFT_LSHIFTRT */
3955
    {
3956
      "rotl.b\t#2,%X0",
3957
      "rotl.w\t#2,%T0",
3958
      "rotl.l\t#2,%S0"
3959
    },
3960
/* SHIFT_ASHIFTRT */
3961
    {
3962
      "rotl.b\t#2,%X0",
3963
      "rotl.w\t#2,%T0",
3964
      "rotl.l\t#2,%S0"
3965
    }
3966
};
3967
 
3968
struct shift_info {
3969
  /* Shift algorithm.  */
3970
  enum shift_alg alg;
3971
 
3972
  /* The number of bits to be shifted by shift1 and shift2.  Valid
3973
     when ALG is SHIFT_SPECIAL.  */
3974
  unsigned int remainder;
3975
 
3976
  /* Special insn for a shift.  Valid when ALG is SHIFT_SPECIAL.  */
3977
  const char *special;
3978
 
3979
  /* Insn for a one-bit shift.  Valid when ALG is either SHIFT_INLINE
3980
     or SHIFT_SPECIAL, and REMAINDER is nonzero.  */
3981
  const char *shift1;
3982
 
3983
  /* Insn for a two-bit shift.  Valid when ALG is either SHIFT_INLINE
3984
     or SHIFT_SPECIAL, and REMAINDER is nonzero.  */
3985
  const char *shift2;
3986
 
3987
  /* CC status for SHIFT_INLINE.  */
3988
  enum attr_cc cc_inline;
3989
 
3990
  /* CC status  for SHIFT_SPECIAL.  */
3991
  enum attr_cc cc_special;
3992
};
3993
 
3994
static void get_shift_alg (enum shift_type,
3995
                           enum shift_mode, unsigned int,
3996
                           struct shift_info *);
3997
 
3998
/* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
3999
   best algorithm for doing the shift.  The assembler code is stored
4000
   in the pointers in INFO.  We achieve the maximum efficiency in most
4001
   cases when !TARGET_H8300.  In case of TARGET_H8300, shifts in
4002
   SImode in particular have a lot of room to optimize.
4003
 
4004
   We first determine the strategy of the shift algorithm by a table
4005
   lookup.  If that tells us to use a hand crafted assembly code, we
4006
   go into the big switch statement to find what that is.  Otherwise,
4007
   we resort to a generic way, such as inlining.  In either case, the
4008
   result is returned through INFO.  */
4009
 
4010
static void
4011
get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode,
4012
               unsigned int count, struct shift_info *info)
4013
{
4014
  enum h8_cpu cpu;
4015
 
4016
  /* Find the target CPU.  */
4017
  if (TARGET_H8300)
4018
    cpu = H8_300;
4019
  else if (TARGET_H8300H)
4020
    cpu = H8_300H;
4021
  else
4022
    cpu = H8_S;
4023
 
4024
  /* Find the shift algorithm.  */
4025
  info->alg = SHIFT_LOOP;
4026
  switch (shift_mode)
4027
    {
4028
    case QIshift:
4029
      if (count < GET_MODE_BITSIZE (QImode))
4030
        info->alg = shift_alg_qi[cpu][shift_type][count];
4031
      break;
4032
 
4033
    case HIshift:
4034
      if (count < GET_MODE_BITSIZE (HImode))
4035
        info->alg = shift_alg_hi[cpu][shift_type][count];
4036
      break;
4037
 
4038
    case SIshift:
4039
      if (count < GET_MODE_BITSIZE (SImode))
4040
        info->alg = shift_alg_si[cpu][shift_type][count];
4041
      break;
4042
 
4043
    default:
4044
      gcc_unreachable ();
4045
    }
4046
 
4047
  /* Fill in INFO.  Return unless we have SHIFT_SPECIAL.  */
4048
  switch (info->alg)
4049
    {
4050
    case SHIFT_INLINE:
4051
      info->remainder = count;
4052
      /* Fall through.  */
4053
 
4054
    case SHIFT_LOOP:
4055
      /* It is up to the caller to know that looping clobbers cc.  */
4056
      info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
4057
      info->shift2 = shift_two[shift_type][shift_mode].assembler;
4058
      info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
4059
      goto end;
4060
 
4061
    case SHIFT_ROT_AND:
4062
      info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
4063
      info->shift2 = rotate_two[shift_type][shift_mode];
4064
      info->cc_inline = CC_CLOBBER;
4065
      goto end;
4066
 
4067
    case SHIFT_SPECIAL:
4068
      /* REMAINDER is 0 for most cases, so initialize it to 0.  */
4069
      info->remainder = 0;
4070
      info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
4071
      info->shift2 = shift_two[shift_type][shift_mode].assembler;
4072
      info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
4073
      info->cc_special = CC_CLOBBER;
4074
      break;
4075
    }
4076
 
4077
  /* Here we only deal with SHIFT_SPECIAL.  */
4078
  switch (shift_mode)
4079
    {
4080
    case QIshift:
4081
      /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
4082
         through the entire value.  */
4083
      gcc_assert (shift_type == SHIFT_ASHIFTRT && count == 7);
4084
      info->special = "shll\t%X0\n\tsubx\t%X0,%X0";
4085
      goto end;
4086
 
4087
    case HIshift:
4088
      if (count == 7)
4089
        {
4090
          switch (shift_type)
4091
            {
4092
            case SHIFT_ASHIFT:
4093
              if (TARGET_H8300)
4094
                info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
4095
              else
4096
                info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
4097
              goto end;
4098
            case SHIFT_LSHIFTRT:
4099
              if (TARGET_H8300)
4100
                info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
4101
              else
4102
                info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
4103
              goto end;
4104
            case SHIFT_ASHIFTRT:
4105
              info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
4106
              goto end;
4107
            }
4108
        }
4109
      else if ((8 <= count && count <= 13)
4110
               || (TARGET_H8300S && count == 14))
4111
        {
4112
          info->remainder = count - 8;
4113
 
4114
          switch (shift_type)
4115
            {
4116
            case SHIFT_ASHIFT:
4117
              info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
4118
              goto end;
4119
            case SHIFT_LSHIFTRT:
4120
              if (TARGET_H8300)
4121
                {
4122
                  info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
4123
                  info->shift1  = "shlr.b\t%s0";
4124
                  info->cc_inline = CC_SET_ZNV;
4125
                }
4126
              else
4127
                {
4128
                  info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0";
4129
                  info->cc_special = CC_SET_ZNV;
4130
                }
4131
              goto end;
4132
            case SHIFT_ASHIFTRT:
4133
              if (TARGET_H8300)
4134
                {
4135
                  info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
4136
                  info->shift1  = "shar.b\t%s0";
4137
                }
4138
              else
4139
                {
4140
                  info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0";
4141
                  info->cc_special = CC_SET_ZNV;
4142
                }
4143
              goto end;
4144
            }
4145
        }
4146
      else if (count == 14)
4147
        {
4148
          switch (shift_type)
4149
            {
4150
            case SHIFT_ASHIFT:
4151
              if (TARGET_H8300)
4152
                info->special = "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
4153
              goto end;
4154
            case SHIFT_LSHIFTRT:
4155
              if (TARGET_H8300)
4156
                info->special = "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
4157
              goto end;
4158
            case SHIFT_ASHIFTRT:
4159
              if (TARGET_H8300)
4160
                info->special = "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
4161
              else if (TARGET_H8300H)
4162
                {
4163
                  info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
4164
                  info->cc_special = CC_SET_ZNV;
4165
                }
4166
              else /* TARGET_H8300S */
4167
                gcc_unreachable ();
4168
              goto end;
4169
            }
4170
        }
4171
      else if (count == 15)
4172
        {
4173
          switch (shift_type)
4174
            {
4175
            case SHIFT_ASHIFT:
4176
              info->special = "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
4177
              goto end;
4178
            case SHIFT_LSHIFTRT:
4179
              info->special = "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
4180
              goto end;
4181
            case SHIFT_ASHIFTRT:
4182
              info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
4183
              goto end;
4184
            }
4185
        }
4186
      gcc_unreachable ();
4187
 
4188
    case SIshift:
4189
      if (TARGET_H8300 && 8 <= count && count <= 9)
4190
        {
4191
          info->remainder = count - 8;
4192
 
4193
          switch (shift_type)
4194
            {
4195
            case SHIFT_ASHIFT:
4196
              info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
4197
              goto end;
4198
            case SHIFT_LSHIFTRT:
4199
              info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
4200
              info->shift1  = "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
4201
              goto end;
4202
            case SHIFT_ASHIFTRT:
4203
              info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
4204
              goto end;
4205
            }
4206
        }
4207
      else if (count == 8 && !TARGET_H8300)
4208
        {
4209
          switch (shift_type)
4210
            {
4211
            case SHIFT_ASHIFT:
4212
              info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
4213
              goto end;
4214
            case SHIFT_LSHIFTRT:
4215
              info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
4216
              goto end;
4217
            case SHIFT_ASHIFTRT:
4218
              info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
4219
              goto end;
4220
            }
4221
        }
4222
      else if (count == 15 && TARGET_H8300)
4223
        {
4224
          switch (shift_type)
4225
            {
4226
            case SHIFT_ASHIFT:
4227
              gcc_unreachable ();
4228
            case SHIFT_LSHIFTRT:
4229
              info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
4230
              goto end;
4231
            case SHIFT_ASHIFTRT:
4232
              info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
4233
              goto end;
4234
            }
4235
        }
4236
      else if (count == 15 && !TARGET_H8300)
4237
        {
4238
          switch (shift_type)
4239
            {
4240
            case SHIFT_ASHIFT:
4241
              info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
4242
              info->cc_special = CC_SET_ZNV;
4243
              goto end;
4244
            case SHIFT_LSHIFTRT:
4245
              info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
4246
              info->cc_special = CC_SET_ZNV;
4247
              goto end;
4248
            case SHIFT_ASHIFTRT:
4249
              gcc_unreachable ();
4250
            }
4251
        }
4252
      else if ((TARGET_H8300 && 16 <= count && count <= 20)
4253
               || (TARGET_H8300H && 16 <= count && count <= 19)
4254
               || (TARGET_H8300S && 16 <= count && count <= 21))
4255
        {
4256
          info->remainder = count - 16;
4257
 
4258
          switch (shift_type)
4259
            {
4260
            case SHIFT_ASHIFT:
4261
              info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4262
              if (TARGET_H8300)
4263
                info->shift1 = "add.w\t%e0,%e0";
4264
              goto end;
4265
            case SHIFT_LSHIFTRT:
4266
              if (TARGET_H8300)
4267
                {
4268
                  info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
4269
                  info->shift1  = "shlr\t%x0\n\trotxr\t%w0";
4270
                }
4271
              else
4272
                {
4273
                  info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0";
4274
                  info->cc_special = CC_SET_ZNV;
4275
                }
4276
              goto end;
4277
            case SHIFT_ASHIFTRT:
4278
              if (TARGET_H8300)
4279
                {
4280
                  info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
4281
                  info->shift1  = "shar\t%x0\n\trotxr\t%w0";
4282
                }
4283
              else
4284
                {
4285
                  info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0";
4286
                  info->cc_special = CC_SET_ZNV;
4287
                }
4288
              goto end;
4289
            }
4290
        }
4291
      else if (TARGET_H8300 && 24 <= count && count <= 28)
4292
        {
4293
          info->remainder = count - 24;
4294
 
4295
          switch (shift_type)
4296
            {
4297
            case SHIFT_ASHIFT:
4298
              info->special = "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
4299
              info->shift1  = "shll.b\t%z0";
4300
              info->cc_inline = CC_SET_ZNV;
4301
              goto end;
4302
            case SHIFT_LSHIFTRT:
4303
              info->special = "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
4304
              info->shift1  = "shlr.b\t%w0";
4305
              info->cc_inline = CC_SET_ZNV;
4306
              goto end;
4307
            case SHIFT_ASHIFTRT:
4308
              info->special = "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0";
4309
              info->shift1  = "shar.b\t%w0";
4310
              info->cc_inline = CC_SET_ZNV;
4311
              goto end;
4312
            }
4313
        }
4314
      else if ((TARGET_H8300H && count == 24)
4315
               || (TARGET_H8300S && 24 <= count && count <= 25))
4316
        {
4317
          info->remainder = count - 24;
4318
 
4319
          switch (shift_type)
4320
            {
4321
            case SHIFT_ASHIFT:
4322
              info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4323
              goto end;
4324
            case SHIFT_LSHIFTRT:
4325
              info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
4326
              info->cc_special = CC_SET_ZNV;
4327
              goto end;
4328
            case SHIFT_ASHIFTRT:
4329
              info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
4330
              info->cc_special = CC_SET_ZNV;
4331
              goto end;
4332
            }
4333
        }
4334
      else if (!TARGET_H8300 && count == 28)
4335
        {
4336
          switch (shift_type)
4337
            {
4338
            case SHIFT_ASHIFT:
4339
              if (TARGET_H8300H)
4340
                info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4341
              else
4342
                info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4343
              goto end;
4344
            case SHIFT_LSHIFTRT:
4345
              if (TARGET_H8300H)
4346
                {
4347
                  info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4348
                  info->cc_special = CC_SET_ZNV;
4349
                }
4350
              else
4351
                info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4352
              goto end;
4353
            case SHIFT_ASHIFTRT:
4354
              gcc_unreachable ();
4355
            }
4356
        }
4357
      else if (!TARGET_H8300 && count == 29)
4358
        {
4359
          switch (shift_type)
4360
            {
4361
            case SHIFT_ASHIFT:
4362
              if (TARGET_H8300H)
4363
                info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4364
              else
4365
                info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4366
              goto end;
4367
            case SHIFT_LSHIFTRT:
4368
              if (TARGET_H8300H)
4369
                {
4370
                  info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4371
                  info->cc_special = CC_SET_ZNV;
4372
                }
4373
              else
4374
                {
4375
                  info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4376
                  info->cc_special = CC_SET_ZNV;
4377
                }
4378
              goto end;
4379
            case SHIFT_ASHIFTRT:
4380
              gcc_unreachable ();
4381
            }
4382
        }
4383
      else if (!TARGET_H8300 && count == 30)
4384
        {
4385
          switch (shift_type)
4386
            {
4387
            case SHIFT_ASHIFT:
4388
              if (TARGET_H8300H)
4389
                info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4390
              else
4391
                info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4392
              goto end;
4393
            case SHIFT_LSHIFTRT:
4394
              if (TARGET_H8300H)
4395
                info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4396
              else
4397
                info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4398
              goto end;
4399
            case SHIFT_ASHIFTRT:
4400
              gcc_unreachable ();
4401
            }
4402
        }
4403
      else if (count == 31)
4404
        {
4405
          if (TARGET_H8300)
4406
            {
4407
              switch (shift_type)
4408
                {
4409
                case SHIFT_ASHIFT:
4410
                  info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
4411
                  goto end;
4412
                case SHIFT_LSHIFTRT:
4413
                  info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
4414
                  goto end;
4415
                case SHIFT_ASHIFTRT:
4416
                  info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
4417
                  goto end;
4418
                }
4419
            }
4420
          else
4421
            {
4422
              switch (shift_type)
4423
                {
4424
                case SHIFT_ASHIFT:
4425
                  info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
4426
                  info->cc_special = CC_SET_ZNV;
4427
                  goto end;
4428
                case SHIFT_LSHIFTRT:
4429
                  info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
4430
                  info->cc_special = CC_SET_ZNV;
4431
                  goto end;
4432
                case SHIFT_ASHIFTRT:
4433
                  info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
4434
                  info->cc_special = CC_SET_ZNV;
4435
                  goto end;
4436
                }
4437
            }
4438
        }
4439
      gcc_unreachable ();
4440
 
4441
    default:
4442
      gcc_unreachable ();
4443
    }
4444
 
4445
 end:
4446
  if (!TARGET_H8300S)
4447
    info->shift2 = NULL;
4448
}
4449
 
4450
/* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
4451
   needed for some shift with COUNT and MODE.  Return 0 otherwise.  */
4452
 
4453
int
4454
h8300_shift_needs_scratch_p (int count, enum machine_mode mode)
4455
{
4456
  enum h8_cpu cpu;
4457
  int a, lr, ar;
4458
 
4459
  if (GET_MODE_BITSIZE (mode) <= count)
4460
    return 1;
4461
 
4462
  /* Find out the target CPU.  */
4463
  if (TARGET_H8300)
4464
    cpu = H8_300;
4465
  else if (TARGET_H8300H)
4466
    cpu = H8_300H;
4467
  else
4468
    cpu = H8_S;
4469
 
4470
  /* Find the shift algorithm.  */
4471
  switch (mode)
4472
    {
4473
    case QImode:
4474
      a  = shift_alg_qi[cpu][SHIFT_ASHIFT][count];
4475
      lr = shift_alg_qi[cpu][SHIFT_LSHIFTRT][count];
4476
      ar = shift_alg_qi[cpu][SHIFT_ASHIFTRT][count];
4477
      break;
4478
 
4479
    case HImode:
4480
      a  = shift_alg_hi[cpu][SHIFT_ASHIFT][count];
4481
      lr = shift_alg_hi[cpu][SHIFT_LSHIFTRT][count];
4482
      ar = shift_alg_hi[cpu][SHIFT_ASHIFTRT][count];
4483
      break;
4484
 
4485
    case SImode:
4486
      a  = shift_alg_si[cpu][SHIFT_ASHIFT][count];
4487
      lr = shift_alg_si[cpu][SHIFT_LSHIFTRT][count];
4488
      ar = shift_alg_si[cpu][SHIFT_ASHIFTRT][count];
4489
      break;
4490
 
4491
    default:
4492
      gcc_unreachable ();
4493
    }
4494
 
4495
  /* On H8/300H, count == 8 uses a scratch register.  */
4496
  return (a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP
4497
          || (TARGET_H8300H && mode == SImode && count == 8));
4498
}
4499
 
4500
/* Output the assembler code for doing shifts.  */
4501
 
4502
const char *
4503
output_a_shift (rtx *operands)
4504
{
4505
  static int loopend_lab;
4506
  rtx shift = operands[3];
4507
  enum machine_mode mode = GET_MODE (shift);
4508
  enum rtx_code code = GET_CODE (shift);
4509
  enum shift_type shift_type;
4510
  enum shift_mode shift_mode;
4511
  struct shift_info info;
4512
  int n;
4513
 
4514
  loopend_lab++;
4515
 
4516
  switch (mode)
4517
    {
4518
    case QImode:
4519
      shift_mode = QIshift;
4520
      break;
4521
    case HImode:
4522
      shift_mode = HIshift;
4523
      break;
4524
    case SImode:
4525
      shift_mode = SIshift;
4526
      break;
4527
    default:
4528
      gcc_unreachable ();
4529
    }
4530
 
4531
  switch (code)
4532
    {
4533
    case ASHIFTRT:
4534
      shift_type = SHIFT_ASHIFTRT;
4535
      break;
4536
    case LSHIFTRT:
4537
      shift_type = SHIFT_LSHIFTRT;
4538
      break;
4539
    case ASHIFT:
4540
      shift_type = SHIFT_ASHIFT;
4541
      break;
4542
    default:
4543
      gcc_unreachable ();
4544
    }
4545
 
4546
  /* This case must be taken care of by one of the two splitters
4547
     that convert a variable shift into a loop.  */
4548
  gcc_assert (GET_CODE (operands[2]) == CONST_INT);
4549
 
4550
  n = INTVAL (operands[2]);
4551
 
4552
  /* If the count is negative, make it 0.  */
4553
  if (n < 0)
4554
    n = 0;
4555
  /* If the count is too big, truncate it.
4556
     ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4557
     do the intuitive thing.  */
4558
  else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4559
    n = GET_MODE_BITSIZE (mode);
4560
 
4561
  get_shift_alg (shift_type, shift_mode, n, &info);
4562
 
4563
  switch (info.alg)
4564
    {
4565
    case SHIFT_SPECIAL:
4566
      output_asm_insn (info.special, operands);
4567
      /* Fall through.  */
4568
 
4569
    case SHIFT_INLINE:
4570
      n = info.remainder;
4571
 
4572
      /* Emit two bit shifts first.  */
4573
      if (info.shift2 != NULL)
4574
        {
4575
          for (; n > 1; n -= 2)
4576
            output_asm_insn (info.shift2, operands);
4577
        }
4578
 
4579
      /* Now emit one bit shifts for any residual.  */
4580
      for (; n > 0; n--)
4581
        output_asm_insn (info.shift1, operands);
4582
      return "";
4583
 
4584
    case SHIFT_ROT_AND:
4585
      {
4586
        int m = GET_MODE_BITSIZE (mode) - n;
4587
        const int mask = (shift_type == SHIFT_ASHIFT
4588
                          ? ((1 << m) - 1) << n
4589
                          : (1 << m) - 1);
4590
        char insn_buf[200];
4591
 
4592
        /* Not all possibilities of rotate are supported.  They shouldn't
4593
           be generated, but let's watch for 'em.  */
4594
        gcc_assert (info.shift1);
4595
 
4596
        /* Emit two bit rotates first.  */
4597
        if (info.shift2 != NULL)
4598
          {
4599
            for (; m > 1; m -= 2)
4600
              output_asm_insn (info.shift2, operands);
4601
          }
4602
 
4603
        /* Now single bit rotates for any residual.  */
4604
        for (; m > 0; m--)
4605
          output_asm_insn (info.shift1, operands);
4606
 
4607
        /* Now mask off the high bits.  */
4608
        switch (mode)
4609
          {
4610
          case QImode:
4611
            sprintf (insn_buf, "and\t#%d,%%X0", mask);
4612
            break;
4613
 
4614
          case HImode:
4615
            gcc_assert (TARGET_H8300H || TARGET_H8300S);
4616
            sprintf (insn_buf, "and.w\t#%d,%%T0", mask);
4617
            break;
4618
 
4619
          default:
4620
            gcc_unreachable ();
4621
          }
4622
 
4623
        output_asm_insn (insn_buf, operands);
4624
        return "";
4625
      }
4626
 
4627
    case SHIFT_LOOP:
4628
      /* A loop to shift by a "large" constant value.
4629
         If we have shift-by-2 insns, use them.  */
4630
      if (info.shift2 != NULL)
4631
        {
4632
          fprintf (asm_out_file, "\tmov.b       #%d,%sl\n", n / 2,
4633
                   names_big[REGNO (operands[4])]);
4634
          fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
4635
          output_asm_insn (info.shift2, operands);
4636
          output_asm_insn ("add #0xff,%X4", operands);
4637
          fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
4638
          if (n % 2)
4639
            output_asm_insn (info.shift1, operands);
4640
        }
4641
      else
4642
        {
4643
          fprintf (asm_out_file, "\tmov.b       #%d,%sl\n", n,
4644
                   names_big[REGNO (operands[4])]);
4645
          fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
4646
          output_asm_insn (info.shift1, operands);
4647
          output_asm_insn ("add #0xff,%X4", operands);
4648
          fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
4649
        }
4650
      return "";
4651
 
4652
    default:
4653
      gcc_unreachable ();
4654
    }
4655
}
4656
 
4657
/* Count the number of assembly instructions in a string TEMPL.  */
4658
 
4659
static unsigned int
4660
h8300_asm_insn_count (const char *templ)
4661
{
4662
  unsigned int count = 1;
4663
 
4664
  for (; *templ; templ++)
4665
    if (*templ == '\n')
4666
      count++;
4667
 
4668
  return count;
4669
}
4670
 
4671
/* Compute the length of a shift insn.  */
4672
 
4673
unsigned int
4674
compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
4675
{
4676
  rtx shift = operands[3];
4677
  enum machine_mode mode = GET_MODE (shift);
4678
  enum rtx_code code = GET_CODE (shift);
4679
  enum shift_type shift_type;
4680
  enum shift_mode shift_mode;
4681
  struct shift_info info;
4682
  unsigned int wlength = 0;
4683
 
4684
  switch (mode)
4685
    {
4686
    case QImode:
4687
      shift_mode = QIshift;
4688
      break;
4689
    case HImode:
4690
      shift_mode = HIshift;
4691
      break;
4692
    case SImode:
4693
      shift_mode = SIshift;
4694
      break;
4695
    default:
4696
      gcc_unreachable ();
4697
    }
4698
 
4699
  switch (code)
4700
    {
4701
    case ASHIFTRT:
4702
      shift_type = SHIFT_ASHIFTRT;
4703
      break;
4704
    case LSHIFTRT:
4705
      shift_type = SHIFT_LSHIFTRT;
4706
      break;
4707
    case ASHIFT:
4708
      shift_type = SHIFT_ASHIFT;
4709
      break;
4710
    default:
4711
      gcc_unreachable ();
4712
    }
4713
 
4714
  if (GET_CODE (operands[2]) != CONST_INT)
4715
    {
4716
      /* Get the assembler code to do one shift.  */
4717
      get_shift_alg (shift_type, shift_mode, 1, &info);
4718
 
4719
      return (4 + h8300_asm_insn_count (info.shift1)) * 2;
4720
    }
4721
  else
4722
    {
4723
      int n = INTVAL (operands[2]);
4724
 
4725
      /* If the count is negative, make it 0.  */
4726
      if (n < 0)
4727
        n = 0;
4728
      /* If the count is too big, truncate it.
4729
         ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4730
         do the intuitive thing.  */
4731
      else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4732
        n = GET_MODE_BITSIZE (mode);
4733
 
4734
      get_shift_alg (shift_type, shift_mode, n, &info);
4735
 
4736
      switch (info.alg)
4737
        {
4738
        case SHIFT_SPECIAL:
4739
          wlength += h8300_asm_insn_count (info.special);
4740
 
4741
          /* Every assembly instruction used in SHIFT_SPECIAL case
4742
             takes 2 bytes except xor.l, which takes 4 bytes, so if we
4743
             see xor.l, we just pretend that xor.l counts as two insns
4744
             so that the insn length will be computed correctly.  */
4745
          if (strstr (info.special, "xor.l") != NULL)
4746
            wlength++;
4747
 
4748
          /* Fall through.  */
4749
 
4750
        case SHIFT_INLINE:
4751
          n = info.remainder;
4752
 
4753
          if (info.shift2 != NULL)
4754
            {
4755
              wlength += h8300_asm_insn_count (info.shift2) * (n / 2);
4756
              n = n % 2;
4757
            }
4758
 
4759
          wlength += h8300_asm_insn_count (info.shift1) * n;
4760
 
4761
          return 2 * wlength;
4762
 
4763
        case SHIFT_ROT_AND:
4764
          {
4765
            int m = GET_MODE_BITSIZE (mode) - n;
4766
 
4767
            /* Not all possibilities of rotate are supported.  They shouldn't
4768
               be generated, but let's watch for 'em.  */
4769
            gcc_assert (info.shift1);
4770
 
4771
            if (info.shift2 != NULL)
4772
              {
4773
                wlength += h8300_asm_insn_count (info.shift2) * (m / 2);
4774
                m = m % 2;
4775
              }
4776
 
4777
            wlength += h8300_asm_insn_count (info.shift1) * m;
4778
 
4779
            /* Now mask off the high bits.  */
4780
            switch (mode)
4781
              {
4782
              case QImode:
4783
                wlength += 1;
4784
                break;
4785
              case HImode:
4786
                wlength += 2;
4787
                break;
4788
              case SImode:
4789
                gcc_assert (!TARGET_H8300);
4790
                wlength += 3;
4791
                break;
4792
              default:
4793
                gcc_unreachable ();
4794
              }
4795
            return 2 * wlength;
4796
          }
4797
 
4798
        case SHIFT_LOOP:
4799
          /* A loop to shift by a "large" constant value.
4800
             If we have shift-by-2 insns, use them.  */
4801
          if (info.shift2 != NULL)
4802
            {
4803
              wlength += 3 + h8300_asm_insn_count (info.shift2);
4804
              if (n % 2)
4805
                wlength += h8300_asm_insn_count (info.shift1);
4806
            }
4807
          else
4808
            {
4809
              wlength += 3 + h8300_asm_insn_count (info.shift1);
4810
            }
4811
          return 2 * wlength;
4812
 
4813
        default:
4814
          gcc_unreachable ();
4815
        }
4816
    }
4817
}
4818
 
4819
/* Compute which flag bits are valid after a shift insn.  */
4820
 
4821
enum attr_cc
4822
compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
4823
{
4824
  rtx shift = operands[3];
4825
  enum machine_mode mode = GET_MODE (shift);
4826
  enum rtx_code code = GET_CODE (shift);
4827
  enum shift_type shift_type;
4828
  enum shift_mode shift_mode;
4829
  struct shift_info info;
4830
  int n;
4831
 
4832
  switch (mode)
4833
    {
4834
    case QImode:
4835
      shift_mode = QIshift;
4836
      break;
4837
    case HImode:
4838
      shift_mode = HIshift;
4839
      break;
4840
    case SImode:
4841
      shift_mode = SIshift;
4842
      break;
4843
    default:
4844
      gcc_unreachable ();
4845
    }
4846
 
4847
  switch (code)
4848
    {
4849
    case ASHIFTRT:
4850
      shift_type = SHIFT_ASHIFTRT;
4851
      break;
4852
    case LSHIFTRT:
4853
      shift_type = SHIFT_LSHIFTRT;
4854
      break;
4855
    case ASHIFT:
4856
      shift_type = SHIFT_ASHIFT;
4857
      break;
4858
    default:
4859
      gcc_unreachable ();
4860
    }
4861
 
4862
  /* This case must be taken care of by one of the two splitters
4863
     that convert a variable shift into a loop.  */
4864
  gcc_assert (GET_CODE (operands[2]) == CONST_INT);
4865
 
4866
  n = INTVAL (operands[2]);
4867
 
4868
  /* If the count is negative, make it 0.  */
4869
  if (n < 0)
4870
    n = 0;
4871
  /* If the count is too big, truncate it.
4872
     ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4873
     do the intuitive thing.  */
4874
  else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4875
    n = GET_MODE_BITSIZE (mode);
4876
 
4877
  get_shift_alg (shift_type, shift_mode, n, &info);
4878
 
4879
  switch (info.alg)
4880
    {
4881
    case SHIFT_SPECIAL:
4882
      if (info.remainder == 0)
4883
        return info.cc_special;
4884
 
4885
      /* Fall through.  */
4886
 
4887
    case SHIFT_INLINE:
4888
      return info.cc_inline;
4889
 
4890
    case SHIFT_ROT_AND:
4891
      /* This case always ends with an and instruction.  */
4892
      return CC_SET_ZNV;
4893
 
4894
    case SHIFT_LOOP:
4895
      /* A loop to shift by a "large" constant value.
4896
         If we have shift-by-2 insns, use them.  */
4897
      if (info.shift2 != NULL)
4898
        {
4899
          if (n % 2)
4900
            return info.cc_inline;
4901
        }
4902
      return CC_CLOBBER;
4903
 
4904
    default:
4905
      gcc_unreachable ();
4906
    }
4907
}
4908
 
4909
/* A rotation by a non-constant will cause a loop to be generated, in
4910
   which a rotation by one bit is used.  A rotation by a constant,
4911
   including the one in the loop, will be taken care of by
4912
   output_a_rotate () at the insn emit time.  */
4913
 
4914
int
4915
expand_a_rotate (rtx operands[])
4916
{
4917
  rtx dst = operands[0];
4918
  rtx src = operands[1];
4919
  rtx rotate_amount = operands[2];
4920
  enum machine_mode mode = GET_MODE (dst);
4921
 
4922
  if (h8sx_classify_shift (mode, ROTATE, rotate_amount) == H8SX_SHIFT_UNARY)
4923
    return false;
4924
 
4925
  /* We rotate in place.  */
4926
  emit_move_insn (dst, src);
4927
 
4928
  if (GET_CODE (rotate_amount) != CONST_INT)
4929
    {
4930
      rtx counter = gen_reg_rtx (QImode);
4931
      rtx start_label = gen_label_rtx ();
4932
      rtx end_label = gen_label_rtx ();
4933
 
4934
      /* If the rotate amount is less than or equal to 0,
4935
         we go out of the loop.  */
4936
      emit_cmp_and_jump_insns (rotate_amount, const0_rtx, LE, NULL_RTX,
4937
                               QImode, 0, end_label);
4938
 
4939
      /* Initialize the loop counter.  */
4940
      emit_move_insn (counter, rotate_amount);
4941
 
4942
      emit_label (start_label);
4943
 
4944
      /* Rotate by one bit.  */
4945
      switch (mode)
4946
        {
4947
        case QImode:
4948
          emit_insn (gen_rotlqi3_1 (dst, dst, const1_rtx));
4949
          break;
4950
        case HImode:
4951
          emit_insn (gen_rotlhi3_1 (dst, dst, const1_rtx));
4952
          break;
4953
        case SImode:
4954
          emit_insn (gen_rotlsi3_1 (dst, dst, const1_rtx));
4955
          break;
4956
        default:
4957
          gcc_unreachable ();
4958
        }
4959
 
4960
      /* Decrement the counter by 1.  */
4961
      emit_insn (gen_addqi3 (counter, counter, constm1_rtx));
4962
 
4963
      /* If the loop counter is nonzero, we go back to the beginning
4964
         of the loop.  */
4965
      emit_cmp_and_jump_insns (counter, const0_rtx, NE, NULL_RTX, QImode, 1,
4966
                               start_label);
4967
 
4968
      emit_label (end_label);
4969
    }
4970
  else
4971
    {
4972
      /* Rotate by AMOUNT bits.  */
4973
      switch (mode)
4974
        {
4975
        case QImode:
4976
          emit_insn (gen_rotlqi3_1 (dst, dst, rotate_amount));
4977
          break;
4978
        case HImode:
4979
          emit_insn (gen_rotlhi3_1 (dst, dst, rotate_amount));
4980
          break;
4981
        case SImode:
4982
          emit_insn (gen_rotlsi3_1 (dst, dst, rotate_amount));
4983
          break;
4984
        default:
4985
          gcc_unreachable ();
4986
        }
4987
    }
4988
 
4989
  return 1;
4990
}
4991
 
4992
/* Output a rotate insn.  */
4993
 
4994
const char *
4995
output_a_rotate (enum rtx_code code, rtx *operands)
4996
{
4997
  rtx dst = operands[0];
4998
  rtx rotate_amount = operands[2];
4999
  enum shift_mode rotate_mode;
5000
  enum shift_type rotate_type;
5001
  const char *insn_buf;
5002
  int bits;
5003
  int amount;
5004
  enum machine_mode mode = GET_MODE (dst);
5005
 
5006
  gcc_assert (GET_CODE (rotate_amount) == CONST_INT);
5007
 
5008
  switch (mode)
5009
    {
5010
    case QImode:
5011
      rotate_mode = QIshift;
5012
      break;
5013
    case HImode:
5014
      rotate_mode = HIshift;
5015
      break;
5016
    case SImode:
5017
      rotate_mode = SIshift;
5018
      break;
5019
    default:
5020
      gcc_unreachable ();
5021
    }
5022
 
5023
  switch (code)
5024
    {
5025
    case ROTATERT:
5026
      rotate_type = SHIFT_ASHIFT;
5027
      break;
5028
    case ROTATE:
5029
      rotate_type = SHIFT_LSHIFTRT;
5030
      break;
5031
    default:
5032
      gcc_unreachable ();
5033
    }
5034
 
5035
  amount = INTVAL (rotate_amount);
5036
 
5037
  /* Clean up AMOUNT.  */
5038
  if (amount < 0)
5039
    amount = 0;
5040
  if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
5041
    amount = GET_MODE_BITSIZE (mode);
5042
 
5043
  /* Determine the faster direction.  After this phase, amount will be
5044
     at most a half of GET_MODE_BITSIZE (mode).  */
5045
  if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
5046
    {
5047
      /* Flip the direction.  */
5048
      amount = GET_MODE_BITSIZE (mode) - amount;
5049
      rotate_type =
5050
        (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
5051
    }
5052
 
5053
  /* See if a byte swap (in HImode) or a word swap (in SImode) can
5054
     boost up the rotation.  */
5055
  if ((mode == HImode && TARGET_H8300 && amount >= 5)
5056
      || (mode == HImode && TARGET_H8300H && amount >= 6)
5057
      || (mode == HImode && TARGET_H8300S && amount == 8)
5058
      || (mode == SImode && TARGET_H8300H && amount >= 10)
5059
      || (mode == SImode && TARGET_H8300S && amount >= 13))
5060
    {
5061
      switch (mode)
5062
        {
5063
        case HImode:
5064
          /* This code works on any family.  */
5065
          insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
5066
          output_asm_insn (insn_buf, operands);
5067
          break;
5068
 
5069
        case SImode:
5070
          /* This code works on the H8/300H and H8S.  */
5071
          insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
5072
          output_asm_insn (insn_buf, operands);
5073
          break;
5074
 
5075
        default:
5076
          gcc_unreachable ();
5077
        }
5078
 
5079
      /* Adjust AMOUNT and flip the direction.  */
5080
      amount = GET_MODE_BITSIZE (mode) / 2 - amount;
5081
      rotate_type =
5082
        (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
5083
    }
5084
 
5085
  /* Output rotate insns.  */
5086
  for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2)
5087
    {
5088
      if (bits == 2)
5089
        insn_buf = rotate_two[rotate_type][rotate_mode];
5090
      else
5091
        insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode];
5092
 
5093
      for (; amount >= bits; amount -= bits)
5094
        output_asm_insn (insn_buf, operands);
5095
    }
5096
 
5097
  return "";
5098
}
5099
 
5100
/* Compute the length of a rotate insn.  */
5101
 
5102
unsigned int
5103
compute_a_rotate_length (rtx *operands)
5104
{
5105
  rtx src = operands[1];
5106
  rtx amount_rtx = operands[2];
5107
  enum machine_mode mode = GET_MODE (src);
5108
  int amount;
5109
  unsigned int length = 0;
5110
 
5111
  gcc_assert (GET_CODE (amount_rtx) == CONST_INT);
5112
 
5113
  amount = INTVAL (amount_rtx);
5114
 
5115
  /* Clean up AMOUNT.  */
5116
  if (amount < 0)
5117
    amount = 0;
5118
  if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
5119
    amount = GET_MODE_BITSIZE (mode);
5120
 
5121
  /* Determine the faster direction.  After this phase, amount
5122
     will be at most a half of GET_MODE_BITSIZE (mode).  */
5123
  if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
5124
    /* Flip the direction.  */
5125
    amount = GET_MODE_BITSIZE (mode) - amount;
5126
 
5127
  /* See if a byte swap (in HImode) or a word swap (in SImode) can
5128
     boost up the rotation.  */
5129
  if ((mode == HImode && TARGET_H8300 && amount >= 5)
5130
      || (mode == HImode && TARGET_H8300H && amount >= 6)
5131
      || (mode == HImode && TARGET_H8300S && amount == 8)
5132
      || (mode == SImode && TARGET_H8300H && amount >= 10)
5133
      || (mode == SImode && TARGET_H8300S && amount >= 13))
5134
    {
5135
      /* Adjust AMOUNT and flip the direction.  */
5136
      amount = GET_MODE_BITSIZE (mode) / 2 - amount;
5137
      length += 6;
5138
    }
5139
 
5140
  /* We use 2-bit rotations on the H8S.  */
5141
  if (TARGET_H8300S)
5142
    amount = amount / 2 + amount % 2;
5143
 
5144
  /* The H8/300 uses three insns to rotate one bit, taking 6
5145
     length.  */
5146
  length += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2);
5147
 
5148
  return length;
5149
}
5150
 
5151
/* Fix the operands of a gen_xxx so that it could become a bit
5152
   operating insn.  */
5153
 
5154
int
5155
fix_bit_operand (rtx *operands, enum rtx_code code)
5156
{
5157
  /* The bit_operand predicate accepts any memory during RTL generation, but
5158
     only 'U' memory afterwards, so if this is a MEM operand, we must force
5159
     it to be valid for 'U' by reloading the address.  */
5160
 
5161
  if (code == AND
5162
      ? single_zero_operand (operands[2], QImode)
5163
      : single_one_operand (operands[2], QImode))
5164
    {
5165
      /* OK to have a memory dest.  */
5166
      if (GET_CODE (operands[0]) == MEM
5167
          && !satisfies_constraint_U (operands[0]))
5168
        {
5169
          rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
5170
                                 copy_to_mode_reg (Pmode,
5171
                                                   XEXP (operands[0], 0)));
5172
          MEM_COPY_ATTRIBUTES (mem, operands[0]);
5173
          operands[0] = mem;
5174
        }
5175
 
5176
      if (GET_CODE (operands[1]) == MEM
5177
          && !satisfies_constraint_U (operands[1]))
5178
        {
5179
          rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
5180
                                 copy_to_mode_reg (Pmode,
5181
                                                   XEXP (operands[1], 0)));
5182
          MEM_COPY_ATTRIBUTES (mem, operands[0]);
5183
          operands[1] = mem;
5184
        }
5185
      return 0;
5186
    }
5187
 
5188
  /* Dest and src op must be register.  */
5189
 
5190
  operands[1] = force_reg (QImode, operands[1]);
5191
  {
5192
    rtx res = gen_reg_rtx (QImode);
5193
    switch (code)
5194
      {
5195
      case AND:
5196
        emit_insn (gen_andqi3_1 (res, operands[1], operands[2]));
5197
        break;
5198
      case IOR:
5199
        emit_insn (gen_iorqi3_1 (res, operands[1], operands[2]));
5200
        break;
5201
      case XOR:
5202
        emit_insn (gen_xorqi3_1 (res, operands[1], operands[2]));
5203
        break;
5204
      default:
5205
        gcc_unreachable ();
5206
      }
5207
    emit_insn (gen_movqi (operands[0], res));
5208
  }
5209
  return 1;
5210
}
5211
 
5212
/* Return nonzero if FUNC is an interrupt function as specified
5213
   by the "interrupt" attribute.  */
5214
 
5215
static int
5216
h8300_interrupt_function_p (tree func)
5217
{
5218
  tree a;
5219
 
5220
  if (TREE_CODE (func) != FUNCTION_DECL)
5221
    return 0;
5222
 
5223
  a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
5224
  return a != NULL_TREE;
5225
}
5226
 
5227
/* Return nonzero if FUNC is a saveall function as specified by the
5228
   "saveall" attribute.  */
5229
 
5230
static int
5231
h8300_saveall_function_p (tree func)
5232
{
5233
  tree a;
5234
 
5235
  if (TREE_CODE (func) != FUNCTION_DECL)
5236
    return 0;
5237
 
5238
  a = lookup_attribute ("saveall", DECL_ATTRIBUTES (func));
5239
  return a != NULL_TREE;
5240
}
5241
 
5242
/* Return nonzero if FUNC is an OS_Task function as specified
5243
   by the "OS_Task" attribute.  */
5244
 
5245
static int
5246
h8300_os_task_function_p (tree func)
5247
{
5248
  tree a;
5249
 
5250
  if (TREE_CODE (func) != FUNCTION_DECL)
5251
    return 0;
5252
 
5253
  a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func));
5254
  return a != NULL_TREE;
5255
}
5256
 
5257
/* Return nonzero if FUNC is a monitor function as specified
5258
   by the "monitor" attribute.  */
5259
 
5260
static int
5261
h8300_monitor_function_p (tree func)
5262
{
5263
  tree a;
5264
 
5265
  if (TREE_CODE (func) != FUNCTION_DECL)
5266
    return 0;
5267
 
5268
  a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func));
5269
  return a != NULL_TREE;
5270
}
5271
 
5272
/* Return nonzero if FUNC is a function that should be called
5273
   through the function vector.  */
5274
 
5275
int
5276
h8300_funcvec_function_p (tree func)
5277
{
5278
  tree a;
5279
 
5280
  if (TREE_CODE (func) != FUNCTION_DECL)
5281
    return 0;
5282
 
5283
  a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func));
5284
  return a != NULL_TREE;
5285
}
5286
 
5287
/* Return nonzero if DECL is a variable that's in the eight bit
5288
   data area.  */
5289
 
5290
int
5291
h8300_eightbit_data_p (tree decl)
5292
{
5293
  tree a;
5294
 
5295
  if (TREE_CODE (decl) != VAR_DECL)
5296
    return 0;
5297
 
5298
  a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl));
5299
  return a != NULL_TREE;
5300
}
5301
 
5302
/* Return nonzero if DECL is a variable that's in the tiny
5303
   data area.  */
5304
 
5305
int
5306
h8300_tiny_data_p (tree decl)
5307
{
5308
  tree a;
5309
 
5310
  if (TREE_CODE (decl) != VAR_DECL)
5311
    return 0;
5312
 
5313
  a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl));
5314
  return a != NULL_TREE;
5315
}
5316
 
5317
/* Generate an 'interrupt_handler' attribute for decls.  We convert
5318
   all the pragmas to corresponding attributes.  */
5319
 
5320
static void
5321
h8300_insert_attributes (tree node, tree *attributes)
5322
{
5323
  if (TREE_CODE (node) == FUNCTION_DECL)
5324
    {
5325
      if (pragma_interrupt)
5326
        {
5327
          pragma_interrupt = 0;
5328
 
5329
          /* Add an 'interrupt_handler' attribute.  */
5330
          *attributes = tree_cons (get_identifier ("interrupt_handler"),
5331
                                   NULL, *attributes);
5332
        }
5333
 
5334
      if (pragma_saveall)
5335
        {
5336
          pragma_saveall = 0;
5337
 
5338
          /* Add an 'saveall' attribute.  */
5339
          *attributes = tree_cons (get_identifier ("saveall"),
5340
                                   NULL, *attributes);
5341
        }
5342
    }
5343
}
5344
 
5345
/* Supported attributes:
5346
 
5347
   interrupt_handler: output a prologue and epilogue suitable for an
5348
   interrupt handler.
5349
 
5350
   saveall: output a prologue and epilogue that saves and restores
5351
   all registers except the stack pointer.
5352
 
5353
   function_vector: This function should be called through the
5354
   function vector.
5355
 
5356
   eightbit_data: This variable lives in the 8-bit data area and can
5357
   be referenced with 8-bit absolute memory addresses.
5358
 
5359
   tiny_data: This variable lives in the tiny data area and can be
5360
   referenced with 16-bit absolute memory references.  */
5361
 
5362
static const struct attribute_spec h8300_attribute_table[] =
5363
{
5364
  /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
5365
       affects_type_identity } */
5366
  { "interrupt_handler", 0, 0, true,  false, false,
5367
    h8300_handle_fndecl_attribute, false },
5368
  { "saveall",           0, 0, true,  false, false,
5369
    h8300_handle_fndecl_attribute, false },
5370
  { "OS_Task",           0, 0, true,  false, false,
5371
    h8300_handle_fndecl_attribute, false },
5372
  { "monitor",           0, 0, true,  false, false,
5373
    h8300_handle_fndecl_attribute, false },
5374
  { "function_vector",   0, 0, true,  false, false,
5375
    h8300_handle_fndecl_attribute, false },
5376
  { "eightbit_data",     0, 0, true,  false, false,
5377
    h8300_handle_eightbit_data_attribute, false },
5378
  { "tiny_data",         0, 0, true,  false, false,
5379
    h8300_handle_tiny_data_attribute, false },
5380
  { NULL,                0, 0, false, false, false, NULL, false }
5381
};
5382
 
5383
 
5384
/* Handle an attribute requiring a FUNCTION_DECL; arguments as in
5385
   struct attribute_spec.handler.  */
5386
static tree
5387
h8300_handle_fndecl_attribute (tree *node, tree name,
5388
                               tree args ATTRIBUTE_UNUSED,
5389
                               int flags ATTRIBUTE_UNUSED,
5390
                               bool *no_add_attrs)
5391
{
5392
  if (TREE_CODE (*node) != FUNCTION_DECL)
5393
    {
5394
      warning (OPT_Wattributes, "%qE attribute only applies to functions",
5395
               name);
5396
      *no_add_attrs = true;
5397
    }
5398
 
5399
  return NULL_TREE;
5400
}
5401
 
5402
/* Handle an "eightbit_data" attribute; arguments as in
5403
   struct attribute_spec.handler.  */
5404
static tree
5405
h8300_handle_eightbit_data_attribute (tree *node, tree name,
5406
                                      tree args ATTRIBUTE_UNUSED,
5407
                                      int flags ATTRIBUTE_UNUSED,
5408
                                      bool *no_add_attrs)
5409
{
5410
  tree decl = *node;
5411
 
5412
  if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
5413
    {
5414
      DECL_SECTION_NAME (decl) = build_string (7, ".eight");
5415
    }
5416
  else
5417
    {
5418
      warning (OPT_Wattributes, "%qE attribute ignored",
5419
               name);
5420
      *no_add_attrs = true;
5421
    }
5422
 
5423
  return NULL_TREE;
5424
}
5425
 
5426
/* Handle an "tiny_data" attribute; arguments as in
5427
   struct attribute_spec.handler.  */
5428
static tree
5429
h8300_handle_tiny_data_attribute (tree *node, tree name,
5430
                                  tree args ATTRIBUTE_UNUSED,
5431
                                  int flags ATTRIBUTE_UNUSED,
5432
                                  bool *no_add_attrs)
5433
{
5434
  tree decl = *node;
5435
 
5436
  if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
5437
    {
5438
      DECL_SECTION_NAME (decl) = build_string (6, ".tiny");
5439
    }
5440
  else
5441
    {
5442
      warning (OPT_Wattributes, "%qE attribute ignored",
5443
               name);
5444
      *no_add_attrs = true;
5445
    }
5446
 
5447
  return NULL_TREE;
5448
}
5449
 
5450
/* Mark function vectors, and various small data objects.  */
5451
 
5452
static void
5453
h8300_encode_section_info (tree decl, rtx rtl, int first)
5454
{
5455
  int extra_flags = 0;
5456
 
5457
  default_encode_section_info (decl, rtl, first);
5458
 
5459
  if (TREE_CODE (decl) == FUNCTION_DECL
5460
      && h8300_funcvec_function_p (decl))
5461
    extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION;
5462
  else if (TREE_CODE (decl) == VAR_DECL
5463
           && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
5464
    {
5465
      if (h8300_eightbit_data_p (decl))
5466
        extra_flags = SYMBOL_FLAG_EIGHTBIT_DATA;
5467
      else if (first && h8300_tiny_data_p (decl))
5468
        extra_flags = SYMBOL_FLAG_TINY_DATA;
5469
    }
5470
 
5471
  if (extra_flags)
5472
    SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
5473
}
5474
 
5475
/* Output a single-bit extraction.  */
5476
 
5477
const char *
5478
output_simode_bld (int bild, rtx operands[])
5479
{
5480
  if (TARGET_H8300)
5481
    {
5482
      /* Clear the destination register.  */
5483
      output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
5484
 
5485
      /* Now output the bit load or bit inverse load, and store it in
5486
         the destination.  */
5487
      if (bild)
5488
        output_asm_insn ("bild\t%Z2,%Y1", operands);
5489
      else
5490
        output_asm_insn ("bld\t%Z2,%Y1", operands);
5491
 
5492
      output_asm_insn ("bst\t#0,%w0", operands);
5493
    }
5494
  else
5495
    {
5496
      /* Determine if we can clear the destination first.  */
5497
      int clear_first = (REG_P (operands[0]) && REG_P (operands[1])
5498
                         && REGNO (operands[0]) != REGNO (operands[1]));
5499
 
5500
      if (clear_first)
5501
        output_asm_insn ("sub.l\t%S0,%S0", operands);
5502
 
5503
      /* Output the bit load or bit inverse load.  */
5504
      if (bild)
5505
        output_asm_insn ("bild\t%Z2,%Y1", operands);
5506
      else
5507
        output_asm_insn ("bld\t%Z2,%Y1", operands);
5508
 
5509
      if (!clear_first)
5510
        output_asm_insn ("xor.l\t%S0,%S0", operands);
5511
 
5512
      /* Perform the bit store.  */
5513
      output_asm_insn ("rotxl.l\t%S0", operands);
5514
    }
5515
 
5516
  /* All done.  */
5517
  return "";
5518
}
5519
 
5520
/* Delayed-branch scheduling is more effective if we have some idea
5521
   how long each instruction will be.  Use a shorten_branches pass
5522
   to get an initial estimate.  */
5523
 
5524
static void
5525
h8300_reorg (void)
5526
{
5527
  if (flag_delayed_branch)
5528
    shorten_branches (get_insns ());
5529
}
5530
 
5531
#ifndef OBJECT_FORMAT_ELF
5532
static void
5533
h8300_asm_named_section (const char *name, unsigned int flags ATTRIBUTE_UNUSED,
5534
                         tree decl)
5535
{
5536
  /* ??? Perhaps we should be using default_coff_asm_named_section.  */
5537
  fprintf (asm_out_file, "\t.section %s\n", name);
5538
}
5539
#endif /* ! OBJECT_FORMAT_ELF */
5540
 
5541
/* Nonzero if X is a constant address suitable as an 8-bit absolute,
5542
   which is a special case of the 'R' operand.  */
5543
 
5544
int
5545
h8300_eightbit_constant_address_p (rtx x)
5546
{
5547
  /* The ranges of the 8-bit area.  */
5548
  const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode (0xff00, HImode);
5549
  const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode (0xffff, HImode);
5550
  const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00ffff00, SImode);
5551
  const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00ffffff, SImode);
5552
  const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0xffffff00, SImode);
5553
  const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0xffffffff, SImode);
5554
 
5555
  unsigned HOST_WIDE_INT addr;
5556
 
5557
  /* We accept symbols declared with eightbit_data.  */
5558
  if (GET_CODE (x) == SYMBOL_REF)
5559
    return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0;
5560
 
5561
  if (GET_CODE (x) != CONST_INT)
5562
    return 0;
5563
 
5564
  addr = INTVAL (x);
5565
 
5566
  return (0
5567
          || ((TARGET_H8300 || TARGET_NORMAL_MODE) && IN_RANGE (addr, n1, n2))
5568
          || (TARGET_H8300H && IN_RANGE (addr, h1, h2))
5569
          || (TARGET_H8300S && IN_RANGE (addr, s1, s2)));
5570
}
5571
 
5572
/* Nonzero if X is a constant address suitable as an 16-bit absolute
5573
   on H8/300H and H8S.  */
5574
 
5575
int
5576
h8300_tiny_constant_address_p (rtx x)
5577
{
5578
  /* The ranges of the 16-bit area.  */
5579
  const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00000000, SImode);
5580
  const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00007fff, SImode);
5581
  const unsigned HOST_WIDE_INT h3 = trunc_int_for_mode (0x00ff8000, SImode);
5582
  const unsigned HOST_WIDE_INT h4 = trunc_int_for_mode (0x00ffffff, SImode);
5583
  const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0x00000000, SImode);
5584
  const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0x00007fff, SImode);
5585
  const unsigned HOST_WIDE_INT s3 = trunc_int_for_mode (0xffff8000, SImode);
5586
  const unsigned HOST_WIDE_INT s4 = trunc_int_for_mode (0xffffffff, SImode);
5587
 
5588
  unsigned HOST_WIDE_INT addr;
5589
 
5590
  switch (GET_CODE (x))
5591
    {
5592
    case SYMBOL_REF:
5593
      /* In the normal mode, any symbol fits in the 16-bit absolute
5594
         address range.  We also accept symbols declared with
5595
         tiny_data.  */
5596
      return (TARGET_NORMAL_MODE
5597
              || (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_TINY_DATA) != 0);
5598
 
5599
    case CONST_INT:
5600
      addr = INTVAL (x);
5601
      return (TARGET_NORMAL_MODE
5602
              || (TARGET_H8300H
5603
                  && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4)))
5604
              || (TARGET_H8300S
5605
                  && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4))));
5606
 
5607
    case CONST:
5608
      return TARGET_NORMAL_MODE;
5609
 
5610
    default:
5611
      return 0;
5612
    }
5613
 
5614
}
5615
 
5616
/* Return nonzero if ADDR1 and ADDR2 point to consecutive memory
5617
   locations that can be accessed as a 16-bit word.  */
5618
 
5619
int
5620
byte_accesses_mergeable_p (rtx addr1, rtx addr2)
5621
{
5622
  HOST_WIDE_INT offset1, offset2;
5623
  rtx reg1, reg2;
5624
 
5625
  if (REG_P (addr1))
5626
    {
5627
      reg1 = addr1;
5628
      offset1 = 0;
5629
    }
5630
  else if (GET_CODE (addr1) == PLUS
5631
           && REG_P (XEXP (addr1, 0))
5632
           && GET_CODE (XEXP (addr1, 1)) == CONST_INT)
5633
    {
5634
      reg1 = XEXP (addr1, 0);
5635
      offset1 = INTVAL (XEXP (addr1, 1));
5636
    }
5637
  else
5638
    return 0;
5639
 
5640
  if (REG_P (addr2))
5641
    {
5642
      reg2 = addr2;
5643
      offset2 = 0;
5644
    }
5645
  else if (GET_CODE (addr2) == PLUS
5646
           && REG_P (XEXP (addr2, 0))
5647
           && GET_CODE (XEXP (addr2, 1)) == CONST_INT)
5648
    {
5649
      reg2 = XEXP (addr2, 0);
5650
      offset2 = INTVAL (XEXP (addr2, 1));
5651
    }
5652
  else
5653
    return 0;
5654
 
5655
  if (((reg1 == stack_pointer_rtx && reg2 == stack_pointer_rtx)
5656
       || (reg1 == frame_pointer_rtx && reg2 == frame_pointer_rtx))
5657
      && offset1 % 2 == 0
5658
      && offset1 + 1 == offset2)
5659
    return 1;
5660
 
5661
  return 0;
5662
}
5663
 
5664
/* Return nonzero if we have the same comparison insn as I3 two insns
5665
   before I3.  I3 is assumed to be a comparison insn.  */
5666
 
5667
int
5668
same_cmp_preceding_p (rtx i3)
5669
{
5670
  rtx i1, i2;
5671
 
5672
  /* Make sure we have a sequence of three insns.  */
5673
  i2 = prev_nonnote_insn (i3);
5674
  if (i2 == NULL_RTX)
5675
    return 0;
5676
  i1 = prev_nonnote_insn (i2);
5677
  if (i1 == NULL_RTX)
5678
    return 0;
5679
 
5680
  return (INSN_P (i1) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
5681
          && any_condjump_p (i2) && onlyjump_p (i2));
5682
}
5683
 
5684
/* Return nonzero if we have the same comparison insn as I1 two insns
5685
   after I1.  I1 is assumed to be a comparison insn.  */
5686
 
5687
int
5688
same_cmp_following_p (rtx i1)
5689
{
5690
  rtx i2, i3;
5691
 
5692
  /* Make sure we have a sequence of three insns.  */
5693
  i2 = next_nonnote_insn (i1);
5694
  if (i2 == NULL_RTX)
5695
    return 0;
5696
  i3 = next_nonnote_insn (i2);
5697
  if (i3 == NULL_RTX)
5698
    return 0;
5699
 
5700
  return (INSN_P (i3) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
5701
          && any_condjump_p (i2) && onlyjump_p (i2));
5702
}
5703
 
5704
/* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes
5705
   (or pops) N registers.  OPERANDS are assumed to be an array of
5706
   registers.  */
5707
 
5708
int
5709
h8300_regs_ok_for_stm (int n, rtx operands[])
5710
{
5711
  switch (n)
5712
    {
5713
    case 2:
5714
      return ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
5715
              || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
5716
              || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5));
5717
    case 3:
5718
      return ((REGNO (operands[0]) == 0
5719
               && REGNO (operands[1]) == 1
5720
               && REGNO (operands[2]) == 2)
5721
              || (REGNO (operands[0]) == 4
5722
                  && REGNO (operands[1]) == 5
5723
                  && REGNO (operands[2]) == 6));
5724
 
5725
    case 4:
5726
      return (REGNO (operands[0]) == 0
5727
              && REGNO (operands[1]) == 1
5728
              && REGNO (operands[2]) == 2
5729
              && REGNO (operands[3]) == 3);
5730
    default:
5731
      gcc_unreachable ();
5732
    }
5733
}
5734
 
5735
/* Return nonzero if register OLD_REG can be renamed to register NEW_REG.  */
5736
 
5737
int
5738
h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
5739
                            unsigned int new_reg)
5740
{
5741
  /* Interrupt functions can only use registers that have already been
5742
     saved by the prologue, even if they would normally be
5743
     call-clobbered.  */
5744
 
5745
  if (h8300_current_function_interrupt_function_p ()
5746
      && !df_regs_ever_live_p (new_reg))
5747
    return 0;
5748
 
5749
  return 1;
5750
}
5751
 
5752
/* Returns true if register REGNO is safe to be allocated as a scratch
5753
   register in the current function.  */
5754
 
5755
static bool
5756
h8300_hard_regno_scratch_ok (unsigned int regno)
5757
{
5758
  if (h8300_current_function_interrupt_function_p ()
5759
      && ! WORD_REG_USED (regno))
5760
    return false;
5761
 
5762
  return true;
5763
}
5764
 
5765
 
5766
/* Return nonzero if X is a REG or SUBREG suitable as a base register.  */
5767
 
5768
static int
5769
h8300_rtx_ok_for_base_p (rtx x, int strict)
5770
{
5771
  /* Strip off SUBREG if any.  */
5772
  if (GET_CODE (x) == SUBREG)
5773
    x = SUBREG_REG (x);
5774
 
5775
  return (REG_P (x)
5776
          && (strict
5777
              ? REG_OK_FOR_BASE_STRICT_P (x)
5778
              : REG_OK_FOR_BASE_NONSTRICT_P (x)));
5779
}
5780
 
5781
/* Return nozero if X is a legitimate address.  On the H8/300, a
5782
   legitimate address has the form REG, REG+CONSTANT_ADDRESS or
5783
   CONSTANT_ADDRESS.  */
5784
 
5785
static bool
5786
h8300_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
5787
{
5788
  /* The register indirect addresses like @er0 is always valid.  */
5789
  if (h8300_rtx_ok_for_base_p (x, strict))
5790
    return 1;
5791
 
5792
  if (CONSTANT_ADDRESS_P (x))
5793
    return 1;
5794
 
5795
  if (TARGET_H8300SX
5796
      && (   GET_CODE (x) == PRE_INC
5797
          || GET_CODE (x) == PRE_DEC
5798
          || GET_CODE (x) == POST_INC
5799
          || GET_CODE (x) == POST_DEC)
5800
      && h8300_rtx_ok_for_base_p (XEXP (x, 0), strict))
5801
    return 1;
5802
 
5803
  if (GET_CODE (x) == PLUS
5804
      && CONSTANT_ADDRESS_P (XEXP (x, 1))
5805
      && h8300_rtx_ok_for_base_p (h8300_get_index (XEXP (x, 0),
5806
                                                   mode, 0), strict))
5807
    return 1;
5808
 
5809
  return 0;
5810
}
5811
 
5812
/* Worker function for HARD_REGNO_NREGS.
5813
 
5814
   We pretend the MAC register is 32bits -- we don't have any data
5815
   types on the H8 series to handle more than 32bits.  */
5816
 
5817
int
5818
h8300_hard_regno_nregs (int regno ATTRIBUTE_UNUSED, enum machine_mode mode)
5819
{
5820
  return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5821
}
5822
 
5823
/* Worker function for HARD_REGNO_MODE_OK.  */
5824
 
5825
int
5826
h8300_hard_regno_mode_ok (int regno, enum machine_mode mode)
5827
{
5828
  if (TARGET_H8300)
5829
    /* If an even reg, then anything goes.  Otherwise the mode must be
5830
       QI or HI.  */
5831
    return ((regno & 1) == 0) || (mode == HImode) || (mode == QImode);
5832
  else
5833
    /* MAC register can only be of SImode.  Otherwise, anything
5834
       goes.  */
5835
    return regno == MAC_REG ? mode == SImode : 1;
5836
}
5837
 
5838
/* Helper function for the move patterns.  Make sure a move is legitimate.  */
5839
 
5840
bool
5841
h8300_move_ok (rtx dest, rtx src)
5842
{
5843
  rtx addr, other;
5844
 
5845
  /* Validate that at least one operand is a register.  */
5846
  if (MEM_P (dest))
5847
    {
5848
      if (MEM_P (src) || CONSTANT_P (src))
5849
        return false;
5850
      addr = XEXP (dest, 0);
5851
      other = src;
5852
    }
5853
  else if (MEM_P (src))
5854
    {
5855
      addr = XEXP (src, 0);
5856
      other = dest;
5857
    }
5858
  else
5859
    return true;
5860
 
5861
  /* Validate that auto-inc doesn't affect OTHER.  */
5862
  if (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC)
5863
    return true;
5864
  addr = XEXP (addr, 0);
5865
 
5866
  if (addr == stack_pointer_rtx)
5867
    return register_no_sp_elim_operand (other, VOIDmode);
5868
  else
5869
    return !reg_overlap_mentioned_p(other, addr);
5870
}
5871
 
5872
/* Perform target dependent optabs initialization.  */
5873
static void
5874
h8300_init_libfuncs (void)
5875
{
5876
  set_optab_libfunc (smul_optab, HImode, "__mulhi3");
5877
  set_optab_libfunc (sdiv_optab, HImode, "__divhi3");
5878
  set_optab_libfunc (udiv_optab, HImode, "__udivhi3");
5879
  set_optab_libfunc (smod_optab, HImode, "__modhi3");
5880
  set_optab_libfunc (umod_optab, HImode, "__umodhi3");
5881
}
5882
 
5883
/* Worker function for TARGET_FUNCTION_VALUE.
5884
 
5885
   On the H8 the return value is in R0/R1.  */
5886
 
5887
static rtx
5888
h8300_function_value (const_tree ret_type,
5889
                      const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
5890
                      bool outgoing ATTRIBUTE_UNUSED)
5891
{
5892
  return gen_rtx_REG (TYPE_MODE (ret_type), R0_REG);
5893
}
5894
 
5895
/* Worker function for TARGET_LIBCALL_VALUE.
5896
 
5897
   On the H8 the return value is in R0/R1.  */
5898
 
5899
static rtx
5900
h8300_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
5901
{
5902
  return gen_rtx_REG (mode, R0_REG);
5903
}
5904
 
5905
/* Worker function for TARGET_FUNCTION_VALUE_REGNO_P.
5906
 
5907
   On the H8, R0 is the only register thus used.  */
5908
 
5909
static bool
5910
h8300_function_value_regno_p (const unsigned int regno)
5911
{
5912
  return (regno == R0_REG);
5913
}
5914
 
5915
/* Worker function for TARGET_RETURN_IN_MEMORY.  */
5916
 
5917
static bool
5918
h8300_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
5919
{
5920
  return (TYPE_MODE (type) == BLKmode
5921
          || GET_MODE_SIZE (TYPE_MODE (type)) > (TARGET_H8300 ? 4 : 8));
5922
}
5923
 
5924
/* We emit the entire trampoline here.  Depending on the pointer size,
5925
   we use a different trampoline.
5926
 
5927
   Pmode == HImode
5928
              vvvv context
5929
   1 0000 7903xxxx              mov.w   #0x1234,r3
5930
   2 0004 5A00xxxx              jmp     @0x1234
5931
              ^^^^ function
5932
 
5933
   Pmode == SImode
5934
              vvvvvvvv context
5935
   2 0000 7A03xxxxxxxx          mov.l   #0x12345678,er3
5936
   3 0006 5Axxxxxx              jmp     @0x123456
5937
            ^^^^^^ function
5938
*/
5939
 
5940
static void
5941
h8300_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
5942
{
5943
  rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
5944
  rtx mem;
5945
 
5946
  if (Pmode == HImode)
5947
    {
5948
      mem = adjust_address (m_tramp, HImode, 0);
5949
      emit_move_insn (mem, GEN_INT (0x7903));
5950
      mem = adjust_address (m_tramp, Pmode, 2);
5951
      emit_move_insn (mem, cxt);
5952
      mem = adjust_address (m_tramp, HImode, 4);
5953
      emit_move_insn (mem, GEN_INT (0x5a00));
5954
      mem = adjust_address (m_tramp, Pmode, 6);
5955
      emit_move_insn (mem, fnaddr);
5956
    }
5957
  else
5958
    {
5959
      rtx tem;
5960
 
5961
      mem = adjust_address (m_tramp, HImode, 0);
5962
      emit_move_insn (mem, GEN_INT (0x7a03));
5963
      mem = adjust_address (m_tramp, Pmode, 2);
5964
      emit_move_insn (mem, cxt);
5965
 
5966
      tem = copy_to_reg (fnaddr);
5967
      emit_insn (gen_andsi3 (tem, tem, GEN_INT (0x00ffffff)));
5968
      emit_insn (gen_iorsi3 (tem, tem, GEN_INT (0x5a000000)));
5969
      mem = adjust_address (m_tramp, SImode, 6);
5970
      emit_move_insn (mem, tem);
5971
    }
5972
}
5973
 
5974
/* Initialize the GCC target structure.  */
5975
#undef TARGET_ATTRIBUTE_TABLE
5976
#define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
5977
 
5978
#undef TARGET_ASM_ALIGNED_HI_OP
5979
#define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
5980
 
5981
#undef TARGET_ASM_FILE_START
5982
#define TARGET_ASM_FILE_START h8300_file_start
5983
#undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
5984
#define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
5985
 
5986
#undef TARGET_ASM_FILE_END
5987
#define TARGET_ASM_FILE_END h8300_file_end
5988
 
5989
#undef TARGET_PRINT_OPERAND
5990
#define TARGET_PRINT_OPERAND h8300_print_operand
5991
#undef TARGET_PRINT_OPERAND_ADDRESS
5992
#define TARGET_PRINT_OPERAND_ADDRESS h8300_print_operand_address
5993
#undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
5994
#define TARGET_PRINT_OPERAND_PUNCT_VALID_P h8300_print_operand_punct_valid_p
5995
 
5996
#undef TARGET_ENCODE_SECTION_INFO
5997
#define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
5998
 
5999
#undef TARGET_INSERT_ATTRIBUTES
6000
#define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
6001
 
6002
#undef TARGET_REGISTER_MOVE_COST
6003
#define TARGET_REGISTER_MOVE_COST h8300_register_move_cost
6004
 
6005
#undef TARGET_RTX_COSTS
6006
#define TARGET_RTX_COSTS h8300_rtx_costs
6007
 
6008
#undef TARGET_INIT_LIBFUNCS
6009
#define TARGET_INIT_LIBFUNCS h8300_init_libfuncs
6010
 
6011
#undef TARGET_FUNCTION_VALUE
6012
#define TARGET_FUNCTION_VALUE h8300_function_value
6013
 
6014
#undef TARGET_LIBCALL_VALUE
6015
#define TARGET_LIBCALL_VALUE h8300_libcall_value
6016
 
6017
#undef TARGET_FUNCTION_VALUE_REGNO_P
6018
#define TARGET_FUNCTION_VALUE_REGNO_P h8300_function_value_regno_p
6019
 
6020
#undef TARGET_RETURN_IN_MEMORY
6021
#define TARGET_RETURN_IN_MEMORY h8300_return_in_memory
6022
 
6023
#undef TARGET_FUNCTION_ARG
6024
#define TARGET_FUNCTION_ARG h8300_function_arg
6025
 
6026
#undef TARGET_FUNCTION_ARG_ADVANCE
6027
#define TARGET_FUNCTION_ARG_ADVANCE h8300_function_arg_advance
6028
 
6029
#undef  TARGET_MACHINE_DEPENDENT_REORG
6030
#define TARGET_MACHINE_DEPENDENT_REORG h8300_reorg
6031
 
6032
#undef TARGET_HARD_REGNO_SCRATCH_OK
6033
#define TARGET_HARD_REGNO_SCRATCH_OK h8300_hard_regno_scratch_ok
6034
 
6035
#undef TARGET_LEGITIMATE_ADDRESS_P
6036
#define TARGET_LEGITIMATE_ADDRESS_P     h8300_legitimate_address_p
6037
 
6038
#undef TARGET_CAN_ELIMINATE
6039
#define TARGET_CAN_ELIMINATE h8300_can_eliminate
6040
 
6041
#undef TARGET_CONDITIONAL_REGISTER_USAGE
6042
#define TARGET_CONDITIONAL_REGISTER_USAGE h8300_conditional_register_usage
6043
 
6044
#undef TARGET_TRAMPOLINE_INIT
6045
#define TARGET_TRAMPOLINE_INIT h8300_trampoline_init
6046
 
6047
#undef TARGET_OPTION_OVERRIDE
6048
#define TARGET_OPTION_OVERRIDE h8300_option_override
6049
 
6050
#undef TARGET_MODE_DEPENDENT_ADDRESS_P
6051
#define TARGET_MODE_DEPENDENT_ADDRESS_P h8300_mode_dependent_address_p
6052
 
6053
struct gcc_target targetm = TARGET_INITIALIZER;

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