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jeremybenn |
;; Atom Scheduling
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;; Copyright (C) 2009, 2010 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; .
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;;
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;; Atom is an in-order core with two integer pipelines.
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(define_attr "atom_unit" "sishuf,simul,jeu,complex,other"
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(const_string "other"))
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(define_attr "atom_sse_attr" "rcp,movdup,lfence,fence,prefetch,sqrt,mxcsr,other"
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(const_string "other"))
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(define_automaton "atom")
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;; Atom has two ports: port 0 and port 1 connecting to all execution units
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(define_cpu_unit "atom-port-0,atom-port-1" "atom")
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;; EU: Execution Unit
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;; Atom EUs are connected by port 0 or port 1.
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(define_cpu_unit "atom-eu-0, atom-eu-1,
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atom-imul-1, atom-imul-2, atom-imul-3, atom-imul-4"
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"atom")
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;; Some EUs have duplicated copied and can be accessed via either
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;; port 0 or port 1
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;; (define_reservation "atom-port-either" "(atom-port-0 | atom-port-1)")
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;;; Some instructions is dual-pipe execution, need both ports
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;;; Complex multi-op macro-instructoins need both ports and all EUs
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(define_reservation "atom-port-dual" "(atom-port-0 + atom-port-1)")
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(define_reservation "atom-all-eu" "(atom-eu-0 + atom-eu-1 +
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atom-imul-1 + atom-imul-2 + atom-imul-3 +
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atom-imul-4)")
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;;; Most of simple instructions have 1 cycle latency. Some of them
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;;; issue in port 0, some in port 0 and some in either port.
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(define_reservation "atom-simple-0" "(atom-port-0 + atom-eu-0)")
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(define_reservation "atom-simple-1" "(atom-port-1 + atom-eu-1)")
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(define_reservation "atom-simple-either" "(atom-simple-0 | atom-simple-1)")
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;;; Some insn issues in port 0 with 3 cycle latency and 1 cycle tput
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(define_reservation "atom-eu-0-3-1" "(atom-port-0 + atom-eu-0, nothing*2)")
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;;; fmul insn can have 4 or 5 cycles latency
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(define_reservation "atom-fmul-5c" "(atom-port-0 + atom-eu-0), nothing*4")
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(define_reservation "atom-fmul-4c" "(atom-port-0 + atom-eu-0), nothing*3")
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;;; fadd can has 5 cycles latency depends on instruction forms
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(define_reservation "atom-fadd-5c" "(atom-port-1 + atom-eu-1), nothing*5")
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;;; imul insn has 5 cycles latency
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(define_reservation "atom-imul-32"
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"atom-imul-1, atom-imul-2, atom-imul-3, atom-imul-4,
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atom-port-0")
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;;; imul instruction excludes other non-FP instructions.
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(exclusion_set "atom-eu-0, atom-eu-1"
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"atom-imul-1, atom-imul-2, atom-imul-3, atom-imul-4")
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;;; dual-execution instructions can have 1,2,4,5 cycles latency depends on
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;;; instruction forms
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(define_reservation "atom-dual-1c" "(atom-port-dual + atom-eu-0 + atom-eu-1)")
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(define_reservation "atom-dual-2c"
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"(atom-port-dual + atom-eu-0 + atom-eu-1, nothing)")
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(define_reservation "atom-dual-5c"
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"(atom-port-dual + atom-eu-0 + atom-eu-1, nothing*4)")
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;;; Complex macro-instruction has variants of latency, and uses both ports.
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(define_reservation "atom-complex" "(atom-port-dual + atom-all-eu)")
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(define_insn_reservation "atom_other" 9
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "other")
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(eq_attr "atom_unit" "!jeu")))
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"atom-complex, atom-all-eu*8")
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;; return has type "other" with atom_unit "jeu"
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(define_insn_reservation "atom_other_2" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "other")
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(eq_attr "atom_unit" "jeu")))
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"atom-dual-1c")
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(define_insn_reservation "atom_multi" 9
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(and (eq_attr "cpu" "atom")
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(eq_attr "type" "multi"))
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"atom-complex, atom-all-eu*8")
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;; Normal alu insns without carry
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(define_insn_reservation "atom_alu" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "alu")
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(and (eq_attr "memory" "none")
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(eq_attr "use_carry" "0"))))
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"atom-simple-either")
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;; Normal alu insns without carry
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(define_insn_reservation "atom_alu_mem" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "alu")
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(and (eq_attr "memory" "!none")
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(eq_attr "use_carry" "0"))))
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"atom-simple-either")
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;; Alu insn consuming CF, such as add/sbb
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(define_insn_reservation "atom_alu_carry" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "alu")
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(and (eq_attr "memory" "none")
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(eq_attr "use_carry" "1"))))
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"atom-simple-either")
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;; Alu insn consuming CF, such as add/sbb
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(define_insn_reservation "atom_alu_carry_mem" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "alu")
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(and (eq_attr "memory" "!none")
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(eq_attr "use_carry" "1"))))
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"atom-simple-either")
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(define_insn_reservation "atom_alu1" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "alu1")
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(eq_attr "memory" "none")))
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"atom-simple-either")
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(define_insn_reservation "atom_alu1_mem" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "alu1")
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(eq_attr "memory" "!none")))
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"atom-simple-either")
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(define_insn_reservation "atom_negnot" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "negnot")
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(eq_attr "memory" "none")))
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"atom-simple-either")
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(define_insn_reservation "atom_negnot_mem" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "negnot")
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(eq_attr "memory" "!none")))
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"atom-simple-either")
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(define_insn_reservation "atom_imov" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "imov")
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(eq_attr "memory" "none")))
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"atom-simple-either")
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(define_insn_reservation "atom_imov_mem" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "imov")
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(eq_attr "memory" "!none")))
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"atom-simple-either")
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;; 16<-16, 32<-32
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(define_insn_reservation "atom_imovx" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "imovx")
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(and (eq_attr "memory" "none")
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(ior (and (match_operand:HI 0 "register_operand")
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(match_operand:HI 1 "general_operand"))
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(and (match_operand:SI 0 "register_operand")
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(match_operand:SI 1 "general_operand"))))))
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"atom-simple-either")
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;; 16<-16, 32<-32, mem
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(define_insn_reservation "atom_imovx_mem" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "imovx")
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(and (eq_attr "memory" "!none")
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(ior (and (match_operand:HI 0 "register_operand")
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(match_operand:HI 1 "general_operand"))
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(and (match_operand:SI 0 "register_operand")
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(match_operand:SI 1 "general_operand"))))))
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"atom-simple-either")
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;; 32<-16, 32<-8, 64<-16, 64<-8, 64<-32, 8<-8
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(define_insn_reservation "atom_imovx_2" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "imovx")
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(and (eq_attr "memory" "none")
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(ior (match_operand:QI 0 "register_operand")
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(ior (and (match_operand:SI 0 "register_operand")
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(not (match_operand:SI 1 "general_operand")))
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(match_operand:DI 0 "register_operand"))))))
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"atom-simple-0")
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;; 32<-16, 32<-8, 64<-16, 64<-8, 64<-32, 8<-8, mem
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(define_insn_reservation "atom_imovx_2_mem" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "imovx")
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(and (eq_attr "memory" "!none")
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(ior (match_operand:QI 0 "register_operand")
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(ior (and (match_operand:SI 0 "register_operand")
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(not (match_operand:SI 1 "general_operand")))
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(match_operand:DI 0 "register_operand"))))))
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"atom-simple-0")
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;; 16<-8
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(define_insn_reservation "atom_imovx_3" 3
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "imovx")
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(and (match_operand:HI 0 "register_operand")
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(match_operand:QI 1 "general_operand"))))
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"atom-complex, atom-all-eu*2")
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(define_insn_reservation "atom_lea" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "lea")
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(eq_attr "mode" "!HI")))
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"atom-simple-either")
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;; lea 16bit address is complex insn
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(define_insn_reservation "atom_lea_2" 2
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "lea")
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(eq_attr "mode" "HI")))
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"atom-complex, atom-all-eu")
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(define_insn_reservation "atom_incdec" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "incdec")
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(eq_attr "memory" "none")))
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"atom-simple-either")
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(define_insn_reservation "atom_incdec_mem" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "incdec")
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(eq_attr "memory" "!none")))
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"atom-simple-either")
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;; simple shift instruction use SHIFT eu, none memory
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(define_insn_reservation "atom_ishift" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "ishift")
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(and (eq_attr "memory" "none") (eq_attr "prefix_0f" "0"))))
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"atom-simple-0")
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;; simple shift instruction use SHIFT eu, memory
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(define_insn_reservation "atom_ishift_mem" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "ishift")
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(and (eq_attr "memory" "!none") (eq_attr "prefix_0f" "0"))))
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"atom-simple-0")
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;; DF shift (prefixed with 0f) is complex insn with latency of 7 cycles
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(define_insn_reservation "atom_ishift_3" 7
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "ishift")
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(eq_attr "prefix_0f" "1")))
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"atom-complex, atom-all-eu*6")
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(define_insn_reservation "atom_ishift1" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "ishift1")
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(eq_attr "memory" "none")))
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"atom-simple-0")
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(define_insn_reservation "atom_ishift1_mem" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "ishift1")
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(eq_attr "memory" "!none")))
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"atom-simple-0")
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(define_insn_reservation "atom_rotate" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "rotate")
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(eq_attr "memory" "none")))
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"atom-simple-0")
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(define_insn_reservation "atom_rotate_mem" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "rotate")
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(eq_attr "memory" "!none")))
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"atom-simple-0")
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(define_insn_reservation "atom_rotate1" 1
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(and (eq_attr "cpu" "atom")
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(and (eq_attr "type" "rotate1")
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(eq_attr "memory" "none")))
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"atom-simple-0")
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|
|
(define_insn_reservation "atom_rotate1_mem" 1
|
| 302 |
|
|
(and (eq_attr "cpu" "atom")
|
| 303 |
|
|
(and (eq_attr "type" "rotate1")
|
| 304 |
|
|
(eq_attr "memory" "!none")))
|
| 305 |
|
|
"atom-simple-0")
|
| 306 |
|
|
|
| 307 |
|
|
(define_insn_reservation "atom_imul" 5
|
| 308 |
|
|
(and (eq_attr "cpu" "atom")
|
| 309 |
|
|
(and (eq_attr "type" "imul")
|
| 310 |
|
|
(and (eq_attr "memory" "none") (eq_attr "mode" "SI"))))
|
| 311 |
|
|
"atom-imul-32")
|
| 312 |
|
|
|
| 313 |
|
|
(define_insn_reservation "atom_imul_mem" 5
|
| 314 |
|
|
(and (eq_attr "cpu" "atom")
|
| 315 |
|
|
(and (eq_attr "type" "imul")
|
| 316 |
|
|
(and (eq_attr "memory" "!none") (eq_attr "mode" "SI"))))
|
| 317 |
|
|
"atom-imul-32")
|
| 318 |
|
|
|
| 319 |
|
|
;; latency set to 10 as common 64x64 imul
|
| 320 |
|
|
(define_insn_reservation "atom_imul_3" 10
|
| 321 |
|
|
(and (eq_attr "cpu" "atom")
|
| 322 |
|
|
(and (eq_attr "type" "imul")
|
| 323 |
|
|
(eq_attr "mode" "!SI")))
|
| 324 |
|
|
"atom-complex, atom-all-eu*9")
|
| 325 |
|
|
|
| 326 |
|
|
(define_insn_reservation "atom_idiv" 65
|
| 327 |
|
|
(and (eq_attr "cpu" "atom")
|
| 328 |
|
|
(eq_attr "type" "idiv"))
|
| 329 |
|
|
"atom-complex, atom-all-eu*32, nothing*32")
|
| 330 |
|
|
|
| 331 |
|
|
(define_insn_reservation "atom_icmp" 1
|
| 332 |
|
|
(and (eq_attr "cpu" "atom")
|
| 333 |
|
|
(and (eq_attr "type" "icmp")
|
| 334 |
|
|
(eq_attr "memory" "none")))
|
| 335 |
|
|
"atom-simple-either")
|
| 336 |
|
|
|
| 337 |
|
|
(define_insn_reservation "atom_icmp_mem" 1
|
| 338 |
|
|
(and (eq_attr "cpu" "atom")
|
| 339 |
|
|
(and (eq_attr "type" "icmp")
|
| 340 |
|
|
(eq_attr "memory" "!none")))
|
| 341 |
|
|
"atom-simple-either")
|
| 342 |
|
|
|
| 343 |
|
|
(define_insn_reservation "atom_test" 1
|
| 344 |
|
|
(and (eq_attr "cpu" "atom")
|
| 345 |
|
|
(and (eq_attr "type" "test")
|
| 346 |
|
|
(eq_attr "memory" "none")))
|
| 347 |
|
|
"atom-simple-either")
|
| 348 |
|
|
|
| 349 |
|
|
(define_insn_reservation "atom_test_mem" 1
|
| 350 |
|
|
(and (eq_attr "cpu" "atom")
|
| 351 |
|
|
(and (eq_attr "type" "test")
|
| 352 |
|
|
(eq_attr "memory" "!none")))
|
| 353 |
|
|
"atom-simple-either")
|
| 354 |
|
|
|
| 355 |
|
|
(define_insn_reservation "atom_ibr" 1
|
| 356 |
|
|
(and (eq_attr "cpu" "atom")
|
| 357 |
|
|
(and (eq_attr "type" "ibr")
|
| 358 |
|
|
(eq_attr "memory" "!load")))
|
| 359 |
|
|
"atom-simple-1")
|
| 360 |
|
|
|
| 361 |
|
|
;; complex if jump target is from address
|
| 362 |
|
|
(define_insn_reservation "atom_ibr_2" 2
|
| 363 |
|
|
(and (eq_attr "cpu" "atom")
|
| 364 |
|
|
(and (eq_attr "type" "ibr")
|
| 365 |
|
|
(eq_attr "memory" "load")))
|
| 366 |
|
|
"atom-complex, atom-all-eu")
|
| 367 |
|
|
|
| 368 |
|
|
(define_insn_reservation "atom_setcc" 1
|
| 369 |
|
|
(and (eq_attr "cpu" "atom")
|
| 370 |
|
|
(and (eq_attr "type" "setcc")
|
| 371 |
|
|
(eq_attr "memory" "!store")))
|
| 372 |
|
|
"atom-simple-either")
|
| 373 |
|
|
|
| 374 |
|
|
;; 2 cycles complex if target is in memory
|
| 375 |
|
|
(define_insn_reservation "atom_setcc_2" 2
|
| 376 |
|
|
(and (eq_attr "cpu" "atom")
|
| 377 |
|
|
(and (eq_attr "type" "setcc")
|
| 378 |
|
|
(eq_attr "memory" "store")))
|
| 379 |
|
|
"atom-complex, atom-all-eu")
|
| 380 |
|
|
|
| 381 |
|
|
(define_insn_reservation "atom_icmov" 1
|
| 382 |
|
|
(and (eq_attr "cpu" "atom")
|
| 383 |
|
|
(and (eq_attr "type" "icmov")
|
| 384 |
|
|
(eq_attr "memory" "none")))
|
| 385 |
|
|
"atom-simple-either")
|
| 386 |
|
|
|
| 387 |
|
|
(define_insn_reservation "atom_icmov_mem" 1
|
| 388 |
|
|
(and (eq_attr "cpu" "atom")
|
| 389 |
|
|
(and (eq_attr "type" "icmov")
|
| 390 |
|
|
(eq_attr "memory" "!none")))
|
| 391 |
|
|
"atom-simple-either")
|
| 392 |
|
|
|
| 393 |
|
|
;; UCODE if segreg, ignored
|
| 394 |
|
|
(define_insn_reservation "atom_push" 2
|
| 395 |
|
|
(and (eq_attr "cpu" "atom")
|
| 396 |
|
|
(eq_attr "type" "push"))
|
| 397 |
|
|
"atom-dual-2c")
|
| 398 |
|
|
|
| 399 |
|
|
;; pop r64 is 1 cycle. UCODE if segreg, ignored
|
| 400 |
|
|
(define_insn_reservation "atom_pop" 1
|
| 401 |
|
|
(and (eq_attr "cpu" "atom")
|
| 402 |
|
|
(and (eq_attr "type" "pop")
|
| 403 |
|
|
(eq_attr "mode" "DI")))
|
| 404 |
|
|
"atom-dual-1c")
|
| 405 |
|
|
|
| 406 |
|
|
;; pop non-r64 is 2 cycles. UCODE if segreg, ignored
|
| 407 |
|
|
(define_insn_reservation "atom_pop_2" 2
|
| 408 |
|
|
(and (eq_attr "cpu" "atom")
|
| 409 |
|
|
(and (eq_attr "type" "pop")
|
| 410 |
|
|
(eq_attr "mode" "!DI")))
|
| 411 |
|
|
"atom-dual-2c")
|
| 412 |
|
|
|
| 413 |
|
|
;; UCODE if segreg, ignored
|
| 414 |
|
|
(define_insn_reservation "atom_call" 1
|
| 415 |
|
|
(and (eq_attr "cpu" "atom")
|
| 416 |
|
|
(eq_attr "type" "call"))
|
| 417 |
|
|
"atom-dual-1c")
|
| 418 |
|
|
|
| 419 |
|
|
(define_insn_reservation "atom_callv" 1
|
| 420 |
|
|
(and (eq_attr "cpu" "atom")
|
| 421 |
|
|
(eq_attr "type" "callv"))
|
| 422 |
|
|
"atom-dual-1c")
|
| 423 |
|
|
|
| 424 |
|
|
(define_insn_reservation "atom_leave" 3
|
| 425 |
|
|
(and (eq_attr "cpu" "atom")
|
| 426 |
|
|
(eq_attr "type" "leave"))
|
| 427 |
|
|
"atom-complex, atom-all-eu*2")
|
| 428 |
|
|
|
| 429 |
|
|
(define_insn_reservation "atom_str" 3
|
| 430 |
|
|
(and (eq_attr "cpu" "atom")
|
| 431 |
|
|
(eq_attr "type" "str"))
|
| 432 |
|
|
"atom-complex, atom-all-eu*2")
|
| 433 |
|
|
|
| 434 |
|
|
(define_insn_reservation "atom_sselog" 1
|
| 435 |
|
|
(and (eq_attr "cpu" "atom")
|
| 436 |
|
|
(and (eq_attr "type" "sselog")
|
| 437 |
|
|
(eq_attr "memory" "none")))
|
| 438 |
|
|
"atom-simple-either")
|
| 439 |
|
|
|
| 440 |
|
|
(define_insn_reservation "atom_sselog_mem" 1
|
| 441 |
|
|
(and (eq_attr "cpu" "atom")
|
| 442 |
|
|
(and (eq_attr "type" "sselog")
|
| 443 |
|
|
(eq_attr "memory" "!none")))
|
| 444 |
|
|
"atom-simple-either")
|
| 445 |
|
|
|
| 446 |
|
|
(define_insn_reservation "atom_sselog1" 1
|
| 447 |
|
|
(and (eq_attr "cpu" "atom")
|
| 448 |
|
|
(and (eq_attr "type" "sselog1")
|
| 449 |
|
|
(eq_attr "memory" "none")))
|
| 450 |
|
|
"atom-simple-0")
|
| 451 |
|
|
|
| 452 |
|
|
(define_insn_reservation "atom_sselog1_mem" 1
|
| 453 |
|
|
(and (eq_attr "cpu" "atom")
|
| 454 |
|
|
(and (eq_attr "type" "sselog1")
|
| 455 |
|
|
(eq_attr "memory" "!none")))
|
| 456 |
|
|
"atom-simple-0")
|
| 457 |
|
|
|
| 458 |
|
|
;; not pmad, not psad
|
| 459 |
|
|
(define_insn_reservation "atom_sseiadd" 1
|
| 460 |
|
|
(and (eq_attr "cpu" "atom")
|
| 461 |
|
|
(and (eq_attr "type" "sseiadd")
|
| 462 |
|
|
(and (not (match_operand:V2DI 0 "register_operand"))
|
| 463 |
|
|
(and (eq_attr "atom_unit" "!simul")
|
| 464 |
|
|
(eq_attr "atom_unit" "!complex")))))
|
| 465 |
|
|
"atom-simple-either")
|
| 466 |
|
|
|
| 467 |
|
|
;; pmad, psad and 64
|
| 468 |
|
|
(define_insn_reservation "atom_sseiadd_2" 4
|
| 469 |
|
|
(and (eq_attr "cpu" "atom")
|
| 470 |
|
|
(and (eq_attr "type" "sseiadd")
|
| 471 |
|
|
(and (not (match_operand:V2DI 0 "register_operand"))
|
| 472 |
|
|
(and (eq_attr "atom_unit" "simul" )
|
| 473 |
|
|
(eq_attr "mode" "DI")))))
|
| 474 |
|
|
"atom-fmul-4c")
|
| 475 |
|
|
|
| 476 |
|
|
;; pmad, psad and 128
|
| 477 |
|
|
(define_insn_reservation "atom_sseiadd_3" 5
|
| 478 |
|
|
(and (eq_attr "cpu" "atom")
|
| 479 |
|
|
(and (eq_attr "type" "sseiadd")
|
| 480 |
|
|
(and (not (match_operand:V2DI 0 "register_operand"))
|
| 481 |
|
|
(and (eq_attr "atom_unit" "simul" )
|
| 482 |
|
|
(eq_attr "mode" "TI")))))
|
| 483 |
|
|
"atom-fmul-5c")
|
| 484 |
|
|
|
| 485 |
|
|
;; if paddq(64 bit op), phadd/phsub
|
| 486 |
|
|
(define_insn_reservation "atom_sseiadd_4" 6
|
| 487 |
|
|
(and (eq_attr "cpu" "atom")
|
| 488 |
|
|
(and (eq_attr "type" "sseiadd")
|
| 489 |
|
|
(ior (match_operand:V2DI 0 "register_operand")
|
| 490 |
|
|
(eq_attr "atom_unit" "complex"))))
|
| 491 |
|
|
"atom-complex, atom-all-eu*5")
|
| 492 |
|
|
|
| 493 |
|
|
;; if immediate op.
|
| 494 |
|
|
(define_insn_reservation "atom_sseishft" 1
|
| 495 |
|
|
(and (eq_attr "cpu" "atom")
|
| 496 |
|
|
(and (eq_attr "type" "sseishft")
|
| 497 |
|
|
(and (eq_attr "atom_unit" "!sishuf")
|
| 498 |
|
|
(match_operand 2 "immediate_operand"))))
|
| 499 |
|
|
"atom-simple-either")
|
| 500 |
|
|
|
| 501 |
|
|
;; if palignr or psrldq
|
| 502 |
|
|
(define_insn_reservation "atom_sseishft_2" 1
|
| 503 |
|
|
(and (eq_attr "cpu" "atom")
|
| 504 |
|
|
(ior (eq_attr "type" "sseishft1")
|
| 505 |
|
|
(and (eq_attr "type" "sseishft")
|
| 506 |
|
|
(and (eq_attr "atom_unit" "sishuf")
|
| 507 |
|
|
(match_operand 2 "immediate_operand")))))
|
| 508 |
|
|
"atom-simple-0")
|
| 509 |
|
|
|
| 510 |
|
|
;; if reg/mem op
|
| 511 |
|
|
(define_insn_reservation "atom_sseishft_3" 2
|
| 512 |
|
|
(and (eq_attr "cpu" "atom")
|
| 513 |
|
|
(and (eq_attr "type" "sseishft")
|
| 514 |
|
|
(not (match_operand 2 "immediate_operand"))))
|
| 515 |
|
|
"atom-complex, atom-all-eu")
|
| 516 |
|
|
|
| 517 |
|
|
(define_insn_reservation "atom_sseimul" 1
|
| 518 |
|
|
(and (eq_attr "cpu" "atom")
|
| 519 |
|
|
(eq_attr "type" "sseimul"))
|
| 520 |
|
|
"atom-simple-0")
|
| 521 |
|
|
|
| 522 |
|
|
;; rcpss or rsqrtss
|
| 523 |
|
|
(define_insn_reservation "atom_sse" 4
|
| 524 |
|
|
(and (eq_attr "cpu" "atom")
|
| 525 |
|
|
(and (eq_attr "type" "sse")
|
| 526 |
|
|
(and (eq_attr "atom_sse_attr" "rcp") (eq_attr "mode" "SF"))))
|
| 527 |
|
|
"atom-fmul-4c")
|
| 528 |
|
|
|
| 529 |
|
|
;; movshdup, movsldup. Suggest to type sseishft
|
| 530 |
|
|
(define_insn_reservation "atom_sse_2" 1
|
| 531 |
|
|
(and (eq_attr "cpu" "atom")
|
| 532 |
|
|
(and (eq_attr "type" "sse")
|
| 533 |
|
|
(eq_attr "atom_sse_attr" "movdup")))
|
| 534 |
|
|
"atom-simple-0")
|
| 535 |
|
|
|
| 536 |
|
|
;; lfence
|
| 537 |
|
|
(define_insn_reservation "atom_sse_3" 1
|
| 538 |
|
|
(and (eq_attr "cpu" "atom")
|
| 539 |
|
|
(and (eq_attr "type" "sse")
|
| 540 |
|
|
(eq_attr "atom_sse_attr" "lfence")))
|
| 541 |
|
|
"atom-simple-either")
|
| 542 |
|
|
|
| 543 |
|
|
;; sfence,clflush,mfence, prefetch
|
| 544 |
|
|
(define_insn_reservation "atom_sse_4" 1
|
| 545 |
|
|
(and (eq_attr "cpu" "atom")
|
| 546 |
|
|
(and (eq_attr "type" "sse")
|
| 547 |
|
|
(ior (eq_attr "atom_sse_attr" "fence")
|
| 548 |
|
|
(eq_attr "atom_sse_attr" "prefetch"))))
|
| 549 |
|
|
"atom-simple-0")
|
| 550 |
|
|
|
| 551 |
|
|
;; rcpps, rsqrtss, sqrt, ldmxcsr
|
| 552 |
|
|
(define_insn_reservation "atom_sse_5" 7
|
| 553 |
|
|
(and (eq_attr "cpu" "atom")
|
| 554 |
|
|
(and (eq_attr "type" "sse")
|
| 555 |
|
|
(ior (ior (eq_attr "atom_sse_attr" "sqrt")
|
| 556 |
|
|
(eq_attr "atom_sse_attr" "mxcsr"))
|
| 557 |
|
|
(and (eq_attr "atom_sse_attr" "rcp")
|
| 558 |
|
|
(eq_attr "mode" "V4SF")))))
|
| 559 |
|
|
"atom-complex, atom-all-eu*6")
|
| 560 |
|
|
|
| 561 |
|
|
;; xmm->xmm
|
| 562 |
|
|
(define_insn_reservation "atom_ssemov" 1
|
| 563 |
|
|
(and (eq_attr "cpu" "atom")
|
| 564 |
|
|
(and (eq_attr "type" "ssemov")
|
| 565 |
|
|
(and (match_operand 0 "register_operand" "xy") (match_operand 1 "register_operand" "xy"))))
|
| 566 |
|
|
"atom-simple-either")
|
| 567 |
|
|
|
| 568 |
|
|
;; reg->xmm
|
| 569 |
|
|
(define_insn_reservation "atom_ssemov_2" 1
|
| 570 |
|
|
(and (eq_attr "cpu" "atom")
|
| 571 |
|
|
(and (eq_attr "type" "ssemov")
|
| 572 |
|
|
(and (match_operand 0 "register_operand" "xy") (match_operand 1 "register_operand" "r"))))
|
| 573 |
|
|
"atom-simple-0")
|
| 574 |
|
|
|
| 575 |
|
|
;; xmm->reg
|
| 576 |
|
|
(define_insn_reservation "atom_ssemov_3" 3
|
| 577 |
|
|
(and (eq_attr "cpu" "atom")
|
| 578 |
|
|
(and (eq_attr "type" "ssemov")
|
| 579 |
|
|
(and (match_operand 0 "register_operand" "r") (match_operand 1 "register_operand" "xy"))))
|
| 580 |
|
|
"atom-eu-0-3-1")
|
| 581 |
|
|
|
| 582 |
|
|
;; mov mem
|
| 583 |
|
|
(define_insn_reservation "atom_ssemov_4" 1
|
| 584 |
|
|
(and (eq_attr "cpu" "atom")
|
| 585 |
|
|
(and (eq_attr "type" "ssemov")
|
| 586 |
|
|
(and (eq_attr "movu" "0") (eq_attr "memory" "!none"))))
|
| 587 |
|
|
"atom-simple-0")
|
| 588 |
|
|
|
| 589 |
|
|
;; movu mem
|
| 590 |
|
|
(define_insn_reservation "atom_ssemov_5" 2
|
| 591 |
|
|
(and (eq_attr "cpu" "atom")
|
| 592 |
|
|
(and (eq_attr "type" "ssemov")
|
| 593 |
|
|
(ior (eq_attr "movu" "1") (eq_attr "memory" "!none"))))
|
| 594 |
|
|
"atom-complex, atom-all-eu")
|
| 595 |
|
|
|
| 596 |
|
|
;; no memory simple
|
| 597 |
|
|
(define_insn_reservation "atom_sseadd" 5
|
| 598 |
|
|
(and (eq_attr "cpu" "atom")
|
| 599 |
|
|
(and (eq_attr "type" "sseadd")
|
| 600 |
|
|
(and (eq_attr "memory" "none")
|
| 601 |
|
|
(and (eq_attr "mode" "!V2DF")
|
| 602 |
|
|
(eq_attr "atom_unit" "!complex")))))
|
| 603 |
|
|
"atom-fadd-5c")
|
| 604 |
|
|
|
| 605 |
|
|
;; memory simple
|
| 606 |
|
|
(define_insn_reservation "atom_sseadd_mem" 5
|
| 607 |
|
|
(and (eq_attr "cpu" "atom")
|
| 608 |
|
|
(and (eq_attr "type" "sseadd")
|
| 609 |
|
|
(and (eq_attr "memory" "!none")
|
| 610 |
|
|
(and (eq_attr "mode" "!V2DF")
|
| 611 |
|
|
(eq_attr "atom_unit" "!complex")))))
|
| 612 |
|
|
"atom-dual-5c")
|
| 613 |
|
|
|
| 614 |
|
|
;; maxps, minps, *pd, hadd, hsub
|
| 615 |
|
|
(define_insn_reservation "atom_sseadd_3" 8
|
| 616 |
|
|
(and (eq_attr "cpu" "atom")
|
| 617 |
|
|
(and (eq_attr "type" "sseadd")
|
| 618 |
|
|
(ior (eq_attr "mode" "V2DF") (eq_attr "atom_unit" "complex"))))
|
| 619 |
|
|
"atom-complex, atom-all-eu*7")
|
| 620 |
|
|
|
| 621 |
|
|
;; Except dppd/dpps
|
| 622 |
|
|
(define_insn_reservation "atom_ssemul" 5
|
| 623 |
|
|
(and (eq_attr "cpu" "atom")
|
| 624 |
|
|
(and (eq_attr "type" "ssemul")
|
| 625 |
|
|
(eq_attr "mode" "!SF")))
|
| 626 |
|
|
"atom-fmul-5c")
|
| 627 |
|
|
|
| 628 |
|
|
;; Except dppd/dpps, 4 cycle if mulss
|
| 629 |
|
|
(define_insn_reservation "atom_ssemul_2" 4
|
| 630 |
|
|
(and (eq_attr "cpu" "atom")
|
| 631 |
|
|
(and (eq_attr "type" "ssemul")
|
| 632 |
|
|
(eq_attr "mode" "SF")))
|
| 633 |
|
|
"atom-fmul-4c")
|
| 634 |
|
|
|
| 635 |
|
|
(define_insn_reservation "atom_ssecmp" 1
|
| 636 |
|
|
(and (eq_attr "cpu" "atom")
|
| 637 |
|
|
(eq_attr "type" "ssecmp"))
|
| 638 |
|
|
"atom-simple-either")
|
| 639 |
|
|
|
| 640 |
|
|
(define_insn_reservation "atom_ssecomi" 10
|
| 641 |
|
|
(and (eq_attr "cpu" "atom")
|
| 642 |
|
|
(eq_attr "type" "ssecomi"))
|
| 643 |
|
|
"atom-complex, atom-all-eu*9")
|
| 644 |
|
|
|
| 645 |
|
|
;; no memory and cvtpi2ps, cvtps2pi, cvttps2pi
|
| 646 |
|
|
(define_insn_reservation "atom_ssecvt" 5
|
| 647 |
|
|
(and (eq_attr "cpu" "atom")
|
| 648 |
|
|
(and (eq_attr "type" "ssecvt")
|
| 649 |
|
|
(ior (and (match_operand:V2SI 0 "register_operand")
|
| 650 |
|
|
(match_operand:V4SF 1 "register_operand"))
|
| 651 |
|
|
(and (match_operand:V4SF 0 "register_operand")
|
| 652 |
|
|
(match_operand:V2SI 1 "register_operand")))))
|
| 653 |
|
|
"atom-fadd-5c")
|
| 654 |
|
|
|
| 655 |
|
|
;; memory and cvtpi2ps, cvtps2pi, cvttps2pi
|
| 656 |
|
|
(define_insn_reservation "atom_ssecvt_2" 5
|
| 657 |
|
|
(and (eq_attr "cpu" "atom")
|
| 658 |
|
|
(and (eq_attr "type" "ssecvt")
|
| 659 |
|
|
(ior (and (match_operand:V2SI 0 "register_operand")
|
| 660 |
|
|
(match_operand:V4SF 1 "memory_operand"))
|
| 661 |
|
|
(and (match_operand:V4SF 0 "register_operand")
|
| 662 |
|
|
(match_operand:V2SI 1 "memory_operand")))))
|
| 663 |
|
|
"atom-dual-5c")
|
| 664 |
|
|
|
| 665 |
|
|
;; otherwise. 7 cycles average for cvtss2sd
|
| 666 |
|
|
(define_insn_reservation "atom_ssecvt_3" 7
|
| 667 |
|
|
(and (eq_attr "cpu" "atom")
|
| 668 |
|
|
(and (eq_attr "type" "ssecvt")
|
| 669 |
|
|
(not (ior (and (match_operand:V2SI 0 "register_operand")
|
| 670 |
|
|
(match_operand:V4SF 1 "nonimmediate_operand"))
|
| 671 |
|
|
(and (match_operand:V4SF 0 "register_operand")
|
| 672 |
|
|
(match_operand:V2SI 1 "nonimmediate_operand"))))))
|
| 673 |
|
|
"atom-complex, atom-all-eu*6")
|
| 674 |
|
|
|
| 675 |
|
|
;; memory and cvtsi2sd
|
| 676 |
|
|
(define_insn_reservation "atom_sseicvt" 5
|
| 677 |
|
|
(and (eq_attr "cpu" "atom")
|
| 678 |
|
|
(and (eq_attr "type" "sseicvt")
|
| 679 |
|
|
(and (match_operand:V2DF 0 "register_operand")
|
| 680 |
|
|
(match_operand:SI 1 "memory_operand"))))
|
| 681 |
|
|
"atom-dual-5c")
|
| 682 |
|
|
|
| 683 |
|
|
;; otherwise. 8 cycles average for cvtsd2si
|
| 684 |
|
|
(define_insn_reservation "atom_sseicvt_2" 8
|
| 685 |
|
|
(and (eq_attr "cpu" "atom")
|
| 686 |
|
|
(and (eq_attr "type" "sseicvt")
|
| 687 |
|
|
(not (and (match_operand:V2DF 0 "register_operand")
|
| 688 |
|
|
(match_operand:SI 1 "memory_operand")))))
|
| 689 |
|
|
"atom-complex, atom-all-eu*7")
|
| 690 |
|
|
|
| 691 |
|
|
(define_insn_reservation "atom_ssediv" 62
|
| 692 |
|
|
(and (eq_attr "cpu" "atom")
|
| 693 |
|
|
(eq_attr "type" "ssediv"))
|
| 694 |
|
|
"atom-complex, atom-all-eu*12, nothing*49")
|
| 695 |
|
|
|
| 696 |
|
|
;; simple for fmov
|
| 697 |
|
|
(define_insn_reservation "atom_fmov" 1
|
| 698 |
|
|
(and (eq_attr "cpu" "atom")
|
| 699 |
|
|
(and (eq_attr "type" "fmov")
|
| 700 |
|
|
(eq_attr "memory" "none")))
|
| 701 |
|
|
"atom-simple-either")
|
| 702 |
|
|
|
| 703 |
|
|
;; simple for fmov
|
| 704 |
|
|
(define_insn_reservation "atom_fmov_mem" 1
|
| 705 |
|
|
(and (eq_attr "cpu" "atom")
|
| 706 |
|
|
(and (eq_attr "type" "fmov")
|
| 707 |
|
|
(eq_attr "memory" "!none")))
|
| 708 |
|
|
"atom-simple-either")
|
| 709 |
|
|
|
| 710 |
|
|
;; Define bypass here
|
| 711 |
|
|
|
| 712 |
|
|
;; There will be no stall from lea to non-mem EX insns
|
| 713 |
|
|
(define_bypass 0 "atom_lea"
|
| 714 |
|
|
"atom_alu_carry,
|
| 715 |
|
|
atom_alu,atom_alu1,atom_negnot,atom_imov,atom_imovx,
|
| 716 |
|
|
atom_incdec, atom_setcc, atom_icmov, atom_pop")
|
| 717 |
|
|
|
| 718 |
|
|
(define_bypass 0 "atom_lea"
|
| 719 |
|
|
"atom_alu_mem, atom_alu_carry_mem, atom_alu1_mem,
|
| 720 |
|
|
atom_imovx_mem, atom_imovx_2_mem,
|
| 721 |
|
|
atom_imov_mem, atom_icmov_mem, atom_fmov_mem"
|
| 722 |
|
|
"!ix86_agi_dependent")
|
| 723 |
|
|
|
| 724 |
|
|
;; There will be 3 cycles stall from EX insns to AGAN insns LEA
|
| 725 |
|
|
(define_bypass 4 "atom_alu_carry,
|
| 726 |
|
|
atom_alu,atom_alu1,atom_negnot,atom_imov,atom_imovx,
|
| 727 |
|
|
atom_incdec,atom_ishift,atom_ishift1,atom_rotate,
|
| 728 |
|
|
atom_rotate1, atom_setcc, atom_icmov, atom_pop,
|
| 729 |
|
|
atom_alu_mem, atom_alu_carry_mem, atom_alu1_mem,
|
| 730 |
|
|
atom_imovx_mem, atom_imovx_2_mem,
|
| 731 |
|
|
atom_imov_mem, atom_icmov_mem, atom_fmov_mem"
|
| 732 |
|
|
"atom_lea")
|
| 733 |
|
|
|
| 734 |
|
|
;; There will be 3 cycles stall from EX insns to insns need addr calculation
|
| 735 |
|
|
(define_bypass 4 "atom_alu_carry,
|
| 736 |
|
|
atom_alu,atom_alu1,atom_negnot,atom_imov,atom_imovx,
|
| 737 |
|
|
atom_incdec,atom_ishift,atom_ishift1,atom_rotate,
|
| 738 |
|
|
atom_rotate1, atom_setcc, atom_icmov, atom_pop,
|
| 739 |
|
|
atom_imovx_mem, atom_imovx_2_mem,
|
| 740 |
|
|
atom_alu_mem, atom_alu_carry_mem, atom_alu1_mem,
|
| 741 |
|
|
atom_imov_mem, atom_icmov_mem, atom_fmov_mem"
|
| 742 |
|
|
"atom_alu_mem, atom_alu_carry_mem, atom_alu1_mem,
|
| 743 |
|
|
atom_negnot_mem, atom_imov_mem, atom_incdec_mem,
|
| 744 |
|
|
atom_imovx_mem, atom_imovx_2_mem,
|
| 745 |
|
|
atom_imul_mem, atom_icmp_mem,
|
| 746 |
|
|
atom_test_mem, atom_icmov_mem, atom_sselog_mem,
|
| 747 |
|
|
atom_sselog1_mem, atom_fmov_mem, atom_sseadd_mem,
|
| 748 |
|
|
atom_ishift_mem, atom_ishift1_mem,
|
| 749 |
|
|
atom_rotate_mem, atom_rotate1_mem"
|
| 750 |
|
|
"ix86_agi_dependent")
|
| 751 |
|
|
|
| 752 |
|
|
;; Stall from imul to lea is 8 cycles.
|
| 753 |
|
|
(define_bypass 9 "atom_imul, atom_imul_mem" "atom_lea")
|
| 754 |
|
|
|
| 755 |
|
|
;; Stall from imul to memory address is 8 cycles.
|
| 756 |
|
|
(define_bypass 9 "atom_imul, atom_imul_mem"
|
| 757 |
|
|
"atom_alu_mem, atom_alu_carry_mem, atom_alu1_mem,
|
| 758 |
|
|
atom_negnot_mem, atom_imov_mem, atom_incdec_mem,
|
| 759 |
|
|
atom_ishift_mem, atom_ishift1_mem, atom_rotate_mem,
|
| 760 |
|
|
atom_rotate1_mem, atom_imul_mem, atom_icmp_mem,
|
| 761 |
|
|
atom_test_mem, atom_icmov_mem, atom_sselog_mem,
|
| 762 |
|
|
atom_sselog1_mem, atom_fmov_mem, atom_sseadd_mem"
|
| 763 |
|
|
"ix86_agi_dependent")
|
| 764 |
|
|
|
| 765 |
|
|
;; There will be 0 cycle stall from cmp/test to jcc
|
| 766 |
|
|
|
| 767 |
|
|
;; There will be 1 cycle stall from flag producer to cmov and adc/sbb
|
| 768 |
|
|
(define_bypass 2 "atom_icmp, atom_test, atom_alu, atom_alu_carry,
|
| 769 |
|
|
atom_alu1, atom_negnot, atom_incdec, atom_ishift,
|
| 770 |
|
|
atom_ishift1, atom_rotate, atom_rotate1"
|
| 771 |
|
|
"atom_icmov, atom_alu_carry")
|
| 772 |
|
|
|
| 773 |
|
|
;; lea to shift count stall is 2 cycles
|
| 774 |
|
|
(define_bypass 3 "atom_lea"
|
| 775 |
|
|
"atom_ishift, atom_ishift1, atom_rotate, atom_rotate1,
|
| 776 |
|
|
atom_ishift_mem, atom_ishift1_mem,
|
| 777 |
|
|
atom_rotate_mem, atom_rotate1_mem"
|
| 778 |
|
|
"ix86_dep_by_shift_count")
|
| 779 |
|
|
|
| 780 |
|
|
;; lea to shift source stall is 1 cycle
|
| 781 |
|
|
(define_bypass 2 "atom_lea"
|
| 782 |
|
|
"atom_ishift, atom_ishift1, atom_rotate, atom_rotate1"
|
| 783 |
|
|
"!ix86_dep_by_shift_count")
|
| 784 |
|
|
|
| 785 |
|
|
;; non-lea to shift count stall is 1 cycle
|
| 786 |
|
|
(define_bypass 2 "atom_alu_carry,
|
| 787 |
|
|
atom_alu,atom_alu1,atom_negnot,atom_imov,atom_imovx,
|
| 788 |
|
|
atom_incdec,atom_ishift,atom_ishift1,atom_rotate,
|
| 789 |
|
|
atom_rotate1, atom_setcc, atom_icmov, atom_pop,
|
| 790 |
|
|
atom_alu_mem, atom_alu_carry_mem, atom_alu1_mem,
|
| 791 |
|
|
atom_imovx_mem, atom_imovx_2_mem,
|
| 792 |
|
|
atom_imov_mem, atom_icmov_mem, atom_fmov_mem"
|
| 793 |
|
|
"atom_ishift, atom_ishift1, atom_rotate, atom_rotate1,
|
| 794 |
|
|
atom_ishift_mem, atom_ishift1_mem,
|
| 795 |
|
|
atom_rotate_mem, atom_rotate1_mem"
|
| 796 |
|
|
"ix86_dep_by_shift_count")
|
