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jeremybenn |
;; Copyright (C) 2010, Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; .
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;;
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;; AMD bdver1 Scheduling
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;;
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;; The bdver1 contains four pipelined FP units, two integer units and
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;; two address generation units.
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;;
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;; The predecode logic is determining boundaries of instructions in the 64
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;; byte cache line. So the cache line straddling problem of K6 might be issue
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;; here as well, but it is not noted in the documentation.
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;;
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;; Three DirectPath instructions decoders and only one VectorPath decoder
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;; is available. They can decode three DirectPath instructions or one
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;; VectorPath instruction per cycle.
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;;
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;; The load/store queue unit is not attached to the schedulers but
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;; communicates with all the execution units separately instead.
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(define_attr "bdver1_decode" "direct,vector,double"
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(const_string "direct"))
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(define_automaton "bdver1,bdver1_int,bdver1_load,bdver1_mult,bdver1_fp")
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(define_cpu_unit "bdver1-decode0" "bdver1")
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(define_cpu_unit "bdver1-decode1" "bdver1")
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(define_cpu_unit "bdver1-decode2" "bdver1")
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(define_cpu_unit "bdver1-decodev" "bdver1")
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;; Model the fact that double decoded instruction may take 2 cycles
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;; to decode when decoder2 and decoder0 in next cycle
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;; is used (this is needed to allow throughput of 1.5 double decoded
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;; instructions per cycle).
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;;
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;; In order to avoid dependence between reservation of decoder
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;; and other units, we model decoder as two stage fully pipelined unit
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;; and only double decoded instruction may occupy unit in the first cycle.
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;; With this scheme however two double instructions can be issued cycle0.
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;;
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;; Avoid this by using presence set requiring decoder0 to be allocated
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;; too. Vector decoded instructions then can't be issued when modeled
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;; as consuming decoder0+decoder1+decoder2.
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;; We solve that by specialized vector decoder unit and exclusion set.
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(presence_set "bdver1-decode2" "bdver1-decode0")
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(exclusion_set "bdver1-decodev" "bdver1-decode0,bdver1-decode1,bdver1-decode2")
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(define_reservation "bdver1-vector" "nothing,bdver1-decodev")
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(define_reservation "bdver1-direct1" "nothing,bdver1-decode1")
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(define_reservation "bdver1-direct" "nothing,
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(bdver1-decode0 | bdver1-decode1
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| bdver1-decode2)")
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;; Double instructions behaves like two direct instructions.
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(define_reservation "bdver1-double" "((bdver1-decode2,bdver1-decode0)
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| (nothing,(bdver1-decode0 + bdver1-decode1))
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| (nothing,(bdver1-decode1 + bdver1-decode2)))")
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(define_cpu_unit "bdver1-ieu0" "bdver1_int")
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(define_cpu_unit "bdver1-ieu1" "bdver1_int")
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(define_reservation "bdver1-ieu" "(bdver1-ieu0 | bdver1-ieu1)")
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(define_cpu_unit "bdver1-agu0" "bdver1_int")
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(define_cpu_unit "bdver1-agu1" "bdver1_int")
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(define_reservation "bdver1-agu" "(bdver1-agu0 | bdver1-agu1)")
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(define_cpu_unit "bdver1-mult" "bdver1_mult")
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(define_cpu_unit "bdver1-load0" "bdver1_load")
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(define_cpu_unit "bdver1-load1" "bdver1_load")
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(define_reservation "bdver1-load" "bdver1-agu,
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(bdver1-load0 | bdver1-load1),nothing")
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;; 128bit SSE instructions issue two loads at once.
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(define_reservation "bdver1-load2" "bdver1-agu,
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(bdver1-load0 + bdver1-load1),nothing")
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(define_reservation "bdver1-store" "(bdver1-load0 | bdver1-load1)")
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;; 128bit SSE instructions issue two stores at once.
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(define_reservation "bdver1-store2" "(bdver1-load0 + bdver1-load1)")
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;; The FP operations start to execute at stage 12 in the pipeline, while
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;; integer operations start to execute at stage 9 for athlon and 11 for K8
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;; Compensate the difference for athlon because it results in significantly
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;; smaller automata.
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;; NOTE: the above information was just copied from athlon.md, and was not
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;; actually verified for bdver1.
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(define_reservation "bdver1-fpsched" "nothing,nothing,nothing")
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;; The floating point loads.
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(define_reservation "bdver1-fpload" "(bdver1-fpsched + bdver1-load)")
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(define_reservation "bdver1-fpload2" "(bdver1-fpsched + bdver1-load2)")
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;; Four FP units.
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(define_cpu_unit "bdver1-ffma0" "bdver1_fp")
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(define_cpu_unit "bdver1-ffma1" "bdver1_fp")
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(define_cpu_unit "bdver1-fmal0" "bdver1_fp")
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(define_cpu_unit "bdver1-fmal1" "bdver1_fp")
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(define_reservation "bdver1-ffma" "(bdver1-ffma0 | bdver1-ffma1)")
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(define_reservation "bdver1-fcvt" "bdver1-ffma0")
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(define_reservation "bdver1-fmma" "bdver1-ffma0")
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(define_reservation "bdver1-fxbar" "bdver1-ffma1")
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(define_reservation "bdver1-fmal" "(bdver1-fmal0 | bdver1-fmal1)")
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(define_reservation "bdver1-fsto" "bdver1-fmal1")
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;; Vector operations usually consume many of pipes.
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(define_reservation "bdver1-fvector" "(bdver1-ffma0 + bdver1-ffma1
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+ bdver1-fmal0 + bdver1-fmal1)")
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;; Jump instructions are executed in the branch unit completely transparent to us.
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(define_insn_reservation "bdver1_call" 0
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(and (eq_attr "cpu" "bdver1,bdver2")
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(eq_attr "type" "call,callv"))
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"bdver1-double,bdver1-agu,bdver1-ieu")
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;; PUSH mem is double path.
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(define_insn_reservation "bdver1_push" 1
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(and (eq_attr "cpu" "bdver1,bdver2")
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(eq_attr "type" "push"))
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"bdver1-direct,bdver1-agu,bdver1-store")
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;; POP r16/mem are double path.
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(define_insn_reservation "bdver1_pop" 1
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(and (eq_attr "cpu" "bdver1,bdver2")
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(eq_attr "type" "pop"))
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"bdver1-direct,(bdver1-ieu+bdver1-load)")
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;; LEAVE no latency info so far, assume same with amdfam10.
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(define_insn_reservation "bdver1_leave" 3
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(and (eq_attr "cpu" "bdver1,bdver2")
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(eq_attr "type" "leave"))
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"bdver1-vector,(bdver1-ieu+bdver1-load)")
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;; LEA executes in AGU unit with 1 cycle latency on BDVER1.
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(define_insn_reservation "bdver1_lea" 1
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(and (eq_attr "cpu" "bdver1,bdver2")
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(eq_attr "type" "lea"))
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"bdver1-direct,bdver1-agu,nothing")
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;; MUL executes in special multiplier unit attached to IEU1.
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(define_insn_reservation "bdver1_imul_DI" 6
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(and (eq_attr "cpu" "bdver1,bdver2")
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(and (eq_attr "type" "imul")
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(and (eq_attr "mode" "DI")
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(eq_attr "memory" "none,unknown"))))
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"bdver1-direct1,bdver1-ieu1,bdver1-mult,nothing,bdver1-ieu1")
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(define_insn_reservation "bdver1_imul" 4
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(and (eq_attr "cpu" "bdver1,bdver2")
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(and (eq_attr "type" "imul")
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(eq_attr "memory" "none,unknown")))
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"bdver1-direct1,bdver1-ieu1,bdver1-mult,bdver1-ieu1")
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(define_insn_reservation "bdver1_imul_mem_DI" 10
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(and (eq_attr "cpu" "bdver1,bdver2")
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(and (eq_attr "type" "imul")
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(and (eq_attr "mode" "DI")
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(eq_attr "memory" "load,both"))))
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"bdver1-direct1,bdver1-load,bdver1-ieu,bdver1-mult,nothing,bdver1-ieu")
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(define_insn_reservation "bdver1_imul_mem" 8
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(and (eq_attr "cpu" "bdver1,bdver2")
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(and (eq_attr "type" "imul")
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(eq_attr "memory" "load,both")))
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"bdver1-direct1,bdver1-load,bdver1-ieu,bdver1-mult,bdver1-ieu")
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;; IDIV cannot execute in parallel with other instructions. Dealing with it
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;; as with short latency vector instruction is good approximation avoiding
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;; scheduler from trying too hard to can hide it's latency by overlap with
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;; other instructions.
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;; ??? Experiments show that the IDIV can overlap with roughly 6 cycles
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;; of the other code.
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(define_insn_reservation "bdver1_idiv" 6
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(and (eq_attr "cpu" "bdver1,bdver2")
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(and (eq_attr "type" "idiv")
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(eq_attr "memory" "none,unknown")))
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"bdver1-vector,(bdver1-ieu0*6+(bdver1-fpsched,bdver1-fvector))")
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(define_insn_reservation "bdver1_idiv_mem" 10
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(and (eq_attr "cpu" "bdver1,bdver2")
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(and (eq_attr "type" "idiv")
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(eq_attr "memory" "load,both")))
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"bdver1-vector,((bdver1-load,bdver1-ieu0*6)+(bdver1-fpsched,bdver1-fvector))")
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;; The parallelism of string instructions is not documented. Model it same way
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;; as IDIV to create smaller automata. This probably does not matter much.
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;; Using the same heuristics for bdver1 as amdfam10 and K8 with IDIV.
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(define_insn_reservation "bdver1_str" 6
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(and (eq_attr "cpu" "bdver1,bdver2")
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(and (eq_attr "type" "str")
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(eq_attr "memory" "load,both,store")))
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"bdver1-vector,bdver1-load,bdver1-ieu0*6")
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;; Integer instructions.
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(define_insn_reservation "bdver1_idirect" 1
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(and (eq_attr "cpu" "bdver1,bdver2")
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(and (eq_attr "bdver1_decode" "direct")
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(and (eq_attr "unit" "integer,unknown")
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(eq_attr "memory" "none,unknown"))))
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"bdver1-direct,bdver1-ieu")
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(define_insn_reservation "bdver1_ivector" 2
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(and (eq_attr "cpu" "bdver1,bdver2")
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(and (eq_attr "bdver1_decode" "vector")
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(and (eq_attr "unit" "integer,unknown")
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(eq_attr "memory" "none,unknown"))))
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"bdver1-vector,bdver1-ieu,bdver1-ieu")
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(define_insn_reservation "bdver1_idirect_loadmov" 4
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(and (eq_attr "cpu" "bdver1,bdver2")
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(and (eq_attr "type" "imov")
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(eq_attr "memory" "load")))
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"bdver1-direct,bdver1-load")
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(define_insn_reservation "bdver1_idirect_load" 5
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(and (eq_attr "cpu" "bdver1,bdver2")
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(and (eq_attr "bdver1_decode" "direct")
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(and (eq_attr "unit" "integer,unknown")
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(eq_attr "memory" "load"))))
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"bdver1-direct,bdver1-load,bdver1-ieu")
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(define_insn_reservation "bdver1_ivector_load" 6
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(and (eq_attr "cpu" "bdver1,bdver2")
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(and (eq_attr "bdver1_decode" "vector")
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(and (eq_attr "unit" "integer,unknown")
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(eq_attr "memory" "load"))))
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"bdver1-vector,bdver1-load,bdver1-ieu,bdver1-ieu")
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(define_insn_reservation "bdver1_idirect_movstore" 4
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(and (eq_attr "cpu" "bdver1,bdver2")
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(and (eq_attr "type" "imov")
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(eq_attr "memory" "store")))
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"bdver1-direct,bdver1-agu,bdver1-store")
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(define_insn_reservation "bdver1_idirect_both" 4
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(and (eq_attr "cpu" "bdver1,bdver2")
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(and (eq_attr "bdver1_decode" "direct")
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(and (eq_attr "unit" "integer,unknown")
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(eq_attr "memory" "both"))))
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"bdver1-direct,bdver1-load,
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bdver1-ieu,bdver1-store,
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bdver1-store")
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(define_insn_reservation "bdver1_ivector_both" 5
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(and (eq_attr "cpu" "bdver1,bdver2")
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(and (eq_attr "bdver1_decode" "vector")
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(and (eq_attr "unit" "integer,unknown")
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(eq_attr "memory" "both"))))
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"bdver1-vector,bdver1-load,
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bdver1-ieu,
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bdver1-ieu,
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bdver1-store")
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(define_insn_reservation "bdver1_idirect_store" 4
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(and (eq_attr "cpu" "bdver1,bdver2")
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(and (eq_attr "bdver1_decode" "direct")
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(and (eq_attr "unit" "integer,unknown")
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(eq_attr "memory" "store"))))
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"bdver1-direct,(bdver1-ieu+bdver1-agu),
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bdver1-store")
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(define_insn_reservation "bdver1_ivector_store" 5
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(and (eq_attr "cpu" "bdver1,bdver2")
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(and (eq_attr "bdver1_decode" "vector")
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(and (eq_attr "unit" "integer,unknown")
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(eq_attr "memory" "store"))))
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"bdver1-vector,(bdver1-ieu+bdver1-agu),bdver1-ieu,
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bdver1-store")
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;; BDVER1 floating point units.
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(define_insn_reservation "bdver1_fldxf" 13
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(and (eq_attr "cpu" "bdver1,bdver2")
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(and (eq_attr "type" "fmov")
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(and (eq_attr "memory" "load")
|
| 273 |
|
|
(eq_attr "mode" "XF"))))
|
| 274 |
|
|
"bdver1-vector,bdver1-fpload2,bdver1-fvector*9")
|
| 275 |
|
|
(define_insn_reservation "bdver1_fld" 5
|
| 276 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 277 |
|
|
(and (eq_attr "type" "fmov")
|
| 278 |
|
|
(eq_attr "memory" "load")))
|
| 279 |
|
|
"bdver1-direct,bdver1-fpload,bdver1-ffma")
|
| 280 |
|
|
(define_insn_reservation "bdver1_fstxf" 8
|
| 281 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 282 |
|
|
(and (eq_attr "type" "fmov")
|
| 283 |
|
|
(and (eq_attr "memory" "store,both")
|
| 284 |
|
|
(eq_attr "mode" "XF"))))
|
| 285 |
|
|
"bdver1-vector,(bdver1-fpsched+bdver1-agu),(bdver1-store2+(bdver1-fvector*6))")
|
| 286 |
|
|
(define_insn_reservation "bdver1_fst" 2
|
| 287 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 288 |
|
|
(and (eq_attr "type" "fmov")
|
| 289 |
|
|
(eq_attr "memory" "store,both")))
|
| 290 |
|
|
"bdver1-double,(bdver1-fpsched+bdver1-agu),(bdver1-fsto+bdver1-store)")
|
| 291 |
|
|
(define_insn_reservation "bdver1_fist" 2
|
| 292 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 293 |
|
|
(eq_attr "type" "fistp,fisttp"))
|
| 294 |
|
|
"bdver1-double,(bdver1-fpsched+bdver1-agu),(bdver1-fsto+bdver1-store)")
|
| 295 |
|
|
(define_insn_reservation "bdver1_fmov_bdver1" 2
|
| 296 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 297 |
|
|
(eq_attr "type" "fmov"))
|
| 298 |
|
|
"bdver1-direct,bdver1-fpsched,bdver1-ffma")
|
| 299 |
|
|
(define_insn_reservation "bdver1_fadd_load" 10
|
| 300 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 301 |
|
|
(and (eq_attr "type" "fop")
|
| 302 |
|
|
(eq_attr "memory" "load")))
|
| 303 |
|
|
"bdver1-direct,bdver1-fpload,bdver1-ffma")
|
| 304 |
|
|
(define_insn_reservation "bdver1_fadd" 6
|
| 305 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 306 |
|
|
(eq_attr "type" "fop"))
|
| 307 |
|
|
"bdver1-direct,bdver1-fpsched,bdver1-ffma")
|
| 308 |
|
|
(define_insn_reservation "bdver1_fmul_load" 10
|
| 309 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 310 |
|
|
(and (eq_attr "type" "fmul")
|
| 311 |
|
|
(eq_attr "memory" "load")))
|
| 312 |
|
|
"bdver1-double,bdver1-fpload,bdver1-ffma")
|
| 313 |
|
|
(define_insn_reservation "bdver1_fmul" 6
|
| 314 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 315 |
|
|
(eq_attr "type" "fmul"))
|
| 316 |
|
|
"bdver1-direct,bdver1-fpsched,bdver1-ffma")
|
| 317 |
|
|
(define_insn_reservation "bdver1_fsgn" 2
|
| 318 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 319 |
|
|
(eq_attr "type" "fsgn"))
|
| 320 |
|
|
"bdver1-direct,bdver1-fpsched,bdver1-ffma")
|
| 321 |
|
|
(define_insn_reservation "bdver1_fdiv_load" 46
|
| 322 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 323 |
|
|
(and (eq_attr "type" "fdiv")
|
| 324 |
|
|
(eq_attr "memory" "load")))
|
| 325 |
|
|
"bdver1-direct,bdver1-fpload,bdver1-ffma")
|
| 326 |
|
|
(define_insn_reservation "bdver1_fdiv" 42
|
| 327 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 328 |
|
|
(eq_attr "type" "fdiv"))
|
| 329 |
|
|
"bdver1-direct,bdver1-fpsched,bdver1-ffma")
|
| 330 |
|
|
(define_insn_reservation "bdver1_fpspc_load" 103
|
| 331 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 332 |
|
|
(and (eq_attr "type" "fpspc")
|
| 333 |
|
|
(eq_attr "memory" "load")))
|
| 334 |
|
|
"bdver1-vector,bdver1-fpload,bdver1-fvector")
|
| 335 |
|
|
(define_insn_reservation "bdver1_fpspc" 100
|
| 336 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 337 |
|
|
(and (eq_attr "type" "fpspc")
|
| 338 |
|
|
(eq_attr "memory" "load")))
|
| 339 |
|
|
"bdver1-vector,bdver1-fpload,bdver1-fvector")
|
| 340 |
|
|
(define_insn_reservation "bdver1_fcmov_load" 17
|
| 341 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 342 |
|
|
(and (eq_attr "type" "fcmov")
|
| 343 |
|
|
(eq_attr "memory" "load")))
|
| 344 |
|
|
"bdver1-vector,bdver1-fpload,bdver1-fvector")
|
| 345 |
|
|
(define_insn_reservation "bdver1_fcmov" 15
|
| 346 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 347 |
|
|
(eq_attr "type" "fcmov"))
|
| 348 |
|
|
"bdver1-vector,bdver1-fpsched,bdver1-fvector")
|
| 349 |
|
|
(define_insn_reservation "bdver1_fcomi_load" 6
|
| 350 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 351 |
|
|
(and (eq_attr "type" "fcmp")
|
| 352 |
|
|
(and (eq_attr "bdver1_decode" "double")
|
| 353 |
|
|
(eq_attr "memory" "load"))))
|
| 354 |
|
|
"bdver1-double,bdver1-fpload,(bdver1-ffma | bdver1-fsto)")
|
| 355 |
|
|
(define_insn_reservation "bdver1_fcomi" 2
|
| 356 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 357 |
|
|
(and (eq_attr "bdver1_decode" "double")
|
| 358 |
|
|
(eq_attr "type" "fcmp")))
|
| 359 |
|
|
"bdver1-double,bdver1-fpsched,(bdver1-ffma | bdver1-fsto)")
|
| 360 |
|
|
(define_insn_reservation "bdver1_fcom_load" 6
|
| 361 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 362 |
|
|
(and (eq_attr "type" "fcmp")
|
| 363 |
|
|
(eq_attr "memory" "load")))
|
| 364 |
|
|
"bdver1-direct,bdver1-fpload,bdver1-ffma")
|
| 365 |
|
|
(define_insn_reservation "bdver1_fcom" 2
|
| 366 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 367 |
|
|
(eq_attr "type" "fcmp"))
|
| 368 |
|
|
"bdver1-direct,bdver1-fpsched,bdver1-ffma")
|
| 369 |
|
|
(define_insn_reservation "bdver1_fxch" 2
|
| 370 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 371 |
|
|
(eq_attr "type" "fxch"))
|
| 372 |
|
|
"bdver1-direct,bdver1-fpsched,bdver1-ffma")
|
| 373 |
|
|
|
| 374 |
|
|
;; SSE loads.
|
| 375 |
|
|
(define_insn_reservation "bdver1_ssevector_avx128_unaligned_load" 4
|
| 376 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 377 |
|
|
(and (eq_attr "type" "ssemov")
|
| 378 |
|
|
(and (eq_attr "prefix" "vex")
|
| 379 |
|
|
(and (eq_attr "movu" "1")
|
| 380 |
|
|
(and (eq_attr "mode" "V4SF,V2DF")
|
| 381 |
|
|
(eq_attr "memory" "load"))))))
|
| 382 |
|
|
"bdver1-direct,bdver1-fpload")
|
| 383 |
|
|
(define_insn_reservation "bdver1_ssevector_avx256_unaligned_load" 5
|
| 384 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 385 |
|
|
(and (eq_attr "type" "ssemov")
|
| 386 |
|
|
(and (eq_attr "movu" "1")
|
| 387 |
|
|
(and (eq_attr "mode" "V8SF,V4DF")
|
| 388 |
|
|
(eq_attr "memory" "load")))))
|
| 389 |
|
|
"bdver1-double,bdver1-fpload")
|
| 390 |
|
|
(define_insn_reservation "bdver1_ssevector_sse128_unaligned_load" 4
|
| 391 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 392 |
|
|
(and (eq_attr "type" "ssemov")
|
| 393 |
|
|
(and (eq_attr "movu" "1")
|
| 394 |
|
|
(and (eq_attr "mode" "V4SF,V2DF")
|
| 395 |
|
|
(eq_attr "memory" "load")))))
|
| 396 |
|
|
"bdver1-direct,bdver1-fpload,bdver1-fmal")
|
| 397 |
|
|
(define_insn_reservation "bdver1_ssevector_avx128_load" 4
|
| 398 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 399 |
|
|
(and (eq_attr "type" "ssemov")
|
| 400 |
|
|
(and (eq_attr "prefix" "vex")
|
| 401 |
|
|
(and (eq_attr "mode" "V4SF,V2DF,TI")
|
| 402 |
|
|
(eq_attr "memory" "load")))))
|
| 403 |
|
|
"bdver1-direct,bdver1-fpload,bdver1-fmal")
|
| 404 |
|
|
(define_insn_reservation "bdver1_ssevector_avx256_load" 5
|
| 405 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 406 |
|
|
(and (eq_attr "type" "ssemov")
|
| 407 |
|
|
(and (eq_attr "mode" "V8SF,V4DF,OI")
|
| 408 |
|
|
(eq_attr "memory" "load"))))
|
| 409 |
|
|
"bdver1-double,bdver1-fpload,bdver1-fmal")
|
| 410 |
|
|
(define_insn_reservation "bdver1_ssevector_sse128_load" 4
|
| 411 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 412 |
|
|
(and (eq_attr "type" "ssemov")
|
| 413 |
|
|
(and (eq_attr "mode" "V4SF,V2DF,TI")
|
| 414 |
|
|
(eq_attr "memory" "load"))))
|
| 415 |
|
|
"bdver1-direct,bdver1-fpload")
|
| 416 |
|
|
(define_insn_reservation "bdver1_ssescalar_movq_load" 4
|
| 417 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 418 |
|
|
(and (eq_attr "type" "ssemov")
|
| 419 |
|
|
(and (eq_attr "mode" "DI")
|
| 420 |
|
|
(eq_attr "memory" "load"))))
|
| 421 |
|
|
"bdver1-direct,bdver1-fpload,bdver1-fmal")
|
| 422 |
|
|
(define_insn_reservation "bdver1_ssescalar_vmovss_load" 4
|
| 423 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 424 |
|
|
(and (eq_attr "type" "ssemov")
|
| 425 |
|
|
(and (eq_attr "prefix" "vex")
|
| 426 |
|
|
(and (eq_attr "mode" "SF")
|
| 427 |
|
|
(eq_attr "memory" "load")))))
|
| 428 |
|
|
"bdver1-direct,bdver1-fpload")
|
| 429 |
|
|
(define_insn_reservation "bdver1_ssescalar_sse128_load" 4
|
| 430 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 431 |
|
|
(and (eq_attr "type" "ssemov")
|
| 432 |
|
|
(and (eq_attr "mode" "SF,DF")
|
| 433 |
|
|
(eq_attr "memory" "load"))))
|
| 434 |
|
|
"bdver1-direct,bdver1-fpload, bdver1-ffma")
|
| 435 |
|
|
(define_insn_reservation "bdver1_mmxsse_load" 4
|
| 436 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 437 |
|
|
(and (eq_attr "type" "mmxmov,ssemov")
|
| 438 |
|
|
(eq_attr "memory" "load")))
|
| 439 |
|
|
"bdver1-direct,bdver1-fpload, bdver1-fmal")
|
| 440 |
|
|
|
| 441 |
|
|
;; SSE stores.
|
| 442 |
|
|
(define_insn_reservation "bdver1_sse_store_avx256" 5
|
| 443 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 444 |
|
|
(and (eq_attr "type" "ssemov")
|
| 445 |
|
|
(and (eq_attr "mode" "V8SF,V4DF,OI")
|
| 446 |
|
|
(eq_attr "memory" "store,both"))))
|
| 447 |
|
|
"bdver1-double,(bdver1-fpsched+bdver1-agu),((bdver1-fsto+bdver1-store)*2)")
|
| 448 |
|
|
(define_insn_reservation "bdver1_sse_store" 4
|
| 449 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 450 |
|
|
(and (eq_attr "type" "ssemov")
|
| 451 |
|
|
(and (eq_attr "mode" "V4SF,V2DF,TI")
|
| 452 |
|
|
(eq_attr "memory" "store,both"))))
|
| 453 |
|
|
"bdver1-direct,(bdver1-fpsched+bdver1-agu),((bdver1-fsto+bdver1-store)*2)")
|
| 454 |
|
|
(define_insn_reservation "bdver1_mmxsse_store_short" 4
|
| 455 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 456 |
|
|
(and (eq_attr "type" "mmxmov,ssemov")
|
| 457 |
|
|
(eq_attr "memory" "store,both")))
|
| 458 |
|
|
"bdver1-direct,(bdver1-fpsched+bdver1-agu),(bdver1-fsto+bdver1-store)")
|
| 459 |
|
|
|
| 460 |
|
|
;; Register moves.
|
| 461 |
|
|
(define_insn_reservation "bdver1_ssevector_avx256" 3
|
| 462 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 463 |
|
|
(and (eq_attr "type" "ssemov")
|
| 464 |
|
|
(and (eq_attr "mode" "V8SF,V4DF,OI")
|
| 465 |
|
|
(eq_attr "memory" "none"))))
|
| 466 |
|
|
"bdver1-double,bdver1-fpsched,bdver1-fmal")
|
| 467 |
|
|
(define_insn_reservation "bdver1_movss_movsd" 2
|
| 468 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 469 |
|
|
(and (eq_attr "type" "ssemov")
|
| 470 |
|
|
(and (eq_attr "mode" "SF,DF")
|
| 471 |
|
|
(eq_attr "memory" "none"))))
|
| 472 |
|
|
"bdver1-direct,bdver1-fpsched,bdver1-ffma")
|
| 473 |
|
|
(define_insn_reservation "bdver1_mmxssemov" 2
|
| 474 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 475 |
|
|
(and (eq_attr "type" "mmxmov,ssemov")
|
| 476 |
|
|
(eq_attr "memory" "none")))
|
| 477 |
|
|
"bdver1-direct,bdver1-fpsched,bdver1-fmal")
|
| 478 |
|
|
;; SSE logs.
|
| 479 |
|
|
(define_insn_reservation "bdver1_sselog_load_256" 7
|
| 480 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 481 |
|
|
(and (eq_attr "type" "sselog,sselog1")
|
| 482 |
|
|
(and (eq_attr "mode" "V8SF")
|
| 483 |
|
|
(eq_attr "memory" "load"))))
|
| 484 |
|
|
"bdver1-double,bdver1-fpload,bdver1-fmal")
|
| 485 |
|
|
(define_insn_reservation "bdver1_sselog_256" 3
|
| 486 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 487 |
|
|
(and (eq_attr "type" "sselog,sselog1")
|
| 488 |
|
|
(eq_attr "mode" "V8SF")))
|
| 489 |
|
|
"bdver1-double,bdver1-fpsched,bdver1-fmal")
|
| 490 |
|
|
(define_insn_reservation "bdver1_sselog_load" 6
|
| 491 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 492 |
|
|
(and (eq_attr "type" "sselog,sselog1")
|
| 493 |
|
|
(eq_attr "memory" "load")))
|
| 494 |
|
|
"bdver1-direct,bdver1-fpload,bdver1-fxbar")
|
| 495 |
|
|
(define_insn_reservation "bdver1_sselog" 2
|
| 496 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 497 |
|
|
(eq_attr "type" "sselog,sselog1"))
|
| 498 |
|
|
"bdver1-direct,bdver1-fpsched,bdver1-fxbar")
|
| 499 |
|
|
|
| 500 |
|
|
;; PCMP actually executes in FMAL.
|
| 501 |
|
|
(define_insn_reservation "bdver1_ssecmp_load" 6
|
| 502 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 503 |
|
|
(and (eq_attr "type" "ssecmp")
|
| 504 |
|
|
(eq_attr "memory" "load")))
|
| 505 |
|
|
"bdver1-direct,bdver1-fpload,bdver1-ffma")
|
| 506 |
|
|
(define_insn_reservation "bdver1_ssecmp" 2
|
| 507 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 508 |
|
|
(eq_attr "type" "ssecmp"))
|
| 509 |
|
|
"bdver1-direct,bdver1-fpsched,bdver1-ffma")
|
| 510 |
|
|
(define_insn_reservation "bdver1_ssecomi_load" 6
|
| 511 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 512 |
|
|
(and (eq_attr "type" "ssecomi")
|
| 513 |
|
|
(eq_attr "memory" "load")))
|
| 514 |
|
|
"bdver1-double,bdver1-fpload,(bdver1-ffma | bdver1-fsto)")
|
| 515 |
|
|
(define_insn_reservation "bdver1_ssecomi" 2
|
| 516 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 517 |
|
|
(eq_attr "type" "ssecomi"))
|
| 518 |
|
|
"bdver1-double,bdver1-fpsched,(bdver1-ffma | bdver1-fsto)")
|
| 519 |
|
|
|
| 520 |
|
|
;; Conversions behaves very irregularly and the scheduling is critical here.
|
| 521 |
|
|
;; Take each instruction separately.
|
| 522 |
|
|
|
| 523 |
|
|
;; 256 bit conversion.
|
| 524 |
|
|
(define_insn_reservation "bdver1_vcvtX2Y_avx256_load" 8
|
| 525 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 526 |
|
|
(and (eq_attr "type" "ssecvt")
|
| 527 |
|
|
(and (eq_attr "memory" "load")
|
| 528 |
|
|
(ior (ior (match_operand:V4DF 0 "register_operand")
|
| 529 |
|
|
(ior (match_operand:V8SF 0 "register_operand")
|
| 530 |
|
|
(match_operand:V8SI 0 "register_operand")))
|
| 531 |
|
|
(ior (match_operand:V4DF 1 "nonimmediate_operand")
|
| 532 |
|
|
(ior (match_operand:V8SF 1 "nonimmediate_operand")
|
| 533 |
|
|
(match_operand:V8SI 1 "nonimmediate_operand")))))))
|
| 534 |
|
|
"bdver1-vector,bdver1-fpload,bdver1-fvector")
|
| 535 |
|
|
(define_insn_reservation "bdver1_vcvtX2Y_avx256" 4
|
| 536 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 537 |
|
|
(and (eq_attr "type" "ssecvt")
|
| 538 |
|
|
(and (eq_attr "memory" "none")
|
| 539 |
|
|
(ior (ior (match_operand:V4DF 0 "register_operand")
|
| 540 |
|
|
(ior (match_operand:V8SF 0 "register_operand")
|
| 541 |
|
|
(match_operand:V8SI 0 "register_operand")))
|
| 542 |
|
|
(ior (match_operand:V4DF 1 "nonimmediate_operand")
|
| 543 |
|
|
(ior (match_operand:V8SF 1 "nonimmediate_operand")
|
| 544 |
|
|
(match_operand:V8SI 1 "nonimmediate_operand")))))))
|
| 545 |
|
|
"bdver1-vector,bdver1-fpsched,bdver1-fvector")
|
| 546 |
|
|
;; CVTSS2SD, CVTSD2SS.
|
| 547 |
|
|
(define_insn_reservation "bdver1_ssecvt_cvtss2sd_load" 8
|
| 548 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 549 |
|
|
(and (eq_attr "type" "ssecvt")
|
| 550 |
|
|
(and (eq_attr "mode" "SF,DF")
|
| 551 |
|
|
(eq_attr "memory" "load"))))
|
| 552 |
|
|
"bdver1-direct,bdver1-fpload,bdver1-fcvt")
|
| 553 |
|
|
(define_insn_reservation "bdver1_ssecvt_cvtss2sd" 4
|
| 554 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 555 |
|
|
(and (eq_attr "type" "ssecvt")
|
| 556 |
|
|
(and (eq_attr "mode" "SF,DF")
|
| 557 |
|
|
(eq_attr "memory" "none"))))
|
| 558 |
|
|
"bdver1-direct,bdver1-fpsched,bdver1-fcvt")
|
| 559 |
|
|
;; CVTSI2SD, CVTSI2SS, CVTSI2SDQ, CVTSI2SSQ.
|
| 560 |
|
|
(define_insn_reservation "bdver1_sseicvt_cvtsi2sd_load" 8
|
| 561 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 562 |
|
|
(and (eq_attr "type" "sseicvt")
|
| 563 |
|
|
(and (eq_attr "mode" "SF,DF")
|
| 564 |
|
|
(eq_attr "memory" "load"))))
|
| 565 |
|
|
"bdver1-direct,bdver1-fpload,bdver1-fcvt")
|
| 566 |
|
|
(define_insn_reservation "bdver1_sseicvt_cvtsi2sd" 4
|
| 567 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 568 |
|
|
(and (eq_attr "type" "sseicvt")
|
| 569 |
|
|
(and (eq_attr "mode" "SF,DF")
|
| 570 |
|
|
(eq_attr "memory" "none"))))
|
| 571 |
|
|
"bdver1-double,bdver1-fpsched,(nothing | bdver1-fcvt)")
|
| 572 |
|
|
;; CVTPD2PS.
|
| 573 |
|
|
(define_insn_reservation "bdver1_ssecvt_cvtpd2ps_load" 8
|
| 574 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 575 |
|
|
(and (eq_attr "type" "ssecvt")
|
| 576 |
|
|
(and (eq_attr "memory" "load")
|
| 577 |
|
|
(and (match_operand:V4SF 0 "register_operand")
|
| 578 |
|
|
(match_operand:V2DF 1 "nonimmediate_operand")))))
|
| 579 |
|
|
"bdver1-double,bdver1-fpload,(bdver1-fxbar | bdver1-fcvt)")
|
| 580 |
|
|
(define_insn_reservation "bdver1_ssecvt_cvtpd2ps" 4
|
| 581 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 582 |
|
|
(and (eq_attr "type" "ssecvt")
|
| 583 |
|
|
(and (eq_attr "memory" "none")
|
| 584 |
|
|
(and (match_operand:V4SF 0 "register_operand")
|
| 585 |
|
|
(match_operand:V2DF 1 "nonimmediate_operand")))))
|
| 586 |
|
|
"bdver1-double,bdver1-fpsched,(bdver1-fxbar | bdver1-fcvt)")
|
| 587 |
|
|
;; CVTPI2PS, CVTDQ2PS.
|
| 588 |
|
|
(define_insn_reservation "bdver1_ssecvt_cvtdq2ps_load" 8
|
| 589 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 590 |
|
|
(and (eq_attr "type" "ssecvt")
|
| 591 |
|
|
(and (eq_attr "memory" "load")
|
| 592 |
|
|
(and (match_operand:V4SF 0 "register_operand")
|
| 593 |
|
|
(ior (match_operand:V2SI 1 "nonimmediate_operand")
|
| 594 |
|
|
(match_operand:V4SI 1 "nonimmediate_operand"))))))
|
| 595 |
|
|
"bdver1-direct,bdver1-fpload,bdver1-fcvt")
|
| 596 |
|
|
(define_insn_reservation "bdver1_ssecvt_cvtdq2ps" 4
|
| 597 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 598 |
|
|
(and (eq_attr "type" "ssecvt")
|
| 599 |
|
|
(and (eq_attr "memory" "none")
|
| 600 |
|
|
(and (match_operand:V4SF 0 "register_operand")
|
| 601 |
|
|
(ior (match_operand:V2SI 1 "nonimmediate_operand")
|
| 602 |
|
|
(match_operand:V4SI 1 "nonimmediate_operand"))))))
|
| 603 |
|
|
"bdver1-direct,bdver1-fpsched,bdver1-fcvt")
|
| 604 |
|
|
;; CVTDQ2PD.
|
| 605 |
|
|
(define_insn_reservation "bdver1_ssecvt_cvtdq2pd_load" 8
|
| 606 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 607 |
|
|
(and (eq_attr "type" "ssecvt")
|
| 608 |
|
|
(and (eq_attr "memory" "load")
|
| 609 |
|
|
(and (match_operand:V2DF 0 "register_operand")
|
| 610 |
|
|
(match_operand:V4SI 1 "nonimmediate_operand")))))
|
| 611 |
|
|
"bdver1-double,bdver1-fpload,(bdver1-fxbar | bdver1-fcvt)")
|
| 612 |
|
|
(define_insn_reservation "bdver1_ssecvt_cvtdq2pd" 4
|
| 613 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 614 |
|
|
(and (eq_attr "type" "ssecvt")
|
| 615 |
|
|
(and (eq_attr "memory" "none")
|
| 616 |
|
|
(and (match_operand:V2DF 0 "register_operand")
|
| 617 |
|
|
(match_operand:V4SI 1 "nonimmediate_operand")))))
|
| 618 |
|
|
"bdver1-double,bdver1-fpsched,(bdver1-fxbar | bdver1-fcvt)")
|
| 619 |
|
|
;; CVTPS2PD, CVTPI2PD.
|
| 620 |
|
|
(define_insn_reservation "bdver1_ssecvt_cvtps2pd_load" 6
|
| 621 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 622 |
|
|
(and (eq_attr "type" "ssecvt")
|
| 623 |
|
|
(and (eq_attr "memory" "load")
|
| 624 |
|
|
(and (match_operand:V2DF 0 "register_operand")
|
| 625 |
|
|
(ior (match_operand:V2SI 1 "nonimmediate_operand")
|
| 626 |
|
|
(match_operand:V4SF 1 "nonimmediate_operand"))))))
|
| 627 |
|
|
"bdver1-double,bdver1-fpload,(bdver1-fxbar | bdver1-fcvt)")
|
| 628 |
|
|
(define_insn_reservation "bdver1_ssecvt_cvtps2pd" 2
|
| 629 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 630 |
|
|
(and (eq_attr "type" "ssecvt")
|
| 631 |
|
|
(and (eq_attr "memory" "load")
|
| 632 |
|
|
(and (match_operand:V2DF 0 "register_operand")
|
| 633 |
|
|
(ior (match_operand:V2SI 1 "nonimmediate_operand")
|
| 634 |
|
|
(match_operand:V4SF 1 "nonimmediate_operand"))))))
|
| 635 |
|
|
"bdver1-double,bdver1-fpsched,(bdver1-fxbar | bdver1-fcvt)")
|
| 636 |
|
|
;; CVTSD2SI, CVTSD2SIQ, CVTSS2SI, CVTSS2SIQ, CVTTSD2SI, CVTTSD2SIQ, CVTTSS2SI, CVTTSS2SIQ.
|
| 637 |
|
|
(define_insn_reservation "bdver1_ssecvt_cvtsX2si_load" 8
|
| 638 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 639 |
|
|
(and (eq_attr "type" "sseicvt")
|
| 640 |
|
|
(and (eq_attr "mode" "SI,DI")
|
| 641 |
|
|
(eq_attr "memory" "load"))))
|
| 642 |
|
|
"bdver1-double,bdver1-fpload,(bdver1-fcvt | bdver1-fsto)")
|
| 643 |
|
|
(define_insn_reservation "bdver1_ssecvt_cvtsX2si" 4
|
| 644 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 645 |
|
|
(and (eq_attr "type" "sseicvt")
|
| 646 |
|
|
(and (eq_attr "mode" "SI,DI")
|
| 647 |
|
|
(eq_attr "memory" "none"))))
|
| 648 |
|
|
"bdver1-double,bdver1-fpsched,(bdver1-fcvt | bdver1-fsto)")
|
| 649 |
|
|
;; CVTPD2PI, CVTTPD2PI.
|
| 650 |
|
|
(define_insn_reservation "bdver1_ssecvt_cvtpd2pi_load" 8
|
| 651 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 652 |
|
|
(and (eq_attr "type" "ssecvt")
|
| 653 |
|
|
(and (eq_attr "memory" "load")
|
| 654 |
|
|
(and (match_operand:V2DF 1 "nonimmediate_operand")
|
| 655 |
|
|
(match_operand:V2SI 0 "register_operand")))))
|
| 656 |
|
|
"bdver1-double,bdver1-fpload,(bdver1-fcvt | bdver1-fxbar)")
|
| 657 |
|
|
(define_insn_reservation "bdver1_ssecvt_cvtpd2pi" 4
|
| 658 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 659 |
|
|
(and (eq_attr "type" "ssecvt")
|
| 660 |
|
|
(and (eq_attr "memory" "none")
|
| 661 |
|
|
(and (match_operand:V2DF 1 "nonimmediate_operand")
|
| 662 |
|
|
(match_operand:V2SI 0 "register_operand")))))
|
| 663 |
|
|
"bdver1-double,bdver1-fpsched,(bdver1-fcvt | bdver1-fxbar)")
|
| 664 |
|
|
;; CVTPD2DQ, CVTTPD2DQ.
|
| 665 |
|
|
(define_insn_reservation "bdver1_ssecvt_cvtpd2dq_load" 6
|
| 666 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 667 |
|
|
(and (eq_attr "type" "ssecvt")
|
| 668 |
|
|
(and (eq_attr "memory" "load")
|
| 669 |
|
|
(and (match_operand:V2DF 1 "nonimmediate_operand")
|
| 670 |
|
|
(match_operand:V4SI 0 "register_operand")))))
|
| 671 |
|
|
"bdver1-double,bdver1-fpload,(bdver1-fcvt | bdver1-fxbar)")
|
| 672 |
|
|
(define_insn_reservation "bdver1_ssecvt_cvtpd2dq" 2
|
| 673 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 674 |
|
|
(and (eq_attr "type" "ssecvt")
|
| 675 |
|
|
(and (eq_attr "memory" "none")
|
| 676 |
|
|
(and (match_operand:V2DF 1 "nonimmediate_operand")
|
| 677 |
|
|
(match_operand:V4SI 0 "register_operand")))))
|
| 678 |
|
|
"bdver1-double,bdver1-fpsched,(bdver1-fcvt | bdver1-fxbar)")
|
| 679 |
|
|
;; CVTPS2PI, CVTTPS2PI, CVTPS2DQ, CVTTPS2DQ.
|
| 680 |
|
|
(define_insn_reservation "bdver1_ssecvt_cvtps2pi_load" 8
|
| 681 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 682 |
|
|
(and (eq_attr "type" "ssecvt")
|
| 683 |
|
|
(and (eq_attr "memory" "load")
|
| 684 |
|
|
(and (match_operand:V4SF 1 "nonimmediate_operand")
|
| 685 |
|
|
(ior (match_operand: V2SI 0 "register_operand")
|
| 686 |
|
|
(match_operand: V4SI 0 "register_operand"))))))
|
| 687 |
|
|
"bdver1-direct,bdver1-fpload,bdver1-fcvt")
|
| 688 |
|
|
(define_insn_reservation "bdver1_ssecvt_cvtps2pi" 4
|
| 689 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 690 |
|
|
(and (eq_attr "type" "ssecvt")
|
| 691 |
|
|
(and (eq_attr "memory" "none")
|
| 692 |
|
|
(and (match_operand:V4SF 1 "nonimmediate_operand")
|
| 693 |
|
|
(ior (match_operand: V2SI 0 "register_operand")
|
| 694 |
|
|
(match_operand: V4SI 0 "register_operand"))))))
|
| 695 |
|
|
"bdver1-direct,bdver1-fpsched,bdver1-fcvt")
|
| 696 |
|
|
|
| 697 |
|
|
;; SSE MUL, ADD, and MULADD.
|
| 698 |
|
|
(define_insn_reservation "bdver1_ssemuladd_load_256" 11
|
| 699 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 700 |
|
|
(and (eq_attr "type" "ssemul,sseadd,ssemuladd")
|
| 701 |
|
|
(and (eq_attr "mode" "V8SF,V4DF")
|
| 702 |
|
|
(eq_attr "memory" "load"))))
|
| 703 |
|
|
"bdver1-double,bdver1-fpload,bdver1-ffma")
|
| 704 |
|
|
(define_insn_reservation "bdver1_ssemuladd_256" 7
|
| 705 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 706 |
|
|
(and (eq_attr "type" "ssemul,sseadd,ssemuladd")
|
| 707 |
|
|
(and (eq_attr "mode" "V8SF,V4DF")
|
| 708 |
|
|
(eq_attr "memory" "none"))))
|
| 709 |
|
|
"bdver1-double,bdver1-fpsched,bdver1-ffma")
|
| 710 |
|
|
(define_insn_reservation "bdver1_ssemuladd_load" 10
|
| 711 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 712 |
|
|
(and (eq_attr "type" "ssemul,sseadd,ssemuladd")
|
| 713 |
|
|
(eq_attr "memory" "load")))
|
| 714 |
|
|
"bdver1-direct,bdver1-fpload,bdver1-ffma")
|
| 715 |
|
|
(define_insn_reservation "bdver1_ssemuladd" 6
|
| 716 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 717 |
|
|
(and (eq_attr "type" "ssemul,sseadd,ssemuladd")
|
| 718 |
|
|
(eq_attr "memory" "none")))
|
| 719 |
|
|
"bdver1-direct,bdver1-fpsched,bdver1-ffma")
|
| 720 |
|
|
(define_insn_reservation "bdver1_sseimul_load" 8
|
| 721 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 722 |
|
|
(and (eq_attr "type" "sseimul")
|
| 723 |
|
|
(eq_attr "memory" "load")))
|
| 724 |
|
|
"bdver1-direct,bdver1-fpload,bdver1-fmma")
|
| 725 |
|
|
(define_insn_reservation "bdver1_sseimul" 4
|
| 726 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 727 |
|
|
(and (eq_attr "type" "sseimul")
|
| 728 |
|
|
(eq_attr "memory" "none")))
|
| 729 |
|
|
"bdver1-direct,bdver1-fpsched,bdver1-fmma")
|
| 730 |
|
|
(define_insn_reservation "bdver1_sseiadd_load" 6
|
| 731 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 732 |
|
|
(and (eq_attr "type" "sseiadd")
|
| 733 |
|
|
(eq_attr "memory" "load")))
|
| 734 |
|
|
"bdver1-direct,bdver1-fpload,bdver1-fmal")
|
| 735 |
|
|
(define_insn_reservation "bdver1_sseiadd" 2
|
| 736 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 737 |
|
|
(and (eq_attr "type" "sseiadd")
|
| 738 |
|
|
(eq_attr "memory" "none")))
|
| 739 |
|
|
"bdver1-direct,bdver1-fpsched,bdver1-fmal")
|
| 740 |
|
|
|
| 741 |
|
|
;; SSE DIV: no throughput information (assume same as amdfam10).
|
| 742 |
|
|
(define_insn_reservation "bdver1_ssediv_double_load_256" 31
|
| 743 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 744 |
|
|
(and (eq_attr "type" "ssediv")
|
| 745 |
|
|
(and (eq_attr "mode" "V4DF")
|
| 746 |
|
|
(eq_attr "memory" "load"))))
|
| 747 |
|
|
"bdver1-double,bdver1-fpload,(bdver1-ffma0*17 | bdver1-ffma1*17)")
|
| 748 |
|
|
(define_insn_reservation "bdver1_ssediv_double_256" 27
|
| 749 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 750 |
|
|
(and (eq_attr "type" "ssediv")
|
| 751 |
|
|
(and (eq_attr "mode" "V4DF")
|
| 752 |
|
|
(eq_attr "memory" "none"))))
|
| 753 |
|
|
"bdver1-double,bdver1-fpsched,(bdver1-ffma0*17 | bdver1-ffma1*17)")
|
| 754 |
|
|
(define_insn_reservation "bdver1_ssediv_single_load_256" 28
|
| 755 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 756 |
|
|
(and (eq_attr "type" "ssediv")
|
| 757 |
|
|
(and (eq_attr "mode" "V8SF")
|
| 758 |
|
|
(eq_attr "memory" "load"))))
|
| 759 |
|
|
"bdver1-double,bdver1-fpload,(bdver1-ffma0*17 | bdver1-ffma1*17)")
|
| 760 |
|
|
(define_insn_reservation "bdver1_ssediv_single_256" 24
|
| 761 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 762 |
|
|
(and (eq_attr "type" "ssediv")
|
| 763 |
|
|
(and (eq_attr "mode" "V8SF")
|
| 764 |
|
|
(eq_attr "memory" "none"))))
|
| 765 |
|
|
"bdver1-double,bdver1-fpsched,(bdver1-ffma0*17 | bdver1-ffma1*17)")
|
| 766 |
|
|
(define_insn_reservation "bdver1_ssediv_double_load" 31
|
| 767 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 768 |
|
|
(and (eq_attr "type" "ssediv")
|
| 769 |
|
|
(and (eq_attr "mode" "DF,V2DF")
|
| 770 |
|
|
(eq_attr "memory" "load"))))
|
| 771 |
|
|
"bdver1-direct,bdver1-fpload,(bdver1-ffma0*17 | bdver1-ffma1*17)")
|
| 772 |
|
|
(define_insn_reservation "bdver1_ssediv_double" 27
|
| 773 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 774 |
|
|
(and (eq_attr "type" "ssediv")
|
| 775 |
|
|
(and (eq_attr "mode" "DF,V2DF")
|
| 776 |
|
|
(eq_attr "memory" "none"))))
|
| 777 |
|
|
"bdver1-direct,bdver1-fpsched,(bdver1-ffma0*17 | bdver1-ffma1*17)")
|
| 778 |
|
|
(define_insn_reservation "bdver1_ssediv_single_load" 28
|
| 779 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 780 |
|
|
(and (eq_attr "type" "ssediv")
|
| 781 |
|
|
(and (eq_attr "mode" "SF,V4SF")
|
| 782 |
|
|
(eq_attr "memory" "load"))))
|
| 783 |
|
|
"bdver1-direct,bdver1-fpload,(bdver1-ffma0*17 | bdver1-ffma1*17)")
|
| 784 |
|
|
(define_insn_reservation "bdver1_ssediv_single" 24
|
| 785 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 786 |
|
|
(and (eq_attr "type" "ssediv")
|
| 787 |
|
|
(and (eq_attr "mode" "SF,V4SF")
|
| 788 |
|
|
(eq_attr "memory" "none"))))
|
| 789 |
|
|
"bdver1-direct,bdver1-fpsched,(bdver1-ffma0*17 | bdver1-ffma1*17)")
|
| 790 |
|
|
|
| 791 |
|
|
(define_insn_reservation "bdver1_sseins" 3
|
| 792 |
|
|
(and (eq_attr "cpu" "bdver1,bdver2")
|
| 793 |
|
|
(and (eq_attr "type" "sseins")
|
| 794 |
|
|
(eq_attr "mode" "TI")))
|
| 795 |
|
|
"bdver1-direct,bdver1-fpsched,bdver1-fxbar")
|
| 796 |
|
|
|
