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[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [config/] [i386/] [driver-i386.c] - Blame information for rev 709

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1 709 jeremybenn
/* Subroutines for the gcc driver.
2
   Copyright (C) 2006, 2007, 2008, 2010 Free Software Foundation, Inc.
3
 
4
This file is part of GCC.
5
 
6
GCC is free software; you can redistribute it and/or modify
7
it under the terms of the GNU General Public License as published by
8
the Free Software Foundation; either version 3, or (at your option)
9
any later version.
10
 
11
GCC is distributed in the hope that it will be useful,
12
but WITHOUT ANY WARRANTY; without even the implied warranty of
13
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
GNU General Public License for more details.
15
 
16
You should have received a copy of the GNU General Public License
17
along with GCC; see the file COPYING3.  If not see
18
<http://www.gnu.org/licenses/>.  */
19
 
20
#include "config.h"
21
#include "system.h"
22
#include "coretypes.h"
23
#include "tm.h"
24
 
25
const char *host_detect_local_cpu (int argc, const char **argv);
26
 
27
#ifdef __GNUC__
28
#include "cpuid.h"
29
 
30
struct cache_desc
31
{
32
  unsigned sizekb;
33
  unsigned assoc;
34
  unsigned line;
35
};
36
 
37
/* Returns command line parameters that describe size and
38
   cache line size of the processor caches.  */
39
 
40
static char *
41
describe_cache (struct cache_desc level1, struct cache_desc level2)
42
{
43
  char size[100], line[100], size2[100];
44
 
45
  /* At the moment, gcc does not use the information
46
     about the associativity of the cache.  */
47
 
48
  snprintf (size, sizeof (size),
49
            "--param l1-cache-size=%u ", level1.sizekb);
50
  snprintf (line, sizeof (line),
51
            "--param l1-cache-line-size=%u ", level1.line);
52
 
53
  snprintf (size2, sizeof (size2),
54
            "--param l2-cache-size=%u ", level2.sizekb);
55
 
56
  return concat (size, line, size2, NULL);
57
}
58
 
59
/* Detect L2 cache parameters using CPUID extended function 0x80000006.  */
60
 
61
static void
62
detect_l2_cache (struct cache_desc *level2)
63
{
64
  unsigned eax, ebx, ecx, edx;
65
  unsigned assoc;
66
 
67
  __cpuid (0x80000006, eax, ebx, ecx, edx);
68
 
69
  level2->sizekb = (ecx >> 16) & 0xffff;
70
  level2->line = ecx & 0xff;
71
 
72
  assoc = (ecx >> 12) & 0xf;
73
  if (assoc == 6)
74
    assoc = 8;
75
  else if (assoc == 8)
76
    assoc = 16;
77
  else if (assoc >= 0xa && assoc <= 0xc)
78
    assoc = 32 + (assoc - 0xa) * 16;
79
  else if (assoc >= 0xd && assoc <= 0xe)
80
    assoc = 96 + (assoc - 0xd) * 32;
81
 
82
  level2->assoc = assoc;
83
}
84
 
85
/* Returns the description of caches for an AMD processor.  */
86
 
87
static const char *
88
detect_caches_amd (unsigned max_ext_level)
89
{
90
  unsigned eax, ebx, ecx, edx;
91
 
92
  struct cache_desc level1, level2 = {0, 0, 0};
93
 
94
  if (max_ext_level < 0x80000005)
95
    return "";
96
 
97
  __cpuid (0x80000005, eax, ebx, ecx, edx);
98
 
99
  level1.sizekb = (ecx >> 24) & 0xff;
100
  level1.assoc = (ecx >> 16) & 0xff;
101
  level1.line = ecx & 0xff;
102
 
103
  if (max_ext_level >= 0x80000006)
104
    detect_l2_cache (&level2);
105
 
106
  return describe_cache (level1, level2);
107
}
108
 
109
/* Decodes the size, the associativity and the cache line size of
110
   L1/L2 caches of an Intel processor.  Values are based on
111
   "Intel Processor Identification and the CPUID Instruction"
112
   [Application Note 485], revision -032, December 2007.  */
113
 
114
static void
115
decode_caches_intel (unsigned reg, bool xeon_mp,
116
                     struct cache_desc *level1, struct cache_desc *level2)
117
{
118
  int i;
119
 
120
  for (i = 24; i >= 0; i -= 8)
121
    switch ((reg >> i) & 0xff)
122
      {
123
      case 0x0a:
124
        level1->sizekb = 8; level1->assoc = 2; level1->line = 32;
125
        break;
126
      case 0x0c:
127
        level1->sizekb = 16; level1->assoc = 4; level1->line = 32;
128
        break;
129
      case 0x2c:
130
        level1->sizekb = 32; level1->assoc = 8; level1->line = 64;
131
        break;
132
      case 0x39:
133
        level2->sizekb = 128; level2->assoc = 4; level2->line = 64;
134
        break;
135
      case 0x3a:
136
        level2->sizekb = 192; level2->assoc = 6; level2->line = 64;
137
        break;
138
      case 0x3b:
139
        level2->sizekb = 128; level2->assoc = 2; level2->line = 64;
140
        break;
141
      case 0x3c:
142
        level2->sizekb = 256; level2->assoc = 4; level2->line = 64;
143
        break;
144
      case 0x3d:
145
        level2->sizekb = 384; level2->assoc = 6; level2->line = 64;
146
        break;
147
      case 0x3e:
148
        level2->sizekb = 512; level2->assoc = 4; level2->line = 64;
149
        break;
150
      case 0x41:
151
        level2->sizekb = 128; level2->assoc = 4; level2->line = 32;
152
        break;
153
      case 0x42:
154
        level2->sizekb = 256; level2->assoc = 4; level2->line = 32;
155
        break;
156
      case 0x43:
157
        level2->sizekb = 512; level2->assoc = 4; level2->line = 32;
158
        break;
159
      case 0x44:
160
        level2->sizekb = 1024; level2->assoc = 4; level2->line = 32;
161
        break;
162
      case 0x45:
163
        level2->sizekb = 2048; level2->assoc = 4; level2->line = 32;
164
        break;
165
      case 0x49:
166
        if (xeon_mp)
167
          break;
168
        level2->sizekb = 4096; level2->assoc = 16; level2->line = 64;
169
        break;
170
      case 0x4e:
171
        level2->sizekb = 6144; level2->assoc = 24; level2->line = 64;
172
        break;
173
      case 0x60:
174
        level1->sizekb = 16; level1->assoc = 8; level1->line = 64;
175
        break;
176
      case 0x66:
177
        level1->sizekb = 8; level1->assoc = 4; level1->line = 64;
178
        break;
179
      case 0x67:
180
        level1->sizekb = 16; level1->assoc = 4; level1->line = 64;
181
        break;
182
      case 0x68:
183
        level1->sizekb = 32; level1->assoc = 4; level1->line = 64;
184
        break;
185
      case 0x78:
186
        level2->sizekb = 1024; level2->assoc = 4; level2->line = 64;
187
        break;
188
      case 0x79:
189
        level2->sizekb = 128; level2->assoc = 8; level2->line = 64;
190
        break;
191
      case 0x7a:
192
        level2->sizekb = 256; level2->assoc = 8; level2->line = 64;
193
        break;
194
      case 0x7b:
195
        level2->sizekb = 512; level2->assoc = 8; level2->line = 64;
196
        break;
197
      case 0x7c:
198
        level2->sizekb = 1024; level2->assoc = 8; level2->line = 64;
199
        break;
200
      case 0x7d:
201
        level2->sizekb = 2048; level2->assoc = 8; level2->line = 64;
202
        break;
203
      case 0x7f:
204
        level2->sizekb = 512; level2->assoc = 2; level2->line = 64;
205
        break;
206
      case 0x82:
207
        level2->sizekb = 256; level2->assoc = 8; level2->line = 32;
208
        break;
209
      case 0x83:
210
        level2->sizekb = 512; level2->assoc = 8; level2->line = 32;
211
        break;
212
      case 0x84:
213
        level2->sizekb = 1024; level2->assoc = 8; level2->line = 32;
214
        break;
215
      case 0x85:
216
        level2->sizekb = 2048; level2->assoc = 8; level2->line = 32;
217
        break;
218
      case 0x86:
219
        level2->sizekb = 512; level2->assoc = 4; level2->line = 64;
220
        break;
221
      case 0x87:
222
        level2->sizekb = 1024; level2->assoc = 8; level2->line = 64;
223
 
224
      default:
225
        break;
226
      }
227
}
228
 
229
/* Detect cache parameters using CPUID function 2.  */
230
 
231
static void
232
detect_caches_cpuid2 (bool xeon_mp,
233
                      struct cache_desc *level1, struct cache_desc *level2)
234
{
235
  unsigned regs[4];
236
  int nreps, i;
237
 
238
  __cpuid (2, regs[0], regs[1], regs[2], regs[3]);
239
 
240
  nreps = regs[0] & 0x0f;
241
  regs[0] &= ~0x0f;
242
 
243
  while (--nreps >= 0)
244
    {
245
      for (i = 0; i < 4; i++)
246
        if (regs[i] && !((regs[i] >> 31) & 1))
247
          decode_caches_intel (regs[i], xeon_mp, level1, level2);
248
 
249
      if (nreps)
250
        __cpuid (2, regs[0], regs[1], regs[2], regs[3]);
251
    }
252
}
253
 
254
/* Detect cache parameters using CPUID function 4. This
255
   method doesn't require hardcoded tables.  */
256
 
257
enum cache_type
258
{
259
  CACHE_END = 0,
260
  CACHE_DATA = 1,
261
  CACHE_INST = 2,
262
  CACHE_UNIFIED = 3
263
};
264
 
265
static void
266
detect_caches_cpuid4 (struct cache_desc *level1, struct cache_desc *level2,
267
                      struct cache_desc *level3)
268
{
269
  struct cache_desc *cache;
270
 
271
  unsigned eax, ebx, ecx, edx;
272
  int count;
273
 
274
  for (count = 0;; count++)
275
    {
276
      __cpuid_count(4, count, eax, ebx, ecx, edx);
277
      switch (eax & 0x1f)
278
        {
279
        case CACHE_END:
280
          return;
281
        case CACHE_DATA:
282
        case CACHE_UNIFIED:
283
          {
284
            switch ((eax >> 5) & 0x07)
285
              {
286
              case 1:
287
                cache = level1;
288
                break;
289
              case 2:
290
                cache = level2;
291
                break;
292
              case 3:
293
                cache = level3;
294
                break;
295
              default:
296
                cache = NULL;
297
              }
298
 
299
            if (cache)
300
              {
301
                unsigned sets = ecx + 1;
302
                unsigned part = ((ebx >> 12) & 0x03ff) + 1;
303
 
304
                cache->assoc = ((ebx >> 22) & 0x03ff) + 1;
305
                cache->line = (ebx & 0x0fff) + 1;
306
 
307
                cache->sizekb = (cache->assoc * part
308
                                 * cache->line * sets) / 1024;
309
              }
310
          }
311
        default:
312
          break;
313
        }
314
    }
315
}
316
 
317
/* Returns the description of caches for an Intel processor.  */
318
 
319
static const char *
320
detect_caches_intel (bool xeon_mp, unsigned max_level,
321
                     unsigned max_ext_level, unsigned *l2sizekb)
322
{
323
  struct cache_desc level1 = {0, 0, 0}, level2 = {0, 0, 0}, level3 = {0, 0, 0};
324
 
325
  if (max_level >= 4)
326
    detect_caches_cpuid4 (&level1, &level2, &level3);
327
  else if (max_level >= 2)
328
    detect_caches_cpuid2 (xeon_mp, &level1, &level2);
329
  else
330
    return "";
331
 
332
  if (level1.sizekb == 0)
333
    return "";
334
 
335
  /* Let the L3 replace the L2. This assumes inclusive caches
336
     and single threaded program for now. */
337
  if (level3.sizekb)
338
    level2 = level3;
339
 
340
  /* Intel CPUs are equipped with AMD style L2 cache info.  Try this
341
     method if other methods fail to provide L2 cache parameters.  */
342
  if (level2.sizekb == 0 && max_ext_level >= 0x80000006)
343
    detect_l2_cache (&level2);
344
 
345
  *l2sizekb = level2.sizekb;
346
 
347
  return describe_cache (level1, level2);
348
}
349
 
350
enum vendor_signatures
351
{
352
  SIG_INTEL =   0x756e6547 /* Genu */,
353
  SIG_AMD =     0x68747541 /* Auth */
354
};
355
 
356
enum processor_signatures
357
{
358
  SIG_GEODE =   0x646f6547 /* Geod */
359
};
360
 
361
/* This will be called by the spec parser in gcc.c when it sees
362
   a %:local_cpu_detect(args) construct.  Currently it will be called
363
   with either "arch" or "tune" as argument depending on if -march=native
364
   or -mtune=native is to be substituted.
365
 
366
   It returns a string containing new command line parameters to be
367
   put at the place of the above two options, depending on what CPU
368
   this is executed.  E.g. "-march=k8" on an AMD64 machine
369
   for -march=native.
370
 
371
   ARGC and ARGV are set depending on the actual arguments given
372
   in the spec.  */
373
 
374
const char *host_detect_local_cpu (int argc, const char **argv)
375
{
376
  enum processor_type processor = PROCESSOR_I386;
377
  const char *cpu = "i386";
378
 
379
  const char *cache = "";
380
  const char *options = "";
381
 
382
  unsigned int eax, ebx, ecx, edx;
383
 
384
  unsigned int max_level, ext_level;
385
 
386
  unsigned int vendor;
387
  unsigned int model, family;
388
 
389
  unsigned int has_sse3, has_ssse3, has_cmpxchg16b;
390
  unsigned int has_cmpxchg8b, has_cmov, has_mmx, has_sse, has_sse2;
391
 
392
  /* Extended features */
393
  unsigned int has_lahf_lm = 0, has_sse4a = 0;
394
  unsigned int has_longmode = 0, has_3dnowp = 0, has_3dnow = 0;
395
  unsigned int has_movbe = 0, has_sse4_1 = 0, has_sse4_2 = 0;
396
  unsigned int has_popcnt = 0, has_aes = 0, has_avx = 0, has_avx2 = 0;
397
  unsigned int has_pclmul = 0, has_abm = 0, has_lwp = 0;
398
  unsigned int has_fma = 0, has_fma4 = 0, has_xop = 0;
399
  unsigned int has_bmi = 0, has_bmi2 = 0, has_tbm = 0, has_lzcnt = 0;
400
 
401
  bool arch;
402
 
403
  unsigned int l2sizekb = 0;
404
 
405
  if (argc < 1)
406
    return NULL;
407
 
408
  arch = !strcmp (argv[0], "arch");
409
 
410
  if (!arch && strcmp (argv[0], "tune"))
411
    return NULL;
412
 
413
  max_level = __get_cpuid_max (0, &vendor);
414
  if (max_level < 1)
415
    goto done;
416
 
417
  __cpuid (1, eax, ebx, ecx, edx);
418
 
419
  model = (eax >> 4) & 0x0f;
420
  family = (eax >> 8) & 0x0f;
421
  if (vendor == SIG_INTEL)
422
    {
423
      unsigned int extended_model, extended_family;
424
 
425
      extended_model = (eax >> 12) & 0xf0;
426
      extended_family = (eax >> 20) & 0xff;
427
      if (family == 0x0f)
428
        {
429
          family += extended_family;
430
          model += extended_model;
431
        }
432
      else if (family == 0x06)
433
        model += extended_model;
434
    }
435
 
436
  has_sse3 = ecx & bit_SSE3;
437
  has_ssse3 = ecx & bit_SSSE3;
438
  has_sse4_1 = ecx & bit_SSE4_1;
439
  has_sse4_2 = ecx & bit_SSE4_2;
440
  has_avx = ecx & bit_AVX;
441
  has_cmpxchg16b = ecx & bit_CMPXCHG16B;
442
  has_movbe = ecx & bit_MOVBE;
443
  has_popcnt = ecx & bit_POPCNT;
444
  has_aes = ecx & bit_AES;
445
  has_pclmul = ecx & bit_PCLMUL;
446
  has_fma = ecx & bit_FMA;
447
 
448
  has_cmpxchg8b = edx & bit_CMPXCHG8B;
449
  has_cmov = edx & bit_CMOV;
450
  has_mmx = edx & bit_MMX;
451
  has_sse = edx & bit_SSE;
452
  has_sse2 = edx & bit_SSE2;
453
 
454
  if (max_level >= 7)
455
    {
456
      __cpuid_count (7, 0, eax, ebx, ecx, edx);
457
 
458
      has_bmi = ebx & bit_BMI;
459
      has_avx2 = ebx & bit_AVX2;
460
      has_bmi2 = ebx & bit_BMI2;
461
    }
462
 
463
  /* Check cpuid level of extended features.  */
464
  __cpuid (0x80000000, ext_level, ebx, ecx, edx);
465
 
466
  if (ext_level > 0x80000000)
467
    {
468
      __cpuid (0x80000001, eax, ebx, ecx, edx);
469
 
470
      has_lahf_lm = ecx & bit_LAHF_LM;
471
      has_sse4a = ecx & bit_SSE4a;
472
      has_abm = ecx & bit_ABM;
473
      has_lwp = ecx & bit_LWP;
474
      has_fma4 = ecx & bit_FMA4;
475
      has_xop = ecx & bit_XOP;
476
      has_tbm = ecx & bit_TBM;
477
      has_lzcnt = ecx & bit_LZCNT;
478
 
479
      has_longmode = edx & bit_LM;
480
      has_3dnowp = edx & bit_3DNOWP;
481
      has_3dnow = edx & bit_3DNOW;
482
    }
483
 
484
  if (!arch)
485
    {
486
      if (vendor == SIG_AMD)
487
        cache = detect_caches_amd (ext_level);
488
      else if (vendor == SIG_INTEL)
489
        {
490
          bool xeon_mp = (family == 15 && model == 6);
491
          cache = detect_caches_intel (xeon_mp, max_level,
492
                                       ext_level, &l2sizekb);
493
        }
494
    }
495
 
496
  if (vendor == SIG_AMD)
497
    {
498
      unsigned int name;
499
 
500
      /* Detect geode processor by its processor signature.  */
501
      if (ext_level > 0x80000001)
502
        __cpuid (0x80000002, name, ebx, ecx, edx);
503
      else
504
        name = 0;
505
 
506
      if (name == SIG_GEODE)
507
        processor = PROCESSOR_GEODE;
508
      else if (has_bmi)
509
        processor = PROCESSOR_BDVER2;
510
      else if (has_xop)
511
        processor = PROCESSOR_BDVER1;
512
      else if (has_sse4a && has_ssse3)
513
        processor = PROCESSOR_BTVER1;
514
      else if (has_sse4a)
515
        processor = PROCESSOR_AMDFAM10;
516
      else if (has_sse2 || has_longmode)
517
        processor = PROCESSOR_K8;
518
      else if (has_3dnowp && family == 6)
519
        processor = PROCESSOR_ATHLON;
520
      else if (has_mmx)
521
        processor = PROCESSOR_K6;
522
      else
523
        processor = PROCESSOR_PENTIUM;
524
    }
525
  else
526
    {
527
      switch (family)
528
        {
529
        case 4:
530
          processor = PROCESSOR_I486;
531
          break;
532
        case 5:
533
          processor = PROCESSOR_PENTIUM;
534
          break;
535
        case 6:
536
          processor = PROCESSOR_PENTIUMPRO;
537
          break;
538
        case 15:
539
          processor = PROCESSOR_PENTIUM4;
540
          break;
541
        default:
542
          /* We have no idea.  */
543
          processor = PROCESSOR_GENERIC32;
544
        }
545
    }
546
 
547
  switch (processor)
548
    {
549
    case PROCESSOR_I386:
550
      /* Default.  */
551
      break;
552
    case PROCESSOR_I486:
553
      cpu = "i486";
554
      break;
555
    case PROCESSOR_PENTIUM:
556
      if (arch && has_mmx)
557
        cpu = "pentium-mmx";
558
      else
559
        cpu = "pentium";
560
      break;
561
    case PROCESSOR_PENTIUMPRO:
562
      switch (model)
563
        {
564
        case 0x1c:
565
        case 0x26:
566
          /* Atom.  */
567
          cpu = "atom";
568
          break;
569
        case 0x1a:
570
        case 0x1e:
571
        case 0x1f:
572
        case 0x2e:
573
          /* Nehalem.  */
574
          cpu = "corei7";
575
          break;
576
        case 0x25:
577
        case 0x2c:
578
        case 0x2f:
579
          /* Westmere.  */
580
          cpu = "corei7";
581
          break;
582
        case 0x2a:
583
        case 0x2d:
584
          /* Sandy Bridge.  */
585
          cpu = "corei7-avx";
586
          break;
587
        case 0x17:
588
        case 0x1d:
589
          /* Penryn.  */
590
          cpu = "core2";
591
          break;
592
        case 0x0f:
593
          /* Merom.  */
594
          cpu = "core2";
595
          break;
596
        default:
597
          if (arch)
598
            {
599
              /* This is unknown family 0x6 CPU.  */
600
              if (has_avx)
601
                /* Assume Sandy Bridge.  */
602
                cpu = "corei7-avx";
603
              else if (has_sse4_2)
604
                /* Assume Core i7.  */
605
                cpu = "corei7";
606
              else if (has_ssse3)
607
                {
608
                  if (has_movbe)
609
                    /* Assume Atom.  */
610
                    cpu = "atom";
611
                  else
612
                    /* Assume Core 2.  */
613
                    cpu = "core2";
614
                }
615
              else if (has_sse3)
616
                /* It is Core Duo.  */
617
                cpu = "pentium-m";
618
              else if (has_sse2)
619
                /* It is Pentium M.  */
620
                cpu = "pentium-m";
621
              else if (has_sse)
622
                /* It is Pentium III.  */
623
                cpu = "pentium3";
624
              else if (has_mmx)
625
                /* It is Pentium II.  */
626
                cpu = "pentium2";
627
              else
628
                /* Default to Pentium Pro.  */
629
                cpu = "pentiumpro";
630
            }
631
          else
632
            /* For -mtune, we default to -mtune=generic.  */
633
            cpu = "generic";
634
          break;
635
        }
636
      break;
637
    case PROCESSOR_PENTIUM4:
638
      if (has_sse3)
639
        {
640
          if (has_longmode)
641
            cpu = "nocona";
642
          else
643
            cpu = "prescott";
644
        }
645
      else
646
        cpu = "pentium4";
647
      break;
648
    case PROCESSOR_GEODE:
649
      cpu = "geode";
650
      break;
651
    case PROCESSOR_K6:
652
      if (arch && has_3dnow)
653
        cpu = "k6-3";
654
      else
655
        cpu = "k6";
656
      break;
657
    case PROCESSOR_ATHLON:
658
      if (arch && has_sse)
659
        cpu = "athlon-4";
660
      else
661
        cpu = "athlon";
662
      break;
663
    case PROCESSOR_K8:
664
      if (arch && has_sse3)
665
        cpu = "k8-sse3";
666
      else
667
        cpu = "k8";
668
      break;
669
    case PROCESSOR_AMDFAM10:
670
      cpu = "amdfam10";
671
      break;
672
    case PROCESSOR_BDVER1:
673
      cpu = "bdver1";
674
      break;
675
    case PROCESSOR_BDVER2:
676
      cpu = "bdver2";
677
      break;
678
    case PROCESSOR_BTVER1:
679
      cpu = "btver1";
680
      break;
681
 
682
    default:
683
      /* Use something reasonable.  */
684
      if (arch)
685
        {
686
          if (has_ssse3)
687
            cpu = "core2";
688
          else if (has_sse3)
689
            {
690
              if (has_longmode)
691
                cpu = "nocona";
692
              else
693
                cpu = "prescott";
694
            }
695
          else if (has_sse2)
696
            cpu = "pentium4";
697
          else if (has_cmov)
698
            cpu = "pentiumpro";
699
          else if (has_mmx)
700
            cpu = "pentium-mmx";
701
          else if (has_cmpxchg8b)
702
            cpu = "pentium";
703
        }
704
      else
705
        cpu = "generic";
706
    }
707
 
708
  if (arch)
709
    {
710
      const char *cx16 = has_cmpxchg16b ? " -mcx16" : " -mno-cx16";
711
      const char *sahf = has_lahf_lm ? " -msahf" : " -mno-sahf";
712
      const char *movbe = has_movbe ? " -mmovbe" : " -mno-movbe";
713
      const char *ase = has_aes ? " -maes" : " -mno-aes";
714
      const char *pclmul = has_pclmul ? " -mpclmul" : " -mno-pclmul";
715
      const char *popcnt = has_popcnt ? " -mpopcnt" : " -mno-popcnt";
716
      const char *abm = has_abm ? " -mabm" : " -mno-abm";
717
      const char *lwp = has_lwp ? " -mlwp" : " -mno-lwp";
718
      const char *fma = has_fma ? " -mfma" : " -mno-fma";
719
      const char *fma4 = has_fma4 ? " -mfma4" : " -mno-fma4";
720
      const char *xop = has_xop ? " -mxop" : " -mno-xop";
721
      const char *bmi = has_bmi ? " -mbmi" : " -mno-bmi";
722
      const char *bmi2 = has_bmi2 ? " -mbmi2" : " -mno-bmi2";
723
      const char *tbm = has_tbm ? " -mtbm" : " -mno-tbm";
724
      const char *avx = has_avx ? " -mavx" : " -mno-avx";
725
      const char *avx2 = has_avx2 ? " -mavx2" : " -mno-avx2";
726
      const char *sse4_2 = has_sse4_2 ? " -msse4.2" : " -mno-sse4.2";
727
      const char *sse4_1 = has_sse4_1 ? " -msse4.1" : " -mno-sse4.1";
728
      const char *lzcnt = has_lzcnt ? " -mlzcnt" : " -mno-lzcnt";
729
 
730
      options = concat (options, cx16, sahf, movbe, ase, pclmul,
731
                        popcnt, abm, lwp, fma, fma4, xop, bmi, bmi2,
732
                        tbm, avx, avx2, sse4_2, sse4_1, lzcnt, NULL);
733
    }
734
 
735
done:
736
  return concat (cache, "-m", argv[0], "=", cpu, options, NULL);
737
}
738
#else
739
 
740
/* If we aren't compiling with GCC then the driver will just ignore
741
   -march and -mtune "native" target and will leave to the newly
742
   built compiler to generate code for its default target.  */
743
 
744
const char *host_detect_local_cpu (int argc ATTRIBUTE_UNUSED,
745
                                   const char **argv ATTRIBUTE_UNUSED)
746
{
747
  return NULL;
748
}
749
#endif /* __GNUC__ */

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