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[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [config/] [i386/] [i386.opt] - Blame information for rev 709

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1 709 jeremybenn
; Options for the IA-32 and AMD64 ports of the compiler.
2
 
3
; Copyright (C) 2005, 2006, 2007, 2008, 2009,
4
; 2010, 2011 Free Software Foundation, Inc.
5
;
6
; This file is part of GCC.
7
;
8
; GCC is free software; you can redistribute it and/or modify it under
9
; the terms of the GNU General Public License as published by the Free
10
; Software Foundation; either version 3, or (at your option) any later
11
; version.
12
;
13
; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14
; WARRANTY; without even the implied warranty of MERCHANTABILITY or
15
; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
16
; for more details.
17
;
18
; You should have received a copy of the GNU General Public License
19
; along with GCC; see the file COPYING3.  If not see
20
; .
21
 
22
HeaderInclude
23
config/i386/i386-opts.h
24
 
25
; Bit flags that specify the ISA we are compiling for.
26
Variable
27
HOST_WIDE_INT ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT
28
 
29
; A mask of ix86_isa_flags that includes bit X if X was set or cleared
30
; on the command line.
31
Variable
32
HOST_WIDE_INT ix86_isa_flags_explicit
33
 
34
TargetVariable
35
int recip_mask = RECIP_MASK_DEFAULT
36
 
37
Variable
38
int recip_mask_explicit
39
 
40
TargetSave
41
int x_recip_mask_explicit
42
 
43
;; Definitions to add to the cl_target_option structure
44
;; -march= processor
45
TargetSave
46
unsigned char arch
47
 
48
;; -mtune= processor
49
TargetSave
50
unsigned char tune
51
 
52
;; CPU schedule model
53
TargetSave
54
unsigned char schedule
55
 
56
;; branch cost
57
TargetSave
58
unsigned char branch_cost
59
 
60
;; which flags were passed by the user
61
TargetSave
62
HOST_WIDE_INT x_ix86_isa_flags_explicit
63
 
64
;; which flags were passed by the user
65
TargetSave
66
int ix86_target_flags_explicit
67
 
68
;; whether -mtune was not specified
69
TargetSave
70
unsigned char tune_defaulted
71
 
72
;; whether -march was specified
73
TargetSave
74
unsigned char arch_specified
75
 
76
;; x86 options
77
m128bit-long-double
78
Target RejectNegative Report Mask(128BIT_LONG_DOUBLE) Save
79
sizeof(long double) is 16
80
 
81
m80387
82
Target Report Mask(80387) Save
83
Use hardware fp
84
 
85
m96bit-long-double
86
Target RejectNegative Report InverseMask(128BIT_LONG_DOUBLE) Save
87
sizeof(long double) is 12
88
 
89
maccumulate-outgoing-args
90
Target Report Mask(ACCUMULATE_OUTGOING_ARGS) Save
91
Reserve space for outgoing arguments in the function prologue
92
 
93
malign-double
94
Target Report Mask(ALIGN_DOUBLE) Save
95
Align some doubles on dword boundary
96
 
97
malign-functions=
98
Target RejectNegative Joined UInteger
99
Function starts are aligned to this power of 2
100
 
101
malign-jumps=
102
Target RejectNegative Joined UInteger
103
Jump targets are aligned to this power of 2
104
 
105
malign-loops=
106
Target RejectNegative Joined UInteger
107
Loop code aligned to this power of 2
108
 
109
malign-stringops
110
Target RejectNegative Report InverseMask(NO_ALIGN_STRINGOPS, ALIGN_STRINGOPS) Save
111
Align destination of the string operations
112
 
113
march=
114
Target RejectNegative Joined Var(ix86_arch_string)
115
Generate code for given CPU
116
 
117
masm=
118
Target RejectNegative Joined Enum(asm_dialect) Var(ix86_asm_dialect) Init(ASM_ATT)
119
Use given assembler dialect
120
 
121
Enum
122
Name(asm_dialect) Type(enum asm_dialect)
123
Known assembler dialects (for use with the -masm-dialect= option):
124
 
125
EnumValue
126
Enum(asm_dialect) String(intel) Value(ASM_INTEL)
127
 
128
EnumValue
129
Enum(asm_dialect) String(att) Value(ASM_ATT)
130
 
131
mbranch-cost=
132
Target RejectNegative Joined UInteger Var(ix86_branch_cost)
133
Branches are this expensive (1-5, arbitrary units)
134
 
135
mlarge-data-threshold=
136
Target RejectNegative Joined UInteger Var(ix86_section_threshold) Init(65536)
137
Data greater than given threshold will go into .ldata section in x86-64 medium model
138
 
139
mcmodel=
140
Target RejectNegative Joined Enum(cmodel) Var(ix86_cmodel) Init(CM_32)
141
Use given x86-64 code model
142
 
143
Enum
144
Name(cmodel) Type(enum cmodel)
145
Known code models (for use with the -mcmodel= option):
146
 
147
EnumValue
148
Enum(cmodel) String(small) Value(CM_SMALL)
149
 
150
EnumValue
151
Enum(cmodel) String(medium) Value(CM_MEDIUM)
152
 
153
EnumValue
154
Enum(cmodel) String(large) Value(CM_LARGE)
155
 
156
EnumValue
157
Enum(cmodel) String(32) Value(CM_32)
158
 
159
EnumValue
160
Enum(cmodel) String(kernel) Value(CM_KERNEL)
161
 
162
mcpu=
163
Target RejectNegative Joined Undocumented Alias(mtune=) Warn(%<-mcpu=%> is deprecated; use %<-mtune=%> or %<-march=%> instead)
164
 
165
mfancy-math-387
166
Target RejectNegative Report InverseMask(NO_FANCY_MATH_387, USE_FANCY_MATH_387) Save
167
Generate sin, cos, sqrt for FPU
168
 
169
mforce-drap
170
Target Report Var(ix86_force_drap)
171
Always use Dynamic Realigned Argument Pointer (DRAP) to realign stack
172
 
173
mfp-ret-in-387
174
Target Report Mask(FLOAT_RETURNS) Save
175
Return values of functions in FPU registers
176
 
177
mfpmath=
178
Target RejectNegative Joined Var(ix86_fpmath) Enum(fpmath_unit) Init(FPMATH_387) Save
179
Generate floating point mathematics using given instruction set
180
 
181
Enum
182
Name(fpmath_unit) Type(enum fpmath_unit)
183
Valid arguments to -mfpmath=:
184
 
185
EnumValue
186
Enum(fpmath_unit) String(387) Value(FPMATH_387)
187
 
188
EnumValue
189
Enum(fpmath_unit) String(sse) Value(FPMATH_SSE)
190
 
191
EnumValue
192
Enum(fpmath_unit) String(387,sse) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)})
193
 
194
EnumValue
195
Enum(fpmath_unit) String(387+sse) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)})
196
 
197
EnumValue
198
Enum(fpmath_unit) String(sse,387) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)})
199
 
200
EnumValue
201
Enum(fpmath_unit) String(sse+387) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)})
202
 
203
EnumValue
204
Enum(fpmath_unit) String(both) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)})
205
 
206
mhard-float
207
Target RejectNegative Mask(80387) MaskExists Save
208
Use hardware fp
209
 
210
mieee-fp
211
Target Report Mask(IEEE_FP) Save
212
Use IEEE math for fp comparisons
213
 
214
minline-all-stringops
215
Target Report Mask(INLINE_ALL_STRINGOPS) Save
216
Inline all known string operations
217
 
218
minline-stringops-dynamically
219
Target Report Mask(INLINE_STRINGOPS_DYNAMICALLY) Save
220
Inline memset/memcpy string operations, but perform inline version only for small blocks
221
 
222
mintel-syntax
223
Target Undocumented Alias(masm=, intel, att) Warn(%<-mintel-syntax%> and %<-mno-intel-syntax%> are deprecated; use %<-masm=intel%> and %<-masm=att%> instead)
224
;; Deprecated
225
 
226
mms-bitfields
227
Target Report Mask(MS_BITFIELD_LAYOUT) Save
228
Use native (MS) bitfield layout
229
 
230
mno-align-stringops
231
Target RejectNegative Report Mask(NO_ALIGN_STRINGOPS) Undocumented Save
232
 
233
mno-fancy-math-387
234
Target RejectNegative Report Mask(NO_FANCY_MATH_387) Undocumented Save
235
 
236
mno-push-args
237
Target RejectNegative Report Mask(NO_PUSH_ARGS) Undocumented Save
238
 
239
mno-red-zone
240
Target RejectNegative Report Mask(NO_RED_ZONE) Undocumented Save
241
 
242
momit-leaf-frame-pointer
243
Target Report Mask(OMIT_LEAF_FRAME_POINTER) Save
244
Omit the frame pointer in leaf functions
245
 
246
mpc32
247
Target RejectNegative Report
248
Set 80387 floating-point precision to 32-bit
249
 
250
mpc64
251
Target RejectNegative Report
252
Set 80387 floating-point precision to 64-bit
253
 
254
mpc80
255
Target RejectNegative Report
256
Set 80387 floating-point precision to 80-bit
257
 
258
mpreferred-stack-boundary=
259
Target RejectNegative Joined UInteger Var(ix86_preferred_stack_boundary_arg)
260
Attempt to keep stack aligned to this power of 2
261
 
262
mincoming-stack-boundary=
263
Target RejectNegative Joined UInteger Var(ix86_incoming_stack_boundary_arg)
264
Assume incoming stack aligned to this power of 2
265
 
266
mpush-args
267
Target Report InverseMask(NO_PUSH_ARGS, PUSH_ARGS) Save
268
Use push instructions to save outgoing arguments
269
 
270
mred-zone
271
Target RejectNegative Report InverseMask(NO_RED_ZONE, RED_ZONE) Save
272
Use red-zone in the x86-64 code
273
 
274
mregparm=
275
Target RejectNegative Joined UInteger Var(ix86_regparm)
276
Number of registers used to pass integer arguments
277
 
278
mrtd
279
Target Report Mask(RTD) Save
280
Alternate calling convention
281
 
282
msoft-float
283
Target InverseMask(80387) Save
284
Do not use hardware fp
285
 
286
msseregparm
287
Target RejectNegative Mask(SSEREGPARM) Save
288
Use SSE register passing conventions for SF and DF mode
289
 
290
mstackrealign
291
Target Report Var(ix86_force_align_arg_pointer) Init(-1)
292
Realign stack in prologue
293
 
294
mstack-arg-probe
295
Target Report Mask(STACK_PROBE) Save
296
Enable stack probing
297
 
298
mstringop-strategy=
299
Target RejectNegative Joined Enum(stringop_alg) Var(ix86_stringop_alg) Init(no_stringop)
300
Chose strategy to generate stringop using
301
 
302
Enum
303
Name(stringop_alg) Type(enum stringop_alg)
304
Valid arguments to -mstringop-strategy=:
305
 
306
EnumValue
307
Enum(stringop_alg) String(rep_byte) Value(rep_prefix_1_byte)
308
 
309
EnumValue
310
Enum(stringop_alg) String(libcall) Value(libcall)
311
 
312
EnumValue
313
Enum(stringop_alg) String(rep_4byte) Value(rep_prefix_4_byte)
314
 
315
EnumValue
316
Enum(stringop_alg) String(rep_8byte) Value(rep_prefix_8_byte)
317
 
318
EnumValue
319
Enum(stringop_alg) String(byte_loop) Value(loop_1_byte)
320
 
321
EnumValue
322
Enum(stringop_alg) String(loop) Value(loop)
323
 
324
EnumValue
325
Enum(stringop_alg) String(unrolled_loop) Value(unrolled_loop)
326
 
327
mtls-dialect=
328
Target RejectNegative Joined Var(ix86_tls_dialect) Enum(tls_dialect) Init(TLS_DIALECT_GNU)
329
Use given thread-local storage dialect
330
 
331
Enum
332
Name(tls_dialect) Type(enum tls_dialect)
333
Known TLS dialects (for use with the -mtls-dialect= option):
334
 
335
EnumValue
336
Enum(tls_dialect) String(gnu) Value(TLS_DIALECT_GNU)
337
 
338
EnumValue
339
Enum(tls_dialect) String(gnu2) Value(TLS_DIALECT_GNU2)
340
 
341
mtls-direct-seg-refs
342
Target Report Mask(TLS_DIRECT_SEG_REFS)
343
Use direct references against %gs when accessing tls data
344
 
345
mtune=
346
Target RejectNegative Joined Var(ix86_tune_string)
347
Schedule code for given CPU
348
 
349
mabi=
350
Target RejectNegative Joined Var(ix86_abi) Enum(calling_abi) Init(SYSV_ABI)
351
Generate code that conforms to the given ABI
352
 
353
Enum
354
Name(calling_abi) Type(enum calling_abi)
355
Known ABIs (for use with the -mabi= option):
356
 
357
EnumValue
358
Enum(calling_abi) String(sysv) Value(SYSV_ABI)
359
 
360
EnumValue
361
Enum(calling_abi) String(ms) Value(MS_ABI)
362
 
363
mveclibabi=
364
Target RejectNegative Joined Var(ix86_veclibabi_type) Enum(ix86_veclibabi) Init(ix86_veclibabi_type_none)
365
Vector library ABI to use
366
 
367
Enum
368
Name(ix86_veclibabi) Type(enum ix86_veclibabi)
369
Known vectorization library ABIs (for use with the -mveclibabi= option):
370
 
371
EnumValue
372
Enum(ix86_veclibabi) String(svml) Value(ix86_veclibabi_type_svml)
373
 
374
EnumValue
375
Enum(ix86_veclibabi) String(acml) Value(ix86_veclibabi_type_acml)
376
 
377
mvect8-ret-in-mem
378
Target Report Mask(VECT8_RETURNS) Save
379
Return 8-byte vectors in memory
380
 
381
mrecip
382
Target Report Mask(RECIP) Save
383
Generate reciprocals instead of divss and sqrtss.
384
 
385
mrecip=
386
Target Report RejectNegative Joined Var(ix86_recip_name)
387
Control generation of reciprocal estimates.
388
 
389
mcld
390
Target Report Mask(CLD) Save
391
Generate cld instruction in the function prologue.
392
 
393
mvzeroupper
394
Target Report Mask(VZEROUPPER) Save
395
Generate vzeroupper instruction before a transfer of control flow out of
396
the function.
397
 
398
mdispatch-scheduler
399
Target RejectNegative Var(flag_dispatch_scheduler)
400
Do dispatch scheduling if processor is bdver1 or bdver2 and Haifa scheduling
401
is selected.
402
 
403
mprefer-avx128
404
Target Report Mask(PREFER_AVX128) SAVE
405
Use 128-bit AVX instructions instead of 256-bit AVX instructions in the auto-vectorizer.
406
 
407
;; ISA support
408
 
409
m32
410
Target RejectNegative Negative(m64) Report InverseMask(ISA_64BIT) Var(ix86_isa_flags) Save
411
Generate 32bit i386 code
412
 
413
m64
414
Target RejectNegative Negative(mx32) Report Mask(ISA_64BIT) Var(ix86_isa_flags) Save
415
Generate 64bit x86-64 code
416
 
417
mx32
418
Target RejectNegative Negative(m32) Report Mask(ISA_X32) Var(ix86_isa_flags) Save
419
Generate 32bit x86-64 code
420
 
421
mmmx
422
Target Report Mask(ISA_MMX) Var(ix86_isa_flags) Save
423
Support MMX built-in functions
424
 
425
m3dnow
426
Target Report Mask(ISA_3DNOW) Var(ix86_isa_flags) Save
427
Support 3DNow! built-in functions
428
 
429
m3dnowa
430
Target Undocumented Mask(ISA_3DNOW_A) Var(ix86_isa_flags) Save
431
Support Athlon 3Dnow! built-in functions
432
 
433
msse
434
Target Report Mask(ISA_SSE) Var(ix86_isa_flags) Save
435
Support MMX and SSE built-in functions and code generation
436
 
437
msse2
438
Target Report Mask(ISA_SSE2) Var(ix86_isa_flags) Save
439
Support MMX, SSE and SSE2 built-in functions and code generation
440
 
441
msse3
442
Target Report Mask(ISA_SSE3) Var(ix86_isa_flags) Save
443
Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation
444
 
445
mssse3
446
Target Report Mask(ISA_SSSE3) Var(ix86_isa_flags) Save
447
Support MMX, SSE, SSE2, SSE3 and SSSE3 built-in functions and code generation
448
 
449
msse4.1
450
Target Report Mask(ISA_SSE4_1) Var(ix86_isa_flags) Save
451
Support MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 built-in functions and code generation
452
 
453
msse4.2
454
Target Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save
455
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation
456
 
457
msse4
458
Target RejectNegative Report Mask(ISA_SSE4_2) MaskExists Var(ix86_isa_flags) Save
459
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation
460
 
461
mno-sse4
462
Target RejectNegative Report InverseMask(ISA_SSE4_1) MaskExists Var(ix86_isa_flags) Save
463
Do not support SSE4.1 and SSE4.2 built-in functions and code generation
464
 
465
msse5
466
Target Undocumented Alias(mavx) Warn(%<-msse5%> was removed)
467
;; Deprecated
468
 
469
mavx
470
Target Report Mask(ISA_AVX) Var(ix86_isa_flags) Save
471
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 and AVX built-in functions and code generation
472
 
473
mavx2
474
Target Report Mask(ISA_AVX2) Var(ix86_isa_flags) Save
475
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and AVX2 built-in functions and code generation
476
 
477
mfma
478
Target Report Mask(ISA_FMA) Var(ix86_isa_flags) Save
479
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and FMA built-in functions and code generation
480
 
481
msse4a
482
Target Report Mask(ISA_SSE4A) Var(ix86_isa_flags) Save
483
Support MMX, SSE, SSE2, SSE3 and SSE4A built-in functions and code generation
484
 
485
mfma4
486
Target Report Mask(ISA_FMA4) Var(ix86_isa_flags) Save
487
Support FMA4 built-in functions and code generation
488
 
489
mxop
490
Target Report Mask(ISA_XOP) Var(ix86_isa_flags) Save
491
Support XOP built-in functions and code generation
492
 
493
mlwp
494
Target Report Mask(ISA_LWP) Var(ix86_isa_flags) Save
495
Support LWP built-in functions and code generation
496
 
497
mabm
498
Target Report Mask(ISA_ABM) Var(ix86_isa_flags) Save
499
Support code generation of Advanced Bit Manipulation (ABM) instructions.
500
 
501
mpopcnt
502
Target Report Mask(ISA_POPCNT) Var(ix86_isa_flags) Save
503
Support code generation of popcnt instruction.
504
 
505
mbmi
506
Target Report Mask(ISA_BMI) Var(ix86_isa_flags) Save
507
Support BMI built-in functions and code generation
508
 
509
mbmi2
510
Target Report Mask(ISA_BMI2) Var(ix86_isa_flags) Save
511
Support BMI2 built-in functions and code generation
512
 
513
mlzcnt
514
Target Report Mask(ISA_LZCNT) Var(ix86_isa_flags) Save
515
Support LZCNT built-in function and code generation
516
 
517
mtbm
518
Target Report Mask(ISA_TBM) Var(ix86_isa_flags) Save
519
Support TBM built-in functions and code generation
520
 
521
mcx16
522
Target Report Mask(ISA_CX16) Var(ix86_isa_flags) Save
523
Support code generation of cmpxchg16b instruction.
524
 
525
msahf
526
Target Report Mask(ISA_SAHF) Var(ix86_isa_flags) Save
527
Support code generation of sahf instruction in 64bit x86-64 code.
528
 
529
mmovbe
530
Target Report Mask(ISA_MOVBE) Var(ix86_isa_flags) Save
531
Support code generation of movbe instruction.
532
 
533
mcrc32
534
Target Report Mask(ISA_CRC32) Var(ix86_isa_flags) Save
535
Support code generation of crc32 instruction.
536
 
537
maes
538
Target Report Mask(ISA_AES) Var(ix86_isa_flags) Save
539
Support AES built-in functions and code generation
540
 
541
mpclmul
542
Target Report Mask(ISA_PCLMUL) Var(ix86_isa_flags) Save
543
Support PCLMUL built-in functions and code generation
544
 
545
msse2avx
546
Target Report Var(ix86_sse2avx)
547
Encode SSE instructions with VEX prefix
548
 
549
mfsgsbase
550
Target Report Mask(ISA_FSGSBASE) Var(ix86_isa_flags) Save
551
Support FSGSBASE built-in functions and code generation
552
 
553
mrdrnd
554
Target Report Mask(ISA_RDRND) Var(ix86_isa_flags) Save
555
Support RDRND built-in functions and code generation
556
 
557
mf16c
558
Target Report Mask(ISA_F16C) Var(ix86_isa_flags) Save
559
Support F16C built-in functions and code generation
560
 
561
mfentry
562
Target Report Var(flag_fentry) Init(-1)
563
Emit profiling counter call at function entry before prologue.
564
 
565
m8bit-idiv
566
Target Report Mask(USE_8BIT_IDIV) Save
567
Expand 32bit/64bit integer divide into 8bit unsigned integer divide with run-time check
568
 
569
mavx256-split-unaligned-load
570
Target Report Mask(AVX256_SPLIT_UNALIGNED_LOAD) Save
571
Split 32-byte AVX unaligned load
572
 
573
mavx256-split-unaligned-store
574
Target Report Mask(AVX256_SPLIT_UNALIGNED_STORE) Save
575
Split 32-byte AVX unaligned store

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