OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [config/] [ia64/] [vect.md] - Blame information for rev 848

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 709 jeremybenn 
;; IA-64 machine description for vector operations.
2 
;; Copyright (C) 2004, 2005, 2007, 2010 Free Software Foundation, Inc.
3 
;;
4 
;; This file is part of GCC.
5 
;;
6 
;; GCC is free software; you can redistribute it and/or modify
7 
;; it under the terms of the GNU General Public License as published by
8 
;; the Free Software Foundation; either version 3, or (at your option)
9 
;; any later version.
10 
;;
11 
;; GCC is distributed in the hope that it will be useful,
12 
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14 
;; GNU General Public License for more details.
15 
;;
16 
;; You should have received a copy of the GNU General Public License
17 
;; along with GCC; see the file COPYING3.  If not see
18 
;; .
19 
 
20 
 
21 
;; Integer vector operations
22 
 
23 
(define_mode_iterator VEC [V8QI V4HI V2SI V2SF])
24 
(define_mode_iterator VECINT [V8QI V4HI V2SI])
25 
(define_mode_iterator VECINT12 [V8QI V4HI])
26 
(define_mode_iterator VECINT24 [V4HI V2SI])
27 
(define_mode_attr vecsize [(V8QI "1") (V4HI "2") (V2SI "4")])
28 
(define_mode_attr vecwider [(V8QI "V4HI") (V4HI "V2SI")])
29 
(define_mode_attr vecint
30 
  [(V8QI "V8QI") (V4HI "V4HI") (V2SI "V2SI") (V2SF "V2SI")])
31 
 
32 
(define_expand "mov"
33 
  [(set (match_operand:VECINT 0 "general_operand" "")
34 
        (match_operand:VECINT 1 "general_operand" ""))]
35 
  ""
36 
{
37 
  rtx op1 = ia64_expand_move (operands[0], operands[1]);
38 
  if (!op1)
39 
    DONE;
40 
  operands[1] = op1;
41 
})
42 
 
43 
(define_insn "*mov_internal"
44 
  [(set (match_operand:VECINT 0 "destination_operand"
45 
                                        "=r,r,r,r,m ,*f ,*f,Q ,r ,*f")
46 
        (match_operand:VECINT 1 "move_operand"
47 
                                        "rU,W,i,m,rU,U*f,Q ,*f,*f,r "))]
48 
  "ia64_move_ok (operands[0], operands[1])"
49 
  "@
50 
   mov %0 = %r1
51 
   addl %0 = %v1, r0
52 
   movl %0 = %v1
53 
   ld8%O1 %0 = %1%P1
54 
   st8%Q0 %0 = %r1%P0
55 
   mov %0 = %F1
56 
   ldf8 %0 = %1%P1
57 
   stf8 %0 = %1%P0
58 
   getf.sig %0 = %1
59 
   setf.sig %0 = %1"
60 
  [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,fmisc,fld,stf,frfr,tofr")])
61 
 
62 
(define_insn "one_cmpl2"
63 
  [(set (match_operand:VECINT 0 "gr_register_operand" "=r")
64 
        (not:VECINT (match_operand:VECINT 1 "gr_register_operand" "r")))]
65 
  ""
66 
  "andcm %0 = -1, %1"
67 
  [(set_attr "itanium_class" "ilog")])
68 
 
69 
(define_insn "and3"
70 
  [(set (match_operand:VECINT 0 "grfr_register_operand" "=r,*f")
71 
        (and:VECINT
72 
          (match_operand:VECINT 1 "grfr_register_operand" "r,*f")
73 
          (match_operand:VECINT 2 "grfr_reg_or_8bit_operand" "r,*f")))]
74 
  ""
75 
  "@
76 
   and %0 = %2, %1
77 
   fand %0 = %2, %1"
78 
  [(set_attr "itanium_class" "ilog,fmisc")])
79 
 
80 
(define_insn "*andnot"
81 
  [(set (match_operand:VECINT 0 "grfr_register_operand" "=r,*f")
82 
        (and:VECINT
83 
          (not:VECINT (match_operand:VECINT 1 "grfr_register_operand" "r,*f"))
84 
          (match_operand:VECINT 2 "grfr_reg_or_8bit_operand" "r,*f")))]
85 
  ""
86 
  "@
87 
   andcm %0 = %2, %1
88 
   fandcm %0 = %2, %1"
89 
  [(set_attr "itanium_class" "ilog,fmisc")])
90 
 
91 
(define_insn "ior3"
92 
  [(set (match_operand:VECINT 0 "grfr_register_operand" "=r,*f")
93 
        (ior:VECINT
94 
          (match_operand:VECINT 1 "grfr_register_operand" "r,*f")
95 
          (match_operand:VECINT 2 "grfr_reg_or_8bit_operand" "r,*f")))]
96 
  ""
97 
  "@
98 
   or %0 = %2, %1
99 
   for %0 = %2, %1"
100 
  [(set_attr "itanium_class" "ilog,fmisc")])
101 
 
102 
(define_insn "xor3"
103 
  [(set (match_operand:VECINT 0 "grfr_register_operand" "=r,*f")
104 
        (xor:VECINT
105 
          (match_operand:VECINT 1 "grfr_register_operand" "r,*f")
106 
          (match_operand:VECINT 2 "grfr_reg_or_8bit_operand" "r,*f")))]
107 
  ""
108 
  "@
109 
   xor %0 = %2, %1
110 
   fxor %0 = %2, %1"
111 
  [(set_attr "itanium_class" "ilog,fmisc")])
112 
 
113 
(define_insn "neg2"
114 
  [(set (match_operand:VECINT 0 "gr_register_operand" "=r")
115 
        (neg:VECINT (match_operand:VECINT 1 "gr_register_operand" "r")))]
116 
  ""
117 
  "psub %0 = r0, %1"
118 
  [(set_attr "itanium_class" "mmalua")])
119 
 
120 
(define_insn "add3"
121 
  [(set (match_operand:VECINT 0 "gr_register_operand" "=r")
122 
        (plus:VECINT (match_operand:VECINT 1 "gr_register_operand" "r")
123 
                     (match_operand:VECINT 2 "gr_register_operand" "r")))]
124 
  ""
125 
  "padd %0 = %1, %2"
126 
  [(set_attr "itanium_class" "mmalua")])
127 
 
128 
(define_insn "*ssadd3"
129 
  [(set (match_operand:VECINT12 0 "gr_register_operand" "=r")
130 
        (ss_plus:VECINT12
131 
          (match_operand:VECINT12 1 "gr_register_operand" "r")
132 
          (match_operand:VECINT12 2 "gr_register_operand" "r")))]
133 
  ""
134 
  "padd.sss %0 = %1, %2"
135 
  [(set_attr "itanium_class" "mmalua")])
136 
 
137 
(define_insn "*usadd3"
138 
  [(set (match_operand:VECINT12 0 "gr_register_operand" "=r")
139 
        (us_plus:VECINT12
140 
          (match_operand:VECINT12 1 "gr_register_operand" "r")
141 
          (match_operand:VECINT12 2 "gr_register_operand" "r")))]
142 
  ""
143 
  "padd.uuu %0 = %1, %2"
144 
  [(set_attr "itanium_class" "mmalua")])
145 
 
146 
(define_insn "sub3"
147 
  [(set (match_operand:VECINT 0 "gr_register_operand" "=r")
148 
        (minus:VECINT (match_operand:VECINT 1 "gr_register_operand" "r")
149 
                      (match_operand:VECINT 2 "gr_register_operand" "r")))]
150 
  ""
151 
  "psub %0 = %1, %2"
152 
  [(set_attr "itanium_class" "mmalua")])
153 
 
154 
(define_insn "*sssub3"
155 
  [(set (match_operand:VECINT12 0 "gr_register_operand" "=r")
156 
        (ss_minus:VECINT12
157 
          (match_operand:VECINT12 1 "gr_register_operand" "r")
158 
          (match_operand:VECINT12 2 "gr_register_operand" "r")))]
159 
  ""
160 
  "psub.sss %0 = %1, %2"
161 
  [(set_attr "itanium_class" "mmalua")])
162 
 
163 
(define_insn "*ussub3"
164 
  [(set (match_operand:VECINT12 0 "gr_register_operand" "=r")
165 
        (us_minus:VECINT12
166 
          (match_operand:VECINT12 1 "gr_register_operand" "r")
167 
          (match_operand:VECINT12 2 "gr_register_operand" "r")))]
168 
  ""
169 
  "psub.uuu %0 = %1, %2"
170 
  [(set_attr "itanium_class" "mmalua")])
171 
 
172 
(define_expand "mulv8qi3"
173 
  [(set (match_operand:V8QI 0 "gr_register_operand" "")
174 
        (mult:V8QI (match_operand:V8QI 1 "gr_register_operand" "r")
175 
                   (match_operand:V8QI 2 "gr_register_operand" "r")))]
176 
  ""
177 
{
178 
  rtx l = gen_reg_rtx (V4HImode);
179 
  rtx h = gen_reg_rtx (V4HImode);
180 
  emit_insn (gen_vec_widen_umult_lo_v8qi (l, operands[1], operands[2]));
181 
  emit_insn (gen_vec_widen_umult_hi_v8qi (h, operands[1], operands[2]));
182 
  if (TARGET_BIG_ENDIAN)
183 
    emit_insn (gen_vec_pack_trunc_v4hi (operands[0], h, l));
184 
  else
185 
    emit_insn (gen_vec_pack_trunc_v4hi (operands[0], l, h));
186 
  DONE;
187 
})
188 
 
189 
(define_expand "vec_widen_umult_lo_v8qi"
190 
  [(match_operand:V4HI 0 "gr_register_operand" "")
191 
   (match_operand:V8QI 1 "gr_register_operand" "")
192 
   (match_operand:V8QI 2 "gr_register_operand" "")]
193 
  ""
194 
{
195 
  rtx op1 = gen_reg_rtx (V4HImode);
196 
  rtx op2 = gen_reg_rtx (V4HImode);
197 
  emit_insn (gen_vec_unpacku_lo_v8qi (op1, operands[1]));
198 
  emit_insn (gen_vec_unpacku_lo_v8qi (op2, operands[2]));
199 
  emit_insn (gen_mulv4hi3 (operands[0], op1, op2));
200 
  DONE;
201 
});
202 
 
203 
(define_expand "vec_widen_umult_hi_v8qi"
204 
  [(match_operand:V4HI 0 "gr_register_operand" "")
205 
   (match_operand:V8QI 1 "gr_register_operand" "")
206 
   (match_operand:V8QI 2 "gr_register_operand" "")]
207 
  ""
208 
{
209 
  rtx op1 = gen_reg_rtx (V4HImode);
210 
  rtx op2 = gen_reg_rtx (V4HImode);
211 
  emit_insn (gen_vec_unpacku_hi_v8qi (op1, operands[1]));
212 
  emit_insn (gen_vec_unpacku_hi_v8qi (op2, operands[2]));
213 
  emit_insn (gen_mulv4hi3 (operands[0], op1, op2));
214 
  DONE;
215 
});
216 
 
217 
(define_expand "vec_widen_smult_lo_v8qi"
218 
  [(match_operand:V4HI 0 "gr_register_operand" "")
219 
   (match_operand:V8QI 1 "gr_register_operand" "")
220 
   (match_operand:V8QI 2 "gr_register_operand" "")]
221 
  ""
222 
{
223 
  rtx op1 = gen_reg_rtx (V4HImode);
224 
  rtx op2 = gen_reg_rtx (V4HImode);
225 
  emit_insn (gen_vec_unpacks_lo_v8qi (op1, operands[1]));
226 
  emit_insn (gen_vec_unpacks_lo_v8qi (op2, operands[2]));
227 
  emit_insn (gen_mulv4hi3 (operands[0], op1, op2));
228 
  DONE;
229 
});
230 
 
231 
(define_expand "vec_widen_smult_hi_v8qi"
232 
  [(match_operand:V4HI 0 "gr_register_operand" "")
233 
   (match_operand:V8QI 1 "gr_register_operand" "")
234 
   (match_operand:V8QI 2 "gr_register_operand" "")]
235 
  ""
236 
{
237 
  rtx op1 = gen_reg_rtx (V4HImode);
238 
  rtx op2 = gen_reg_rtx (V4HImode);
239 
  emit_insn (gen_vec_unpacks_hi_v8qi (op1, operands[1]));
240 
  emit_insn (gen_vec_unpacks_hi_v8qi (op2, operands[2]));
241 
  emit_insn (gen_mulv4hi3 (operands[0], op1, op2));
242 
  DONE;
243 
});
244 
 
245 
(define_insn "mulv4hi3"
246 
  [(set (match_operand:V4HI 0 "gr_register_operand" "=r")
247 
        (mult:V4HI (match_operand:V4HI 1 "gr_register_operand" "r")
248 
                   (match_operand:V4HI 2 "gr_register_operand" "r")))]
249 
  ""
250 
  "pmpyshr2 %0 = %1, %2, 0"
251 
  [(set_attr "itanium_class" "mmmul")])
252 
 
253 
(define_insn "pmpyshr2"
254 
  [(set (match_operand:V4HI 0 "gr_register_operand" "=r")
255 
        (truncate:V4HI
256 
          (ashiftrt:V4SI
257 
            (mult:V4SI
258 
              (sign_extend:V4SI
259 
                (match_operand:V4HI 1 "gr_register_operand" "r"))
260 
              (sign_extend:V4SI
261 
                (match_operand:V4HI 2 "gr_register_operand" "r")))
262 
            (match_operand:SI 3 "pmpyshr_operand" "n"))))]
263 
  ""
264 
  "pmpyshr2 %0 = %1, %2, %3"
265 
  [(set_attr "itanium_class" "mmmul")])
266 
 
267 
(define_insn "pmpyshr2_u"
268 
  [(set (match_operand:V4HI 0 "gr_register_operand" "=r")
269 
        (truncate:V4HI
270 
          (lshiftrt:V4SI
271 
            (mult:V4SI
272 
              (zero_extend:V4SI
273 
                (match_operand:V4HI 1 "gr_register_operand" "r"))
274 
              (zero_extend:V4SI
275 
                (match_operand:V4HI 2 "gr_register_operand" "r")))
276 
            (match_operand:SI 3 "pmpyshr_operand" "n"))))]
277 
  ""
278 
  "pmpyshr2.u %0 = %1, %2, %3"
279 
  [(set_attr "itanium_class" "mmmul")])
280 
 
281 
(define_insn "pmpy2_even"
282 
  [(set (match_operand:V2SI 0 "gr_register_operand" "=r")
283 
        (mult:V2SI
284 
          (vec_select:V2SI
285 
            (sign_extend:V4SI
286 
              (match_operand:V4HI 1 "gr_register_operand" "r"))
287 
            (parallel [(const_int 0) (const_int 2)]))
288 
          (vec_select:V2SI
289 
            (sign_extend:V4SI
290 
              (match_operand:V4HI 2 "gr_register_operand" "r"))
291 
            (parallel [(const_int 0) (const_int 2)]))))]
292 
  ""
293 
{
294 
  /* Recall that vector elements are numbered in memory order.  */
295 
  if (TARGET_BIG_ENDIAN)
296 
    return "%,pmpy2.l %0 = %1, %2";
297 
  else
298 
    return "%,pmpy2.r %0 = %1, %2";
299 
}
300 
  [(set_attr "itanium_class" "mmshf")])
301 
 
302 
(define_insn "pmpy2_odd"
303 
  [(set (match_operand:V2SI 0 "gr_register_operand" "=r")
304 
        (mult:V2SI
305 
          (vec_select:V2SI
306 
            (sign_extend:V4SI
307 
              (match_operand:V4HI 1 "gr_register_operand" "r"))
308 
            (parallel [(const_int 1) (const_int 3)]))
309 
          (vec_select:V2SI
310 
            (sign_extend:V4SI
311 
              (match_operand:V4HI 2 "gr_register_operand" "r"))
312 
            (parallel [(const_int 1) (const_int 3)]))))]
313 
  ""
314 
{
315 
  /* Recall that vector elements are numbered in memory order.  */
316 
  if (TARGET_BIG_ENDIAN)
317 
    return "%,pmpy2.r %0 = %1, %2";
318 
  else
319 
    return "%,pmpy2.l %0 = %1, %2";
320 
}
321 
  [(set_attr "itanium_class" "mmshf")])
322 
 
323 
(define_expand "vec_widen_smult_lo_v4hi"
324 
  [(match_operand:V2SI 0 "gr_register_operand" "")
325 
   (match_operand:V4HI 1 "gr_register_operand" "")
326 
   (match_operand:V4HI 2 "gr_register_operand" "")]
327 
  ""
328 
{
329 
  rtx l = gen_reg_rtx (V4HImode);
330 
  rtx h = gen_reg_rtx (V4HImode);
331 
  emit_insn (gen_mulv4hi3 (l, operands[1], operands[2]));
332 
  emit_insn (gen_pmpyshr2 (h, operands[1], operands[2], GEN_INT (16)));
333 
  ia64_unpack_assemble (operands[0], l, h, false);
334 
  DONE;
335 
})
336 
 
337 
(define_expand "vec_widen_smult_hi_v4hi"
338 
  [(match_operand:V2SI 0 "gr_register_operand" "")
339 
   (match_operand:V4HI 1 "gr_register_operand" "")
340 
   (match_operand:V4HI 2 "gr_register_operand" "")]
341 
  ""
342 
{
343 
  rtx l = gen_reg_rtx (V4HImode);
344 
  rtx h = gen_reg_rtx (V4HImode);
345 
  emit_insn (gen_mulv4hi3 (l, operands[1], operands[2]));
346 
  emit_insn (gen_pmpyshr2 (h, operands[1], operands[2], GEN_INT (16)));
347 
  ia64_unpack_assemble (operands[0], l, h, true);
348 
  DONE;
349 
})
350 
 
351 
(define_expand "vec_widen_umult_lo_v4hi"
352 
  [(match_operand:V2SI 0 "gr_register_operand" "")
353 
   (match_operand:V4HI 1 "gr_register_operand" "")
354 
   (match_operand:V4HI 2 "gr_register_operand" "")]
355 
  ""
356 
{
357 
  rtx l = gen_reg_rtx (V4HImode);
358 
  rtx h = gen_reg_rtx (V4HImode);
359 
  emit_insn (gen_mulv4hi3 (l, operands[1], operands[2]));
360 
  emit_insn (gen_pmpyshr2_u (h, operands[1], operands[2], GEN_INT (16)));
361 
  ia64_unpack_assemble (operands[0], l, h, false);
362 
  DONE;
363 
})
364 
 
365 
(define_expand "vec_widen_umult_hi_v4hi"
366 
  [(match_operand:V2SI 0 "gr_register_operand" "")
367 
   (match_operand:V4HI 1 "gr_register_operand" "")
368 
   (match_operand:V4HI 2 "gr_register_operand" "")]
369 
  ""
370 
{
371 
  rtx l = gen_reg_rtx (V4HImode);
372 
  rtx h = gen_reg_rtx (V4HImode);
373 
  emit_insn (gen_mulv4hi3 (l, operands[1], operands[2]));
374 
  emit_insn (gen_pmpyshr2_u (h, operands[1], operands[2], GEN_INT (16)));
375 
  ia64_unpack_assemble (operands[0], l, h, true);
376 
  DONE;
377 
})
378 
 
379 
(define_expand "mulv2si3"
380 
  [(set (match_operand:V2SI 0 "gr_register_operand" "")
381 
        (mult:V2SI (match_operand:V2SI 1 "gr_register_operand" "r")
382 
                   (match_operand:V2SI 2 "gr_register_operand" "r")))]
383 
  ""
384 
{
385 
  rtx t0, t1, t2, t3, t4, t5, t6, t7, x;
386 
  rtx op1h = gen_lowpart (V4HImode, operands[1]);
387 
  rtx op2h = gen_lowpart (V4HImode, operands[2]);
388 
 
389 
  t0 = gen_reg_rtx (V4HImode);
390 
  t1 = gen_reg_rtx (V4HImode);
391 
  t2 = gen_reg_rtx (V4HImode);
392 
  t3 = gen_reg_rtx (V4HImode);
393 
  t4 = gen_reg_rtx (V2SImode);
394 
  t5 = gen_reg_rtx (V2SImode);
395 
  t6 = gen_reg_rtx (V2SImode);
396 
  t7 = gen_reg_rtx (V2SImode);
397 
 
398 
  /* Consider the HImode components of op1 = DCBA, op2 = ZYXW.
399 
     Consider .l and .h suffixes below the low and high 16 bits
400 
     of the full 32-bit product.  */
401 
 
402 
  /* T0 = CDBA.  */
403 
  x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (4, const1_rtx, const0_rtx,
404 
                                             GEN_INT (3), const2_rtx));
405 
  x = gen_rtx_VEC_SELECT (V4HImode, op1h, x);
406 
  emit_insn (gen_rtx_SET (VOIDmode, t0, x));
407 
 
408 
  /* T1 = DZ.l, CY.l, BX.l, AW.l.  */
409 
  emit_insn (gen_mulv4hi3 (t1, op1h, op2h));
410 
 
411 
  /* T2 = DZ.h, CY.h, BX.h, AW.h.  */
412 
  emit_insn (gen_pmpyshr2_u (t2, op1h, op2h, GEN_INT (16)));
413 
 
414 
  /* T3 = CZ.l, DY.l, AX.l, BW.l.  */
415 
  emit_insn (gen_mulv4hi3 (t3, t0, op2h));
416 
 
417 
  /* T4 = CY.h, CY.l, AW.h, AW.l = CY, AW.  */
418 
  x = gen_lowpart (V4HImode, t4);
419 
  if (TARGET_BIG_ENDIAN)
420 
    x = gen_mix2_odd (x, t2, t1);
421 
  else
422 
    x = gen_mix2_even (x, t1, t2);
423 
  emit_insn (x);
424 
 
425 
  /* T5 = CZ.l, 0, AX.l, 0 = CZ << 16, AX << 16.  */
426 
  x = gen_lowpart (V4HImode, t5);
427 
  if (TARGET_BIG_ENDIAN)
428 
    x = gen_mix2_even (x, t3, CONST0_RTX (V4HImode));
429 
  else
430 
    x = gen_mix2_odd (x, CONST0_RTX (V4HImode), t3);
431 
  emit_insn (x);
432 
 
433 
  /* T6 = DY.l, 0, BW.l, 0 = DY << 16, BW << 16.  */
434 
  x = gen_lowpart (V4HImode, t6);
435 
  if (TARGET_BIG_ENDIAN)
436 
    x = gen_mix2_odd (x, t3, CONST0_RTX (V4HImode));
437 
  else
438 
    x = gen_mix2_even (x, CONST0_RTX (V4HImode), t3);
439 
  emit_insn (x);
440 
 
441 
  emit_insn (gen_addv2si3 (t7, t4, t5));
442 
  emit_insn (gen_addv2si3 (operands[0], t6, t7));
443 
  DONE;
444 
})
445 
 
446 
(define_expand "umax3"
447 
  [(set (match_operand:VECINT 0 "gr_register_operand" "")
448 
        (umax:VECINT (match_operand:VECINT 1 "gr_register_operand" "")
449 
                     (match_operand:VECINT 2 "gr_register_operand" "")))]
450 
  ""
451 
{
452 
  if (ia64_expand_vecint_minmax (UMAX, mode, operands))
453 
    DONE;
454 
})
455 
 
456 
(define_expand "smax3"
457 
  [(set (match_operand:VECINT 0 "gr_register_operand" "")
458 
        (smax:VECINT (match_operand:VECINT 1 "gr_reg_or_0_operand" "")
459 
                     (match_operand:VECINT 2 "gr_reg_or_0_operand" "")))]
460 
  ""
461 
{
462 
  if (ia64_expand_vecint_minmax (SMAX, mode, operands))
463 
    DONE;
464 
})
465 
 
466 
(define_expand "umin3"
467 
  [(set (match_operand:VECINT 0 "gr_register_operand" "")
468 
        (umin:VECINT (match_operand:VECINT 1 "gr_register_operand" "")
469 
                     (match_operand:VECINT 2 "gr_register_operand" "")))]
470 
  ""
471 
{
472 
  if (ia64_expand_vecint_minmax (UMIN, mode, operands))
473 
    DONE;
474 
})
475 
 
476 
(define_expand "smin3"
477 
  [(set (match_operand:VECINT 0 "gr_register_operand" "")
478 
        (smin:VECINT (match_operand:VECINT 1 "gr_reg_or_0_operand" "")
479 
                     (match_operand:VECINT 2 "gr_reg_or_0_operand" "")))]
480 
  ""
481 
{
482 
  if (ia64_expand_vecint_minmax (SMIN, mode, operands))
483 
    DONE;
484 
})
485 
 
486 
(define_insn "*umaxv8qi3"
487 
  [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
488 
        (umax:V8QI (match_operand:V8QI 1 "gr_register_operand" "r")
489 
                   (match_operand:V8QI 2 "gr_register_operand" "r")))]
490 
  ""
491 
  "pmax1.u %0 = %1, %2"
492 
  [(set_attr "itanium_class" "mmshf")])
493 
 
494 
(define_insn "*smaxv4hi3"
495 
  [(set (match_operand:V4HI 0 "gr_register_operand" "=r")
496 
        (smax:V4HI (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU")
497 
                   (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU")))]
498 
  ""
499 
  "pmax2 %0 = %r1, %r2"
500 
  [(set_attr "itanium_class" "mmshf")])
501 
 
502 
(define_insn "*uminv8qi3"
503 
  [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
504 
        (umin:V8QI (match_operand:V8QI 1 "gr_register_operand" "r")
505 
                   (match_operand:V8QI 2 "gr_register_operand" "r")))]
506 
  ""
507 
  "pmin1.u %0 = %1, %2"
508 
  [(set_attr "itanium_class" "mmshf")])
509 
 
510 
(define_insn "*sminv4hi3"
511 
  [(set (match_operand:V4HI 0 "gr_register_operand" "=r")
512 
        (smin:V4HI (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU")
513 
                   (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU")))]
514 
  ""
515 
  "pmin2 %0 = %r1, %r2"
516 
  [(set_attr "itanium_class" "mmshf")])
517 
 
518 
(define_insn "ashl3"
519 
  [(set (match_operand:VECINT24 0 "gr_register_operand" "=r")
520 
        (ashift:VECINT24
521 
          (match_operand:VECINT24 1 "gr_register_operand" "r")
522 
          (match_operand:DI 2 "gr_reg_or_5bit_operand" "rn")))]
523 
  ""
524 
  "pshl %0 = %1, %2"
525 
  [(set_attr "itanium_class" "mmshf")])
526 
 
527 
(define_insn "ashr3"
528 
  [(set (match_operand:VECINT24 0 "gr_register_operand" "=r")
529 
        (ashiftrt:VECINT24
530 
          (match_operand:VECINT24 1 "gr_register_operand" "r")
531 
          (match_operand:DI 2 "gr_reg_or_5bit_operand" "rn")))]
532 
  ""
533 
  "pshr %0 = %1, %2"
534 
  [(set_attr "itanium_class" "mmshf")])
535 
 
536 
(define_insn "lshr3"
537 
  [(set (match_operand:VECINT24 0 "gr_register_operand" "=r")
538 
        (lshiftrt:VECINT24
539 
          (match_operand:VECINT24 1 "gr_register_operand" "r")
540 
          (match_operand:DI 2 "gr_reg_or_5bit_operand" "rn")))]
541 
  ""
542 
  "pshr.u %0 = %1, %2"
543 
  [(set_attr "itanium_class" "mmshf")])
544 
 
545 
(define_expand "vec_shl_"
546 
  [(set (match_operand:VECINT 0 "gr_register_operand" "")
547 
        (ashift:DI (match_operand:VECINT 1 "gr_register_operand" "")
548 
                   (match_operand:DI 2 "gr_reg_or_6bit_operand" "")))]
549 
  ""
550 
{
551 
  operands[0] = gen_lowpart (DImode, operands[0]);
552 
  operands[1] = gen_lowpart (DImode, operands[1]);
553 
})
554 
 
555 
(define_expand "vec_shr_"
556 
  [(set (match_operand:VECINT 0 "gr_register_operand" "")
557 
        (lshiftrt:DI (match_operand:VECINT 1 "gr_register_operand" "")
558 
                     (match_operand:DI 2 "gr_reg_or_6bit_operand" "")))]
559 
  ""
560 
{
561 
  operands[0] = gen_lowpart (DImode, operands[0]);
562 
  operands[1] = gen_lowpart (DImode, operands[1]);
563 
})
564 
 
565 
(define_expand "widen_usumv8qi3"
566 
  [(match_operand:V4HI 0 "gr_register_operand" "")
567 
   (match_operand:V8QI 1 "gr_register_operand" "")
568 
   (match_operand:V4HI 2 "gr_register_operand" "")]
569 
  ""
570 
{
571 
  ia64_expand_widen_sum (operands, true);
572 
  DONE;
573 
})
574 
 
575 
(define_expand "widen_usumv4hi3"
576 
  [(match_operand:V2SI 0 "gr_register_operand" "")
577 
   (match_operand:V4HI 1 "gr_register_operand" "")
578 
   (match_operand:V2SI 2 "gr_register_operand" "")]
579 
  ""
580 
{
581 
  ia64_expand_widen_sum (operands, true);
582 
  DONE;
583 
})
584 
 
585 
(define_expand "widen_ssumv8qi3"
586 
  [(match_operand:V4HI 0 "gr_register_operand" "")
587 
   (match_operand:V8QI 1 "gr_register_operand" "")
588 
   (match_operand:V4HI 2 "gr_register_operand" "")]
589 
  ""
590 
{
591 
  ia64_expand_widen_sum (operands, false);
592 
  DONE;
593 
})
594 
 
595 
(define_expand "widen_ssumv4hi3"
596 
  [(match_operand:V2SI 0 "gr_register_operand" "")
597 
   (match_operand:V4HI 1 "gr_register_operand" "")
598 
   (match_operand:V2SI 2 "gr_register_operand" "")]
599 
  ""
600 
{
601 
  ia64_expand_widen_sum (operands, false);
602 
  DONE;
603 
})
604 
 
605 
(define_expand "udot_prodv8qi"
606 
  [(match_operand:V2SI 0 "gr_register_operand" "")
607 
   (match_operand:V8QI 1 "gr_register_operand" "")
608 
   (match_operand:V8QI 2 "gr_register_operand" "")
609 
   (match_operand:V2SI 3 "gr_register_operand" "")]
610 
  ""
611 
{
612 
  ia64_expand_dot_prod_v8qi (operands, true);
613 
  DONE;
614 
})
615 
 
616 
(define_expand "sdot_prodv8qi"
617 
  [(match_operand:V2SI 0 "gr_register_operand" "")
618 
   (match_operand:V8QI 1 "gr_register_operand" "")
619 
   (match_operand:V8QI 2 "gr_register_operand" "")
620 
   (match_operand:V2SI 3 "gr_register_operand" "")]
621 
  ""
622 
{
623 
  ia64_expand_dot_prod_v8qi (operands, false);
624 
  DONE;
625 
})
626 
 
627 
(define_expand "sdot_prodv4hi"
628 
  [(match_operand:V2SI 0 "gr_register_operand" "")
629 
   (match_operand:V4HI 1 "gr_register_operand" "")
630 
   (match_operand:V4HI 2 "gr_register_operand" "")
631 
   (match_operand:V2SI 3 "gr_register_operand" "")]
632 
  ""
633 
{
634 
  rtx e, o, t;
635 
 
636 
  e = gen_reg_rtx (V2SImode);
637 
  o = gen_reg_rtx (V2SImode);
638 
  t = gen_reg_rtx (V2SImode);
639 
 
640 
  emit_insn (gen_pmpy2_even (e, operands[1], operands[2]));
641 
  emit_insn (gen_pmpy2_odd (o, operands[1], operands[2]));
642 
  emit_insn (gen_addv2si3 (t, e, operands[3]));
643 
  emit_insn (gen_addv2si3 (operands[0], t, o));
644 
  DONE;
645 
})
646 
 
647 
(define_expand "udot_prodv4hi"
648 
  [(match_operand:V2SI 0 "gr_register_operand" "")
649 
   (match_operand:V4HI 1 "gr_register_operand" "")
650 
   (match_operand:V4HI 2 "gr_register_operand" "")
651 
   (match_operand:V2SI 3 "gr_register_operand" "")]
652 
  ""
653 
{
654 
  rtx l, h, t;
655 
 
656 
  l = gen_reg_rtx (V2SImode);
657 
  h = gen_reg_rtx (V2SImode);
658 
  t = gen_reg_rtx (V2SImode);
659 
 
660 
  emit_insn (gen_vec_widen_umult_lo_v4hi (l, operands[1], operands[2]));
661 
  emit_insn (gen_vec_widen_umult_hi_v4hi (h, operands[1], operands[2]));
662 
  emit_insn (gen_addv2si3 (t, l, operands[3]));
663 
  emit_insn (gen_addv2si3 (operands[0], t, h));
664 
  DONE;
665 
})
666 
 
667 
(define_expand "vcond"
668 
  [(set (match_operand:VECINT 0 "gr_register_operand" "")
669 
        (if_then_else:VECINT
670 
          (match_operator 3 ""
671 
            [(match_operand:VECINT 4 "gr_reg_or_0_operand" "")
672 
             (match_operand:VECINT 5 "gr_reg_or_0_operand" "")])
673 
          (match_operand:VECINT 1 "gr_reg_or_0_operand" "")
674 
          (match_operand:VECINT 2 "gr_reg_or_0_operand" "")))]
675 
  ""
676 
{
677 
  ia64_expand_vecint_cmov (operands);
678 
  DONE;
679 
})
680 
 
681 
(define_expand "vcondu"
682 
  [(set (match_operand:VECINT 0 "gr_register_operand" "")
683 
        (if_then_else:VECINT
684 
          (match_operator 3 ""
685 
            [(match_operand:VECINT 4 "gr_reg_or_0_operand" "")
686 
             (match_operand:VECINT 5 "gr_reg_or_0_operand" "")])
687 
          (match_operand:VECINT 1 "gr_reg_or_0_operand" "")
688 
          (match_operand:VECINT 2 "gr_reg_or_0_operand" "")))]
689 
  ""
690 
{
691 
  ia64_expand_vecint_cmov (operands);
692 
  DONE;
693 
})
694 
 
695 
(define_insn "*cmpeq_"
696 
  [(set (match_operand:VECINT 0 "gr_register_operand" "=r")
697 
        (eq:VECINT (match_operand:VECINT 1 "gr_reg_or_0_operand" "rU")
698 
                   (match_operand:VECINT 2 "gr_reg_or_0_operand" "rU")))]
699 
  ""
700 
  "pcmp.eq %0 = %r1, %r2"
701 
  [(set_attr "itanium_class" "mmalua")])
702 
 
703 
(define_insn "*cmpgt_"
704 
  [(set (match_operand:VECINT 0 "gr_register_operand" "=r")
705 
        (gt:VECINT (match_operand:VECINT 1 "gr_reg_or_0_operand" "rU")
706 
                   (match_operand:VECINT 2 "gr_reg_or_0_operand" "rU")))]
707 
  ""
708 
  "pcmp.gt %0 = %r1, %r2"
709 
  [(set_attr "itanium_class" "mmalua")])
710 
 
711 
(define_insn "vec_pack_ssat_v4hi"
712 
  [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
713 
        (vec_concat:V8QI
714 
          (ss_truncate:V4QI
715 
            (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU"))
716 
          (ss_truncate:V4QI
717 
            (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU"))))]
718 
  ""
719 
{
720 
  /* Recall that vector elements are numbered in memory order.  */
721 
  if (TARGET_BIG_ENDIAN)
722 
    return "%,pack2.sss %0 = %r2, %r1";
723 
  else
724 
    return "%,pack2.sss %0 = %r1, %r2";
725 
}
726 
  [(set_attr "itanium_class" "mmshf")])
727 
 
728 
(define_insn "vec_pack_usat_v4hi"
729 
  [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
730 
        (vec_concat:V8QI
731 
          (us_truncate:V4QI
732 
            (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU"))
733 
          (us_truncate:V4QI
734 
            (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU"))))]
735 
  ""
736 
{
737 
  /* Recall that vector elements are numbered in memory order.  */
738 
  if (TARGET_BIG_ENDIAN)
739 
    return "%,pack2.uss %0 = %r2, %r1";
740 
  else
741 
    return "%,pack2.uss %0 = %r1, %r2";
742 
}
743 
  [(set_attr "itanium_class" "mmshf")])
744 
 
745 
(define_insn "vec_pack_ssat_v2si"
746 
  [(set (match_operand:V4HI 0 "gr_register_operand" "=r")
747 
        (vec_concat:V4HI
748 
          (ss_truncate:V2HI
749 
            (match_operand:V2SI 1 "gr_reg_or_0_operand" "rU"))
750 
          (ss_truncate:V2HI
751 
            (match_operand:V2SI 2 "gr_reg_or_0_operand" "rU"))))]
752 
  ""
753 
{
754 
  /* Recall that vector elements are numbered in memory order.  */
755 
  if (TARGET_BIG_ENDIAN)
756 
    return "%,pack4.sss %0 = %r2, %r1";
757 
  else
758 
    return "%,pack4.sss %0 = %r1, %r2";
759 
}
760 
  [(set_attr "itanium_class" "mmshf")])
761 
 
762 
(define_insn "*vec_interleave_lowv8qi"
763 
  [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
764 
        (vec_select:V8QI
765 
          (vec_concat:V16QI
766 
            (match_operand:V8QI 1 "gr_reg_or_0_operand" "rU")
767 
            (match_operand:V8QI 2 "gr_reg_or_0_operand" "rU"))
768 
          (parallel [(const_int 0) (const_int 8)
769 
                     (const_int 1) (const_int 9)
770 
                     (const_int 2) (const_int 10)
771 
                     (const_int 3) (const_int 11)])))]
772 
  ""
773 
{
774 
  /* Recall that vector elements are numbered in memory order.  */
775 
  if (TARGET_BIG_ENDIAN)
776 
    return "%,unpack1.l %0 = %r1, %r2";
777 
  else
778 
    return "%,unpack1.l %0 = %r2, %r1";
779 
}
780 
  [(set_attr "itanium_class" "mmshf")])
781 
 
782 
(define_insn "*vec_interleave_highv8qi"
783 
  [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
784 
        (vec_select:V8QI
785 
          (vec_concat:V16QI
786 
            (match_operand:V8QI 1 "gr_reg_or_0_operand" "rU")
787 
            (match_operand:V8QI 2 "gr_reg_or_0_operand" "rU"))
788 
          (parallel [(const_int 4) (const_int 12)
789 
                     (const_int 5) (const_int 13)
790 
                     (const_int 6) (const_int 14)
791 
                     (const_int 7) (const_int 15)])))]
792 
  ""
793 
{
794 
  /* Recall that vector elements are numbered in memory order.  */
795 
  if (TARGET_BIG_ENDIAN)
796 
    return "%,unpack1.h %0 = %r1, %r2";
797 
  else
798 
    return "%,unpack1.h %0 = %r2, %r1";
799 
}
800 
  [(set_attr "itanium_class" "mmshf")])
801 
 
802 
(define_insn "*mix1_even"
803 
  [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
804 
        (vec_select:V8QI
805 
          (vec_concat:V16QI
806 
            (match_operand:V8QI 1 "gr_reg_or_0_operand" "rU")
807 
            (match_operand:V8QI 2 "gr_reg_or_0_operand" "rU"))
808 
          (parallel [(const_int 0) (const_int 8)
809 
                     (const_int 2) (const_int 10)
810 
                     (const_int 4) (const_int 12)
811 
                     (const_int 6) (const_int 14)])))]
812 
  ""
813 
{
814 
  /* Recall that vector elements are numbered in memory order.  */
815 
  if (TARGET_BIG_ENDIAN)
816 
    return "%,mix1.l %0 = %r1, %r2";
817 
  else
818 
    return "%,mix1.r %0 = %r2, %r1";
819 
}
820 
  [(set_attr "itanium_class" "mmshf")])
821 
 
822 
(define_insn "*mix1_odd"
823 
  [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
824 
        (vec_select:V8QI
825 
          (vec_concat:V16QI
826 
            (match_operand:V8QI 1 "gr_reg_or_0_operand" "rU")
827 
            (match_operand:V8QI 2 "gr_reg_or_0_operand" "rU"))
828 
          (parallel [(const_int 1) (const_int 9)
829 
                     (const_int 3) (const_int 11)
830 
                     (const_int 5) (const_int 13)
831 
                     (const_int 7) (const_int 15)])))]
832 
  ""
833 
{
834 
  /* Recall that vector elements are numbered in memory order.  */
835 
  if (TARGET_BIG_ENDIAN)
836 
    return "%,mix1.r %0 = %r1, %r2";
837 
  else
838 
    return "%,mix1.l %0 = %r2, %r1";
839 
}
840 
  [(set_attr "itanium_class" "mmshf")])
841 
 
842 
(define_insn "*mux1_rev"
843 
  [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
844 
        (vec_select:V8QI
845 
          (match_operand:V8QI 1 "gr_register_operand" "r")
846 
          (parallel [(const_int 7) (const_int 6)
847 
                     (const_int 5) (const_int 4)
848 
                     (const_int 3) (const_int 2)
849 
                     (const_int 1) (const_int 0)])))]
850 
  ""
851 
  "mux1 %0 = %1, @rev"
852 
  [(set_attr "itanium_class" "mmshf")])
853 
 
854 
(define_insn "*mux1_mix"
855 
  [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
856 
        (vec_select:V8QI
857 
          (match_operand:V8QI 1 "gr_register_operand" "r")
858 
          (parallel [(const_int 0) (const_int 4)
859 
                     (const_int 2) (const_int 6)
860 
                     (const_int 1) (const_int 5)
861 
                     (const_int 3) (const_int 7)])))]
862 
  ""
863 
  "mux1 %0 = %1, @mix"
864 
  [(set_attr "itanium_class" "mmshf")])
865 
 
866 
(define_insn "*mux1_shuf"
867 
  [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
868 
        (vec_select:V8QI
869 
          (match_operand:V8QI 1 "gr_register_operand" "r")
870 
          (parallel [(const_int 0) (const_int 4)
871 
                     (const_int 1) (const_int 5)
872 
                     (const_int 2) (const_int 6)
873 
                     (const_int 3) (const_int 7)])))]
874 
  ""
875 
  "mux1 %0 = %1, @shuf"
876 
  [(set_attr "itanium_class" "mmshf")])
877 
 
878 
(define_insn "*mux1_alt"
879 
  [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
880 
        (vec_select:V8QI
881 
          (match_operand:V8QI 1 "gr_register_operand" "r")
882 
          (parallel [(const_int 0) (const_int 2)
883 
                     (const_int 4) (const_int 6)
884 
                     (const_int 1) (const_int 3)
885 
                     (const_int 5) (const_int 7)])))]
886 
  ""
887 
  "mux1 %0 = %1, @alt"
888 
  [(set_attr "itanium_class" "mmshf")])
889 
 
890 
(define_insn "*mux1_brcst_v8qi"
891 
  [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
892 
        (vec_select:V8QI
893 
          (match_operand:V8QI 1 "gr_register_operand" "r")
894 
          (parallel [(match_operand 2 "mux1_brcst_element" "")
895 
                     (match_dup 2)
896 
                     (match_dup 2)
897 
                     (match_dup 2)
898 
                     (match_dup 2)
899 
                     (match_dup 2)
900 
                     (match_dup 2)
901 
                     (match_dup 2)])))]
902 
  ""
903 
  "mux1 %0 = %1, @brcst"
904 
  [(set_attr "itanium_class" "mmshf")])
905 
 
906 
(define_insn "mux1_brcst_qi"
907 
  [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
908 
        (vec_duplicate:V8QI
909 
          (match_operand:QI 1 "gr_register_operand" "r")))]
910 
  ""
911 
  "mux1 %0 = %1, @brcst"
912 
  [(set_attr "itanium_class" "mmshf")])
913 
 
914 
(define_insn "*vec_interleave_lowv4hi"
915 
  [(set (match_operand:V4HI 0 "gr_register_operand" "=r")
916 
        (vec_select:V4HI
917 
          (vec_concat:V8HI
918 
            (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU")
919 
            (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU"))
920 
          (parallel [(const_int 0) (const_int 4)
921 
                     (const_int 1) (const_int 5)])))]
922 
  ""
923 
{
924 
  /* Recall that vector elements are numbered in memory order.  */
925 
  if (TARGET_BIG_ENDIAN)
926 
    return "%,unpack2.l %0 = %r1, %r2";
927 
  else
928 
    return "%,unpack2.l %0 = %r2, %r1";
929 
}
930 
  [(set_attr "itanium_class" "mmshf")])
931 
 
932 
(define_insn "*vec_interleave_highv4hi"
933 
  [(set (match_operand:V4HI 0 "gr_register_operand" "=r")
934 
        (vec_select:V4HI
935 
          (vec_concat:V8HI
936 
            (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU")
937 
            (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU"))
938 
          (parallel [(const_int 2) (const_int 6)
939 
                     (const_int 3) (const_int 7)])))]
940 
  ""
941 
{
942 
  /* Recall that vector elements are numbered in memory order.  */
943 
  if (TARGET_BIG_ENDIAN)
944 
    return "%,unpack2.h %0 = %r1, %r2";
945 
  else
946 
    return "%,unpack2.h %0 = %r2, %r1";
947 
}
948 
  [(set_attr "itanium_class" "mmshf")])
949 
 
950 
(define_insn "mix2_even"
951 
  [(set (match_operand:V4HI 0 "gr_register_operand" "=r")
952 
        (vec_select:V4HI
953 
          (vec_concat:V8HI
954 
            (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU")
955 
            (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU"))
956 
          (parallel [(const_int 0) (const_int 4)
957 
                     (const_int 2) (const_int 6)])))]
958 
  ""
959 
{
960 
  /* Recall that vector elements are numbered in memory order.  */
961 
  if (TARGET_BIG_ENDIAN)
962 
    return "%,mix2.l %0 = %r1, %r2";
963 
  else
964 
    return "%,mix2.r %0 = %r2, %r1";
965 
}
966 
  [(set_attr "itanium_class" "mmshf")])
967 
 
968 
(define_insn "mix2_odd"
969 
  [(set (match_operand:V4HI 0 "gr_register_operand" "=r")
970 
        (vec_select:V4HI
971 
          (vec_concat:V8HI
972 
            (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU")
973 
            (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU"))
974 
          (parallel [(const_int 1) (const_int 5)
975 
                     (const_int 3) (const_int 7)])))]
976 
  ""
977 
{
978 
  /* Recall that vector elements are numbered in memory order.  */
979 
  if (TARGET_BIG_ENDIAN)
980 
    return "%,mix2.r %0 = %r1, %r2";
981 
  else
982 
    return "%,mix2.l %0 = %r2, %r1";
983 
}
984 
  [(set_attr "itanium_class" "mmshf")])
985 
 
986 
(define_insn "*mux2"
987 
  [(set (match_operand:V4HI 0 "gr_register_operand" "=r")
988 
        (vec_select:V4HI
989 
          (match_operand:V4HI 1 "gr_register_operand" "r")
990 
          (parallel [(match_operand 2 "const_int_2bit_operand" "")
991 
                     (match_operand 3 "const_int_2bit_operand" "")
992 
                     (match_operand 4 "const_int_2bit_operand" "")
993 
                     (match_operand 5 "const_int_2bit_operand" "")])))]
994 
  ""
995 
{
996 
  int mask = 0;
997 
  if (TARGET_BIG_ENDIAN)
998 
    {
999 
      mask |= (3 - INTVAL (operands[2])) << 6;
1000 
      mask |= (3 - INTVAL (operands[3])) << 4;
1001 
      mask |= (3 - INTVAL (operands[4])) << 2;
1002 
      mask |= 3 - INTVAL (operands[5]);
1003 
    }
1004 
  else
1005 
    {
1006 
      mask |= INTVAL (operands[2]);
1007 
      mask |= INTVAL (operands[3]) << 2;
1008 
      mask |= INTVAL (operands[4]) << 4;
1009 
      mask |= INTVAL (operands[5]) << 6;
1010 
    }
1011 
  operands[2] = GEN_INT (mask);
1012 
  return "%,mux2 %0 = %1, %2";
1013 
}
1014 
  [(set_attr "itanium_class" "mmshf")])
1015 
 
1016 
(define_insn "*mux2_brcst_hi"
1017 
  [(set (match_operand:V4HI 0 "gr_register_operand" "=r")
1018 
        (vec_duplicate:V4HI
1019 
          (match_operand:HI 1 "gr_register_operand" "r")))]
1020 
  ""
1021 
  "mux2 %0 = %1, 0"
1022 
  [(set_attr "itanium_class" "mmshf")])
1023 
 
1024 
(define_insn "*vec_interleave_lowv2si"
1025 
  [(set (match_operand:V2SI 0 "gr_register_operand" "=r")
1026 
        (vec_select:V2SI
1027 
          (vec_concat:V4SI
1028 
            (match_operand:V2SI 1 "gr_reg_or_0_operand" "rU")
1029 
            (match_operand:V2SI 2 "gr_reg_or_0_operand" "rU"))
1030 
          (parallel [(const_int 0) (const_int 2)])))]
1031 
  ""
1032 
{
1033 
  /* Recall that vector elements are numbered in memory order.  */
1034 
  if (TARGET_BIG_ENDIAN)
1035 
    return "%,unpack4.l %0 = %r1, %r2";
1036 
  else
1037 
    return "%,unpack4.l %0 = %r2, %r1";
1038 
}
1039 
  [(set_attr "itanium_class" "mmshf")])
1040 
 
1041 
(define_insn "*vec_interleave_highv2si"
1042 
  [(set (match_operand:V2SI 0 "gr_register_operand" "=r")
1043 
        (vec_select:V2SI
1044 
          (vec_concat:V4SI
1045 
            (match_operand:V2SI 1 "gr_reg_or_0_operand" "rU")
1046 
            (match_operand:V2SI 2 "gr_reg_or_0_operand" "rU"))
1047 
          (parallel [(const_int 1) (const_int 3)])))]
1048 
  ""
1049 
{
1050 
  /* Recall that vector elements are numbered in memory order.  */
1051 
  if (TARGET_BIG_ENDIAN)
1052 
    return "%,unpack4.h %0 = %r1, %r2";
1053 
  else
1054 
    return "%,unpack4.h %0 = %r2, %r1";
1055 
}
1056 
  [(set_attr "itanium_class" "mmshf")])
1057 
 
1058 
(define_expand "vec_initv2si"
1059 
  [(match_operand:V2SI 0 "gr_register_operand" "")
1060 
   (match_operand 1 "" "")]
1061 
  ""
1062 
{
1063 
  rtx op1 = XVECEXP (operands[1], 0, 0);
1064 
  rtx op2 = XVECEXP (operands[1], 0, 1);
1065 
  rtx x;
1066 
 
1067 
  if (GET_CODE (op1) == CONST_INT && GET_CODE (op2) == CONST_INT)
1068 
    {
1069 
      x = gen_rtx_CONST_VECTOR (V2SImode, XVEC (operands[1], 0));
1070 
      emit_move_insn (operands[0], x);
1071 
      DONE;
1072 
    }
1073 
 
1074 
  if (!gr_reg_or_0_operand (op1, SImode))
1075 
    op1 = force_reg (SImode, op1);
1076 
  if (!gr_reg_or_0_operand (op2, SImode))
1077 
    op2 = force_reg (SImode, op2);
1078 
 
1079 
  x = gen_rtx_VEC_CONCAT (V2SImode, op1, op2);
1080 
  emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
1081 
  DONE;
1082 
})
1083 
 
1084 
(define_insn "*vecinit_v2si"
1085 
  [(set (match_operand:V2SI 0 "gr_register_operand" "=r")
1086 
        (vec_concat:V2SI
1087 
          (match_operand:SI 1 "gr_reg_or_0_operand" "rO")
1088 
          (match_operand:SI 2 "gr_reg_or_0_operand" "rO")))]
1089 
  ""
1090 
{
1091 
  /* Recall that vector elements are numbered in memory order.  */
1092 
  if (TARGET_BIG_ENDIAN)
1093 
    return "%,unpack4.l %0 = %r1, %r2";
1094 
  else
1095 
    return "%,unpack4.l %0 = %r2, %r1";
1096 
}
1097 
  [(set_attr "itanium_class" "mmshf")])
1098 
 
1099 
;; Missing operations
1100 
;; padd.uus
1101 
;; pavg
1102 
;; pavgsub
1103 
;; psad
1104 
;; pshladd
1105 
;; pshradd
1106 
;; psub.uus
1107 
 
1108 
;; Floating point vector operations
1109 
 
1110 
(define_expand "movv2sf"
1111 
  [(set (match_operand:V2SF 0 "general_operand" "")
1112 
        (match_operand:V2SF 1 "general_operand" ""))]
1113 
  ""
1114 
{
1115 
  rtx op1 = ia64_expand_move (operands[0], operands[1]);
1116 
  if (!op1)
1117 
    DONE;
1118 
  operands[1] = op1;
1119 
})
1120 
 
1121 
(define_insn "*movv2sf_internal"
1122 
  [(set (match_operand:V2SF 0 "destination_operand"
1123 
                                        "=f,f,f,Q,*r ,*r,*r,*r,m ,f ,*r")
1124 
        (match_operand:V2SF 1 "move_operand"
1125 
                                        "fU,Y,Q,f,U*r,W ,i ,m ,*r,*r,f "))]
1126 
  "ia64_move_ok (operands[0], operands[1])"
1127 
{
1128 
  static const char * const alt[] = {
1129 
    "%,mov %0 = %F1",
1130 
    "%,fpack %0 = %F2, %F1",
1131 
    "%,ldf8 %0 = %1%P1",
1132 
    "%,stf8 %0 = %1%P0",
1133 
    "%,mov %0 = %r1",
1134 
    "%,addl %0 = %v1, r0",
1135 
    "%,movl %0 = %v1",
1136 
    "%,ld8%O1 %0 = %1%P1",
1137 
    "%,st8%Q0 %0 = %r1%P0",
1138 
    "%,setf.sig %0 = %1",
1139 
    "%,getf.sig %0 = %1"
1140 
  };
1141 
 
1142 
  if (which_alternative == 1)
1143 
    {
1144 
      operands[2] = XVECEXP (operands[1], 0, TARGET_BIG_ENDIAN ? 0 : 1);
1145 
      operands[1] = XVECEXP (operands[1], 0, TARGET_BIG_ENDIAN ? 1 : 0);
1146 
    }
1147 
 
1148 
  return alt[which_alternative];
1149 
}
1150 
  [(set_attr "itanium_class" "fmisc,fmisc,fld,stf,ialu,ialu,long_i,ld,st,tofr,frfr")])
1151 
 
1152 
(define_insn "absv2sf2"
1153 
  [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
1154 
        (abs:V2SF (match_operand:V2SF 1 "fr_register_operand" "f")))]
1155 
  ""
1156 
  "fpabs %0 = %1"
1157 
  [(set_attr "itanium_class" "fmisc")])
1158 
 
1159 
(define_insn "negv2sf2"
1160 
  [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
1161 
        (neg:V2SF (match_operand:V2SF 1 "fr_register_operand" "f")))]
1162 
  ""
1163 
  "fpneg %0 = %1"
1164 
  [(set_attr "itanium_class" "fmisc")])
1165 
 
1166 
(define_insn "*negabsv2sf2"
1167 
  [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
1168 
        (neg:V2SF
1169 
          (abs:V2SF (match_operand:V2SF 1 "fr_register_operand" "f"))))]
1170 
  ""
1171 
  "fpnegabs %0 = %1"
1172 
  [(set_attr "itanium_class" "fmisc")])
1173 
 
1174 
(define_expand "addv2sf3"
1175 
  [(set (match_operand:V2SF 0 "fr_register_operand" "")
1176 
        (fma:V2SF (match_operand:V2SF 1 "fr_register_operand" "")
1177 
                  (match_dup 3)
1178 
                  (match_operand:V2SF 2 "fr_register_operand" "")))]
1179 
  ""
1180 
{
1181 
  rtvec v = gen_rtvec (2, CONST1_RTX (SFmode), CONST1_RTX (SFmode));
1182 
  operands[3] = force_reg (V2SFmode, gen_rtx_CONST_VECTOR (V2SFmode, v));
1183 
})
1184 
 
1185 
(define_expand "subv2sf3"
1186 
  [(set (match_operand:V2SF 0 "fr_register_operand" "")
1187 
        (fma:V2SF
1188 
          (match_operand:V2SF 1 "fr_register_operand" "")
1189 
          (match_dup 3)
1190 
          (neg:V2SF (match_operand:V2SF 2 "fr_register_operand" ""))))]
1191 
  ""
1192 
{
1193 
  rtvec v = gen_rtvec (2, CONST1_RTX (SFmode), CONST1_RTX (SFmode));
1194 
  operands[3] = force_reg (V2SFmode, gen_rtx_CONST_VECTOR (V2SFmode, v));
1195 
})
1196 
 
1197 
(define_insn "mulv2sf3"
1198 
  [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
1199 
        (mult:V2SF (match_operand:V2SF 1 "fr_register_operand" "f")
1200 
                   (match_operand:V2SF 2 "fr_register_operand" "f")))]
1201 
  ""
1202 
  "fpmpy %0 = %1, %2"
1203 
  [(set_attr "itanium_class" "fmac")])
1204 
 
1205 
(define_insn "fmav2sf4"
1206 
  [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
1207 
        (fma:V2SF
1208 
          (match_operand:V2SF 1 "fr_register_operand" "f")
1209 
          (match_operand:V2SF 2 "fr_register_operand" "f")
1210 
          (match_operand:V2SF 3 "fr_register_operand" "f")))]
1211 
  ""
1212 
  "fpma %0 = %1, %2, %3"
1213 
  [(set_attr "itanium_class" "fmac")])
1214 
 
1215 
(define_insn "fmsv2sf4"
1216 
  [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
1217 
        (fma:V2SF
1218 
          (match_operand:V2SF 1 "fr_register_operand" "f")
1219 
          (match_operand:V2SF 2 "fr_register_operand" "f")
1220 
          (neg:V2SF (match_operand:V2SF 3 "fr_register_operand" "f"))))]
1221 
  ""
1222 
  "fpms %0 = %1, %2, %3"
1223 
  [(set_attr "itanium_class" "fmac")])
1224 
 
1225 
(define_insn "*fpnmpy"
1226 
  [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
1227 
        (neg:V2SF
1228 
          (mult:V2SF (match_operand:V2SF 1 "fr_register_operand" "f")
1229 
                     (match_operand:V2SF 2 "fr_register_operand" "f"))))]
1230 
  ""
1231 
  "fpnmpy %0 = %1, %2"
1232 
  [(set_attr "itanium_class" "fmac")])
1233 
 
1234 
(define_insn "fnmav2sf4"
1235 
  [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
1236 
        (fma:V2SF
1237 
          (neg:V2SF (match_operand:V2SF 1 "fr_register_operand" "f"))
1238 
          (match_operand:V2SF 2 "fr_register_operand" "f")
1239 
          (match_operand:V2SF 3 "fr_register_operand" "f")))]
1240 
  ""
1241 
  "fpnma %0 = %1, %2, %3"
1242 
  [(set_attr "itanium_class" "fmac")])
1243 
 
1244 
(define_insn "smaxv2sf3"
1245 
  [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
1246 
        (smax:V2SF (match_operand:V2SF 1 "fr_register_operand" "f")
1247 
                   (match_operand:V2SF 2 "fr_register_operand" "f")))]
1248 
  ""
1249 
  "fpmax %0 = %1, %2"
1250 
  [(set_attr "itanium_class" "fmisc")])
1251 
 
1252 
(define_insn "sminv2sf3"
1253 
  [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
1254 
        (smin:V2SF (match_operand:V2SF 1 "fr_register_operand" "f")
1255 
                   (match_operand:V2SF 2 "fr_register_operand" "f")))]
1256 
  ""
1257 
  "fpmin %0 = %1, %2"
1258 
  [(set_attr "itanium_class" "fmisc")])
1259 
 
1260 
(define_expand "reduc_splus_v2sf"
1261 
  [(match_operand:V2SF 0 "fr_register_operand" "")
1262 
   (match_operand:V2SF 1 "fr_register_operand" "")]
1263 
  ""
1264 
{
1265 
  rtx tmp = gen_reg_rtx (V2SFmode);
1266 
  if (TARGET_BIG_ENDIAN)
1267 
    emit_insn (gen_fswap (tmp, CONST0_RTX (V2SFmode), operands[1]));
1268 
  else
1269 
    emit_insn (gen_fswap (tmp, operands[1], CONST0_RTX (V2SFmode)));
1270 
  emit_insn (gen_addv2sf3 (operands[0], operands[1], tmp));
1271 
  DONE;
1272 
})
1273 
 
1274 
(define_expand "reduc_smax_v2sf"
1275 
  [(match_operand:V2SF 0 "fr_register_operand" "")
1276 
   (match_operand:V2SF 1 "fr_register_operand" "")]
1277 
  ""
1278 
{
1279 
  rtx tmp = gen_reg_rtx (V2SFmode);
1280 
  if (TARGET_BIG_ENDIAN)
1281 
    emit_insn (gen_fswap (tmp, CONST0_RTX (V2SFmode), operands[1]));
1282 
  else
1283 
    emit_insn (gen_fswap (tmp, operands[1], CONST0_RTX (V2SFmode)));
1284 
  emit_insn (gen_smaxv2sf3 (operands[0], operands[1], tmp));
1285 
  DONE;
1286 
})
1287 
 
1288 
(define_expand "reduc_smin_v2sf"
1289 
  [(match_operand:V2SF 0 "fr_register_operand" "")
1290 
   (match_operand:V2SF 1 "fr_register_operand" "")]
1291 
  ""
1292 
{
1293 
  rtx tmp = gen_reg_rtx (V2SFmode);
1294 
  if (TARGET_BIG_ENDIAN)
1295 
    emit_insn (gen_fswap (tmp, CONST0_RTX (V2SFmode), operands[1]));
1296 
  else
1297 
    emit_insn (gen_fswap (tmp, operands[1], CONST0_RTX (V2SFmode)));
1298 
  emit_insn (gen_sminv2sf3 (operands[0], operands[1], tmp));
1299 
  DONE;
1300 
})
1301 
 
1302 
(define_expand "vcondv2sfv2sf"
1303 
  [(set (match_operand:V2SF 0 "fr_register_operand" "")
1304 
        (if_then_else:V2SF
1305 
          (match_operator 3 ""
1306 
            [(match_operand:V2SF 4 "fr_reg_or_0_operand" "")
1307 
             (match_operand:V2SF 5 "fr_reg_or_0_operand" "")])
1308 
          (match_operand:V2SF 1 "fr_reg_or_0_operand" "")
1309 
          (match_operand:V2SF 2 "fr_reg_or_0_operand" "")))]
1310 
  ""
1311 
{
1312 
  rtx x, cmp;
1313 
 
1314 
  cmp = gen_reg_rtx (V2SFmode);
1315 
  PUT_MODE (operands[3], V2SFmode);
1316 
  emit_insn (gen_rtx_SET (VOIDmode, cmp, operands[3]));
1317 
 
1318 
  x = gen_rtx_IF_THEN_ELSE (V2SFmode, cmp, operands[1], operands[2]);
1319 
  emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
1320 
  DONE;
1321 
})
1322 
 
1323 
(define_insn "*fpcmp"
1324 
  [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
1325 
        (match_operator:V2SF 3 "comparison_operator"
1326 
          [(match_operand:V2SF 1 "fr_reg_or_0_operand" "fU")
1327 
           (match_operand:V2SF 2 "fr_reg_or_0_operand" "fU")]))]
1328 
  ""
1329 
  "fpcmp.%D3 %0 = %F1, %F2"
1330 
  [(set_attr "itanium_class" "fmisc")])
1331 
 
1332 
(define_insn "*fselect"
1333 
  [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
1334 
        (if_then_else:V2SF
1335 
          (match_operand:V2SF 1 "fr_register_operand" "f")
1336 
          (match_operand:V2SF 2 "fr_reg_or_0_operand" "fU")
1337 
          (match_operand:V2SF 3 "fr_reg_or_0_operand" "fU")))]
1338 
  ""
1339 
  "fselect %0 = %F2, %F3, %1"
1340 
  [(set_attr "itanium_class" "fmisc")])
1341 
 
1342 
(define_expand "vec_initv2sf"
1343 
  [(match_operand:V2SF 0 "fr_register_operand" "")
1344 
   (match_operand 1 "" "")]
1345 
  ""
1346 
{
1347 
  rtx op1 = XVECEXP (operands[1], 0, 0);
1348 
  rtx op2 = XVECEXP (operands[1], 0, 1);
1349 
  rtx x;
1350 
 
1351 
  if (GET_CODE (op1) == CONST_DOUBLE && GET_CODE (op2) == CONST_DOUBLE)
1352 
    {
1353 
      x = gen_rtx_CONST_VECTOR (V2SFmode, XVEC (operands[1], 0));
1354 
      emit_move_insn (operands[0], x);
1355 
      DONE;
1356 
    }
1357 
 
1358 
  if (!fr_reg_or_fp01_operand (op1, SFmode))
1359 
    op1 = force_reg (SFmode, op1);
1360 
  if (!fr_reg_or_fp01_operand (op2, SFmode))
1361 
    op2 = force_reg (SFmode, op2);
1362 
 
1363 
  emit_insn (gen_fpack (operands[0], op1, op2));
1364 
  DONE;
1365 
})
1366 
 
1367 
(define_insn "fpack"
1368 
  [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
1369 
        (vec_concat:V2SF
1370 
          (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
1371 
          (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
1372 
  ""
1373 
{
1374 
  /* Recall that vector elements are numbered in memory order.  */
1375 
  if (TARGET_BIG_ENDIAN)
1376 
    return "%,fpack %0 = %F1, %F2";
1377 
  else
1378 
    return "%,fpack %0 = %F2, %F1";
1379 
}
1380 
  [(set_attr "itanium_class" "fmisc")])
1381 
 
1382 
(define_insn "fswap"
1383 
  [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
1384 
        (vec_select:V2SF
1385 
          (vec_concat:V4SF
1386 
            (match_operand:V2SF 1 "fr_reg_or_0_operand" "fU")
1387 
            (match_operand:V2SF 2 "fr_reg_or_0_operand" "fU"))
1388 
          (parallel [(const_int 1) (const_int 2)])))]
1389 
  ""
1390 
{
1391 
  /* Recall that vector elements are numbered in memory order.  */
1392 
  if (TARGET_BIG_ENDIAN)
1393 
    return "%,fswap %0 = %F2, %F1";
1394 
  else
1395 
    return "%,fswap %0 = %F1, %F2";
1396 
}
1397 
  [(set_attr "itanium_class" "fmisc")])
1398 
 
1399 
(define_insn "*vec_interleave_highv2sf"
1400 
  [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
1401 
        (vec_select:V2SF
1402 
          (vec_concat:V4SF
1403 
            (match_operand:V2SF 1 "fr_reg_or_0_operand" "fU")
1404 
            (match_operand:V2SF 2 "fr_reg_or_0_operand" "fU"))
1405 
          (parallel [(const_int 1) (const_int 3)])))]
1406 
  ""
1407 
{
1408 
  /* Recall that vector elements are numbered in memory order.  */
1409 
  if (TARGET_BIG_ENDIAN)
1410 
    return "%,fmix.l %0 = %F1, %F2";
1411 
  else
1412 
    return "%,fmix.l %0 = %F2, %F1";
1413 
}
1414 
  [(set_attr "itanium_class" "fmisc")])
1415 
 
1416 
(define_insn "*vec_interleave_lowv2sf"
1417 
  [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
1418 
        (vec_select:V2SF
1419 
          (vec_concat:V4SF
1420 
            (match_operand:V2SF 1 "fr_reg_or_0_operand" "fU")
1421 
            (match_operand:V2SF 2 "fr_reg_or_0_operand" "fU"))
1422 
          (parallel [(const_int 0) (const_int 2)])))]
1423 
  ""
1424 
{
1425 
  /* Recall that vector elements are numbered in memory order.  */
1426 
  if (TARGET_BIG_ENDIAN)
1427 
    return "%,fmix.r %0 = %F1, %F2";
1428 
  else
1429 
    return "%,fmix.r %0 = %F2, %F1";
1430 
}
1431 
  [(set_attr "itanium_class" "fmisc")])
1432 
 
1433 
(define_insn "fmix_lr"
1434 
  [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
1435 
        (vec_select:V2SF
1436 
          (vec_concat:V4SF
1437 
            (match_operand:V2SF 1 "fr_reg_or_0_operand" "fU")
1438 
            (match_operand:V2SF 2 "fr_reg_or_0_operand" "fU"))
1439 
          (parallel [(const_int 0) (const_int 3)])))]
1440 
  ""
1441 
{
1442 
  /* Recall that vector elements are numbered in memory order.  */
1443 
  if (TARGET_BIG_ENDIAN)
1444 
    return "%,fmix.lr %0 = %F1, %F2";
1445 
  else
1446 
    return "%,fmix.lr %0 = %F2, %F1";
1447 
}
1448 
  [(set_attr "itanium_class" "fmisc")])
1449 
 
1450 
(define_expand "vec_setv2sf"
1451 
  [(match_operand:V2SF 0 "fr_register_operand" "")
1452 
   (match_operand:SF 1 "fr_register_operand" "")
1453 
   (match_operand 2 "const_int_operand" "")]
1454 
  ""
1455 
{
1456 
  ia64_expand_vec_setv2sf (operands);
1457 
  DONE;
1458 
})
1459 
 
1460 
(define_insn_and_split "*vec_extractv2sf_0_le"
1461 
  [(set (match_operand:SF 0 "nonimmediate_operand" "=r,f,m")
1462 
        (unspec:SF [(match_operand:V2SF 1 "nonimmediate_operand" "rfm,rm,r")
1463 
                    (const_int 0)]
1464 
                   UNSPEC_VECT_EXTR))]
1465 
  "!TARGET_BIG_ENDIAN"
1466 
  "#"
1467 
  "reload_completed"
1468 
  [(set (match_dup 0) (match_dup 1))]
1469 
{
1470 
  if (REG_P (operands[1]) && FR_REGNO_P (REGNO (operands[1])))
1471 
    operands[0] = gen_rtx_REG (V2SFmode, REGNO (operands[0]));
1472 
  else if (MEM_P (operands[1]))
1473 
    operands[1] = adjust_address (operands[1], SFmode, 0);
1474 
  else
1475 
    operands[1] = gen_rtx_REG (SFmode, REGNO (operands[1]));
1476 
})
1477 
 
1478 
(define_insn_and_split "*vec_extractv2sf_0_be"
1479 
  [(set (match_operand:SF 0 "register_operand" "=rf,r")
1480 
        (unspec:SF [(match_operand:V2SF 1 "nonimmediate_operand" "m,r")
1481 
                    (const_int 0)]
1482 
                   UNSPEC_VECT_EXTR))]
1483 
  "TARGET_BIG_ENDIAN"
1484 
  "#"
1485 
  "reload_completed"
1486 
  [(set (match_dup 0) (match_dup 1))]
1487 
{
1488 
  if (MEM_P (operands[1]))
1489 
    operands[1] = adjust_address (operands[1], SFmode, 0);
1490 
  else
1491 
    {
1492 
      emit_insn (gen_lshrdi3 (operands[0], operands[1], GEN_INT (32)));
1493 
      DONE;
1494 
    }
1495 
})
1496 
 
1497 
(define_insn_and_split "*vec_extractv2sf_1_le"
1498 
  [(set (match_operand:SF 0 "register_operand" "=r")
1499 
        (unspec:SF [(match_operand:V2SF 1 "register_operand" "r")
1500 
                    (const_int 1)]
1501 
                   UNSPEC_VECT_EXTR))]
1502 
  "!TARGET_BIG_ENDIAN"
1503 
  "#"
1504 
  "&& reload_completed"
1505 
  [(const_int 0)]
1506 
{
1507 
  operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
1508 
  operands[1] = gen_rtx_REG (DImode, REGNO (operands[1]));
1509 
  emit_insn (gen_lshrdi3 (operands[0], operands[1], GEN_INT (32)));
1510 
  DONE;
1511 
})
1512 
 
1513 
(define_insn_and_split "*vec_extractv2sf_1_be"
1514 
  [(set (match_operand:SF 0 "register_operand" "=rf")
1515 
        (unspec:SF [(match_operand:V2SF 1 "register_operand" "r")
1516 
                    (const_int 1)]
1517 
                   UNSPEC_VECT_EXTR))]
1518 
  "TARGET_BIG_ENDIAN"
1519 
  "#"
1520 
  "&& reload_completed"
1521 
  [(set (match_dup 0) (match_dup 1))]
1522 
{
1523 
  operands[1] = gen_rtx_REG (SFmode, REGNO (operands[1]));
1524 
})
1525 
 
1526 
(define_expand "vec_extractv2sf"
1527 
  [(set (match_operand:SF 0 "register_operand" "")
1528 
        (unspec:SF [(match_operand:V2SF 1 "register_operand" "")
1529 
                    (match_operand:DI 2 "const_int_operand" "")]
1530 
                   UNSPEC_VECT_EXTR))]
1531 
  ""
1532 
  "")
1533 
 
1534 
(define_expand "vec_unpacku_lo_"
1535 
  [(match_operand: 0 "register_operand" "")
1536 
   (match_operand:VECINT12   1 "register_operand" "")]
1537 
  ""
1538 
{
1539 
  ia64_expand_unpack (operands, true, false);
1540 
  DONE;
1541 
})
1542 
 
1543 
(define_expand "vec_unpacku_hi_"
1544 
  [(match_operand: 0 "register_operand" "")
1545 
   (match_operand:VECINT12   1 "register_operand" "")]
1546 
  ""
1547 
{
1548 
  ia64_expand_unpack (operands, true, true);
1549 
  DONE;
1550 
})
1551 
 
1552 
(define_expand "vec_unpacks_lo_"
1553 
  [(match_operand: 0 "register_operand" "")
1554 
   (match_operand:VECINT12   1 "register_operand" "")]
1555 
  ""
1556 
{
1557 
  ia64_expand_unpack (operands, false, false);
1558 
  DONE;
1559 
})
1560 
 
1561 
(define_expand "vec_unpacks_hi_"
1562 
  [(match_operand: 0 "register_operand" "")
1563 
   (match_operand:VECINT12   1 "register_operand" "")]
1564 
  ""
1565 
{
1566 
  ia64_expand_unpack (operands, false, true);
1567 
  DONE;
1568 
})
1569 
 
1570 
(define_expand "vec_pack_trunc_v4hi"
1571 
  [(match_operand:V8QI 0 "gr_register_operand" "")
1572 
   (match_operand:V4HI 1 "gr_register_operand" "")
1573 
   (match_operand:V4HI 2 "gr_register_operand" "")]
1574 
  ""
1575 
{
1576 
  rtx op1 = gen_lowpart (V8QImode, operands[1]);
1577 
  rtx op2 = gen_lowpart (V8QImode, operands[2]);
1578 
  ia64_expand_vec_perm_even_odd (operands[0], op1, op2, TARGET_BIG_ENDIAN);
1579 
  DONE;
1580 
})
1581 
 
1582 
(define_expand "vec_pack_trunc_v2si"
1583 
  [(match_operand:V4HI 0 "gr_register_operand" "")
1584 
   (match_operand:V2SI 1 "gr_register_operand" "")
1585 
   (match_operand:V2SI 2 "gr_register_operand" "")]
1586 
  ""
1587 
{
1588 
  rtx op1 = gen_lowpart (V4HImode, operands[1]);
1589 
  rtx op2 = gen_lowpart (V4HImode, operands[2]);
1590 
  ia64_expand_vec_perm_even_odd (operands[0], op1, op2, TARGET_BIG_ENDIAN);
1591 
  DONE;
1592 
})
1593 
 
1594 
(define_expand "vec_perm_const"
1595 
  [(match_operand:VEC 0 "register_operand" "")
1596 
   (match_operand:VEC 1 "register_operand" "")
1597 
   (match_operand:VEC 2 "register_operand" "")
1598 
   (match_operand: 3 "" "")]
1599 
  ""
1600 
{
1601 
  if (ia64_expand_vec_perm_const (operands))
1602 
    DONE;
1603 
  else
1604 
    FAIL;
1605 
})
1606 
 
1607 
;; Missing operations
1608 
;; fprcpa
1609 
;; fpsqrta

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.