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Line No. Rev Author Line
1 709 jeremybenn 
;; Machine Descriptions for R8C/M16C/M32C
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;; Copyright (C) 2005, 2007, 2010
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;; Free Software Foundation, Inc.
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;; Contributed by Red Hat.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;;
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
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;; License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3.  If not see
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;; .
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22 
;; add, sub
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24 
(define_insn "addqi3"
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  [(set (match_operand:QI 0 "mra_or_sp_operand"
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                  "=SdRhl,SdRhl,??Rmm,??Rmm, *Raa,*Raa,SdRhl,??Rmm")
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        (plus:QI (match_operand:QI 1 "mra_operand"
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                  "%0,0,0,0, 0,0,0,0")
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                 (match_operand:QI 2 "mrai_operand"
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                  "iSdRhl,?Rmm,iSdRhl,?Rmm, iSdRhl,?Rmm,*Raa,*Raa")))]
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  ""
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  "add.b\t%2,%0"
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  [(set_attr "flags" "oszc")]
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  )
35 
 
36 
(define_insn "addhi3"
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  [(set (match_operand:HI 0 "m32c_nonimmediate_operand"
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                  "=SdRhi,SdRhi,??Rmm,??Rmm, SdRhi,??Rmm, Rhi, Raw, Raw, !Rsp")
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        (plus:HI (match_operand:HI 1 "m32c_any_operand"
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                  "%0,0,0,0, 0,0, Raw, Rfb, Rfb, 0")
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                 (match_operand:HI 2 "m32c_any_operand"
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                  "IU2sSdRhi,?Rmm,IU2sSdRhi,?Rmm, IM2,IM2, IS2IU2, I00, IS1, i")))]
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  ""
44 
  "@
45 
   add.w\t%2,%0
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   add.w\t%2,%0
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   add.w\t%2,%0
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   add.w\t%2,%0
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   sub.w\t%m2,%0
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   sub.w\t%m2,%0
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   mova\t%d2[%1],%0
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   stc\t%1,%0
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   mova\t%D2[%1],%0
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   add.w\t%2,%0"
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  [(set_attr "flags" "oszc,oszc,oszc,oszc,oszc,oszc,n,n,n,oszc")]
56 
  )
57 
 
58 
(define_insn "addpsi3"
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  [(set (match_operand:PSI 0 "m32c_nonimmediate_operand" "=Rpi,Raa,SdRpi,SdRpi,Rsp*Rmm, Rpi,Rpi")
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        (plus:PSI (match_operand:PSI 1 "m32c_nonimmediate_operand" "0,0,0,0,0, Raa,Rad")
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                  (match_operand:PSI 2 "m32c_any_operand" "Is3,IS1,iSdRpi,?Rmm,i, i,IS2")))]
62 
  "TARGET_A24"
63 
  "@
64 
   add.l:q\t%2,%0
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   addx\t%2,%0
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   add.l\t%2,%0
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   add.l\t%2,%0
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   add.l\t%2,%0
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   mova\t%d2[%1],%0
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   mova\t%D2[%1],%0"
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  [(set_attr "flags" "oszc,oszc,oszc,oszc,oszc,n,n")]
72 
  )
73 
 
74 
(define_expand "addsi3"
75 
  [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
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        (plus:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0")
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                 (match_operand:SI 2 "mrai_operand" "iRsiSd,?Rmm,iRsiSd,?Rmm")))]
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  "TARGET_A24 ||TARGET_A16"
79 
  ""
80 
  )
81 
 
82 
(define_insn "addsi3_1"
83 
  [(set (match_operand:SI 0 "mra_operand" "=RsiSd,??Rmm,RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd")
84 
        (plus:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0,0,0,0,0")
85 
                 (match_operand 2 "mrai_operand" "IU2,IU2,i,?Rmm,i,RsiSd,?Rmm,RsiSd")))]
86 
  "TARGET_A16"
87 
  "*
88 
 
89 
  switch (which_alternative)
90 
    {
91 
    case 0:
92 
      return \"add.w %X2,%h0\;adcf.w %H0\";
93 
    case 1:
94 
      return \"add.w %X2,%h0\;adcf.w %H0\";
95 
    case 2:
96 
      if (GET_CODE (operands[2]) == SYMBOL_REF)
97 
        {
98 
          output_asm_insn (\"add.w #%%lo(%d2),%h0\",operands);
99 
          return \"adc.w #%%hi(%d2),%H0\";
100 
        }
101 
      else
102 
        {
103 
          output_asm_insn (\"add.w %X2,%h0\",operands);
104 
          operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
105 
          return \"adc.w %X2,%H0\";
106 
        }
107 
    case 3:
108 
      return \"add.w %h2,%h0\;adc.w %H2,%H0\";
109 
    case 4:
110 
      output_asm_insn (\"add.w %X2,%h0\",operands);
111 
      operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
112 
      return \"adc.w %X2,%H0\";
113 
    case 5:
114 
      return \"add.w %h2,%h0\;adc.w %H2,%H0\";
115 
    case 6:
116 
      return \"add.w %h2,%h0\;adc.w %H2,%H0\";
117 
    case 7:
118 
      return \"add.w %h2,%h0\;adc.w %H2,%H0\";
119 
    default:
120 
      gcc_unreachable ();
121 
    }"
122 
  [(set_attr "flags" "x,x,x,x,x,x,x,x")]
123 
)
124 
 
125 
(define_insn "addsi3_2"
126 
  [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
127 
        (plus:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0")
128 
                 (match_operand:SI 2 "mrai_operand" "iRsiSd,?Rmm,iRsiSd,?Rmm")))]
129 
  "TARGET_A24"
130 
  "add.l\t%2,%0"
131 
  [(set_attr "flags" "oszc")]
132 
)
133 
 
134 
(define_insn "subqi3"
135 
  [(set (match_operand:QI 0 "mra_or_sp_operand"
136 
                   "=SdRhl,SdRhl,??Rmm,??Rmm, Raa,Raa,SdRhl,??Rmm, *Rsp")
137 
        (minus:QI (match_operand:QI 1 "mra_operand"
138 
                   "0,0,0,0, 0,0,0,0, 0")
139 
                  (match_operand:QI 2 "mrai_operand"
140 
                   "iSdRhl,?Rmm,iSdRhl,?Rmm, iSdRhl,?Rmm,Raa,Raa, i")))]
141 
  ""
142 
  "sub.b\t%2,%0"
143 
  [(set_attr "flags" "oszc")]
144 
  )
145 
 
146 
(define_insn "subhi3"
147 
  [(set (match_operand:HI 0 "mra_operand"
148 
                   "=SdRhi,SdRhi,??Rmm,??Rmm, SdRhi,??Rmm")
149 
        (minus:HI (match_operand:HI 1 "mras_operand"
150 
                   "0,0,0,0, 0,0")
151 
                  (match_operand:HI 2 "mrai_operand"
152 
                   "IU2SdRhi,?Rmm,IU2SdRhi,?Rmm, IM2,IM2")))]
153 
  ""
154 
  "@
155 
   sub.w\t%2,%0
156 
   sub.w\t%2,%0
157 
   sub.w\t%2,%0
158 
   sub.w\t%2,%0
159 
   add.w\t%m2,%0
160 
   add.w\t%m2,%0"
161 
  [(set_attr "flags" "oszc,oszc,oszc,oszc,oszc,oszc")]
162 
  )
163 
 
164 
(define_insn "subpsi3"
165 
  [(set (match_operand:PSI 0 "mra_operand" "=RpiSd,RpiSd,??Rmm,??Rmm")
166 
        (minus:PSI (match_operand:PSI 1 "mra_operand" "0,0,0,0")
167 
                   (match_operand:PSI 2 "mrai_operand" "iRpiSd,?Rmm,iRpiSd,?Rmm")))]
168 
  "TARGET_A24"
169 
  "sub.%&\t%2,%0"
170 
  [(set_attr "flags" "oszc")]
171 
  )
172 
 
173 
(define_expand "subsi3"
174 
  [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
175 
        (minus:SI (match_operand:SI 1 "mra_operand" "0,0,0,0")
176 
                  (match_operand:SI 2 "mrai_operand" "iRsiSd,?Rmm,iRsiSd,?Rmm")))]
177 
  "TARGET_A24 ||TARGET_A16"
178 
  ""
179 
)
180 
 
181 
(define_insn "subsi3_1"
182 
  [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd")
183 
        (minus:SI (match_operand:SI 1 "mra_operand" "0,0,0,0,0,0")
184 
                  (match_operand:SI 2 "mrai_operand" "i,?Rmm,i,RsiSd,?Rmm,RsiSd")))]
185 
  "TARGET_A16"
186 
  "*
187 
  switch (which_alternative)
188 
    {
189 
    case 0:
190 
      output_asm_insn (\"sub.w %X2,%h0\",operands);
191 
      operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
192 
      return \"sbb.w %X2,%H0\";
193 
    case 1:
194 
      return \"sub.w %h2,%h0\;sbb.w %H2,%H0\";
195 
    case 2:
196 
      output_asm_insn (\"sub.w %X2,%h0\",operands);
197 
      operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
198 
      return \"sbb.w %X2,%H0\";
199 
    case 3:
200 
      return \"sub.w %h2,%h0\;sbb.w %H2,%H0\";
201 
    case 4:
202 
      return \"sub.w %h2,%h0\;sbb.w %H2,%H0\";
203 
    case 5:
204 
      return \"sub.w %h2,%h0\;sbb.w %H2,%H0\";
205 
    default:
206 
      gcc_unreachable ();
207 
    }"
208 
  [(set_attr "flags" "x,x,x,x,x,x")]
209 
)
210 
 
211 
(define_insn "subsi3_2"
212 
  [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
213 
        (minus:SI (match_operand:SI 1 "mra_operand" "0,0,0,0")
214 
                  (match_operand:SI 2 "mrai_operand" "iRsiSd,?Rmm,iRsiSd,?Rmm")))]
215 
  "TARGET_A24"
216 
  "sub.l\t%2,%0"
217 
  [(set_attr "flags" "oszc,oszc,oszc,oszc")]
218 
)
219 
 
220 
(define_insn "negqi2"
221 
  [(set (match_operand:QI 0 "mra_operand" "=SdRhl,??Rmm")
222 
        (neg:QI (match_operand:QI 1 "mra_operand" "0,0")))]
223 
  ""
224 
  "neg.b\t%0"
225 
  [(set_attr "flags" "oszc,oszc")]
226 
  )
227 
 
228 
(define_insn "neghi2"
229 
  [(set (match_operand:HI 0 "mra_operand" "=SdRhi,??Rmm")
230 
        (neg:HI (match_operand:HI 1 "mra_operand" "0,0")))]
231 
  ""
232 
  "neg.w\t%0"
233 
  [(set_attr "flags" "oszc,oszc")]
234 
  )
235 
 
236 
; We can negate an SImode by operating on the subparts.  GCC deals
237 
; with this itself for larger modes, but not SI.
238 
(define_insn "negsi2"
239 
  [(set (match_operand:SI 0 "mra_operand" "=SdR03,??Rmm")
240 
        (neg:SI (match_operand:SI 1 "mra_operand" "0,0")))]
241 
  ""
242 
  "not.w %h0 | not.w %H0 | add.w #1,%h0 | adcf.w %H0"
243 
  [(set_attr "flags" "x")]
244 
  )
245 
 
246 
(define_insn "absqi2"
247 
  [(set (match_operand:QI 0 "mra_operand" "=RhlSd,??Rmm")
248 
        (abs:QI (match_operand:QI 1 "mra_operand" "0,0")))]
249 
  ""
250 
  "abs.b\t%0"
251 
  [(set_attr "flags" "oszc")]
252 
  )
253 
 
254 
(define_insn "abshi2"
255 
  [(set (match_operand:HI 0 "mra_operand" "=RhiSd,??Rmm")
256 
        (abs:HI (match_operand:HI 1 "mra_operand" "0,0")))]
257 
  ""
258 
  "abs.w\t%0"
259 
  [(set_attr "flags" "oszc")]
260 
  )

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