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[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [config/] [m32c/] [m32c.opt] - Blame information for rev 801

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Line No. Rev Author Line
1 709 jeremybenn
; Target Options for R8C/M16C/M32C
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; Copyright (C) 2005, 2007, 2011
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; Free Software Foundation, Inc.
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; Contributed by Red Hat.
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;
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; This file is part of GCC.
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;
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; GCC is free software; you can redistribute it and/or modify it
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; under the terms of the GNU General Public License as published
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; by the Free Software Foundation; either version 3, or (at your
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; option) any later version.
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;
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; GCC is distributed in the hope that it will be useful, but WITHOUT
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; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
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; License for more details.
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;
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; You should have received a copy of the GNU General Public License
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; along with GCC; see the file COPYING3.  If not see
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; .
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msim
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Target
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-msim   Use simulator runtime
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mcpu=r8c
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Target RejectNegative Var(target_cpu,'r') Init('r')
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-mcpu=r8c       Compile code for R8C variants
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mcpu=m16c
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Target RejectNegative Var(target_cpu,'6')
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-mcpu=m16c      Compile code for M16C variants
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mcpu=m32cm
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Target RejectNegative Var(target_cpu,'m')
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-mcpu=m32cm     Compile code for M32CM variants
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mcpu=m32c
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Target RejectNegative Var(target_cpu,'3')
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-mcpu=m32c      Compile code for M32C variants
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memregs=
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Target RejectNegative Joined UInteger Var(target_memregs) Init(16)
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-memregs=       Number of memreg bytes (default: 16, range: 0..16)

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