OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [config/] [m32c/] [mov.md] - Blame information for rev 720

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 709 jeremybenn 
;; Machine Descriptions for R8C/M16C/M32C
2 
;; Copyright (C) 2005, 2007, 2008, 2010
3 
;; Free Software Foundation, Inc.
4 
;; Contributed by Red Hat.
5 
;;
6 
;; This file is part of GCC.
7 
;;
8 
;; GCC is free software; you can redistribute it and/or modify it
9 
;; under the terms of the GNU General Public License as published
10 
;; by the Free Software Foundation; either version 3, or (at your
11 
;; option) any later version.
12 
;;
13 
;; GCC is distributed in the hope that it will be useful, but WITHOUT
14 
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 
;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
16 
;; License for more details.
17 
;;
18 
;; You should have received a copy of the GNU General Public License
19 
;; along with GCC; see the file COPYING3.  If not see
20 
;; .
21 
 
22 
;; move, push, extend, etc.
23 
 
24 
;; Be careful to never create an alternative that has memory as both
25 
;; src and dest, as that makes gcc think that mem-mem moves in general
26 
;; are supported.  While the chip does support this, it only has two
27 
;; address registers and sometimes gcc requires more than that.  One
28 
;; example is code like this: a = *b where both a and b are spilled to
29 
;; the stack.
30 
 
31 
(define_insn "mov_far_op1"
32 
  [(set (match_operand:QHI 0 "register_operand" "=Rhi")
33 
        (mem:QHI (plus:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "Ra0"))
34 
                         (match_operand 2 "immediate_operand" "si"))))
35 
   ]
36 
  ""
37 
  "lde.\t%D2[%1],%0"
38 
  [(set_attr "flags" "sz")]
39 
  )
40 
 
41 
(define_insn "mov_far_op2"
42 
  [(set (mem:QHI (plus:SI (sign_extend:SI (match_operand:HI 0 "register_operand" "Ra0"))
43 
                         (match_operand 1 "immediate_operand" "si")))
44 
        (match_operand:QHI 2 "register_operand"
45 
                          "=Rhi"))
46 
   ]
47 
  ""
48 
  "ste.\t%2,%D1[%0]"
49 
  [(set_attr "flags" "sz")]
50 
  )
51 
 
52 
;; Match push/pop before mov.b for passing char as arg,
53 
;; e.g. stdlib/efgcvt.c.
54 
(define_insn "movqi_op"
55 
  [(set (match_operand:QI 0 "m32c_nonimmediate_operand"
56 
                          "=SF,Rhi*Rmm, Rqi*Rmm, <,          RqiSd*Rmm, SdSs,    Rqi*Rmm, Sd")
57 
        (match_operand:QI 1 "m32c_any_operand"
58 
                          "Rhi*Rmm,SF, iRqi*Rmm, iRqiSd*Rmm, >,         Rqi*Rmm, SdSs,    i"))]
59 
  "m32c_mov_ok (operands, QImode)"
60 
  "@
61 
    lde.b\t%1,%0
62 
    ste.b\t%1,%0
63 
    mov.b\t%1,%0
64 
    push.b\t%1
65 
    pop.b\t%0
66 
    mov.b\t%1,%0
67 
    mov.b\t%1,%0
68 
    mov.b\t%1,%0"
69 
  [(set_attr "flags" "sz,sz,sz,*,*,sz,sz,sz")]
70 
  )
71 
 
72 
(define_expand "movqi"
73 
  [(set (match_operand:QI 0 "nonimmediate_operand" "=RqiSd*Rmm")
74 
        (match_operand:QI 1 "general_operand" "iRqiSd*Rmm"))]
75 
  ""
76 
  "if (m32c_prepare_move (operands, QImode)) DONE;"
77 
  )
78 
 
79 
 
80 
(define_insn "movhi_op"
81 
  [(set (match_operand:HI 0 "m32c_nonimmediate_operand"
82 
                          "=SF,Rhi*Rmm, Rhi*Rmm,     Sd, SdSs,   *Rcr, RhiSd*Rmm, <, RhiSd*Rmm, <, *Rcr")
83 
        (match_operand:HI 1 "m32c_any_operand"
84 
                          " Rhi*Rmm,SF, iRhi*RmmSdSs, i, Rhi*Rmm, RhiSd*Rmm, *Rcr, iRhiSd*Rmm, >, *Rcr, >"))]
85 
  "m32c_mov_ok (operands, HImode)"
86 
  "@
87 
   ste.w\t%1,%0
88 
   lde.w\t%1,%0
89 
   mov.w\t%1,%0
90 
   mov.w\t%1,%0
91 
   mov.w\t%1,%0
92 
   ldc\t%1,%0
93 
   stc\t%1,%0
94 
   push.w\t%1
95 
   pop.w\t%0
96 
   pushc\t%1
97 
   popc\t%0"
98 
  [(set_attr "flags" "sz,sz,sz,sz,sz,n,n,n,n,n,n")]
99 
  )
100 
 
101 
(define_expand "movhi"
102 
  [(set (match_operand:HI 0 "m32c_nonimmediate_operand" "=RhiSd*Rmm")
103 
        (match_operand:HI 1 "m32c_any_operand" "iRhiSd*Rmm"))]
104 
  ""
105 
  "if (m32c_prepare_move (operands, HImode)) DONE;"
106 
  )
107 
 
108 
 
109 
(define_insn "movpsi_op"
110 
  [(set (match_operand:PSI 0 "m32c_nonimmediate_operand"
111 
                           "=Raa, SdRmmRpi,  Rcl,  RpiSd*Rmm, <,       <, Rcl, RpiRaa*Rmm")
112 
        (match_operand:PSI 1 "m32c_any_operand"
113 
                           "sIU3, iSdRmmRpi, iRpiSd*Rmm, Rcl, Rpi*Rmm, Rcl, >, >"))]
114 
  "TARGET_A24 && m32c_mov_ok (operands, PSImode)"
115 
  "@
116 
   mov.l:s\t%1,%0
117 
   mov.l\t%1,%0
118 
   ldc\t%1,%0
119 
   stc\t%1,%0
120 
   push.l\t%1
121 
   pushc\t%1
122 
   popc\t%0
123 
   #"
124 
  [(set_attr "flags" "sz,sz,n,n,n,n,n,*")]
125 
  )
126 
 
127 
 
128 
;; The intention here is to combine the add with the move to create an
129 
;; indexed move.  GCC doesn't always figure this out itself.
130 
 
131 
(define_peephole2
132 
  [(set (match_operand:HPSI 0 "register_operand" "")
133 
        (plus:HPSI (match_operand:HPSI 1 "register_operand" "")
134 
                   (match_operand:HPSI 2 "immediate_operand" "")))
135 
   (set (match_operand:QHSI 3 "nonimmediate_operand" "")
136 
        (mem:QHSI (match_operand:HPSI 4 "register_operand" "")))]
137 
  "REGNO (operands[0]) == REGNO (operands[1])
138 
   && REGNO (operands[0]) == REGNO (operands[4])
139 
   && (rtx_equal_p (operands[0], operands[3])
140 
       || (dead_or_set_p (peep2_next_insn (1), operands[4])
141 
          && ! reg_mentioned_p (operands[0], operands[3])))"
142 
  [(set (match_dup 3)
143 
        (mem:QHSI (plus:HPSI (match_dup 1)
144 
                             (match_dup 2))))]
145 
  "")
146 
 
147 
(define_peephole2
148 
  [(set (match_operand:HPSI 0 "register_operand" "")
149 
        (plus:HPSI (match_operand:HPSI 1 "register_operand" "")
150 
                   (match_operand:HPSI 2 "immediate_operand" "")))
151 
   (set (mem:QHSI (match_operand:HPSI 4 "register_operand" ""))
152 
        (match_operand:QHSI 3 "m32c_any_operand" ""))]
153 
  "REGNO (operands[0]) == REGNO (operands[1])
154 
   && REGNO (operands[0]) == REGNO (operands[4])
155 
   && dead_or_set_p (peep2_next_insn (1), operands[4])
156 
   && ! reg_mentioned_p (operands[0], operands[3])"
157 
  [(set (mem:QHSI (plus:HPSI (match_dup 1)
158 
                             (match_dup 2)))
159 
        (match_dup 3))]
160 
  "")
161 
 
162 
; Peephole to generate SImode mov instructions for storing an
163 
; immediate double data to a memory location.
164 
(define_peephole2
165 
  [(set (match_operand:HI 0 "memory_operand" "")
166 
        (match_operand 1 "const_int_operand" ""))
167 
   (set (match_operand:HI 2 "memory_operand" "")
168 
        (match_operand 3 "const_int_operand" ""))]
169 
   "TARGET_A24 && m32c_immd_dbl_mov (operands, HImode)"
170 
   [(set (match_dup 4) (match_dup 5))]
171 
   ""
172 
)
173 
 
174 
; Some PSI moves must be split.
175 
(define_split
176 
  [(set (match_operand:PSI 0 "m32c_nonimmediate_operand" "")
177 
        (match_operand:PSI 1 "m32c_any_operand" ""))]
178 
  "reload_completed && m32c_split_psi_p (operands)"
179 
  [(set (match_dup 2)
180 
        (match_dup 3))
181 
   (set (match_dup 4)
182 
        (match_dup 5))]
183 
  "m32c_split_move (operands, PSImode, 3);"
184 
  )
185 
 
186 
(define_expand "movpsi"
187 
  [(set (match_operand:PSI 0 "m32c_nonimmediate_operand" "")
188 
        (match_operand:PSI 1 "m32c_any_operand" ""))]
189 
  ""
190 
  "if (m32c_prepare_move (operands, PSImode)) DONE;"
191 
  )
192 
 
193 
 
194 
 
195 
(define_expand "movsi"
196 
  [(set (match_operand:SI 0 "m32c_nonimmediate_operand" "=RsiSd*Rmm")
197 
        (match_operand:SI 1 "m32c_any_operand" "iRsiSd*Rmm"))]
198 
  ""
199 
  "if (m32c_split_move (operands, SImode, 0)) DONE;"
200 
  )
201 
 
202 
; All SI moves are split if TARGET_A16
203 
(define_insn_and_split "movsi_splittable"
204 
  [(set (match_operand:SI 0 "m32c_nonimmediate_operand" "=RsiRaa<*Rmm,  RsiRaaSd*Rmm,  Ss")
205 
        (match_operand:SI 1 "m32c_any_operand" "iRsiRaaSd*Rmm,  iRsiRaa>*Rmm,  RsiRaa*Rmm"))]
206 
  "TARGET_A16"
207 
  "#"
208 
  "TARGET_A16"
209 
  [(pc)]
210 
  "m32c_split_move (operands, SImode, 1); DONE;"
211 
  )
212 
 
213 
; The movsi pattern doesn't always match because sometimes the modes
214 
; don't match.
215 
(define_insn "push_a01_l"
216 
  [(set (mem:SI (pre_dec:PSI (reg:PSI SP_REGNO)))
217 
        (match_operand 0 "a_operand" "Raa"))]
218 
  ""
219 
  "push.l\t%0"
220 
  [(set_attr "flags" "n")]
221 
  )
222 
 
223 
(define_insn "movsi_24"
224 
  [(set (match_operand:SI 0 "m32c_nonimmediate_operand"  "=Rsi*Rmm,   Sd,       RsiSd*Rmm,     <")
225 
        (match_operand:SI 1 "m32c_any_operand" "iRsiSd*Rmm, iRsi*Rmm, >, iRsiRaaSd*Rmm"))]
226 
  "TARGET_A24"
227 
  "@
228 
   mov.l\t%1,%0
229 
   mov.l\t%1,%0
230 
   #
231 
   push.l\t%1"
232 
  [(set_attr "flags" "sz,sz,*,n")]
233 
  )
234 
 
235 
(define_expand "movdi"
236 
  [(set (match_operand:DI 0 "m32c_nonimmediate_operand" "=RdiSd*Rmm")
237 
        (match_operand:DI 1 "m32c_any_operand" "iRdiSd*Rmm"))]
238 
  ""
239 
  "if (m32c_split_move (operands, DImode, 0)) DONE;"
240 
  )
241 
 
242 
(define_insn_and_split "movdi_splittable"
243 
  [(set (match_operand:DI 0 "m32c_nonimmediate_operand" "=Rdi<*Rmm,RdiSd*Rmm")
244 
        (match_operand:DI 1 "m32c_any_operand" "iRdiSd*Rmm,iRdi>*Rmm"))]
245 
  ""
246 
  "#"
247 
  "reload_completed"
248 
  [(pc)]
249 
  "m32c_split_move (operands, DImode, 1); DONE;"
250 
  )
251 
 
252 
 
253 
 
254 
 
255 
(define_insn "pushqi"
256 
  [(set (mem:QI (pre_dec:PSI (reg:PSI SP_REGNO)))
257 
        (match_operand:QI 0 "mrai_operand" "iRqiSd*Rmm"))]
258 
  ""
259 
  "push.b\t%0"
260 
  [(set_attr "flags" "n")]
261 
  )
262 
 
263 
(define_expand "pushhi"
264 
  [(set (mem:HI (pre_dec:PSI (reg:PSI SP_REGNO)))
265 
        (match_operand:HI 0 "" ""))]
266 
  ""
267 
  "if (TARGET_A16)
268 
     gen_pushhi_16 (operands[0]);
269 
   else
270 
     gen_pushhi_24 (operands[0]);
271 
   DONE;"
272 
  )
273 
 
274 
(define_insn "pushhi_16"
275 
  [(set (mem:HI (pre_dec:HI (reg:HI SP_REGNO)))
276 
        (match_operand:HI 0 "mrai_operand" "iRhiSd*Rmm,Rcr"))]
277 
  "TARGET_A16"
278 
  "@
279 
   push.w\t%0
280 
   pushc\t%0"
281 
  [(set_attr "flags" "n,n")]
282 
  )
283 
 
284 
(define_insn "pushhi_24"
285 
  [(set (mem:HI (pre_dec:PSI (reg:PSI SP_REGNO)))
286 
        (match_operand:HI 0 "mrai_operand" "iRhiSd*Rmm"))]
287 
  "TARGET_A24"
288 
  "push.w\t%0"
289 
  [(set_attr "flags" "n")]
290 
  )
291 
 
292 
;(define_insn "pushpi"
293 
;  [(set (mem:PSI (pre_dec:PSI (reg:PSI SP_REGNO)))
294 
;        (match_operand:PI 0 "mrai_operand" "iRaa,Rcr"))]
295 
;  "TARGET_A24"
296 
;  "@
297 
;   push.l\t%0
298 
;   pushc\t%0"
299 
;  )
300 
 
301 
(define_insn "pushsi"
302 
  [(set (mem:SI (pre_dec:PSI (reg:PSI SP_REGNO)))
303 
        (match_operand:SI 0 "mrai_operand" "iRsiSd*Rmm"))]
304 
  "TARGET_A24"
305 
  "push.l\t%0"
306 
  [(set_attr "flags" "n")]
307 
  )
308 
 
309 
(define_expand "pophi"
310 
  [(set (match_operand:HI 0 "mra_operand" "=RhiSd*Rmm,Rcr")
311 
        (mem:HI (post_inc:HI (reg:HI SP_REGNO))))]
312 
  ""
313 
  "if (TARGET_A16)
314 
     gen_pophi_16 (operands[0]);
315 
   else
316 
     gen_pophi_24 (operands[0]);
317 
   DONE;"
318 
  )
319 
 
320 
(define_insn "pophi_16"
321 
  [(set (match_operand:HI 0 "mra_operand" "=RhiSd*Rmm,Rcr")
322 
        (mem:HI (post_inc:HI (reg:HI SP_REGNO))))]
323 
  "TARGET_A16"
324 
  "@
325 
   pop.w\t%0
326 
   popc\t%0"
327 
  [(set_attr "flags" "n,n")]
328 
  )
329 
 
330 
(define_insn "pophi_24"
331 
  [(set (match_operand:HI 0 "mra_operand" "=RhiSd*Rmm")
332 
        (mem:HI (post_inc:PSI (reg:PSI SP_REGNO))))]
333 
  "TARGET_A24"
334 
  "pop.w\t%0"
335 
  [(set_attr "flags" "n")]
336 
  )
337 
 
338 
(define_insn "poppsi"
339 
  [(set (match_operand:PSI 0 "cr_operand" "=Rcl")
340 
        (mem:PSI (post_inc:PSI (reg:PSI SP_REGNO))))]
341 
  "TARGET_A24"
342 
  "popc\t%0"
343 
  [(set_attr "flags" "n")]
344 
  )
345 
 
346 
 
347 
;; Rhl used here as an HI-mode Rxl
348 
(define_insn "extendqihi2"
349 
[(set (match_operand:HI 0 "m32c_nonimmediate_operand" "=RhlSd*Rmm")
350 
        (sign_extend:HI (match_operand:QI 1 "mra_operand" "0")))]
351 
  ""
352 
  "exts.b\t%1"
353 
  [(set_attr "flags" "sz")]
354 
  )
355 
 
356 
(define_insn "extendhisi2"
357 
  [(set (match_operand:SI 0 "register_operand" "=R03")
358 
        (sign_extend:SI (match_operand:HI 1 "r0123_operand" "0")))]
359 
  ""
360 
  "*
361 
   if (REGNO(operands[0]) == 0) return \"exts.w\t%1\";
362 
   else return \"mov.w r1,r3 | sha.w #-8,r3 | sha.w #-7,r3\";"
363 
  [(set_attr "flags" "x")]
364 
  )
365 
 
366 
(define_insn "extendhipsi2"
367 
  [(set (match_operand:PSI 0 "register_operand" "=R03")
368 
        (sign_extend:PSI (match_operand:HI 1 "register_operand" "0")))]
369 
  ""
370 
  "*
371 
   if (REGNO(operands[0]) == 0) return \"exts.w\t%1\";
372 
   else return \"mov.w r1,r3 | sha.w #-8,r3 | sha.w #-7,r3\";"
373 
  [(set_attr "flags" "x")]
374 
  )
375 
 
376 
(define_insn "extendpsisi2"
377 
  [(set (match_operand:SI 0 "mr_operand" "=R03Sd*Rmm")
378 
        (sign_extend:SI (match_operand:PSI 1 "mr_operand" "0")))]
379 
  ""
380 
  "; expand psi %1 to si %0"
381 
  [(set_attr "flags" "n")]
382 
  )
383 
 
384 
(define_insn "zero_extendpsisi2"
385 
  [(set (match_operand:SI 0 "mr_operand" "=R03Sd*Rmm")
386 
        (zero_extend:SI (match_operand:PSI 1 "mr_operand" "0")))]
387 
  ""
388 
  "; expand psi %1 to si %0"
389 
  [(set_attr "flags" "n")]
390 
  )
391 
 
392 
(define_insn "zero_extendhipsi2"
393 
  [(set (match_operand:PSI 0 "register_operand" "=Raa")
394 
        (truncate:PSI (zero_extend:SI (match_operand:HI 1 "register_operand" "R03"))))]
395 
  ""
396 
  "mov.w\t%1,%0"
397 
  [(set_attr "flags" "sz")]
398 
  )
399 
 
400 
(define_insn "zero_extendhisi2"
401 
  [(set (match_operand:SI 0 "m32c_nonimmediate_operand" "=RsiSd")
402 
        (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0")))]
403 
  ""
404 
  "mov.w\t#0,%H0"
405 
  [(set_attr "flags" "x")]
406 
  )
407 
 
408 
(define_insn "zero_extendqihi2"
409 
  [(set (match_operand:HI 0 "m32c_nonimmediate_operand" "=?Rhl,RhiSd*Rmm")
410 
        (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,0")))]
411 
  ""
412 
  "@
413 
   mov.b\t#0,%H0
414 
   and.w\t#255,%0"
415 
  [(set_attr "flags" "x,x")]
416 
  )
417 
 
418 
(define_insn "truncsipsi2_16"
419 
  [(set (match_operand:PSI 0 "m32c_nonimmediate_operand" "=RsiRadSd*Rmm,Raa,Rcr,RsiSd*Rmm")
420 
        (truncate:PSI (match_operand:SI 1 "nonimmediate_operand" "0,RsiSd*Rmm,RsiSd*Rmm,Rcr")))]
421 
  "TARGET_A16"
422 
  "@
423 
   ; no-op trunc si %1 to psi %0
424 
   #
425 
   ldc\t%1,%0
426 
   stc\t%1,%0"
427 
  [(set_attr "flags" "n,*,n,n")]
428 
  )
429 
 
430 
(define_insn "trunchiqi2"
431 
  [(set (match_operand:QI 0 "m32c_nonimmediate_operand" "=RqiRmmSd")
432 
        (truncate:QI (match_operand:HI 1 "mra_qi_operand" "0")))]
433 
  ""
434 
  "; no-op trunc hi %1 to qi %0"
435 
  [(set_attr "flags" "n")]
436 
  )
437 
 
438 
(define_insn "truncsipsi2_24"
439 
  [(set (match_operand:PSI 0              "m32c_nonimmediate_operand" "=RsiSd*Rmm,Raa,!Rcl,RsiSd*Rmm")
440 
        (truncate:PSI (match_operand:SI 1 "m32c_nonimmediate_operand" "0,RsiSd*Rmm,RsiSd*Rmm,!Rcl")))]
441 
  "TARGET_A24"
442 
  "@
443 
   ; no-op trunc si %1 to psi %0
444 
   mov.l\t%1,%0
445 
   ldc\t%1,%0
446 
   stc\t%1,%0"
447 
  [(set_attr "flags" "n,sz,n,n")]
448 
  )
449 
 
450 
(define_expand "truncsipsi2"
451 
  [(set (match_operand:PSI 0 "m32c_nonimmediate_operand" "=RsiRadSd*Rmm,Raa,Rcr,RsiSd*Rmm")
452 
        (truncate:PSI (match_operand:SI 1 "m32c_nonimmediate_operand" "0,RsiSd*Rmm,RsiSd*Rmm,Rcr")))]
453 
  ""
454 
  ""
455 
  )
456 
 
457 
(define_expand "reload_inqi"
458 
  [(set (match_operand:QI 2 "" "=&Rqi")
459 
        (match_operand:QI 1 "" ""))
460 
   (set (match_operand:QI 0 "" "")
461 
        (match_dup 2))
462 
   ]
463 
  ""
464 
  "")
465 
 
466 
(define_expand "reload_outqi"
467 
  [(set (match_operand:QI 2 "" "=&Rqi")
468 
        (match_operand:QI 1 "" ""))
469 
   (set (match_operand:QI 0 "" "")
470 
        (match_dup 2))
471 
   ]
472 
  ""
473 
  "")
474 
 
475 
(define_expand "reload_inhi"
476 
  [(set (match_operand:HI 2 "" "=&Rhi")
477 
        (match_operand:HI 1 "" ""))
478 
   (set (match_operand:HI 0 "" "")
479 
        (match_dup 2))
480 
   ]
481 
  ""
482 
  "")
483 
 
484 
(define_expand "reload_outhi"
485 
  [(set (match_operand:HI 2 "" "=&Rhi")
486 
        (match_operand:HI 1 "" ""))
487 
   (set (match_operand:HI 0 "" "")
488 
        (match_dup 2))
489 
   ]
490 
  ""
491 
  "")

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.