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jeremybenn |
;; GCC machine description for m68k synchronization instructions.
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;; Copyright (C) 2011, 2012
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;; Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; .
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(define_expand "atomic_compare_and_swap"
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[(match_operand:QI 0 "register_operand" "") ;; bool success output
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(match_operand:I 1 "register_operand" "") ;; oldval output
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(match_operand:I 2 "memory_operand" "") ;; memory
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(match_operand:I 3 "register_operand" "") ;; expected input
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(match_operand:I 4 "register_operand" "") ;; newval input
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(match_operand:SI 5 "const_int_operand" "") ;; is_weak
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(match_operand:SI 6 "const_int_operand" "") ;; success model
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(match_operand:SI 7 "const_int_operand" "")] ;; failure model
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"TARGET_CAS"
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{
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emit_insn (gen_atomic_compare_and_swap_1
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(operands[0], operands[1], operands[2],
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operands[3], operands[4]));
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emit_insn (gen_negqi2 (operands[0], operands[0]));
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DONE;
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})
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(define_insn "atomic_compare_and_swap_1"
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[(set (match_operand:I 1 "register_operand" "=d")
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(unspec_volatile:I
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[(match_operand:I 2 "memory_operand" "+m")
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(match_operand:I 3 "register_operand" "1")
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(match_operand:I 4 "register_operand" "d")]
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UNSPECV_CAS_1))
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(set (match_dup 2)
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(unspec_volatile:I
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[(match_dup 2) (match_dup 3) (match_dup 4)]
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UNSPECV_CAS_2))
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(set (match_operand:QI 0 "register_operand" "=d")
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(unspec_volatile:QI
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[(match_dup 2) (match_dup 3) (match_dup 4)]
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UNSPECV_CAS_2))]
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"TARGET_CAS"
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;; Elide the seq if operands[0] is dead.
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"cas %1,%4,%2\;seq %0")
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(define_expand "atomic_test_and_set"
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[(match_operand:QI 0 "register_operand" "") ;; bool success output
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(match_operand:QI 1 "memory_operand" "") ;; memory
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(match_operand:SI 2 "const_int_operand" "")] ;; model
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""
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{
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emit_insn (gen_atomic_test_and_set_1 (operands[0], operands[1]));
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emit_insn (gen_negqi2 (operands[0], operands[0]));
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DONE;
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})
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(define_insn "atomic_test_and_set_1"
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[(set (match_operand:QI 0 "register_operand" "=d")
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(unspec_volatile:QI
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[(match_operand:QI 1 "memory_operand" "+m")]
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UNSPECV_TAS_1))
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(set (match_dup 1)
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(unspec_volatile:QI [(match_dup 1)] UNSPECV_TAS_2))]
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""
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"tas %1\;sne %0")
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