OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [config/] [mep/] [intrinsics.md] - Blame information for rev 757

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 709 jeremybenn 
 
2 
 
3 
;; DO NOT EDIT: This file is automatically generated by CGEN.
4 
;; Any changes you make will be discarded when it is next regenerated.
5 
 
6 
 
7 
(define_predicate "cgen_h_sint_12a1_immediate"
8 
  (and (match_code "const_int")
9 
        (match_test "(INTVAL (op) & 0) == 0
10 
                   && INTVAL (op) >= -2048
11 
                   && INTVAL (op) < 2048")))
12 
 
13 
(define_predicate "cgen_h_uint_20a1_immediate"
14 
  (and (match_code "const_int")
15 
        (match_test "(INTVAL (op) & 0) == 0
16 
                   && INTVAL (op) >= 0
17 
                   && INTVAL (op) < 1048576")))
18 
 
19 
(define_predicate "cgen_h_uint_7a1_immediate"
20 
  (and (match_code "const_int")
21 
        (match_test "(INTVAL (op) & 0) == 0
22 
                   && INTVAL (op) >= 0
23 
                   && INTVAL (op) < 128")))
24 
 
25 
(define_predicate "cgen_h_uint_6a2_immediate"
26 
  (and (match_code "const_int")
27 
        (match_test "(INTVAL (op) & 1) == 0
28 
                   && INTVAL (op) >= 0
29 
                   && INTVAL (op) < 128")))
30 
 
31 
(define_predicate "cgen_h_uint_22a4_immediate"
32 
  (and (match_code "const_int")
33 
        (match_test "(INTVAL (op) & 3) == 0
34 
                   && INTVAL (op) >= 0
35 
                   && INTVAL (op) < 33554432")))
36 
 
37 
(define_predicate "cgen_h_sint_2a1_immediate"
38 
  (and (match_code "const_int")
39 
        (match_test "(INTVAL (op) & 0) == 0
40 
                   && INTVAL (op) >= -2
41 
                   && INTVAL (op) < 2")))
42 
 
43 
(define_predicate "cgen_h_uint_24a1_immediate"
44 
  (and (match_code "const_int")
45 
        (match_test "(INTVAL (op) & 0) == 0
46 
                   && INTVAL (op) >= 0
47 
                   && INTVAL (op) < 16777216")))
48 
 
49 
(define_predicate "cgen_h_sint_6a1_immediate"
50 
  (and (match_code "const_int")
51 
        (match_test "(INTVAL (op) & 0) == 0
52 
                   && INTVAL (op) >= -32
53 
                   && INTVAL (op) < 32")))
54 
 
55 
(define_predicate "cgen_h_uint_5a4_immediate"
56 
  (and (match_code "const_int")
57 
        (match_test "(INTVAL (op) & 3) == 0
58 
                   && INTVAL (op) >= 0
59 
                   && INTVAL (op) < 256")))
60 
 
61 
(define_predicate "cgen_h_uint_2a1_immediate"
62 
  (and (match_code "const_int")
63 
        (match_test "(INTVAL (op) & 0) == 0
64 
                   && INTVAL (op) >= 0
65 
                   && INTVAL (op) < 4")))
66 
 
67 
(define_predicate "cgen_h_sint_10a1_immediate"
68 
  (and (match_code "const_int")
69 
        (match_test "(INTVAL (op) & 0) == 0
70 
                   && INTVAL (op) >= -512
71 
                   && INTVAL (op) < 512")))
72 
 
73 
(define_predicate "cgen_h_uint_4a1_immediate"
74 
  (and (match_code "const_int")
75 
        (match_test "(INTVAL (op) & 0) == 0
76 
                   && INTVAL (op) >= 0
77 
                   && INTVAL (op) < 16")))
78 
 
79 
(define_predicate "cgen_h_uint_6a1_immediate"
80 
  (and (match_code "const_int")
81 
        (match_test "(INTVAL (op) & 0) == 0
82 
                   && INTVAL (op) >= 0
83 
                   && INTVAL (op) < 64")))
84 
 
85 
(define_predicate "cgen_h_uint_16a1_immediate"
86 
  (and (match_code "const_int")
87 
        (match_test "(INTVAL (op) & 0) == 0
88 
                   && INTVAL (op) >= 0
89 
                   && INTVAL (op) < 65536")))
90 
 
91 
(define_predicate "cgen_h_uint_8a1_immediate"
92 
  (and (match_code "const_int")
93 
        (match_test "(INTVAL (op) & 0) == 0
94 
                   && INTVAL (op) >= 0
95 
                   && INTVAL (op) < 256")))
96 
 
97 
(define_predicate "cgen_h_sint_16a1_immediate"
98 
  (and (match_code "const_int")
99 
        (match_test "(INTVAL (op) & 0) == 0
100 
                   && INTVAL (op) >= -32768
101 
                   && INTVAL (op) < 32768")))
102 
 
103 
(define_predicate "cgen_h_uint_5a1_immediate"
104 
  (and (match_code "const_int")
105 
        (match_test "(INTVAL (op) & 0) == 0
106 
                   && INTVAL (op) >= 0
107 
                   && INTVAL (op) < 32")))
108 
 
109 
(define_predicate "cgen_h_sint_8a1_immediate"
110 
  (and (match_code "const_int")
111 
        (match_test "(INTVAL (op) & 0) == 0
112 
                   && INTVAL (op) >= -128
113 
                   && INTVAL (op) < 128")))
114 
 
115 
(define_predicate "cgen_h_uint_3a1_immediate"
116 
  (and (match_code "const_int")
117 
        (match_test "(INTVAL (op) & 0) == 0
118 
                   && INTVAL (op) >= 0
119 
                   && INTVAL (op) < 8")))
120 
 
121 
 
122 
 
123 
(define_insn "cgen_intrinsic_cpsmsbslla1_w_C3"
124 
  [(set (reg:SI 87)
125 
        (unspec_volatile:SI [
126 
          (match_operand:DI 0 "general_operand" "x")
127 
          (match_operand:DI 1 "general_operand" "x")
128 
        ] 2198))
129 
   (set (reg:SI 107)
130 
        (unspec_volatile:SI [
131 
          (match_dup 0)
132 
          (match_dup 1)
133 
        ] 2200))
134 
   (set (reg:SI 106)
135 
        (unspec_volatile:SI [
136 
          (match_dup 0)
137 
          (match_dup 1)
138 
        ] 2202))
139 
   (set (reg:SI 105)
140 
        (unspec_volatile:SI [
141 
          (match_dup 0)
142 
          (match_dup 1)
143 
        ] 2204))
144 
   (set (reg:SI 104)
145 
        (unspec_volatile:SI [
146 
          (match_dup 0)
147 
          (match_dup 1)
148 
        ] 2206))]
149 
  "CGEN_ENABLE_INSN_P (0)"
150 
  "cpsmsbslla1.w\\t%0,%1"
151 
  [(set_attr "may_trap" "no")
152 
   (set_attr "latency" "0")
153 
   (set_attr "length" "4")
154 
   (set_attr "slot" "cop")
155 
   (set_attr "slots" "c3")
156 
   (set_attr "stall" "none")])
157 
 
158 
 
159 
(define_insn "cgen_intrinsic_cpsmsbslla1_w_P1"
160 
  [(set (reg:SI 87)
161 
        (unspec_volatile:SI [
162 
          (match_operand:DI 0 "general_operand" "x")
163 
          (match_operand:DI 1 "general_operand" "x")
164 
        ] 2198))
165 
   (set (reg:SI 107)
166 
        (unspec_volatile:SI [
167 
          (match_dup 0)
168 
          (match_dup 1)
169 
        ] 2200))
170 
   (set (reg:SI 106)
171 
        (unspec_volatile:SI [
172 
          (match_dup 0)
173 
          (match_dup 1)
174 
        ] 2202))
175 
   (set (reg:SI 105)
176 
        (unspec_volatile:SI [
177 
          (match_dup 0)
178 
          (match_dup 1)
179 
        ] 2204))
180 
   (set (reg:SI 104)
181 
        (unspec_volatile:SI [
182 
          (match_dup 0)
183 
          (match_dup 1)
184 
        ] 2206))]
185 
  "CGEN_ENABLE_INSN_P (1)"
186 
  "cpsmsbslla1.w\\t%0,%1"
187 
  [(set_attr "may_trap" "no")
188 
   (set_attr "latency" "0")
189 
   (set_attr "length" "4")
190 
   (set_attr "slot" "cop")
191 
   (set_attr "slots" "p1")
192 
   (set_attr "stall" "none")])
193 
 
194 
 
195 
(define_insn "cgen_intrinsic_cpsmsbslua1_w_C3"
196 
  [(set (reg:SI 87)
197 
        (unspec_volatile:SI [
198 
          (match_operand:DI 0 "general_operand" "x")
199 
          (match_operand:DI 1 "general_operand" "x")
200 
        ] 2208))
201 
   (set (reg:SI 111)
202 
        (unspec_volatile:SI [
203 
          (match_dup 0)
204 
          (match_dup 1)
205 
        ] 2210))
206 
   (set (reg:SI 110)
207 
        (unspec_volatile:SI [
208 
          (match_dup 0)
209 
          (match_dup 1)
210 
        ] 2212))
211 
   (set (reg:SI 109)
212 
        (unspec_volatile:SI [
213 
          (match_dup 0)
214 
          (match_dup 1)
215 
        ] 2214))
216 
   (set (reg:SI 108)
217 
        (unspec_volatile:SI [
218 
          (match_dup 0)
219 
          (match_dup 1)
220 
        ] 2216))]
221 
  "CGEN_ENABLE_INSN_P (2)"
222 
  "cpsmsbslua1.w\\t%0,%1"
223 
  [(set_attr "may_trap" "no")
224 
   (set_attr "latency" "0")
225 
   (set_attr "length" "4")
226 
   (set_attr "slot" "cop")
227 
   (set_attr "slots" "c3")
228 
   (set_attr "stall" "none")])
229 
 
230 
 
231 
(define_insn "cgen_intrinsic_cpsmsbslua1_w_P1"
232 
  [(set (reg:SI 87)
233 
        (unspec_volatile:SI [
234 
          (match_operand:DI 0 "general_operand" "x")
235 
          (match_operand:DI 1 "general_operand" "x")
236 
        ] 2208))
237 
   (set (reg:SI 111)
238 
        (unspec_volatile:SI [
239 
          (match_dup 0)
240 
          (match_dup 1)
241 
        ] 2210))
242 
   (set (reg:SI 110)
243 
        (unspec_volatile:SI [
244 
          (match_dup 0)
245 
          (match_dup 1)
246 
        ] 2212))
247 
   (set (reg:SI 109)
248 
        (unspec_volatile:SI [
249 
          (match_dup 0)
250 
          (match_dup 1)
251 
        ] 2214))
252 
   (set (reg:SI 108)
253 
        (unspec_volatile:SI [
254 
          (match_dup 0)
255 
          (match_dup 1)
256 
        ] 2216))]
257 
  "CGEN_ENABLE_INSN_P (3)"
258 
  "cpsmsbslua1.w\\t%0,%1"
259 
  [(set_attr "may_trap" "no")
260 
   (set_attr "latency" "0")
261 
   (set_attr "length" "4")
262 
   (set_attr "slot" "cop")
263 
   (set_attr "slots" "p1")
264 
   (set_attr "stall" "none")])
265 
 
266 
 
267 
(define_insn "cgen_intrinsic_cpsmsbslla1_h_C3"
268 
  [(set (reg:SI 87)
269 
        (unspec_volatile:SI [
270 
          (match_operand:DI 0 "general_operand" "x")
271 
          (match_operand:DI 1 "general_operand" "x")
272 
        ] 2218))
273 
   (set (reg:SI 107)
274 
        (unspec_volatile:SI [
275 
          (match_dup 0)
276 
          (match_dup 1)
277 
        ] 2220))
278 
   (set (reg:SI 106)
279 
        (unspec_volatile:SI [
280 
          (match_dup 0)
281 
          (match_dup 1)
282 
        ] 2222))
283 
   (set (reg:SI 105)
284 
        (unspec_volatile:SI [
285 
          (match_dup 0)
286 
          (match_dup 1)
287 
        ] 2224))
288 
   (set (reg:SI 104)
289 
        (unspec_volatile:SI [
290 
          (match_dup 0)
291 
          (match_dup 1)
292 
        ] 2226))]
293 
  "CGEN_ENABLE_INSN_P (4)"
294 
  "cpsmsbslla1.h\\t%0,%1"
295 
  [(set_attr "may_trap" "no")
296 
   (set_attr "latency" "0")
297 
   (set_attr "length" "4")
298 
   (set_attr "slot" "cop")
299 
   (set_attr "slots" "c3")
300 
   (set_attr "stall" "none")])
301 
 
302 
 
303 
(define_insn "cgen_intrinsic_cpsmsbslla1_h_P1"
304 
  [(set (reg:SI 87)
305 
        (unspec_volatile:SI [
306 
          (match_operand:DI 0 "general_operand" "x")
307 
          (match_operand:DI 1 "general_operand" "x")
308 
        ] 2218))
309 
   (set (reg:SI 107)
310 
        (unspec_volatile:SI [
311 
          (match_dup 0)
312 
          (match_dup 1)
313 
        ] 2220))
314 
   (set (reg:SI 106)
315 
        (unspec_volatile:SI [
316 
          (match_dup 0)
317 
          (match_dup 1)
318 
        ] 2222))
319 
   (set (reg:SI 105)
320 
        (unspec_volatile:SI [
321 
          (match_dup 0)
322 
          (match_dup 1)
323 
        ] 2224))
324 
   (set (reg:SI 104)
325 
        (unspec_volatile:SI [
326 
          (match_dup 0)
327 
          (match_dup 1)
328 
        ] 2226))]
329 
  "CGEN_ENABLE_INSN_P (5)"
330 
  "cpsmsbslla1.h\\t%0,%1"
331 
  [(set_attr "may_trap" "no")
332 
   (set_attr "latency" "0")
333 
   (set_attr "length" "4")
334 
   (set_attr "slot" "cop")
335 
   (set_attr "slots" "p1")
336 
   (set_attr "stall" "none")])
337 
 
338 
 
339 
(define_insn "cgen_intrinsic_cpsmsbslua1_h_C3"
340 
  [(set (reg:SI 87)
341 
        (unspec_volatile:SI [
342 
          (match_operand:DI 0 "general_operand" "x")
343 
          (match_operand:DI 1 "general_operand" "x")
344 
        ] 2228))
345 
   (set (reg:SI 111)
346 
        (unspec_volatile:SI [
347 
          (match_dup 0)
348 
          (match_dup 1)
349 
        ] 2230))
350 
   (set (reg:SI 110)
351 
        (unspec_volatile:SI [
352 
          (match_dup 0)
353 
          (match_dup 1)
354 
        ] 2232))
355 
   (set (reg:SI 109)
356 
        (unspec_volatile:SI [
357 
          (match_dup 0)
358 
          (match_dup 1)
359 
        ] 2234))
360 
   (set (reg:SI 108)
361 
        (unspec_volatile:SI [
362 
          (match_dup 0)
363 
          (match_dup 1)
364 
        ] 2236))]
365 
  "CGEN_ENABLE_INSN_P (6)"
366 
  "cpsmsbslua1.h\\t%0,%1"
367 
  [(set_attr "may_trap" "no")
368 
   (set_attr "latency" "0")
369 
   (set_attr "length" "4")
370 
   (set_attr "slot" "cop")
371 
   (set_attr "slots" "c3")
372 
   (set_attr "stall" "none")])
373 
 
374 
 
375 
(define_insn "cgen_intrinsic_cpsmsbslua1_h_P1"
376 
  [(set (reg:SI 87)
377 
        (unspec_volatile:SI [
378 
          (match_operand:DI 0 "general_operand" "x")
379 
          (match_operand:DI 1 "general_operand" "x")
380 
        ] 2228))
381 
   (set (reg:SI 111)
382 
        (unspec_volatile:SI [
383 
          (match_dup 0)
384 
          (match_dup 1)
385 
        ] 2230))
386 
   (set (reg:SI 110)
387 
        (unspec_volatile:SI [
388 
          (match_dup 0)
389 
          (match_dup 1)
390 
        ] 2232))
391 
   (set (reg:SI 109)
392 
        (unspec_volatile:SI [
393 
          (match_dup 0)
394 
          (match_dup 1)
395 
        ] 2234))
396 
   (set (reg:SI 108)
397 
        (unspec_volatile:SI [
398 
          (match_dup 0)
399 
          (match_dup 1)
400 
        ] 2236))]
401 
  "CGEN_ENABLE_INSN_P (7)"
402 
  "cpsmsbslua1.h\\t%0,%1"
403 
  [(set_attr "may_trap" "no")
404 
   (set_attr "latency" "0")
405 
   (set_attr "length" "4")
406 
   (set_attr "slot" "cop")
407 
   (set_attr "slots" "p1")
408 
   (set_attr "stall" "none")])
409 
 
410 
 
411 
(define_insn "cgen_intrinsic_cpsmadslla1_w_C3"
412 
  [(set (reg:SI 87)
413 
        (unspec_volatile:SI [
414 
          (match_operand:DI 0 "general_operand" "x")
415 
          (match_operand:DI 1 "general_operand" "x")
416 
        ] 2238))
417 
   (set (reg:SI 107)
418 
        (unspec_volatile:SI [
419 
          (match_dup 0)
420 
          (match_dup 1)
421 
        ] 2240))
422 
   (set (reg:SI 106)
423 
        (unspec_volatile:SI [
424 
          (match_dup 0)
425 
          (match_dup 1)
426 
        ] 2242))
427 
   (set (reg:SI 105)
428 
        (unspec_volatile:SI [
429 
          (match_dup 0)
430 
          (match_dup 1)
431 
        ] 2244))
432 
   (set (reg:SI 104)
433 
        (unspec_volatile:SI [
434 
          (match_dup 0)
435 
          (match_dup 1)
436 
        ] 2246))]
437 
  "CGEN_ENABLE_INSN_P (8)"
438 
  "cpsmadslla1.w\\t%0,%1"
439 
  [(set_attr "may_trap" "no")
440 
   (set_attr "latency" "0")
441 
   (set_attr "length" "4")
442 
   (set_attr "slot" "cop")
443 
   (set_attr "slots" "c3")
444 
   (set_attr "stall" "none")])
445 
 
446 
 
447 
(define_insn "cgen_intrinsic_cpsmadslla1_w_P1"
448 
  [(set (reg:SI 87)
449 
        (unspec_volatile:SI [
450 
          (match_operand:DI 0 "general_operand" "x")
451 
          (match_operand:DI 1 "general_operand" "x")
452 
        ] 2238))
453 
   (set (reg:SI 107)
454 
        (unspec_volatile:SI [
455 
          (match_dup 0)
456 
          (match_dup 1)
457 
        ] 2240))
458 
   (set (reg:SI 106)
459 
        (unspec_volatile:SI [
460 
          (match_dup 0)
461 
          (match_dup 1)
462 
        ] 2242))
463 
   (set (reg:SI 105)
464 
        (unspec_volatile:SI [
465 
          (match_dup 0)
466 
          (match_dup 1)
467 
        ] 2244))
468 
   (set (reg:SI 104)
469 
        (unspec_volatile:SI [
470 
          (match_dup 0)
471 
          (match_dup 1)
472 
        ] 2246))]
473 
  "CGEN_ENABLE_INSN_P (9)"
474 
  "cpsmadslla1.w\\t%0,%1"
475 
  [(set_attr "may_trap" "no")
476 
   (set_attr "latency" "0")
477 
   (set_attr "length" "4")
478 
   (set_attr "slot" "cop")
479 
   (set_attr "slots" "p1")
480 
   (set_attr "stall" "none")])
481 
 
482 
 
483 
(define_insn "cgen_intrinsic_cpsmadslua1_w_C3"
484 
  [(set (reg:SI 87)
485 
        (unspec_volatile:SI [
486 
          (match_operand:DI 0 "general_operand" "x")
487 
          (match_operand:DI 1 "general_operand" "x")
488 
        ] 2248))
489 
   (set (reg:SI 111)
490 
        (unspec_volatile:SI [
491 
          (match_dup 0)
492 
          (match_dup 1)
493 
        ] 2250))
494 
   (set (reg:SI 110)
495 
        (unspec_volatile:SI [
496 
          (match_dup 0)
497 
          (match_dup 1)
498 
        ] 2252))
499 
   (set (reg:SI 109)
500 
        (unspec_volatile:SI [
501 
          (match_dup 0)
502 
          (match_dup 1)
503 
        ] 2254))
504 
   (set (reg:SI 108)
505 
        (unspec_volatile:SI [
506 
          (match_dup 0)
507 
          (match_dup 1)
508 
        ] 2256))]
509 
  "CGEN_ENABLE_INSN_P (10)"
510 
  "cpsmadslua1.w\\t%0,%1"
511 
  [(set_attr "may_trap" "no")
512 
   (set_attr "latency" "0")
513 
   (set_attr "length" "4")
514 
   (set_attr "slot" "cop")
515 
   (set_attr "slots" "c3")
516 
   (set_attr "stall" "none")])
517 
 
518 
 
519 
(define_insn "cgen_intrinsic_cpsmadslua1_w_P1"
520 
  [(set (reg:SI 87)
521 
        (unspec_volatile:SI [
522 
          (match_operand:DI 0 "general_operand" "x")
523 
          (match_operand:DI 1 "general_operand" "x")
524 
        ] 2248))
525 
   (set (reg:SI 111)
526 
        (unspec_volatile:SI [
527 
          (match_dup 0)
528 
          (match_dup 1)
529 
        ] 2250))
530 
   (set (reg:SI 110)
531 
        (unspec_volatile:SI [
532 
          (match_dup 0)
533 
          (match_dup 1)
534 
        ] 2252))
535 
   (set (reg:SI 109)
536 
        (unspec_volatile:SI [
537 
          (match_dup 0)
538 
          (match_dup 1)
539 
        ] 2254))
540 
   (set (reg:SI 108)
541 
        (unspec_volatile:SI [
542 
          (match_dup 0)
543 
          (match_dup 1)
544 
        ] 2256))]
545 
  "CGEN_ENABLE_INSN_P (11)"
546 
  "cpsmadslua1.w\\t%0,%1"
547 
  [(set_attr "may_trap" "no")
548 
   (set_attr "latency" "0")
549 
   (set_attr "length" "4")
550 
   (set_attr "slot" "cop")
551 
   (set_attr "slots" "p1")
552 
   (set_attr "stall" "none")])
553 
 
554 
 
555 
(define_insn "cgen_intrinsic_cpsmadslla1_h_C3"
556 
  [(set (reg:SI 87)
557 
        (unspec_volatile:SI [
558 
          (match_operand:DI 0 "general_operand" "x")
559 
          (match_operand:DI 1 "general_operand" "x")
560 
        ] 2258))
561 
   (set (reg:SI 107)
562 
        (unspec_volatile:SI [
563 
          (match_dup 0)
564 
          (match_dup 1)
565 
        ] 2260))
566 
   (set (reg:SI 106)
567 
        (unspec_volatile:SI [
568 
          (match_dup 0)
569 
          (match_dup 1)
570 
        ] 2262))
571 
   (set (reg:SI 105)
572 
        (unspec_volatile:SI [
573 
          (match_dup 0)
574 
          (match_dup 1)
575 
        ] 2264))
576 
   (set (reg:SI 104)
577 
        (unspec_volatile:SI [
578 
          (match_dup 0)
579 
          (match_dup 1)
580 
        ] 2266))]
581 
  "CGEN_ENABLE_INSN_P (12)"
582 
  "cpsmadslla1.h\\t%0,%1"
583 
  [(set_attr "may_trap" "no")
584 
   (set_attr "latency" "0")
585 
   (set_attr "length" "4")
586 
   (set_attr "slot" "cop")
587 
   (set_attr "slots" "c3")
588 
   (set_attr "stall" "none")])
589 
 
590 
 
591 
(define_insn "cgen_intrinsic_cpsmadslla1_h_P1"
592 
  [(set (reg:SI 87)
593 
        (unspec_volatile:SI [
594 
          (match_operand:DI 0 "general_operand" "x")
595 
          (match_operand:DI 1 "general_operand" "x")
596 
        ] 2258))
597 
   (set (reg:SI 107)
598 
        (unspec_volatile:SI [
599 
          (match_dup 0)
600 
          (match_dup 1)
601 
        ] 2260))
602 
   (set (reg:SI 106)
603 
        (unspec_volatile:SI [
604 
          (match_dup 0)
605 
          (match_dup 1)
606 
        ] 2262))
607 
   (set (reg:SI 105)
608 
        (unspec_volatile:SI [
609 
          (match_dup 0)
610 
          (match_dup 1)
611 
        ] 2264))
612 
   (set (reg:SI 104)
613 
        (unspec_volatile:SI [
614 
          (match_dup 0)
615 
          (match_dup 1)
616 
        ] 2266))]
617 
  "CGEN_ENABLE_INSN_P (13)"
618 
  "cpsmadslla1.h\\t%0,%1"
619 
  [(set_attr "may_trap" "no")
620 
   (set_attr "latency" "0")
621 
   (set_attr "length" "4")
622 
   (set_attr "slot" "cop")
623 
   (set_attr "slots" "p1")
624 
   (set_attr "stall" "none")])
625 
 
626 
 
627 
(define_insn "cgen_intrinsic_cpsmadslua1_h_C3"
628 
  [(set (reg:SI 87)
629 
        (unspec_volatile:SI [
630 
          (match_operand:DI 0 "general_operand" "x")
631 
          (match_operand:DI 1 "general_operand" "x")
632 
        ] 2268))
633 
   (set (reg:SI 111)
634 
        (unspec_volatile:SI [
635 
          (match_dup 0)
636 
          (match_dup 1)
637 
        ] 2270))
638 
   (set (reg:SI 110)
639 
        (unspec_volatile:SI [
640 
          (match_dup 0)
641 
          (match_dup 1)
642 
        ] 2272))
643 
   (set (reg:SI 109)
644 
        (unspec_volatile:SI [
645 
          (match_dup 0)
646 
          (match_dup 1)
647 
        ] 2274))
648 
   (set (reg:SI 108)
649 
        (unspec_volatile:SI [
650 
          (match_dup 0)
651 
          (match_dup 1)
652 
        ] 2276))]
653 
  "CGEN_ENABLE_INSN_P (14)"
654 
  "cpsmadslua1.h\\t%0,%1"
655 
  [(set_attr "may_trap" "no")
656 
   (set_attr "latency" "0")
657 
   (set_attr "length" "4")
658 
   (set_attr "slot" "cop")
659 
   (set_attr "slots" "c3")
660 
   (set_attr "stall" "none")])
661 
 
662 
 
663 
(define_insn "cgen_intrinsic_cpsmadslua1_h_P1"
664 
  [(set (reg:SI 87)
665 
        (unspec_volatile:SI [
666 
          (match_operand:DI 0 "general_operand" "x")
667 
          (match_operand:DI 1 "general_operand" "x")
668 
        ] 2268))
669 
   (set (reg:SI 111)
670 
        (unspec_volatile:SI [
671 
          (match_dup 0)
672 
          (match_dup 1)
673 
        ] 2270))
674 
   (set (reg:SI 110)
675 
        (unspec_volatile:SI [
676 
          (match_dup 0)
677 
          (match_dup 1)
678 
        ] 2272))
679 
   (set (reg:SI 109)
680 
        (unspec_volatile:SI [
681 
          (match_dup 0)
682 
          (match_dup 1)
683 
        ] 2274))
684 
   (set (reg:SI 108)
685 
        (unspec_volatile:SI [
686 
          (match_dup 0)
687 
          (match_dup 1)
688 
        ] 2276))]
689 
  "CGEN_ENABLE_INSN_P (15)"
690 
  "cpsmadslua1.h\\t%0,%1"
691 
  [(set_attr "may_trap" "no")
692 
   (set_attr "latency" "0")
693 
   (set_attr "length" "4")
694 
   (set_attr "slot" "cop")
695 
   (set_attr "slots" "p1")
696 
   (set_attr "stall" "none")])
697 
 
698 
 
699 
(define_insn "cgen_intrinsic_cpmulslla1_w_C3"
700 
  [(set (reg:SI 87)
701 
        (unspec_volatile:SI [
702 
          (match_operand:DI 0 "general_operand" "x")
703 
          (match_operand:DI 1 "general_operand" "x")
704 
        ] 2278))
705 
   (set (reg:SI 107)
706 
        (unspec_volatile:SI [
707 
          (match_dup 0)
708 
          (match_dup 1)
709 
        ] 2280))
710 
   (set (reg:SI 106)
711 
        (unspec_volatile:SI [
712 
          (match_dup 0)
713 
          (match_dup 1)
714 
        ] 2282))
715 
   (set (reg:SI 105)
716 
        (unspec_volatile:SI [
717 
          (match_dup 0)
718 
          (match_dup 1)
719 
        ] 2284))
720 
   (set (reg:SI 104)
721 
        (unspec_volatile:SI [
722 
          (match_dup 0)
723 
          (match_dup 1)
724 
        ] 2286))]
725 
  "CGEN_ENABLE_INSN_P (16)"
726 
  "cpmulslla1.w\\t%0,%1"
727 
  [(set_attr "may_trap" "no")
728 
   (set_attr "latency" "0")
729 
   (set_attr "length" "4")
730 
   (set_attr "slot" "cop")
731 
   (set_attr "slots" "c3")
732 
   (set_attr "stall" "none")])
733 
 
734 
 
735 
(define_insn "cgen_intrinsic_cpmulslla1_w_P1"
736 
  [(set (reg:SI 87)
737 
        (unspec_volatile:SI [
738 
          (match_operand:DI 0 "general_operand" "x")
739 
          (match_operand:DI 1 "general_operand" "x")
740 
        ] 2278))
741 
   (set (reg:SI 107)
742 
        (unspec_volatile:SI [
743 
          (match_dup 0)
744 
          (match_dup 1)
745 
        ] 2280))
746 
   (set (reg:SI 106)
747 
        (unspec_volatile:SI [
748 
          (match_dup 0)
749 
          (match_dup 1)
750 
        ] 2282))
751 
   (set (reg:SI 105)
752 
        (unspec_volatile:SI [
753 
          (match_dup 0)
754 
          (match_dup 1)
755 
        ] 2284))
756 
   (set (reg:SI 104)
757 
        (unspec_volatile:SI [
758 
          (match_dup 0)
759 
          (match_dup 1)
760 
        ] 2286))]
761 
  "CGEN_ENABLE_INSN_P (17)"
762 
  "cpmulslla1.w\\t%0,%1"
763 
  [(set_attr "may_trap" "no")
764 
   (set_attr "latency" "0")
765 
   (set_attr "length" "4")
766 
   (set_attr "slot" "cop")
767 
   (set_attr "slots" "p1")
768 
   (set_attr "stall" "none")])
769 
 
770 
 
771 
(define_insn "cgen_intrinsic_cpmulslua1_w_C3"
772 
  [(set (reg:SI 87)
773 
        (unspec_volatile:SI [
774 
          (match_operand:DI 0 "general_operand" "x")
775 
          (match_operand:DI 1 "general_operand" "x")
776 
        ] 2288))
777 
   (set (reg:SI 111)
778 
        (unspec_volatile:SI [
779 
          (match_dup 0)
780 
          (match_dup 1)
781 
        ] 2290))
782 
   (set (reg:SI 110)
783 
        (unspec_volatile:SI [
784 
          (match_dup 0)
785 
          (match_dup 1)
786 
        ] 2292))
787 
   (set (reg:SI 109)
788 
        (unspec_volatile:SI [
789 
          (match_dup 0)
790 
          (match_dup 1)
791 
        ] 2294))
792 
   (set (reg:SI 108)
793 
        (unspec_volatile:SI [
794 
          (match_dup 0)
795 
          (match_dup 1)
796 
        ] 2296))]
797 
  "CGEN_ENABLE_INSN_P (18)"
798 
  "cpmulslua1.w\\t%0,%1"
799 
  [(set_attr "may_trap" "no")
800 
   (set_attr "latency" "0")
801 
   (set_attr "length" "4")
802 
   (set_attr "slot" "cop")
803 
   (set_attr "slots" "c3")
804 
   (set_attr "stall" "none")])
805 
 
806 
 
807 
(define_insn "cgen_intrinsic_cpmulslua1_w_P1"
808 
  [(set (reg:SI 87)
809 
        (unspec_volatile:SI [
810 
          (match_operand:DI 0 "general_operand" "x")
811 
          (match_operand:DI 1 "general_operand" "x")
812 
        ] 2288))
813 
   (set (reg:SI 111)
814 
        (unspec_volatile:SI [
815 
          (match_dup 0)
816 
          (match_dup 1)
817 
        ] 2290))
818 
   (set (reg:SI 110)
819 
        (unspec_volatile:SI [
820 
          (match_dup 0)
821 
          (match_dup 1)
822 
        ] 2292))
823 
   (set (reg:SI 109)
824 
        (unspec_volatile:SI [
825 
          (match_dup 0)
826 
          (match_dup 1)
827 
        ] 2294))
828 
   (set (reg:SI 108)
829 
        (unspec_volatile:SI [
830 
          (match_dup 0)
831 
          (match_dup 1)
832 
        ] 2296))]
833 
  "CGEN_ENABLE_INSN_P (19)"
834 
  "cpmulslua1.w\\t%0,%1"
835 
  [(set_attr "may_trap" "no")
836 
   (set_attr "latency" "0")
837 
   (set_attr "length" "4")
838 
   (set_attr "slot" "cop")
839 
   (set_attr "slots" "p1")
840 
   (set_attr "stall" "none")])
841 
 
842 
 
843 
(define_insn "cgen_intrinsic_cpmulslla1_h_C3"
844 
  [(set (reg:SI 87)
845 
        (unspec_volatile:SI [
846 
          (match_operand:DI 0 "general_operand" "x")
847 
          (match_operand:DI 1 "general_operand" "x")
848 
        ] 2298))
849 
   (set (reg:SI 107)
850 
        (unspec_volatile:SI [
851 
          (match_dup 0)
852 
          (match_dup 1)
853 
        ] 2300))
854 
   (set (reg:SI 106)
855 
        (unspec_volatile:SI [
856 
          (match_dup 0)
857 
          (match_dup 1)
858 
        ] 2302))
859 
   (set (reg:SI 105)
860 
        (unspec_volatile:SI [
861 
          (match_dup 0)
862 
          (match_dup 1)
863 
        ] 2304))
864 
   (set (reg:SI 104)
865 
        (unspec_volatile:SI [
866 
          (match_dup 0)
867 
          (match_dup 1)
868 
        ] 2306))]
869 
  "CGEN_ENABLE_INSN_P (20)"
870 
  "cpmulslla1.h\\t%0,%1"
871 
  [(set_attr "may_trap" "no")
872 
   (set_attr "latency" "0")
873 
   (set_attr "length" "4")
874 
   (set_attr "slot" "cop")
875 
   (set_attr "slots" "c3")
876 
   (set_attr "stall" "none")])
877 
 
878 
 
879 
(define_insn "cgen_intrinsic_cpmulslla1_h_P1"
880 
  [(set (reg:SI 87)
881 
        (unspec_volatile:SI [
882 
          (match_operand:DI 0 "general_operand" "x")
883 
          (match_operand:DI 1 "general_operand" "x")
884 
        ] 2298))
885 
   (set (reg:SI 107)
886 
        (unspec_volatile:SI [
887 
          (match_dup 0)
888 
          (match_dup 1)
889 
        ] 2300))
890 
   (set (reg:SI 106)
891 
        (unspec_volatile:SI [
892 
          (match_dup 0)
893 
          (match_dup 1)
894 
        ] 2302))
895 
   (set (reg:SI 105)
896 
        (unspec_volatile:SI [
897 
          (match_dup 0)
898 
          (match_dup 1)
899 
        ] 2304))
900 
   (set (reg:SI 104)
901 
        (unspec_volatile:SI [
902 
          (match_dup 0)
903 
          (match_dup 1)
904 
        ] 2306))]
905 
  "CGEN_ENABLE_INSN_P (21)"
906 
  "cpmulslla1.h\\t%0,%1"
907 
  [(set_attr "may_trap" "no")
908 
   (set_attr "latency" "0")
909 
   (set_attr "length" "4")
910 
   (set_attr "slot" "cop")
911 
   (set_attr "slots" "p1")
912 
   (set_attr "stall" "none")])
913 
 
914 
 
915 
(define_insn "cgen_intrinsic_cpmulslua1_h_C3"
916 
  [(set (reg:SI 87)
917 
        (unspec_volatile:SI [
918 
          (match_operand:DI 0 "general_operand" "x")
919 
          (match_operand:DI 1 "general_operand" "x")
920 
        ] 2308))
921 
   (set (reg:SI 111)
922 
        (unspec_volatile:SI [
923 
          (match_dup 0)
924 
          (match_dup 1)
925 
        ] 2310))
926 
   (set (reg:SI 110)
927 
        (unspec_volatile:SI [
928 
          (match_dup 0)
929 
          (match_dup 1)
930 
        ] 2312))
931 
   (set (reg:SI 109)
932 
        (unspec_volatile:SI [
933 
          (match_dup 0)
934 
          (match_dup 1)
935 
        ] 2314))
936 
   (set (reg:SI 108)
937 
        (unspec_volatile:SI [
938 
          (match_dup 0)
939 
          (match_dup 1)
940 
        ] 2316))]
941 
  "CGEN_ENABLE_INSN_P (22)"
942 
  "cpmulslua1.h\\t%0,%1"
943 
  [(set_attr "may_trap" "no")
944 
   (set_attr "latency" "0")
945 
   (set_attr "length" "4")
946 
   (set_attr "slot" "cop")
947 
   (set_attr "slots" "c3")
948 
   (set_attr "stall" "none")])
949 
 
950 
 
951 
(define_insn "cgen_intrinsic_cpmulslua1_h_P1"
952 
  [(set (reg:SI 87)
953 
        (unspec_volatile:SI [
954 
          (match_operand:DI 0 "general_operand" "x")
955 
          (match_operand:DI 1 "general_operand" "x")
956 
        ] 2308))
957 
   (set (reg:SI 111)
958 
        (unspec_volatile:SI [
959 
          (match_dup 0)
960 
          (match_dup 1)
961 
        ] 2310))
962 
   (set (reg:SI 110)
963 
        (unspec_volatile:SI [
964 
          (match_dup 0)
965 
          (match_dup 1)
966 
        ] 2312))
967 
   (set (reg:SI 109)
968 
        (unspec_volatile:SI [
969 
          (match_dup 0)
970 
          (match_dup 1)
971 
        ] 2314))
972 
   (set (reg:SI 108)
973 
        (unspec_volatile:SI [
974 
          (match_dup 0)
975 
          (match_dup 1)
976 
        ] 2316))]
977 
  "CGEN_ENABLE_INSN_P (23)"
978 
  "cpmulslua1.h\\t%0,%1"
979 
  [(set_attr "may_trap" "no")
980 
   (set_attr "latency" "0")
981 
   (set_attr "length" "4")
982 
   (set_attr "slot" "cop")
983 
   (set_attr "slots" "p1")
984 
   (set_attr "stall" "none")])
985 
 
986 
 
987 
(define_insn "cgen_intrinsic_cpsmsbla1_w_C3"
988 
  [(set (reg:SI 87)
989 
        (unspec_volatile:SI [
990 
          (match_operand:DI 0 "general_operand" "x")
991 
          (match_operand:DI 1 "general_operand" "x")
992 
        ] 2318))
993 
   (set (reg:SI 107)
994 
        (unspec_volatile:SI [
995 
          (match_dup 0)
996 
          (match_dup 1)
997 
        ] 2320))
998 
   (set (reg:SI 106)
999 
        (unspec_volatile:SI [
1000 
          (match_dup 0)
1001 
          (match_dup 1)
1002 
        ] 2322))
1003 
   (set (reg:SI 105)
1004 
        (unspec_volatile:SI [
1005 
          (match_dup 0)
1006 
          (match_dup 1)
1007 
        ] 2324))
1008 
   (set (reg:SI 104)
1009 
        (unspec_volatile:SI [
1010 
          (match_dup 0)
1011 
          (match_dup 1)
1012 
        ] 2326))]
1013 
  "CGEN_ENABLE_INSN_P (24)"
1014 
  "cpsmsbla1.w\\t%0,%1"
1015 
  [(set_attr "may_trap" "no")
1016 
   (set_attr "latency" "0")
1017 
   (set_attr "length" "4")
1018 
   (set_attr "slot" "cop")
1019 
   (set_attr "slots" "c3")
1020 
   (set_attr "stall" "none")])
1021 
 
1022 
 
1023 
(define_insn "cgen_intrinsic_cpsmsbla1_w_P1"
1024 
  [(set (reg:SI 87)
1025 
        (unspec_volatile:SI [
1026 
          (match_operand:DI 0 "general_operand" "x")
1027 
          (match_operand:DI 1 "general_operand" "x")
1028 
        ] 2318))
1029 
   (set (reg:SI 107)
1030 
        (unspec_volatile:SI [
1031 
          (match_dup 0)
1032 
          (match_dup 1)
1033 
        ] 2320))
1034 
   (set (reg:SI 106)
1035 
        (unspec_volatile:SI [
1036 
          (match_dup 0)
1037 
          (match_dup 1)
1038 
        ] 2322))
1039 
   (set (reg:SI 105)
1040 
        (unspec_volatile:SI [
1041 
          (match_dup 0)
1042 
          (match_dup 1)
1043 
        ] 2324))
1044 
   (set (reg:SI 104)
1045 
        (unspec_volatile:SI [
1046 
          (match_dup 0)
1047 
          (match_dup 1)
1048 
        ] 2326))]
1049 
  "CGEN_ENABLE_INSN_P (25)"
1050 
  "cpsmsbla1.w\\t%0,%1"
1051 
  [(set_attr "may_trap" "no")
1052 
   (set_attr "latency" "0")
1053 
   (set_attr "length" "4")
1054 
   (set_attr "slot" "cop")
1055 
   (set_attr "slots" "p1")
1056 
   (set_attr "stall" "none")])
1057 
 
1058 
 
1059 
(define_insn "cgen_intrinsic_cpsmsbua1_w_C3"
1060 
  [(set (reg:SI 87)
1061 
        (unspec_volatile:SI [
1062 
          (match_operand:DI 0 "general_operand" "x")
1063 
          (match_operand:DI 1 "general_operand" "x")
1064 
        ] 2328))
1065 
   (set (reg:SI 111)
1066 
        (unspec_volatile:SI [
1067 
          (match_dup 0)
1068 
          (match_dup 1)
1069 
        ] 2330))
1070 
   (set (reg:SI 110)
1071 
        (unspec_volatile:SI [
1072 
          (match_dup 0)
1073 
          (match_dup 1)
1074 
        ] 2332))
1075 
   (set (reg:SI 109)
1076 
        (unspec_volatile:SI [
1077 
          (match_dup 0)
1078 
          (match_dup 1)
1079 
        ] 2334))
1080 
   (set (reg:SI 108)
1081 
        (unspec_volatile:SI [
1082 
          (match_dup 0)
1083 
          (match_dup 1)
1084 
        ] 2336))]
1085 
  "CGEN_ENABLE_INSN_P (26)"
1086 
  "cpsmsbua1.w\\t%0,%1"
1087 
  [(set_attr "may_trap" "no")
1088 
   (set_attr "latency" "0")
1089 
   (set_attr "length" "4")
1090 
   (set_attr "slot" "cop")
1091 
   (set_attr "slots" "c3")
1092 
   (set_attr "stall" "none")])
1093 
 
1094 
 
1095 
(define_insn "cgen_intrinsic_cpsmsbua1_w_P1"
1096 
  [(set (reg:SI 87)
1097 
        (unspec_volatile:SI [
1098 
          (match_operand:DI 0 "general_operand" "x")
1099 
          (match_operand:DI 1 "general_operand" "x")
1100 
        ] 2328))
1101 
   (set (reg:SI 111)
1102 
        (unspec_volatile:SI [
1103 
          (match_dup 0)
1104 
          (match_dup 1)
1105 
        ] 2330))
1106 
   (set (reg:SI 110)
1107 
        (unspec_volatile:SI [
1108 
          (match_dup 0)
1109 
          (match_dup 1)
1110 
        ] 2332))
1111 
   (set (reg:SI 109)
1112 
        (unspec_volatile:SI [
1113 
          (match_dup 0)
1114 
          (match_dup 1)
1115 
        ] 2334))
1116 
   (set (reg:SI 108)
1117 
        (unspec_volatile:SI [
1118 
          (match_dup 0)
1119 
          (match_dup 1)
1120 
        ] 2336))]
1121 
  "CGEN_ENABLE_INSN_P (27)"
1122 
  "cpsmsbua1.w\\t%0,%1"
1123 
  [(set_attr "may_trap" "no")
1124 
   (set_attr "latency" "0")
1125 
   (set_attr "length" "4")
1126 
   (set_attr "slot" "cop")
1127 
   (set_attr "slots" "p1")
1128 
   (set_attr "stall" "none")])
1129 
 
1130 
 
1131 
(define_insn "cgen_intrinsic_cpsmsbla1_h_C3"
1132 
  [(set (reg:SI 87)
1133 
        (unspec_volatile:SI [
1134 
          (match_operand:DI 0 "general_operand" "x")
1135 
          (match_operand:DI 1 "general_operand" "x")
1136 
        ] 2338))
1137 
   (set (reg:SI 107)
1138 
        (unspec_volatile:SI [
1139 
          (match_dup 0)
1140 
          (match_dup 1)
1141 
        ] 2340))
1142 
   (set (reg:SI 106)
1143 
        (unspec_volatile:SI [
1144 
          (match_dup 0)
1145 
          (match_dup 1)
1146 
        ] 2342))
1147 
   (set (reg:SI 105)
1148 
        (unspec_volatile:SI [
1149 
          (match_dup 0)
1150 
          (match_dup 1)
1151 
        ] 2344))
1152 
   (set (reg:SI 104)
1153 
        (unspec_volatile:SI [
1154 
          (match_dup 0)
1155 
          (match_dup 1)
1156 
        ] 2346))]
1157 
  "CGEN_ENABLE_INSN_P (28)"
1158 
  "cpsmsbla1.h\\t%0,%1"
1159 
  [(set_attr "may_trap" "no")
1160 
   (set_attr "latency" "0")
1161 
   (set_attr "length" "4")
1162 
   (set_attr "slot" "cop")
1163 
   (set_attr "slots" "c3")
1164 
   (set_attr "stall" "none")])
1165 
 
1166 
 
1167 
(define_insn "cgen_intrinsic_cpsmsbla1_h_P1"
1168 
  [(set (reg:SI 87)
1169 
        (unspec_volatile:SI [
1170 
          (match_operand:DI 0 "general_operand" "x")
1171 
          (match_operand:DI 1 "general_operand" "x")
1172 
        ] 2338))
1173 
   (set (reg:SI 107)
1174 
        (unspec_volatile:SI [
1175 
          (match_dup 0)
1176 
          (match_dup 1)
1177 
        ] 2340))
1178 
   (set (reg:SI 106)
1179 
        (unspec_volatile:SI [
1180 
          (match_dup 0)
1181 
          (match_dup 1)
1182 
        ] 2342))
1183 
   (set (reg:SI 105)
1184 
        (unspec_volatile:SI [
1185 
          (match_dup 0)
1186 
          (match_dup 1)
1187 
        ] 2344))
1188 
   (set (reg:SI 104)
1189 
        (unspec_volatile:SI [
1190 
          (match_dup 0)
1191 
          (match_dup 1)
1192 
        ] 2346))]
1193 
  "CGEN_ENABLE_INSN_P (29)"
1194 
  "cpsmsbla1.h\\t%0,%1"
1195 
  [(set_attr "may_trap" "no")
1196 
   (set_attr "latency" "0")
1197 
   (set_attr "length" "4")
1198 
   (set_attr "slot" "cop")
1199 
   (set_attr "slots" "p1")
1200 
   (set_attr "stall" "none")])
1201 
 
1202 
 
1203 
(define_insn "cgen_intrinsic_cpsmsbua1_h_C3"
1204 
  [(set (reg:SI 87)
1205 
        (unspec_volatile:SI [
1206 
          (match_operand:DI 0 "general_operand" "x")
1207 
          (match_operand:DI 1 "general_operand" "x")
1208 
        ] 2348))
1209 
   (set (reg:SI 111)
1210 
        (unspec_volatile:SI [
1211 
          (match_dup 0)
1212 
          (match_dup 1)
1213 
        ] 2350))
1214 
   (set (reg:SI 110)
1215 
        (unspec_volatile:SI [
1216 
          (match_dup 0)
1217 
          (match_dup 1)
1218 
        ] 2352))
1219 
   (set (reg:SI 109)
1220 
        (unspec_volatile:SI [
1221 
          (match_dup 0)
1222 
          (match_dup 1)
1223 
        ] 2354))
1224 
   (set (reg:SI 108)
1225 
        (unspec_volatile:SI [
1226 
          (match_dup 0)
1227 
          (match_dup 1)
1228 
        ] 2356))]
1229 
  "CGEN_ENABLE_INSN_P (30)"
1230 
  "cpsmsbua1.h\\t%0,%1"
1231 
  [(set_attr "may_trap" "no")
1232 
   (set_attr "latency" "0")
1233 
   (set_attr "length" "4")
1234 
   (set_attr "slot" "cop")
1235 
   (set_attr "slots" "c3")
1236 
   (set_attr "stall" "none")])
1237 
 
1238 
 
1239 
(define_insn "cgen_intrinsic_cpsmsbua1_h_P1"
1240 
  [(set (reg:SI 87)
1241 
        (unspec_volatile:SI [
1242 
          (match_operand:DI 0 "general_operand" "x")
1243 
          (match_operand:DI 1 "general_operand" "x")
1244 
        ] 2348))
1245 
   (set (reg:SI 111)
1246 
        (unspec_volatile:SI [
1247 
          (match_dup 0)
1248 
          (match_dup 1)
1249 
        ] 2350))
1250 
   (set (reg:SI 110)
1251 
        (unspec_volatile:SI [
1252 
          (match_dup 0)
1253 
          (match_dup 1)
1254 
        ] 2352))
1255 
   (set (reg:SI 109)
1256 
        (unspec_volatile:SI [
1257 
          (match_dup 0)
1258 
          (match_dup 1)
1259 
        ] 2354))
1260 
   (set (reg:SI 108)
1261 
        (unspec_volatile:SI [
1262 
          (match_dup 0)
1263 
          (match_dup 1)
1264 
        ] 2356))]
1265 
  "CGEN_ENABLE_INSN_P (31)"
1266 
  "cpsmsbua1.h\\t%0,%1"
1267 
  [(set_attr "may_trap" "no")
1268 
   (set_attr "latency" "0")
1269 
   (set_attr "length" "4")
1270 
   (set_attr "slot" "cop")
1271 
   (set_attr "slots" "p1")
1272 
   (set_attr "stall" "none")])
1273 
 
1274 
 
1275 
(define_insn "cgen_intrinsic_cpsmadla1_w_C3"
1276 
  [(set (reg:SI 87)
1277 
        (unspec_volatile:SI [
1278 
          (match_operand:DI 0 "general_operand" "x")
1279 
          (match_operand:DI 1 "general_operand" "x")
1280 
        ] 2358))
1281 
   (set (reg:SI 107)
1282 
        (unspec_volatile:SI [
1283 
          (match_dup 0)
1284 
          (match_dup 1)
1285 
        ] 2360))
1286 
   (set (reg:SI 106)
1287 
        (unspec_volatile:SI [
1288 
          (match_dup 0)
1289 
          (match_dup 1)
1290 
        ] 2362))
1291 
   (set (reg:SI 105)
1292 
        (unspec_volatile:SI [
1293 
          (match_dup 0)
1294 
          (match_dup 1)
1295 
        ] 2364))
1296 
   (set (reg:SI 104)
1297 
        (unspec_volatile:SI [
1298 
          (match_dup 0)
1299 
          (match_dup 1)
1300 
        ] 2366))]
1301 
  "CGEN_ENABLE_INSN_P (32)"
1302 
  "cpsmadla1.w\\t%0,%1"
1303 
  [(set_attr "may_trap" "no")
1304 
   (set_attr "latency" "0")
1305 
   (set_attr "length" "4")
1306 
   (set_attr "slot" "cop")
1307 
   (set_attr "slots" "c3")
1308 
   (set_attr "stall" "none")])
1309 
 
1310 
 
1311 
(define_insn "cgen_intrinsic_cpsmadla1_w_P1"
1312 
  [(set (reg:SI 87)
1313 
        (unspec_volatile:SI [
1314 
          (match_operand:DI 0 "general_operand" "x")
1315 
          (match_operand:DI 1 "general_operand" "x")
1316 
        ] 2358))
1317 
   (set (reg:SI 107)
1318 
        (unspec_volatile:SI [
1319 
          (match_dup 0)
1320 
          (match_dup 1)
1321 
        ] 2360))
1322 
   (set (reg:SI 106)
1323 
        (unspec_volatile:SI [
1324 
          (match_dup 0)
1325 
          (match_dup 1)
1326 
        ] 2362))
1327 
   (set (reg:SI 105)
1328 
        (unspec_volatile:SI [
1329 
          (match_dup 0)
1330 
          (match_dup 1)
1331 
        ] 2364))
1332 
   (set (reg:SI 104)
1333 
        (unspec_volatile:SI [
1334 
          (match_dup 0)
1335 
          (match_dup 1)
1336 
        ] 2366))]
1337 
  "CGEN_ENABLE_INSN_P (33)"
1338 
  "cpsmadla1.w\\t%0,%1"
1339 
  [(set_attr "may_trap" "no")
1340 
   (set_attr "latency" "0")
1341 
   (set_attr "length" "4")
1342 
   (set_attr "slot" "cop")
1343 
   (set_attr "slots" "p1")
1344 
   (set_attr "stall" "none")])
1345 
 
1346 
 
1347 
(define_insn "cgen_intrinsic_cpsmadua1_w_C3"
1348 
  [(set (reg:SI 87)
1349 
        (unspec_volatile:SI [
1350 
          (match_operand:DI 0 "general_operand" "x")
1351 
          (match_operand:DI 1 "general_operand" "x")
1352 
        ] 2368))
1353 
   (set (reg:SI 111)
1354 
        (unspec_volatile:SI [
1355 
          (match_dup 0)
1356 
          (match_dup 1)
1357 
        ] 2370))
1358 
   (set (reg:SI 110)
1359 
        (unspec_volatile:SI [
1360 
          (match_dup 0)
1361 
          (match_dup 1)
1362 
        ] 2372))
1363 
   (set (reg:SI 109)
1364 
        (unspec_volatile:SI [
1365 
          (match_dup 0)
1366 
          (match_dup 1)
1367 
        ] 2374))
1368 
   (set (reg:SI 108)
1369 
        (unspec_volatile:SI [
1370 
          (match_dup 0)
1371 
          (match_dup 1)
1372 
        ] 2376))]
1373 
  "CGEN_ENABLE_INSN_P (34)"
1374 
  "cpsmadua1.w\\t%0,%1"
1375 
  [(set_attr "may_trap" "no")
1376 
   (set_attr "latency" "0")
1377 
   (set_attr "length" "4")
1378 
   (set_attr "slot" "cop")
1379 
   (set_attr "slots" "c3")
1380 
   (set_attr "stall" "none")])
1381 
 
1382 
 
1383 
(define_insn "cgen_intrinsic_cpsmadua1_w_P1"
1384 
  [(set (reg:SI 87)
1385 
        (unspec_volatile:SI [
1386 
          (match_operand:DI 0 "general_operand" "x")
1387 
          (match_operand:DI 1 "general_operand" "x")
1388 
        ] 2368))
1389 
   (set (reg:SI 111)
1390 
        (unspec_volatile:SI [
1391 
          (match_dup 0)
1392 
          (match_dup 1)
1393 
        ] 2370))
1394 
   (set (reg:SI 110)
1395 
        (unspec_volatile:SI [
1396 
          (match_dup 0)
1397 
          (match_dup 1)
1398 
        ] 2372))
1399 
   (set (reg:SI 109)
1400 
        (unspec_volatile:SI [
1401 
          (match_dup 0)
1402 
          (match_dup 1)
1403 
        ] 2374))
1404 
   (set (reg:SI 108)
1405 
        (unspec_volatile:SI [
1406 
          (match_dup 0)
1407 
          (match_dup 1)
1408 
        ] 2376))]
1409 
  "CGEN_ENABLE_INSN_P (35)"
1410 
  "cpsmadua1.w\\t%0,%1"
1411 
  [(set_attr "may_trap" "no")
1412 
   (set_attr "latency" "0")
1413 
   (set_attr "length" "4")
1414 
   (set_attr "slot" "cop")
1415 
   (set_attr "slots" "p1")
1416 
   (set_attr "stall" "none")])
1417 
 
1418 
 
1419 
(define_insn "cgen_intrinsic_cpsmadla1_h_C3"
1420 
  [(set (reg:SI 87)
1421 
        (unspec_volatile:SI [
1422 
          (match_operand:DI 0 "general_operand" "x")
1423 
          (match_operand:DI 1 "general_operand" "x")
1424 
        ] 2378))
1425 
   (set (reg:SI 107)
1426 
        (unspec_volatile:SI [
1427 
          (match_dup 0)
1428 
          (match_dup 1)
1429 
        ] 2380))
1430 
   (set (reg:SI 106)
1431 
        (unspec_volatile:SI [
1432 
          (match_dup 0)
1433 
          (match_dup 1)
1434 
        ] 2382))
1435 
   (set (reg:SI 105)
1436 
        (unspec_volatile:SI [
1437 
          (match_dup 0)
1438 
          (match_dup 1)
1439 
        ] 2384))
1440 
   (set (reg:SI 104)
1441 
        (unspec_volatile:SI [
1442 
          (match_dup 0)
1443 
          (match_dup 1)
1444 
        ] 2386))]
1445 
  "CGEN_ENABLE_INSN_P (36)"
1446 
  "cpsmadla1.h\\t%0,%1"
1447 
  [(set_attr "may_trap" "no")
1448 
   (set_attr "latency" "0")
1449 
   (set_attr "length" "4")
1450 
   (set_attr "slot" "cop")
1451 
   (set_attr "slots" "c3")
1452 
   (set_attr "stall" "none")])
1453 
 
1454 
 
1455 
(define_insn "cgen_intrinsic_cpsmadla1_h_P1"
1456 
  [(set (reg:SI 87)
1457 
        (unspec_volatile:SI [
1458 
          (match_operand:DI 0 "general_operand" "x")
1459 
          (match_operand:DI 1 "general_operand" "x")
1460 
        ] 2378))
1461 
   (set (reg:SI 107)
1462 
        (unspec_volatile:SI [
1463 
          (match_dup 0)
1464 
          (match_dup 1)
1465 
        ] 2380))
1466 
   (set (reg:SI 106)
1467 
        (unspec_volatile:SI [
1468 
          (match_dup 0)
1469 
          (match_dup 1)
1470 
        ] 2382))
1471 
   (set (reg:SI 105)
1472 
        (unspec_volatile:SI [
1473 
          (match_dup 0)
1474 
          (match_dup 1)
1475 
        ] 2384))
1476 
   (set (reg:SI 104)
1477 
        (unspec_volatile:SI [
1478 
          (match_dup 0)
1479 
          (match_dup 1)
1480 
        ] 2386))]
1481 
  "CGEN_ENABLE_INSN_P (37)"
1482 
  "cpsmadla1.h\\t%0,%1"
1483 
  [(set_attr "may_trap" "no")
1484 
   (set_attr "latency" "0")
1485 
   (set_attr "length" "4")
1486 
   (set_attr "slot" "cop")
1487 
   (set_attr "slots" "p1")
1488 
   (set_attr "stall" "none")])
1489 
 
1490 
 
1491 
(define_insn "cgen_intrinsic_cpsmadua1_h_C3"
1492 
  [(set (reg:SI 87)
1493 
        (unspec_volatile:SI [
1494 
          (match_operand:DI 0 "general_operand" "x")
1495 
          (match_operand:DI 1 "general_operand" "x")
1496 
        ] 2388))
1497 
   (set (reg:SI 111)
1498 
        (unspec_volatile:SI [
1499 
          (match_dup 0)
1500 
          (match_dup 1)
1501 
        ] 2390))
1502 
   (set (reg:SI 110)
1503 
        (unspec_volatile:SI [
1504 
          (match_dup 0)
1505 
          (match_dup 1)
1506 
        ] 2392))
1507 
   (set (reg:SI 109)
1508 
        (unspec_volatile:SI [
1509 
          (match_dup 0)
1510 
          (match_dup 1)
1511 
        ] 2394))
1512 
   (set (reg:SI 108)
1513 
        (unspec_volatile:SI [
1514 
          (match_dup 0)
1515 
          (match_dup 1)
1516 
        ] 2396))]
1517 
  "CGEN_ENABLE_INSN_P (38)"
1518 
  "cpsmadua1.h\\t%0,%1"
1519 
  [(set_attr "may_trap" "no")
1520 
   (set_attr "latency" "0")
1521 
   (set_attr "length" "4")
1522 
   (set_attr "slot" "cop")
1523 
   (set_attr "slots" "c3")
1524 
   (set_attr "stall" "none")])
1525 
 
1526 
 
1527 
(define_insn "cgen_intrinsic_cpsmadua1_h_P1"
1528 
  [(set (reg:SI 87)
1529 
        (unspec_volatile:SI [
1530 
          (match_operand:DI 0 "general_operand" "x")
1531 
          (match_operand:DI 1 "general_operand" "x")
1532 
        ] 2388))
1533 
   (set (reg:SI 111)
1534 
        (unspec_volatile:SI [
1535 
          (match_dup 0)
1536 
          (match_dup 1)
1537 
        ] 2390))
1538 
   (set (reg:SI 110)
1539 
        (unspec_volatile:SI [
1540 
          (match_dup 0)
1541 
          (match_dup 1)
1542 
        ] 2392))
1543 
   (set (reg:SI 109)
1544 
        (unspec_volatile:SI [
1545 
          (match_dup 0)
1546 
          (match_dup 1)
1547 
        ] 2394))
1548 
   (set (reg:SI 108)
1549 
        (unspec_volatile:SI [
1550 
          (match_dup 0)
1551 
          (match_dup 1)
1552 
        ] 2396))]
1553 
  "CGEN_ENABLE_INSN_P (39)"
1554 
  "cpsmadua1.h\\t%0,%1"
1555 
  [(set_attr "may_trap" "no")
1556 
   (set_attr "latency" "0")
1557 
   (set_attr "length" "4")
1558 
   (set_attr "slot" "cop")
1559 
   (set_attr "slots" "p1")
1560 
   (set_attr "stall" "none")])
1561 
 
1562 
 
1563 
(define_insn "cgen_intrinsic_cpmsbla1_w_C3"
1564 
  [(set (reg:SI 87)
1565 
        (unspec_volatile:SI [
1566 
          (match_operand:DI 0 "general_operand" "x")
1567 
          (match_operand:DI 1 "general_operand" "x")
1568 
        ] 2398))
1569 
   (set (reg:SI 107)
1570 
        (unspec_volatile:SI [
1571 
          (match_dup 0)
1572 
          (match_dup 1)
1573 
        ] 2400))
1574 
   (set (reg:SI 106)
1575 
        (unspec_volatile:SI [
1576 
          (match_dup 0)
1577 
          (match_dup 1)
1578 
        ] 2402))
1579 
   (set (reg:SI 105)
1580 
        (unspec_volatile:SI [
1581 
          (match_dup 0)
1582 
          (match_dup 1)
1583 
        ] 2404))
1584 
   (set (reg:SI 104)
1585 
        (unspec_volatile:SI [
1586 
          (match_dup 0)
1587 
          (match_dup 1)
1588 
        ] 2406))]
1589 
  "CGEN_ENABLE_INSN_P (40)"
1590 
  "cpmsbla1.w\\t%0,%1"
1591 
  [(set_attr "may_trap" "no")
1592 
   (set_attr "latency" "0")
1593 
   (set_attr "length" "4")
1594 
   (set_attr "slot" "cop")
1595 
   (set_attr "slots" "c3")
1596 
   (set_attr "stall" "none")])
1597 
 
1598 
 
1599 
(define_insn "cgen_intrinsic_cpmsbla1_w_P1"
1600 
  [(set (reg:SI 87)
1601 
        (unspec_volatile:SI [
1602 
          (match_operand:DI 0 "general_operand" "x")
1603 
          (match_operand:DI 1 "general_operand" "x")
1604 
        ] 2398))
1605 
   (set (reg:SI 107)
1606 
        (unspec_volatile:SI [
1607 
          (match_dup 0)
1608 
          (match_dup 1)
1609 
        ] 2400))
1610 
   (set (reg:SI 106)
1611 
        (unspec_volatile:SI [
1612 
          (match_dup 0)
1613 
          (match_dup 1)
1614 
        ] 2402))
1615 
   (set (reg:SI 105)
1616 
        (unspec_volatile:SI [
1617 
          (match_dup 0)
1618 
          (match_dup 1)
1619 
        ] 2404))
1620 
   (set (reg:SI 104)
1621 
        (unspec_volatile:SI [
1622 
          (match_dup 0)
1623 
          (match_dup 1)
1624 
        ] 2406))]
1625 
  "CGEN_ENABLE_INSN_P (41)"
1626 
  "cpmsbla1.w\\t%0,%1"
1627 
  [(set_attr "may_trap" "no")
1628 
   (set_attr "latency" "0")
1629 
   (set_attr "length" "4")
1630 
   (set_attr "slot" "cop")
1631 
   (set_attr "slots" "p1")
1632 
   (set_attr "stall" "none")])
1633 
 
1634 
 
1635 
(define_insn "cgen_intrinsic_cpmsbua1_w_C3"
1636 
  [(set (reg:SI 87)
1637 
        (unspec_volatile:SI [
1638 
          (match_operand:DI 0 "general_operand" "x")
1639 
          (match_operand:DI 1 "general_operand" "x")
1640 
        ] 2408))
1641 
   (set (reg:SI 111)
1642 
        (unspec_volatile:SI [
1643 
          (match_dup 0)
1644 
          (match_dup 1)
1645 
        ] 2410))
1646 
   (set (reg:SI 110)
1647 
        (unspec_volatile:SI [
1648 
          (match_dup 0)
1649 
          (match_dup 1)
1650 
        ] 2412))
1651 
   (set (reg:SI 109)
1652 
        (unspec_volatile:SI [
1653 
          (match_dup 0)
1654 
          (match_dup 1)
1655 
        ] 2414))
1656 
   (set (reg:SI 108)
1657 
        (unspec_volatile:SI [
1658 
          (match_dup 0)
1659 
          (match_dup 1)
1660 
        ] 2416))]
1661 
  "CGEN_ENABLE_INSN_P (42)"
1662 
  "cpmsbua1.w\\t%0,%1"
1663 
  [(set_attr "may_trap" "no")
1664 
   (set_attr "latency" "0")
1665 
   (set_attr "length" "4")
1666 
   (set_attr "slot" "cop")
1667 
   (set_attr "slots" "c3")
1668 
   (set_attr "stall" "none")])
1669 
 
1670 
 
1671 
(define_insn "cgen_intrinsic_cpmsbua1_w_P1"
1672 
  [(set (reg:SI 87)
1673 
        (unspec_volatile:SI [
1674 
          (match_operand:DI 0 "general_operand" "x")
1675 
          (match_operand:DI 1 "general_operand" "x")
1676 
        ] 2408))
1677 
   (set (reg:SI 111)
1678 
        (unspec_volatile:SI [
1679 
          (match_dup 0)
1680 
          (match_dup 1)
1681 
        ] 2410))
1682 
   (set (reg:SI 110)
1683 
        (unspec_volatile:SI [
1684 
          (match_dup 0)
1685 
          (match_dup 1)
1686 
        ] 2412))
1687 
   (set (reg:SI 109)
1688 
        (unspec_volatile:SI [
1689 
          (match_dup 0)
1690 
          (match_dup 1)
1691 
        ] 2414))
1692 
   (set (reg:SI 108)
1693 
        (unspec_volatile:SI [
1694 
          (match_dup 0)
1695 
          (match_dup 1)
1696 
        ] 2416))]
1697 
  "CGEN_ENABLE_INSN_P (43)"
1698 
  "cpmsbua1.w\\t%0,%1"
1699 
  [(set_attr "may_trap" "no")
1700 
   (set_attr "latency" "0")
1701 
   (set_attr "length" "4")
1702 
   (set_attr "slot" "cop")
1703 
   (set_attr "slots" "p1")
1704 
   (set_attr "stall" "none")])
1705 
 
1706 
 
1707 
(define_insn "cgen_intrinsic_cpmsbla1u_w_C3"
1708 
  [(set (reg:SI 87)
1709 
        (unspec_volatile:SI [
1710 
          (match_operand:DI 0 "general_operand" "x")
1711 
          (match_operand:DI 1 "general_operand" "x")
1712 
        ] 2418))
1713 
   (set (reg:SI 107)
1714 
        (unspec_volatile:SI [
1715 
          (match_dup 0)
1716 
          (match_dup 1)
1717 
        ] 2420))
1718 
   (set (reg:SI 106)
1719 
        (unspec_volatile:SI [
1720 
          (match_dup 0)
1721 
          (match_dup 1)
1722 
        ] 2422))
1723 
   (set (reg:SI 105)
1724 
        (unspec_volatile:SI [
1725 
          (match_dup 0)
1726 
          (match_dup 1)
1727 
        ] 2424))
1728 
   (set (reg:SI 104)
1729 
        (unspec_volatile:SI [
1730 
          (match_dup 0)
1731 
          (match_dup 1)
1732 
        ] 2426))]
1733 
  "CGEN_ENABLE_INSN_P (44)"
1734 
  "cpmsbla1u.w\\t%0,%1"
1735 
  [(set_attr "may_trap" "no")
1736 
   (set_attr "latency" "0")
1737 
   (set_attr "length" "4")
1738 
   (set_attr "slot" "cop")
1739 
   (set_attr "slots" "c3")
1740 
   (set_attr "stall" "none")])
1741 
 
1742 
 
1743 
(define_insn "cgen_intrinsic_cpmsbla1u_w_P1"
1744 
  [(set (reg:SI 87)
1745 
        (unspec_volatile:SI [
1746 
          (match_operand:DI 0 "general_operand" "x")
1747 
          (match_operand:DI 1 "general_operand" "x")
1748 
        ] 2418))
1749 
   (set (reg:SI 107)
1750 
        (unspec_volatile:SI [
1751 
          (match_dup 0)
1752 
          (match_dup 1)
1753 
        ] 2420))
1754 
   (set (reg:SI 106)
1755 
        (unspec_volatile:SI [
1756 
          (match_dup 0)
1757 
          (match_dup 1)
1758 
        ] 2422))
1759 
   (set (reg:SI 105)
1760 
        (unspec_volatile:SI [
1761 
          (match_dup 0)
1762 
          (match_dup 1)
1763 
        ] 2424))
1764 
   (set (reg:SI 104)
1765 
        (unspec_volatile:SI [
1766 
          (match_dup 0)
1767 
          (match_dup 1)
1768 
        ] 2426))]
1769 
  "CGEN_ENABLE_INSN_P (45)"
1770 
  "cpmsbla1u.w\\t%0,%1"
1771 
  [(set_attr "may_trap" "no")
1772 
   (set_attr "latency" "0")
1773 
   (set_attr "length" "4")
1774 
   (set_attr "slot" "cop")
1775 
   (set_attr "slots" "p1")
1776 
   (set_attr "stall" "none")])
1777 
 
1778 
 
1779 
(define_insn "cgen_intrinsic_cpmsbua1u_w_C3"
1780 
  [(set (reg:SI 87)
1781 
        (unspec_volatile:SI [
1782 
          (match_operand:DI 0 "general_operand" "x")
1783 
          (match_operand:DI 1 "general_operand" "x")
1784 
        ] 2428))
1785 
   (set (reg:SI 111)
1786 
        (unspec_volatile:SI [
1787 
          (match_dup 0)
1788 
          (match_dup 1)
1789 
        ] 2430))
1790 
   (set (reg:SI 110)
1791 
        (unspec_volatile:SI [
1792 
          (match_dup 0)
1793 
          (match_dup 1)
1794 
        ] 2432))
1795 
   (set (reg:SI 109)
1796 
        (unspec_volatile:SI [
1797 
          (match_dup 0)
1798 
          (match_dup 1)
1799 
        ] 2434))
1800 
   (set (reg:SI 108)
1801 
        (unspec_volatile:SI [
1802 
          (match_dup 0)
1803 
          (match_dup 1)
1804 
        ] 2436))]
1805 
  "CGEN_ENABLE_INSN_P (46)"
1806 
  "cpmsbua1u.w\\t%0,%1"
1807 
  [(set_attr "may_trap" "no")
1808 
   (set_attr "latency" "0")
1809 
   (set_attr "length" "4")
1810 
   (set_attr "slot" "cop")
1811 
   (set_attr "slots" "c3")
1812 
   (set_attr "stall" "none")])
1813 
 
1814 
 
1815 
(define_insn "cgen_intrinsic_cpmsbua1u_w_P1"
1816 
  [(set (reg:SI 87)
1817 
        (unspec_volatile:SI [
1818 
          (match_operand:DI 0 "general_operand" "x")
1819 
          (match_operand:DI 1 "general_operand" "x")
1820 
        ] 2428))
1821 
   (set (reg:SI 111)
1822 
        (unspec_volatile:SI [
1823 
          (match_dup 0)
1824 
          (match_dup 1)
1825 
        ] 2430))
1826 
   (set (reg:SI 110)
1827 
        (unspec_volatile:SI [
1828 
          (match_dup 0)
1829 
          (match_dup 1)
1830 
        ] 2432))
1831 
   (set (reg:SI 109)
1832 
        (unspec_volatile:SI [
1833 
          (match_dup 0)
1834 
          (match_dup 1)
1835 
        ] 2434))
1836 
   (set (reg:SI 108)
1837 
        (unspec_volatile:SI [
1838 
          (match_dup 0)
1839 
          (match_dup 1)
1840 
        ] 2436))]
1841 
  "CGEN_ENABLE_INSN_P (47)"
1842 
  "cpmsbua1u.w\\t%0,%1"
1843 
  [(set_attr "may_trap" "no")
1844 
   (set_attr "latency" "0")
1845 
   (set_attr "length" "4")
1846 
   (set_attr "slot" "cop")
1847 
   (set_attr "slots" "p1")
1848 
   (set_attr "stall" "none")])
1849 
 
1850 
 
1851 
(define_insn "cgen_intrinsic_cpmsbla1_h_C3"
1852 
  [(set (reg:SI 87)
1853 
        (unspec_volatile:SI [
1854 
          (match_operand:DI 0 "general_operand" "x")
1855 
          (match_operand:DI 1 "general_operand" "x")
1856 
        ] 2438))
1857 
   (set (reg:SI 107)
1858 
        (unspec_volatile:SI [
1859 
          (match_dup 0)
1860 
          (match_dup 1)
1861 
        ] 2440))
1862 
   (set (reg:SI 106)
1863 
        (unspec_volatile:SI [
1864 
          (match_dup 0)
1865 
          (match_dup 1)
1866 
        ] 2442))
1867 
   (set (reg:SI 105)
1868 
        (unspec_volatile:SI [
1869 
          (match_dup 0)
1870 
          (match_dup 1)
1871 
        ] 2444))
1872 
   (set (reg:SI 104)
1873 
        (unspec_volatile:SI [
1874 
          (match_dup 0)
1875 
          (match_dup 1)
1876 
        ] 2446))]
1877 
  "CGEN_ENABLE_INSN_P (48)"
1878 
  "cpmsbla1.h\\t%0,%1"
1879 
  [(set_attr "may_trap" "no")
1880 
   (set_attr "latency" "0")
1881 
   (set_attr "length" "4")
1882 
   (set_attr "slot" "cop")
1883 
   (set_attr "slots" "c3")
1884 
   (set_attr "stall" "none")])
1885 
 
1886 
 
1887 
(define_insn "cgen_intrinsic_cpmsbla1_h_P1"
1888 
  [(set (reg:SI 87)
1889 
        (unspec_volatile:SI [
1890 
          (match_operand:DI 0 "general_operand" "x")
1891 
          (match_operand:DI 1 "general_operand" "x")
1892 
        ] 2438))
1893 
   (set (reg:SI 107)
1894 
        (unspec_volatile:SI [
1895 
          (match_dup 0)
1896 
          (match_dup 1)
1897 
        ] 2440))
1898 
   (set (reg:SI 106)
1899 
        (unspec_volatile:SI [
1900 
          (match_dup 0)
1901 
          (match_dup 1)
1902 
        ] 2442))
1903 
   (set (reg:SI 105)
1904 
        (unspec_volatile:SI [
1905 
          (match_dup 0)
1906 
          (match_dup 1)
1907 
        ] 2444))
1908 
   (set (reg:SI 104)
1909 
        (unspec_volatile:SI [
1910 
          (match_dup 0)
1911 
          (match_dup 1)
1912 
        ] 2446))]
1913 
  "CGEN_ENABLE_INSN_P (49)"
1914 
  "cpmsbla1.h\\t%0,%1"
1915 
  [(set_attr "may_trap" "no")
1916 
   (set_attr "latency" "0")
1917 
   (set_attr "length" "4")
1918 
   (set_attr "slot" "cop")
1919 
   (set_attr "slots" "p1")
1920 
   (set_attr "stall" "none")])
1921 
 
1922 
 
1923 
(define_insn "cgen_intrinsic_cpmsbua1_h_C3"
1924 
  [(set (reg:SI 87)
1925 
        (unspec_volatile:SI [
1926 
          (match_operand:DI 0 "general_operand" "x")
1927 
          (match_operand:DI 1 "general_operand" "x")
1928 
        ] 2448))
1929 
   (set (reg:SI 111)
1930 
        (unspec_volatile:SI [
1931 
          (match_dup 0)
1932 
          (match_dup 1)
1933 
        ] 2450))
1934 
   (set (reg:SI 110)
1935 
        (unspec_volatile:SI [
1936 
          (match_dup 0)
1937 
          (match_dup 1)
1938 
        ] 2452))
1939 
   (set (reg:SI 109)
1940 
        (unspec_volatile:SI [
1941 
          (match_dup 0)
1942 
          (match_dup 1)
1943 
        ] 2454))
1944 
   (set (reg:SI 108)
1945 
        (unspec_volatile:SI [
1946 
          (match_dup 0)
1947 
          (match_dup 1)
1948 
        ] 2456))]
1949 
  "CGEN_ENABLE_INSN_P (50)"
1950 
  "cpmsbua1.h\\t%0,%1"
1951 
  [(set_attr "may_trap" "no")
1952 
   (set_attr "latency" "0")
1953 
   (set_attr "length" "4")
1954 
   (set_attr "slot" "cop")
1955 
   (set_attr "slots" "c3")
1956 
   (set_attr "stall" "none")])
1957 
 
1958 
 
1959 
(define_insn "cgen_intrinsic_cpmsbua1_h_P1"
1960 
  [(set (reg:SI 87)
1961 
        (unspec_volatile:SI [
1962 
          (match_operand:DI 0 "general_operand" "x")
1963 
          (match_operand:DI 1 "general_operand" "x")
1964 
        ] 2448))
1965 
   (set (reg:SI 111)
1966 
        (unspec_volatile:SI [
1967 
          (match_dup 0)
1968 
          (match_dup 1)
1969 
        ] 2450))
1970 
   (set (reg:SI 110)
1971 
        (unspec_volatile:SI [
1972 
          (match_dup 0)
1973 
          (match_dup 1)
1974 
        ] 2452))
1975 
   (set (reg:SI 109)
1976 
        (unspec_volatile:SI [
1977 
          (match_dup 0)
1978 
          (match_dup 1)
1979 
        ] 2454))
1980 
   (set (reg:SI 108)
1981 
        (unspec_volatile:SI [
1982 
          (match_dup 0)
1983 
          (match_dup 1)
1984 
        ] 2456))]
1985 
  "CGEN_ENABLE_INSN_P (51)"
1986 
  "cpmsbua1.h\\t%0,%1"
1987 
  [(set_attr "may_trap" "no")
1988 
   (set_attr "latency" "0")
1989 
   (set_attr "length" "4")
1990 
   (set_attr "slot" "cop")
1991 
   (set_attr "slots" "p1")
1992 
   (set_attr "stall" "none")])
1993 
 
1994 
 
1995 
(define_insn "cgen_intrinsic_cpmadla1_w_C3"
1996 
  [(set (reg:SI 87)
1997 
        (unspec_volatile:SI [
1998 
          (match_operand:DI 0 "general_operand" "x")
1999 
          (match_operand:DI 1 "general_operand" "x")
2000 
        ] 2458))
2001 
   (set (reg:SI 107)
2002 
        (unspec_volatile:SI [
2003 
          (match_dup 0)
2004 
          (match_dup 1)
2005 
        ] 2460))
2006 
   (set (reg:SI 106)
2007 
        (unspec_volatile:SI [
2008 
          (match_dup 0)
2009 
          (match_dup 1)
2010 
        ] 2462))
2011 
   (set (reg:SI 105)
2012 
        (unspec_volatile:SI [
2013 
          (match_dup 0)
2014 
          (match_dup 1)
2015 
        ] 2464))
2016 
   (set (reg:SI 104)
2017 
        (unspec_volatile:SI [
2018 
          (match_dup 0)
2019 
          (match_dup 1)
2020 
        ] 2466))]
2021 
  "CGEN_ENABLE_INSN_P (52)"
2022 
  "cpmadla1.w\\t%0,%1"
2023 
  [(set_attr "may_trap" "no")
2024 
   (set_attr "latency" "0")
2025 
   (set_attr "length" "4")
2026 
   (set_attr "slot" "cop")
2027 
   (set_attr "slots" "c3")
2028 
   (set_attr "stall" "none")])
2029 
 
2030 
 
2031 
(define_insn "cgen_intrinsic_cpmadla1_w_P1"
2032 
  [(set (reg:SI 87)
2033 
        (unspec_volatile:SI [
2034 
          (match_operand:DI 0 "general_operand" "x")
2035 
          (match_operand:DI 1 "general_operand" "x")
2036 
        ] 2458))
2037 
   (set (reg:SI 107)
2038 
        (unspec_volatile:SI [
2039 
          (match_dup 0)
2040 
          (match_dup 1)
2041 
        ] 2460))
2042 
   (set (reg:SI 106)
2043 
        (unspec_volatile:SI [
2044 
          (match_dup 0)
2045 
          (match_dup 1)
2046 
        ] 2462))
2047 
   (set (reg:SI 105)
2048 
        (unspec_volatile:SI [
2049 
          (match_dup 0)
2050 
          (match_dup 1)
2051 
        ] 2464))
2052 
   (set (reg:SI 104)
2053 
        (unspec_volatile:SI [
2054 
          (match_dup 0)
2055 
          (match_dup 1)
2056 
        ] 2466))]
2057 
  "CGEN_ENABLE_INSN_P (53)"
2058 
  "cpmadla1.w\\t%0,%1"
2059 
  [(set_attr "may_trap" "no")
2060 
   (set_attr "latency" "0")
2061 
   (set_attr "length" "4")
2062 
   (set_attr "slot" "cop")
2063 
   (set_attr "slots" "p1")
2064 
   (set_attr "stall" "none")])
2065 
 
2066 
 
2067 
(define_insn "cgen_intrinsic_cpmadua1_w_C3"
2068 
  [(set (reg:SI 87)
2069 
        (unspec_volatile:SI [
2070 
          (match_operand:DI 0 "general_operand" "x")
2071 
          (match_operand:DI 1 "general_operand" "x")
2072 
        ] 2468))
2073 
   (set (reg:SI 111)
2074 
        (unspec_volatile:SI [
2075 
          (match_dup 0)
2076 
          (match_dup 1)
2077 
        ] 2470))
2078 
   (set (reg:SI 110)
2079 
        (unspec_volatile:SI [
2080 
          (match_dup 0)
2081 
          (match_dup 1)
2082 
        ] 2472))
2083 
   (set (reg:SI 109)
2084 
        (unspec_volatile:SI [
2085 
          (match_dup 0)
2086 
          (match_dup 1)
2087 
        ] 2474))
2088 
   (set (reg:SI 108)
2089 
        (unspec_volatile:SI [
2090 
          (match_dup 0)
2091 
          (match_dup 1)
2092 
        ] 2476))]
2093 
  "CGEN_ENABLE_INSN_P (54)"
2094 
  "cpmadua1.w\\t%0,%1"
2095 
  [(set_attr "may_trap" "no")
2096 
   (set_attr "latency" "0")
2097 
   (set_attr "length" "4")
2098 
   (set_attr "slot" "cop")
2099 
   (set_attr "slots" "c3")
2100 
   (set_attr "stall" "none")])
2101 
 
2102 
 
2103 
(define_insn "cgen_intrinsic_cpmadua1_w_P1"
2104 
  [(set (reg:SI 87)
2105 
        (unspec_volatile:SI [
2106 
          (match_operand:DI 0 "general_operand" "x")
2107 
          (match_operand:DI 1 "general_operand" "x")
2108 
        ] 2468))
2109 
   (set (reg:SI 111)
2110 
        (unspec_volatile:SI [
2111 
          (match_dup 0)
2112 
          (match_dup 1)
2113 
        ] 2470))
2114 
   (set (reg:SI 110)
2115 
        (unspec_volatile:SI [
2116 
          (match_dup 0)
2117 
          (match_dup 1)
2118 
        ] 2472))
2119 
   (set (reg:SI 109)
2120 
        (unspec_volatile:SI [
2121 
          (match_dup 0)
2122 
          (match_dup 1)
2123 
        ] 2474))
2124 
   (set (reg:SI 108)
2125 
        (unspec_volatile:SI [
2126 
          (match_dup 0)
2127 
          (match_dup 1)
2128 
        ] 2476))]
2129 
  "CGEN_ENABLE_INSN_P (55)"
2130 
  "cpmadua1.w\\t%0,%1"
2131 
  [(set_attr "may_trap" "no")
2132 
   (set_attr "latency" "0")
2133 
   (set_attr "length" "4")
2134 
   (set_attr "slot" "cop")
2135 
   (set_attr "slots" "p1")
2136 
   (set_attr "stall" "none")])
2137 
 
2138 
 
2139 
(define_insn "cgen_intrinsic_cpmadla1u_w_C3"
2140 
  [(set (reg:SI 87)
2141 
        (unspec_volatile:SI [
2142 
          (match_operand:DI 0 "general_operand" "x")
2143 
          (match_operand:DI 1 "general_operand" "x")
2144 
        ] 2478))
2145 
   (set (reg:SI 107)
2146 
        (unspec_volatile:SI [
2147 
          (match_dup 0)
2148 
          (match_dup 1)
2149 
        ] 2480))
2150 
   (set (reg:SI 106)
2151 
        (unspec_volatile:SI [
2152 
          (match_dup 0)
2153 
          (match_dup 1)
2154 
        ] 2482))
2155 
   (set (reg:SI 105)
2156 
        (unspec_volatile:SI [
2157 
          (match_dup 0)
2158 
          (match_dup 1)
2159 
        ] 2484))
2160 
   (set (reg:SI 104)
2161 
        (unspec_volatile:SI [
2162 
          (match_dup 0)
2163 
          (match_dup 1)
2164 
        ] 2486))]
2165 
  "CGEN_ENABLE_INSN_P (56)"
2166 
  "cpmadla1u.w\\t%0,%1"
2167 
  [(set_attr "may_trap" "no")
2168 
   (set_attr "latency" "0")
2169 
   (set_attr "length" "4")
2170 
   (set_attr "slot" "cop")
2171 
   (set_attr "slots" "c3")
2172 
   (set_attr "stall" "none")])
2173 
 
2174 
 
2175 
(define_insn "cgen_intrinsic_cpmadla1u_w_P1"
2176 
  [(set (reg:SI 87)
2177 
        (unspec_volatile:SI [
2178 
          (match_operand:DI 0 "general_operand" "x")
2179 
          (match_operand:DI 1 "general_operand" "x")
2180 
        ] 2478))
2181 
   (set (reg:SI 107)
2182 
        (unspec_volatile:SI [
2183 
          (match_dup 0)
2184 
          (match_dup 1)
2185 
        ] 2480))
2186 
   (set (reg:SI 106)
2187 
        (unspec_volatile:SI [
2188 
          (match_dup 0)
2189 
          (match_dup 1)
2190 
        ] 2482))
2191 
   (set (reg:SI 105)
2192 
        (unspec_volatile:SI [
2193 
          (match_dup 0)
2194 
          (match_dup 1)
2195 
        ] 2484))
2196 
   (set (reg:SI 104)
2197 
        (unspec_volatile:SI [
2198 
          (match_dup 0)
2199 
          (match_dup 1)
2200 
        ] 2486))]
2201 
  "CGEN_ENABLE_INSN_P (57)"
2202 
  "cpmadla1u.w\\t%0,%1"
2203 
  [(set_attr "may_trap" "no")
2204 
   (set_attr "latency" "0")
2205 
   (set_attr "length" "4")
2206 
   (set_attr "slot" "cop")
2207 
   (set_attr "slots" "p1")
2208 
   (set_attr "stall" "none")])
2209 
 
2210 
 
2211 
(define_insn "cgen_intrinsic_cpmadua1u_w_C3"
2212 
  [(set (reg:SI 87)
2213 
        (unspec_volatile:SI [
2214 
          (match_operand:DI 0 "general_operand" "x")
2215 
          (match_operand:DI 1 "general_operand" "x")
2216 
        ] 2488))
2217 
   (set (reg:SI 111)
2218 
        (unspec_volatile:SI [
2219 
          (match_dup 0)
2220 
          (match_dup 1)
2221 
        ] 2490))
2222 
   (set (reg:SI 110)
2223 
        (unspec_volatile:SI [
2224 
          (match_dup 0)
2225 
          (match_dup 1)
2226 
        ] 2492))
2227 
   (set (reg:SI 109)
2228 
        (unspec_volatile:SI [
2229 
          (match_dup 0)
2230 
          (match_dup 1)
2231 
        ] 2494))
2232 
   (set (reg:SI 108)
2233 
        (unspec_volatile:SI [
2234 
          (match_dup 0)
2235 
          (match_dup 1)
2236 
        ] 2496))]
2237 
  "CGEN_ENABLE_INSN_P (58)"
2238 
  "cpmadua1u.w\\t%0,%1"
2239 
  [(set_attr "may_trap" "no")
2240 
   (set_attr "latency" "0")
2241 
   (set_attr "length" "4")
2242 
   (set_attr "slot" "cop")
2243 
   (set_attr "slots" "c3")
2244 
   (set_attr "stall" "none")])
2245 
 
2246 
 
2247 
(define_insn "cgen_intrinsic_cpmadua1u_w_P1"
2248 
  [(set (reg:SI 87)
2249 
        (unspec_volatile:SI [
2250 
          (match_operand:DI 0 "general_operand" "x")
2251 
          (match_operand:DI 1 "general_operand" "x")
2252 
        ] 2488))
2253 
   (set (reg:SI 111)
2254 
        (unspec_volatile:SI [
2255 
          (match_dup 0)
2256 
          (match_dup 1)
2257 
        ] 2490))
2258 
   (set (reg:SI 110)
2259 
        (unspec_volatile:SI [
2260 
          (match_dup 0)
2261 
          (match_dup 1)
2262 
        ] 2492))
2263 
   (set (reg:SI 109)
2264 
        (unspec_volatile:SI [
2265 
          (match_dup 0)
2266 
          (match_dup 1)
2267 
        ] 2494))
2268 
   (set (reg:SI 108)
2269 
        (unspec_volatile:SI [
2270 
          (match_dup 0)
2271 
          (match_dup 1)
2272 
        ] 2496))]
2273 
  "CGEN_ENABLE_INSN_P (59)"
2274 
  "cpmadua1u.w\\t%0,%1"
2275 
  [(set_attr "may_trap" "no")
2276 
   (set_attr "latency" "0")
2277 
   (set_attr "length" "4")
2278 
   (set_attr "slot" "cop")
2279 
   (set_attr "slots" "p1")
2280 
   (set_attr "stall" "none")])
2281 
 
2282 
 
2283 
(define_insn "cgen_intrinsic_cpmadla1_h_C3"
2284 
  [(set (reg:SI 87)
2285 
        (unspec_volatile:SI [
2286 
          (match_operand:DI 0 "general_operand" "x")
2287 
          (match_operand:DI 1 "general_operand" "x")
2288 
        ] 2498))
2289 
   (set (reg:SI 107)
2290 
        (unspec_volatile:SI [
2291 
          (match_dup 0)
2292 
          (match_dup 1)
2293 
        ] 2500))
2294 
   (set (reg:SI 106)
2295 
        (unspec_volatile:SI [
2296 
          (match_dup 0)
2297 
          (match_dup 1)
2298 
        ] 2502))
2299 
   (set (reg:SI 105)
2300 
        (unspec_volatile:SI [
2301 
          (match_dup 0)
2302 
          (match_dup 1)
2303 
        ] 2504))
2304 
   (set (reg:SI 104)
2305 
        (unspec_volatile:SI [
2306 
          (match_dup 0)
2307 
          (match_dup 1)
2308 
        ] 2506))]
2309 
  "CGEN_ENABLE_INSN_P (60)"
2310 
  "cpmadla1.h\\t%0,%1"
2311 
  [(set_attr "may_trap" "no")
2312 
   (set_attr "latency" "0")
2313 
   (set_attr "length" "4")
2314 
   (set_attr "slot" "cop")
2315 
   (set_attr "slots" "c3")
2316 
   (set_attr "stall" "none")])
2317 
 
2318 
 
2319 
(define_insn "cgen_intrinsic_cpmadla1_h_P1"
2320 
  [(set (reg:SI 87)
2321 
        (unspec_volatile:SI [
2322 
          (match_operand:DI 0 "general_operand" "x")
2323 
          (match_operand:DI 1 "general_operand" "x")
2324 
        ] 2498))
2325 
   (set (reg:SI 107)
2326 
        (unspec_volatile:SI [
2327 
          (match_dup 0)
2328 
          (match_dup 1)
2329 
        ] 2500))
2330 
   (set (reg:SI 106)
2331 
        (unspec_volatile:SI [
2332 
          (match_dup 0)
2333 
          (match_dup 1)
2334 
        ] 2502))
2335 
   (set (reg:SI 105)
2336 
        (unspec_volatile:SI [
2337 
          (match_dup 0)
2338 
          (match_dup 1)
2339 
        ] 2504))
2340 
   (set (reg:SI 104)
2341 
        (unspec_volatile:SI [
2342 
          (match_dup 0)
2343 
          (match_dup 1)
2344 
        ] 2506))]
2345 
  "CGEN_ENABLE_INSN_P (61)"
2346 
  "cpmadla1.h\\t%0,%1"
2347 
  [(set_attr "may_trap" "no")
2348 
   (set_attr "latency" "0")
2349 
   (set_attr "length" "4")
2350 
   (set_attr "slot" "cop")
2351 
   (set_attr "slots" "p1")
2352 
   (set_attr "stall" "none")])
2353 
 
2354 
 
2355 
(define_insn "cgen_intrinsic_cpmadua1_h_C3"
2356 
  [(set (reg:SI 87)
2357 
        (unspec_volatile:SI [
2358 
          (match_operand:DI 0 "general_operand" "x")
2359 
          (match_operand:DI 1 "general_operand" "x")
2360 
        ] 2508))
2361 
   (set (reg:SI 111)
2362 
        (unspec_volatile:SI [
2363 
          (match_dup 0)
2364 
          (match_dup 1)
2365 
        ] 2510))
2366 
   (set (reg:SI 110)
2367 
        (unspec_volatile:SI [
2368 
          (match_dup 0)
2369 
          (match_dup 1)
2370 
        ] 2512))
2371 
   (set (reg:SI 109)
2372 
        (unspec_volatile:SI [
2373 
          (match_dup 0)
2374 
          (match_dup 1)
2375 
        ] 2514))
2376 
   (set (reg:SI 108)
2377 
        (unspec_volatile:SI [
2378 
          (match_dup 0)
2379 
          (match_dup 1)
2380 
        ] 2516))]
2381 
  "CGEN_ENABLE_INSN_P (62)"
2382 
  "cpmadua1.h\\t%0,%1"
2383 
  [(set_attr "may_trap" "no")
2384 
   (set_attr "latency" "0")
2385 
   (set_attr "length" "4")
2386 
   (set_attr "slot" "cop")
2387 
   (set_attr "slots" "c3")
2388 
   (set_attr "stall" "none")])
2389 
 
2390 
 
2391 
(define_insn "cgen_intrinsic_cpmadua1_h_P1"
2392 
  [(set (reg:SI 87)
2393 
        (unspec_volatile:SI [
2394 
          (match_operand:DI 0 "general_operand" "x")
2395 
          (match_operand:DI 1 "general_operand" "x")
2396 
        ] 2508))
2397 
   (set (reg:SI 111)
2398 
        (unspec_volatile:SI [
2399 
          (match_dup 0)
2400 
          (match_dup 1)
2401 
        ] 2510))
2402 
   (set (reg:SI 110)
2403 
        (unspec_volatile:SI [
2404 
          (match_dup 0)
2405 
          (match_dup 1)
2406 
        ] 2512))
2407 
   (set (reg:SI 109)
2408 
        (unspec_volatile:SI [
2409 
          (match_dup 0)
2410 
          (match_dup 1)
2411 
        ] 2514))
2412 
   (set (reg:SI 108)
2413 
        (unspec_volatile:SI [
2414 
          (match_dup 0)
2415 
          (match_dup 1)
2416 
        ] 2516))]
2417 
  "CGEN_ENABLE_INSN_P (63)"
2418 
  "cpmadua1.h\\t%0,%1"
2419 
  [(set_attr "may_trap" "no")
2420 
   (set_attr "latency" "0")
2421 
   (set_attr "length" "4")
2422 
   (set_attr "slot" "cop")
2423 
   (set_attr "slots" "p1")
2424 
   (set_attr "stall" "none")])
2425 
 
2426 
 
2427 
(define_insn "cgen_intrinsic_cpmada1_b_C3"
2428 
  [(set (reg:SI 87)
2429 
        (unspec_volatile:SI [
2430 
          (match_operand:DI 0 "general_operand" "x")
2431 
          (match_operand:DI 1 "general_operand" "x")
2432 
        ] 2518))
2433 
   (set (reg:SI 111)
2434 
        (unspec_volatile:SI [
2435 
          (match_dup 0)
2436 
          (match_dup 1)
2437 
        ] 2520))
2438 
   (set (reg:SI 110)
2439 
        (unspec_volatile:SI [
2440 
          (match_dup 0)
2441 
          (match_dup 1)
2442 
        ] 2522))
2443 
   (set (reg:SI 109)
2444 
        (unspec_volatile:SI [
2445 
          (match_dup 0)
2446 
          (match_dup 1)
2447 
        ] 2524))
2448 
   (set (reg:SI 108)
2449 
        (unspec_volatile:SI [
2450 
          (match_dup 0)
2451 
          (match_dup 1)
2452 
        ] 2526))
2453 
   (set (reg:SI 107)
2454 
        (unspec_volatile:SI [
2455 
          (match_dup 0)
2456 
          (match_dup 1)
2457 
        ] 2528))
2458 
   (set (reg:SI 106)
2459 
        (unspec_volatile:SI [
2460 
          (match_dup 0)
2461 
          (match_dup 1)
2462 
        ] 2530))
2463 
   (set (reg:SI 105)
2464 
        (unspec_volatile:SI [
2465 
          (match_dup 0)
2466 
          (match_dup 1)
2467 
        ] 2532))
2468 
   (set (reg:SI 104)
2469 
        (unspec_volatile:SI [
2470 
          (match_dup 0)
2471 
          (match_dup 1)
2472 
        ] 2534))]
2473 
  "CGEN_ENABLE_INSN_P (64)"
2474 
  "cpmada1.b\\t%0,%1"
2475 
  [(set_attr "may_trap" "no")
2476 
   (set_attr "latency" "0")
2477 
   (set_attr "length" "4")
2478 
   (set_attr "slot" "cop")
2479 
   (set_attr "slots" "c3")
2480 
   (set_attr "stall" "none")])
2481 
 
2482 
 
2483 
(define_insn "cgen_intrinsic_cpmada1_b_P1"
2484 
  [(set (reg:SI 87)
2485 
        (unspec_volatile:SI [
2486 
          (match_operand:DI 0 "general_operand" "x")
2487 
          (match_operand:DI 1 "general_operand" "x")
2488 
        ] 2518))
2489 
   (set (reg:SI 111)
2490 
        (unspec_volatile:SI [
2491 
          (match_dup 0)
2492 
          (match_dup 1)
2493 
        ] 2520))
2494 
   (set (reg:SI 110)
2495 
        (unspec_volatile:SI [
2496 
          (match_dup 0)
2497 
          (match_dup 1)
2498 
        ] 2522))
2499 
   (set (reg:SI 109)
2500 
        (unspec_volatile:SI [
2501 
          (match_dup 0)
2502 
          (match_dup 1)
2503 
        ] 2524))
2504 
   (set (reg:SI 108)
2505 
        (unspec_volatile:SI [
2506 
          (match_dup 0)
2507 
          (match_dup 1)
2508 
        ] 2526))
2509 
   (set (reg:SI 107)
2510 
        (unspec_volatile:SI [
2511 
          (match_dup 0)
2512 
          (match_dup 1)
2513 
        ] 2528))
2514 
   (set (reg:SI 106)
2515 
        (unspec_volatile:SI [
2516 
          (match_dup 0)
2517 
          (match_dup 1)
2518 
        ] 2530))
2519 
   (set (reg:SI 105)
2520 
        (unspec_volatile:SI [
2521 
          (match_dup 0)
2522 
          (match_dup 1)
2523 
        ] 2532))
2524 
   (set (reg:SI 104)
2525 
        (unspec_volatile:SI [
2526 
          (match_dup 0)
2527 
          (match_dup 1)
2528 
        ] 2534))]
2529 
  "CGEN_ENABLE_INSN_P (65)"
2530 
  "cpmada1.b\\t%0,%1"
2531 
  [(set_attr "may_trap" "no")
2532 
   (set_attr "latency" "0")
2533 
   (set_attr "length" "4")
2534 
   (set_attr "slot" "cop")
2535 
   (set_attr "slots" "p1")
2536 
   (set_attr "stall" "none")])
2537 
 
2538 
 
2539 
(define_insn "cgen_intrinsic_cpmada1u_b_C3"
2540 
  [(set (reg:SI 87)
2541 
        (unspec_volatile:SI [
2542 
          (match_operand:DI 0 "general_operand" "x")
2543 
          (match_operand:DI 1 "general_operand" "x")
2544 
        ] 2536))
2545 
   (set (reg:SI 111)
2546 
        (unspec_volatile:SI [
2547 
          (match_dup 0)
2548 
          (match_dup 1)
2549 
        ] 2538))
2550 
   (set (reg:SI 110)
2551 
        (unspec_volatile:SI [
2552 
          (match_dup 0)
2553 
          (match_dup 1)
2554 
        ] 2540))
2555 
   (set (reg:SI 109)
2556 
        (unspec_volatile:SI [
2557 
          (match_dup 0)
2558 
          (match_dup 1)
2559 
        ] 2542))
2560 
   (set (reg:SI 108)
2561 
        (unspec_volatile:SI [
2562 
          (match_dup 0)
2563 
          (match_dup 1)
2564 
        ] 2544))
2565 
   (set (reg:SI 107)
2566 
        (unspec_volatile:SI [
2567 
          (match_dup 0)
2568 
          (match_dup 1)
2569 
        ] 2546))
2570 
   (set (reg:SI 106)
2571 
        (unspec_volatile:SI [
2572 
          (match_dup 0)
2573 
          (match_dup 1)
2574 
        ] 2548))
2575 
   (set (reg:SI 105)
2576 
        (unspec_volatile:SI [
2577 
          (match_dup 0)
2578 
          (match_dup 1)
2579 
        ] 2550))
2580 
   (set (reg:SI 104)
2581 
        (unspec_volatile:SI [
2582 
          (match_dup 0)
2583 
          (match_dup 1)
2584 
        ] 2552))]
2585 
  "CGEN_ENABLE_INSN_P (66)"
2586 
  "cpmada1u.b\\t%0,%1"
2587 
  [(set_attr "may_trap" "no")
2588 
   (set_attr "latency" "0")
2589 
   (set_attr "length" "4")
2590 
   (set_attr "slot" "cop")
2591 
   (set_attr "slots" "c3")
2592 
   (set_attr "stall" "none")])
2593 
 
2594 
 
2595 
(define_insn "cgen_intrinsic_cpmada1u_b_P1"
2596 
  [(set (reg:SI 87)
2597 
        (unspec_volatile:SI [
2598 
          (match_operand:DI 0 "general_operand" "x")
2599 
          (match_operand:DI 1 "general_operand" "x")
2600 
        ] 2536))
2601 
   (set (reg:SI 111)
2602 
        (unspec_volatile:SI [
2603 
          (match_dup 0)
2604 
          (match_dup 1)
2605 
        ] 2538))
2606 
   (set (reg:SI 110)
2607 
        (unspec_volatile:SI [
2608 
          (match_dup 0)
2609 
          (match_dup 1)
2610 
        ] 2540))
2611 
   (set (reg:SI 109)
2612 
        (unspec_volatile:SI [
2613 
          (match_dup 0)
2614 
          (match_dup 1)
2615 
        ] 2542))
2616 
   (set (reg:SI 108)
2617 
        (unspec_volatile:SI [
2618 
          (match_dup 0)
2619 
          (match_dup 1)
2620 
        ] 2544))
2621 
   (set (reg:SI 107)
2622 
        (unspec_volatile:SI [
2623 
          (match_dup 0)
2624 
          (match_dup 1)
2625 
        ] 2546))
2626 
   (set (reg:SI 106)
2627 
        (unspec_volatile:SI [
2628 
          (match_dup 0)
2629 
          (match_dup 1)
2630 
        ] 2548))
2631 
   (set (reg:SI 105)
2632 
        (unspec_volatile:SI [
2633 
          (match_dup 0)
2634 
          (match_dup 1)
2635 
        ] 2550))
2636 
   (set (reg:SI 104)
2637 
        (unspec_volatile:SI [
2638 
          (match_dup 0)
2639 
          (match_dup 1)
2640 
        ] 2552))]
2641 
  "CGEN_ENABLE_INSN_P (67)"
2642 
  "cpmada1u.b\\t%0,%1"
2643 
  [(set_attr "may_trap" "no")
2644 
   (set_attr "latency" "0")
2645 
   (set_attr "length" "4")
2646 
   (set_attr "slot" "cop")
2647 
   (set_attr "slots" "p1")
2648 
   (set_attr "stall" "none")])
2649 
 
2650 
 
2651 
(define_insn "cgen_intrinsic_cpmulla1_w_C3"
2652 
  [(set (reg:SI 107)
2653 
        (unspec_volatile:SI [
2654 
          (match_operand:DI 0 "general_operand" "x")
2655 
          (match_operand:DI 1 "general_operand" "x")
2656 
        ] 2554))
2657 
   (set (reg:SI 106)
2658 
        (unspec_volatile:SI [
2659 
          (match_dup 0)
2660 
          (match_dup 1)
2661 
        ] 2556))
2662 
   (set (reg:SI 105)
2663 
        (unspec_volatile:SI [
2664 
          (match_dup 0)
2665 
          (match_dup 1)
2666 
        ] 2558))
2667 
   (set (reg:SI 104)
2668 
        (unspec_volatile:SI [
2669 
          (match_dup 0)
2670 
          (match_dup 1)
2671 
        ] 2560))]
2672 
  "CGEN_ENABLE_INSN_P (68)"
2673 
  "cpmulla1.w\\t%0,%1"
2674 
  [(set_attr "may_trap" "no")
2675 
   (set_attr "latency" "0")
2676 
   (set_attr "length" "4")
2677 
   (set_attr "slot" "cop")
2678 
   (set_attr "slots" "c3")
2679 
   (set_attr "stall" "none")])
2680 
 
2681 
 
2682 
(define_insn "cgen_intrinsic_cpmulla1_w_P1"
2683 
  [(set (reg:SI 107)
2684 
        (unspec_volatile:SI [
2685 
          (match_operand:DI 0 "general_operand" "x")
2686 
          (match_operand:DI 1 "general_operand" "x")
2687 
        ] 2554))
2688 
   (set (reg:SI 106)
2689 
        (unspec_volatile:SI [
2690 
          (match_dup 0)
2691 
          (match_dup 1)
2692 
        ] 2556))
2693 
   (set (reg:SI 105)
2694 
        (unspec_volatile:SI [
2695 
          (match_dup 0)
2696 
          (match_dup 1)
2697 
        ] 2558))
2698 
   (set (reg:SI 104)
2699 
        (unspec_volatile:SI [
2700 
          (match_dup 0)
2701 
          (match_dup 1)
2702 
        ] 2560))]
2703 
  "CGEN_ENABLE_INSN_P (69)"
2704 
  "cpmulla1.w\\t%0,%1"
2705 
  [(set_attr "may_trap" "no")
2706 
   (set_attr "latency" "0")
2707 
   (set_attr "length" "4")
2708 
   (set_attr "slot" "cop")
2709 
   (set_attr "slots" "p1")
2710 
   (set_attr "stall" "none")])
2711 
 
2712 
 
2713 
(define_insn "cgen_intrinsic_cpmulua1_w_C3"
2714 
  [(set (reg:SI 111)
2715 
        (unspec_volatile:SI [
2716 
          (match_operand:DI 0 "general_operand" "x")
2717 
          (match_operand:DI 1 "general_operand" "x")
2718 
        ] 2562))
2719 
   (set (reg:SI 110)
2720 
        (unspec_volatile:SI [
2721 
          (match_dup 0)
2722 
          (match_dup 1)
2723 
        ] 2564))
2724 
   (set (reg:SI 109)
2725 
        (unspec_volatile:SI [
2726 
          (match_dup 0)
2727 
          (match_dup 1)
2728 
        ] 2566))
2729 
   (set (reg:SI 108)
2730 
        (unspec_volatile:SI [
2731 
          (match_dup 0)
2732 
          (match_dup 1)
2733 
        ] 2568))]
2734 
  "CGEN_ENABLE_INSN_P (70)"
2735 
  "cpmulua1.w\\t%0,%1"
2736 
  [(set_attr "may_trap" "no")
2737 
   (set_attr "latency" "0")
2738 
   (set_attr "length" "4")
2739 
   (set_attr "slot" "cop")
2740 
   (set_attr "slots" "c3")
2741 
   (set_attr "stall" "none")])
2742 
 
2743 
 
2744 
(define_insn "cgen_intrinsic_cpmulua1_w_P1"
2745 
  [(set (reg:SI 111)
2746 
        (unspec_volatile:SI [
2747 
          (match_operand:DI 0 "general_operand" "x")
2748 
          (match_operand:DI 1 "general_operand" "x")
2749 
        ] 2562))
2750 
   (set (reg:SI 110)
2751 
        (unspec_volatile:SI [
2752 
          (match_dup 0)
2753 
          (match_dup 1)
2754 
        ] 2564))
2755 
   (set (reg:SI 109)
2756 
        (unspec_volatile:SI [
2757 
          (match_dup 0)
2758 
          (match_dup 1)
2759 
        ] 2566))
2760 
   (set (reg:SI 108)
2761 
        (unspec_volatile:SI [
2762 
          (match_dup 0)
2763 
          (match_dup 1)
2764 
        ] 2568))]
2765 
  "CGEN_ENABLE_INSN_P (71)"
2766 
  "cpmulua1.w\\t%0,%1"
2767 
  [(set_attr "may_trap" "no")
2768 
   (set_attr "latency" "0")
2769 
   (set_attr "length" "4")
2770 
   (set_attr "slot" "cop")
2771 
   (set_attr "slots" "p1")
2772 
   (set_attr "stall" "none")])
2773 
 
2774 
 
2775 
(define_insn "cgen_intrinsic_cpmulla1u_w_C3"
2776 
  [(set (reg:SI 107)
2777 
        (unspec_volatile:SI [
2778 
          (match_operand:DI 0 "general_operand" "x")
2779 
          (match_operand:DI 1 "general_operand" "x")
2780 
        ] 2570))
2781 
   (set (reg:SI 106)
2782 
        (unspec_volatile:SI [
2783 
          (match_dup 0)
2784 
          (match_dup 1)
2785 
        ] 2572))
2786 
   (set (reg:SI 105)
2787 
        (unspec_volatile:SI [
2788 
          (match_dup 0)
2789 
          (match_dup 1)
2790 
        ] 2574))
2791 
   (set (reg:SI 104)
2792 
        (unspec_volatile:SI [
2793 
          (match_dup 0)
2794 
          (match_dup 1)
2795 
        ] 2576))]
2796 
  "CGEN_ENABLE_INSN_P (72)"
2797 
  "cpmulla1u.w\\t%0,%1"
2798 
  [(set_attr "may_trap" "no")
2799 
   (set_attr "latency" "0")
2800 
   (set_attr "length" "4")
2801 
   (set_attr "slot" "cop")
2802 
   (set_attr "slots" "c3")
2803 
   (set_attr "stall" "none")])
2804 
 
2805 
 
2806 
(define_insn "cgen_intrinsic_cpmulla1u_w_P1"
2807 
  [(set (reg:SI 107)
2808 
        (unspec_volatile:SI [
2809 
          (match_operand:DI 0 "general_operand" "x")
2810 
          (match_operand:DI 1 "general_operand" "x")
2811 
        ] 2570))
2812 
   (set (reg:SI 106)
2813 
        (unspec_volatile:SI [
2814 
          (match_dup 0)
2815 
          (match_dup 1)
2816 
        ] 2572))
2817 
   (set (reg:SI 105)
2818 
        (unspec_volatile:SI [
2819 
          (match_dup 0)
2820 
          (match_dup 1)
2821 
        ] 2574))
2822 
   (set (reg:SI 104)
2823 
        (unspec_volatile:SI [
2824 
          (match_dup 0)
2825 
          (match_dup 1)
2826 
        ] 2576))]
2827 
  "CGEN_ENABLE_INSN_P (73)"
2828 
  "cpmulla1u.w\\t%0,%1"
2829 
  [(set_attr "may_trap" "no")
2830 
   (set_attr "latency" "0")
2831 
   (set_attr "length" "4")
2832 
   (set_attr "slot" "cop")
2833 
   (set_attr "slots" "p1")
2834 
   (set_attr "stall" "none")])
2835 
 
2836 
 
2837 
(define_insn "cgen_intrinsic_cpmulua1u_w_C3"
2838 
  [(set (reg:SI 111)
2839 
        (unspec_volatile:SI [
2840 
          (match_operand:DI 0 "general_operand" "x")
2841 
          (match_operand:DI 1 "general_operand" "x")
2842 
        ] 2578))
2843 
   (set (reg:SI 110)
2844 
        (unspec_volatile:SI [
2845 
          (match_dup 0)
2846 
          (match_dup 1)
2847 
        ] 2580))
2848 
   (set (reg:SI 109)
2849 
        (unspec_volatile:SI [
2850 
          (match_dup 0)
2851 
          (match_dup 1)
2852 
        ] 2582))
2853 
   (set (reg:SI 108)
2854 
        (unspec_volatile:SI [
2855 
          (match_dup 0)
2856 
          (match_dup 1)
2857 
        ] 2584))]
2858 
  "CGEN_ENABLE_INSN_P (74)"
2859 
  "cpmulua1u.w\\t%0,%1"
2860 
  [(set_attr "may_trap" "no")
2861 
   (set_attr "latency" "0")
2862 
   (set_attr "length" "4")
2863 
   (set_attr "slot" "cop")
2864 
   (set_attr "slots" "c3")
2865 
   (set_attr "stall" "none")])
2866 
 
2867 
 
2868 
(define_insn "cgen_intrinsic_cpmulua1u_w_P1"
2869 
  [(set (reg:SI 111)
2870 
        (unspec_volatile:SI [
2871 
          (match_operand:DI 0 "general_operand" "x")
2872 
          (match_operand:DI 1 "general_operand" "x")
2873 
        ] 2578))
2874 
   (set (reg:SI 110)
2875 
        (unspec_volatile:SI [
2876 
          (match_dup 0)
2877 
          (match_dup 1)
2878 
        ] 2580))
2879 
   (set (reg:SI 109)
2880 
        (unspec_volatile:SI [
2881 
          (match_dup 0)
2882 
          (match_dup 1)
2883 
        ] 2582))
2884 
   (set (reg:SI 108)
2885 
        (unspec_volatile:SI [
2886 
          (match_dup 0)
2887 
          (match_dup 1)
2888 
        ] 2584))]
2889 
  "CGEN_ENABLE_INSN_P (75)"
2890 
  "cpmulua1u.w\\t%0,%1"
2891 
  [(set_attr "may_trap" "no")
2892 
   (set_attr "latency" "0")
2893 
   (set_attr "length" "4")
2894 
   (set_attr "slot" "cop")
2895 
   (set_attr "slots" "p1")
2896 
   (set_attr "stall" "none")])
2897 
 
2898 
 
2899 
(define_insn "cgen_intrinsic_cpmulla1_h_C3"
2900 
  [(set (reg:SI 107)
2901 
        (unspec_volatile:SI [
2902 
          (match_operand:DI 0 "general_operand" "x")
2903 
          (match_operand:DI 1 "general_operand" "x")
2904 
        ] 2586))
2905 
   (set (reg:SI 106)
2906 
        (unspec_volatile:SI [
2907 
          (match_dup 0)
2908 
          (match_dup 1)
2909 
        ] 2588))
2910 
   (set (reg:SI 105)
2911 
        (unspec_volatile:SI [
2912 
          (match_dup 0)
2913 
          (match_dup 1)
2914 
        ] 2590))
2915 
   (set (reg:SI 104)
2916 
        (unspec_volatile:SI [
2917 
          (match_dup 0)
2918 
          (match_dup 1)
2919 
        ] 2592))]
2920 
  "CGEN_ENABLE_INSN_P (76)"
2921 
  "cpmulla1.h\\t%0,%1"
2922 
  [(set_attr "may_trap" "no")
2923 
   (set_attr "latency" "0")
2924 
   (set_attr "length" "4")
2925 
   (set_attr "slot" "cop")
2926 
   (set_attr "slots" "c3")
2927 
   (set_attr "stall" "none")])
2928 
 
2929 
 
2930 
(define_insn "cgen_intrinsic_cpmulla1_h_P1"
2931 
  [(set (reg:SI 107)
2932 
        (unspec_volatile:SI [
2933 
          (match_operand:DI 0 "general_operand" "x")
2934 
          (match_operand:DI 1 "general_operand" "x")
2935 
        ] 2586))
2936 
   (set (reg:SI 106)
2937 
        (unspec_volatile:SI [
2938 
          (match_dup 0)
2939 
          (match_dup 1)
2940 
        ] 2588))
2941 
   (set (reg:SI 105)
2942 
        (unspec_volatile:SI [
2943 
          (match_dup 0)
2944 
          (match_dup 1)
2945 
        ] 2590))
2946 
   (set (reg:SI 104)
2947 
        (unspec_volatile:SI [
2948 
          (match_dup 0)
2949 
          (match_dup 1)
2950 
        ] 2592))]
2951 
  "CGEN_ENABLE_INSN_P (77)"
2952 
  "cpmulla1.h\\t%0,%1"
2953 
  [(set_attr "may_trap" "no")
2954 
   (set_attr "latency" "0")
2955 
   (set_attr "length" "4")
2956 
   (set_attr "slot" "cop")
2957 
   (set_attr "slots" "p1")
2958 
   (set_attr "stall" "none")])
2959 
 
2960 
 
2961 
(define_insn "cgen_intrinsic_cpmulua1_h_C3"
2962 
  [(set (reg:SI 111)
2963 
        (unspec_volatile:SI [
2964 
          (match_operand:DI 0 "general_operand" "x")
2965 
          (match_operand:DI 1 "general_operand" "x")
2966 
        ] 2594))
2967 
   (set (reg:SI 110)
2968 
        (unspec_volatile:SI [
2969 
          (match_dup 0)
2970 
          (match_dup 1)
2971 
        ] 2596))
2972 
   (set (reg:SI 109)
2973 
        (unspec_volatile:SI [
2974 
          (match_dup 0)
2975 
          (match_dup 1)
2976 
        ] 2598))
2977 
   (set (reg:SI 108)
2978 
        (unspec_volatile:SI [
2979 
          (match_dup 0)
2980 
          (match_dup 1)
2981 
        ] 2600))]
2982 
  "CGEN_ENABLE_INSN_P (78)"
2983 
  "cpmulua1.h\\t%0,%1"
2984 
  [(set_attr "may_trap" "no")
2985 
   (set_attr "latency" "0")
2986 
   (set_attr "length" "4")
2987 
   (set_attr "slot" "cop")
2988 
   (set_attr "slots" "c3")
2989 
   (set_attr "stall" "none")])
2990 
 
2991 
 
2992 
(define_insn "cgen_intrinsic_cpmulua1_h_P1"
2993 
  [(set (reg:SI 111)
2994 
        (unspec_volatile:SI [
2995 
          (match_operand:DI 0 "general_operand" "x")
2996 
          (match_operand:DI 1 "general_operand" "x")
2997 
        ] 2594))
2998 
   (set (reg:SI 110)
2999 
        (unspec_volatile:SI [
3000 
          (match_dup 0)
3001 
          (match_dup 1)
3002 
        ] 2596))
3003 
   (set (reg:SI 109)
3004 
        (unspec_volatile:SI [
3005 
          (match_dup 0)
3006 
          (match_dup 1)
3007 
        ] 2598))
3008 
   (set (reg:SI 108)
3009 
        (unspec_volatile:SI [
3010 
          (match_dup 0)
3011 
          (match_dup 1)
3012 
        ] 2600))]
3013 
  "CGEN_ENABLE_INSN_P (79)"
3014 
  "cpmulua1.h\\t%0,%1"
3015 
  [(set_attr "may_trap" "no")
3016 
   (set_attr "latency" "0")
3017 
   (set_attr "length" "4")
3018 
   (set_attr "slot" "cop")
3019 
   (set_attr "slots" "p1")
3020 
   (set_attr "stall" "none")])
3021 
 
3022 
 
3023 
(define_insn "cgen_intrinsic_cpmula1_b_C3"
3024 
  [(set (reg:SI 111)
3025 
        (unspec_volatile:SI [
3026 
          (match_operand:DI 0 "general_operand" "x")
3027 
          (match_operand:DI 1 "general_operand" "x")
3028 
        ] 2602))
3029 
   (set (reg:SI 110)
3030 
        (unspec_volatile:SI [
3031 
          (match_dup 0)
3032 
          (match_dup 1)
3033 
        ] 2604))
3034 
   (set (reg:SI 109)
3035 
        (unspec_volatile:SI [
3036 
          (match_dup 0)
3037 
          (match_dup 1)
3038 
        ] 2606))
3039 
   (set (reg:SI 108)
3040 
        (unspec_volatile:SI [
3041 
          (match_dup 0)
3042 
          (match_dup 1)
3043 
        ] 2608))
3044 
   (set (reg:SI 107)
3045 
        (unspec_volatile:SI [
3046 
          (match_dup 0)
3047 
          (match_dup 1)
3048 
        ] 2610))
3049 
   (set (reg:SI 106)
3050 
        (unspec_volatile:SI [
3051 
          (match_dup 0)
3052 
          (match_dup 1)
3053 
        ] 2612))
3054 
   (set (reg:SI 105)
3055 
        (unspec_volatile:SI [
3056 
          (match_dup 0)
3057 
          (match_dup 1)
3058 
        ] 2614))
3059 
   (set (reg:SI 104)
3060 
        (unspec_volatile:SI [
3061 
          (match_dup 0)
3062 
          (match_dup 1)
3063 
        ] 2616))]
3064 
  "CGEN_ENABLE_INSN_P (80)"
3065 
  "cpmula1.b\\t%0,%1"
3066 
  [(set_attr "may_trap" "no")
3067 
   (set_attr "latency" "0")
3068 
   (set_attr "length" "4")
3069 
   (set_attr "slot" "cop")
3070 
   (set_attr "slots" "c3")
3071 
   (set_attr "stall" "none")])
3072 
 
3073 
 
3074 
(define_insn "cgen_intrinsic_cpmula1_b_P1"
3075 
  [(set (reg:SI 111)
3076 
        (unspec_volatile:SI [
3077 
          (match_operand:DI 0 "general_operand" "x")
3078 
          (match_operand:DI 1 "general_operand" "x")
3079 
        ] 2602))
3080 
   (set (reg:SI 110)
3081 
        (unspec_volatile:SI [
3082 
          (match_dup 0)
3083 
          (match_dup 1)
3084 
        ] 2604))
3085 
   (set (reg:SI 109)
3086 
        (unspec_volatile:SI [
3087 
          (match_dup 0)
3088 
          (match_dup 1)
3089 
        ] 2606))
3090 
   (set (reg:SI 108)
3091 
        (unspec_volatile:SI [
3092 
          (match_dup 0)
3093 
          (match_dup 1)
3094 
        ] 2608))
3095 
   (set (reg:SI 107)
3096 
        (unspec_volatile:SI [
3097 
          (match_dup 0)
3098 
          (match_dup 1)
3099 
        ] 2610))
3100 
   (set (reg:SI 106)
3101 
        (unspec_volatile:SI [
3102 
          (match_dup 0)
3103 
          (match_dup 1)
3104 
        ] 2612))
3105 
   (set (reg:SI 105)
3106 
        (unspec_volatile:SI [
3107 
          (match_dup 0)
3108 
          (match_dup 1)
3109 
        ] 2614))
3110 
   (set (reg:SI 104)
3111 
        (unspec_volatile:SI [
3112 
          (match_dup 0)
3113 
          (match_dup 1)
3114 
        ] 2616))]
3115 
  "CGEN_ENABLE_INSN_P (81)"
3116 
  "cpmula1.b\\t%0,%1"
3117 
  [(set_attr "may_trap" "no")
3118 
   (set_attr "latency" "0")
3119 
   (set_attr "length" "4")
3120 
   (set_attr "slot" "cop")
3121 
   (set_attr "slots" "p1")
3122 
   (set_attr "stall" "none")])
3123 
 
3124 
 
3125 
(define_insn "cgen_intrinsic_cpmula1u_b_C3"
3126 
  [(set (reg:SI 111)
3127 
        (unspec_volatile:SI [
3128 
          (match_operand:DI 0 "general_operand" "x")
3129 
          (match_operand:DI 1 "general_operand" "x")
3130 
        ] 2618))
3131 
   (set (reg:SI 110)
3132 
        (unspec_volatile:SI [
3133 
          (match_dup 0)
3134 
          (match_dup 1)
3135 
        ] 2620))
3136 
   (set (reg:SI 109)
3137 
        (unspec_volatile:SI [
3138 
          (match_dup 0)
3139 
          (match_dup 1)
3140 
        ] 2622))
3141 
   (set (reg:SI 108)
3142 
        (unspec_volatile:SI [
3143 
          (match_dup 0)
3144 
          (match_dup 1)
3145 
        ] 2624))
3146 
   (set (reg:SI 107)
3147 
        (unspec_volatile:SI [
3148 
          (match_dup 0)
3149 
          (match_dup 1)
3150 
        ] 2626))
3151 
   (set (reg:SI 106)
3152 
        (unspec_volatile:SI [
3153 
          (match_dup 0)
3154 
          (match_dup 1)
3155 
        ] 2628))
3156 
   (set (reg:SI 105)
3157 
        (unspec_volatile:SI [
3158 
          (match_dup 0)
3159 
          (match_dup 1)
3160 
        ] 2630))
3161 
   (set (reg:SI 104)
3162 
        (unspec_volatile:SI [
3163 
          (match_dup 0)
3164 
          (match_dup 1)
3165 
        ] 2632))]
3166 
  "CGEN_ENABLE_INSN_P (82)"
3167 
  "cpmula1u.b\\t%0,%1"
3168 
  [(set_attr "may_trap" "no")
3169 
   (set_attr "latency" "0")
3170 
   (set_attr "length" "4")
3171 
   (set_attr "slot" "cop")
3172 
   (set_attr "slots" "c3")
3173 
   (set_attr "stall" "none")])
3174 
 
3175 
 
3176 
(define_insn "cgen_intrinsic_cpmula1u_b_P1"
3177 
  [(set (reg:SI 111)
3178 
        (unspec_volatile:SI [
3179 
          (match_operand:DI 0 "general_operand" "x")
3180 
          (match_operand:DI 1 "general_operand" "x")
3181 
        ] 2618))
3182 
   (set (reg:SI 110)
3183 
        (unspec_volatile:SI [
3184 
          (match_dup 0)
3185 
          (match_dup 1)
3186 
        ] 2620))
3187 
   (set (reg:SI 109)
3188 
        (unspec_volatile:SI [
3189 
          (match_dup 0)
3190 
          (match_dup 1)
3191 
        ] 2622))
3192 
   (set (reg:SI 108)
3193 
        (unspec_volatile:SI [
3194 
          (match_dup 0)
3195 
          (match_dup 1)
3196 
        ] 2624))
3197 
   (set (reg:SI 107)
3198 
        (unspec_volatile:SI [
3199 
          (match_dup 0)
3200 
          (match_dup 1)
3201 
        ] 2626))
3202 
   (set (reg:SI 106)
3203 
        (unspec_volatile:SI [
3204 
          (match_dup 0)
3205 
          (match_dup 1)
3206 
        ] 2628))
3207 
   (set (reg:SI 105)
3208 
        (unspec_volatile:SI [
3209 
          (match_dup 0)
3210 
          (match_dup 1)
3211 
        ] 2630))
3212 
   (set (reg:SI 104)
3213 
        (unspec_volatile:SI [
3214 
          (match_dup 0)
3215 
          (match_dup 1)
3216 
        ] 2632))]
3217 
  "CGEN_ENABLE_INSN_P (83)"
3218 
  "cpmula1u.b\\t%0,%1"
3219 
  [(set_attr "may_trap" "no")
3220 
   (set_attr "latency" "0")
3221 
   (set_attr "length" "4")
3222 
   (set_attr "slot" "cop")
3223 
   (set_attr "slots" "p1")
3224 
   (set_attr "stall" "none")])
3225 
 
3226 
 
3227 
(define_insn "cgen_intrinsic_cpssda1_b_C3"
3228 
  [(set (reg:SI 87)
3229 
        (unspec_volatile:SI [
3230 
          (match_operand:DI 0 "general_operand" "x")
3231 
          (match_operand:DI 1 "general_operand" "x")
3232 
        ] 2634))
3233 
   (set (reg:SI 111)
3234 
        (unspec_volatile:SI [
3235 
          (match_dup 0)
3236 
          (match_dup 1)
3237 
        ] 2636))
3238 
   (set (reg:SI 110)
3239 
        (unspec_volatile:SI [
3240 
          (match_dup 0)
3241 
          (match_dup 1)
3242 
        ] 2638))
3243 
   (set (reg:SI 109)
3244 
        (unspec_volatile:SI [
3245 
          (match_dup 0)
3246 
          (match_dup 1)
3247 
        ] 2640))
3248 
   (set (reg:SI 108)
3249 
        (unspec_volatile:SI [
3250 
          (match_dup 0)
3251 
          (match_dup 1)
3252 
        ] 2642))
3253 
   (set (reg:SI 107)
3254 
        (unspec_volatile:SI [
3255 
          (match_dup 0)
3256 
          (match_dup 1)
3257 
        ] 2644))
3258 
   (set (reg:SI 106)
3259 
        (unspec_volatile:SI [
3260 
          (match_dup 0)
3261 
          (match_dup 1)
3262 
        ] 2646))
3263 
   (set (reg:SI 105)
3264 
        (unspec_volatile:SI [
3265 
          (match_dup 0)
3266 
          (match_dup 1)
3267 
        ] 2648))
3268 
   (set (reg:SI 104)
3269 
        (unspec_volatile:SI [
3270 
          (match_dup 0)
3271 
          (match_dup 1)
3272 
        ] 2650))]
3273 
  "CGEN_ENABLE_INSN_P (84)"
3274 
  "cpssda1.b\\t%0,%1"
3275 
  [(set_attr "may_trap" "no")
3276 
   (set_attr "latency" "0")
3277 
   (set_attr "length" "4")
3278 
   (set_attr "slot" "cop")
3279 
   (set_attr "slots" "c3")
3280 
   (set_attr "stall" "none")])
3281 
 
3282 
 
3283 
(define_insn "cgen_intrinsic_cpssda1_b_P1"
3284 
  [(set (reg:SI 111)
3285 
        (unspec_volatile:SI [
3286 
          (match_operand:DI 0 "general_operand" "x")
3287 
          (match_operand:DI 1 "general_operand" "x")
3288 
        ] 2634))
3289 
   (set (reg:SI 110)
3290 
        (unspec_volatile:SI [
3291 
          (match_dup 0)
3292 
          (match_dup 1)
3293 
        ] 2636))
3294 
   (set (reg:SI 109)
3295 
        (unspec_volatile:SI [
3296 
          (match_dup 0)
3297 
          (match_dup 1)
3298 
        ] 2638))
3299 
   (set (reg:SI 108)
3300 
        (unspec_volatile:SI [
3301 
          (match_dup 0)
3302 
          (match_dup 1)
3303 
        ] 2640))
3304 
   (set (reg:SI 107)
3305 
        (unspec_volatile:SI [
3306 
          (match_dup 0)
3307 
          (match_dup 1)
3308 
        ] 2642))
3309 
   (set (reg:SI 106)
3310 
        (unspec_volatile:SI [
3311 
          (match_dup 0)
3312 
          (match_dup 1)
3313 
        ] 2644))
3314 
   (set (reg:SI 105)
3315 
        (unspec_volatile:SI [
3316 
          (match_dup 0)
3317 
          (match_dup 1)
3318 
        ] 2646))
3319 
   (set (reg:SI 104)
3320 
        (unspec_volatile:SI [
3321 
          (match_dup 0)
3322 
          (match_dup 1)
3323 
        ] 2648))]
3324 
  "CGEN_ENABLE_INSN_P (85)"
3325 
  "cpssda1.b\\t%0,%1"
3326 
  [(set_attr "may_trap" "no")
3327 
   (set_attr "latency" "0")
3328 
   (set_attr "length" "4")
3329 
   (set_attr "slot" "cop")
3330 
   (set_attr "slots" "p1")
3331 
   (set_attr "stall" "none")])
3332 
 
3333 
 
3334 
(define_insn "cgen_intrinsic_cpssda1u_b_C3"
3335 
  [(set (reg:SI 87)
3336 
        (unspec_volatile:SI [
3337 
          (match_operand:DI 0 "general_operand" "x")
3338 
          (match_operand:DI 1 "general_operand" "x")
3339 
        ] 2650))
3340 
   (set (reg:SI 111)
3341 
        (unspec_volatile:SI [
3342 
          (match_dup 0)
3343 
          (match_dup 1)
3344 
        ] 2652))
3345 
   (set (reg:SI 110)
3346 
        (unspec_volatile:SI [
3347 
          (match_dup 0)
3348 
          (match_dup 1)
3349 
        ] 2654))
3350 
   (set (reg:SI 109)
3351 
        (unspec_volatile:SI [
3352 
          (match_dup 0)
3353 
          (match_dup 1)
3354 
        ] 2656))
3355 
   (set (reg:SI 108)
3356 
        (unspec_volatile:SI [
3357 
          (match_dup 0)
3358 
          (match_dup 1)
3359 
        ] 2658))
3360 
   (set (reg:SI 107)
3361 
        (unspec_volatile:SI [
3362 
          (match_dup 0)
3363 
          (match_dup 1)
3364 
        ] 2660))
3365 
   (set (reg:SI 106)
3366 
        (unspec_volatile:SI [
3367 
          (match_dup 0)
3368 
          (match_dup 1)
3369 
        ] 2662))
3370 
   (set (reg:SI 105)
3371 
        (unspec_volatile:SI [
3372 
          (match_dup 0)
3373 
          (match_dup 1)
3374 
        ] 2664))
3375 
   (set (reg:SI 104)
3376 
        (unspec_volatile:SI [
3377 
          (match_dup 0)
3378 
          (match_dup 1)
3379 
        ] 2666))]
3380 
  "CGEN_ENABLE_INSN_P (86)"
3381 
  "cpssda1u.b\\t%0,%1"
3382 
  [(set_attr "may_trap" "no")
3383 
   (set_attr "latency" "0")
3384 
   (set_attr "length" "4")
3385 
   (set_attr "slot" "cop")
3386 
   (set_attr "slots" "c3")
3387 
   (set_attr "stall" "none")])
3388 
 
3389 
 
3390 
(define_insn "cgen_intrinsic_cpssda1u_b_P1"
3391 
  [(set (reg:SI 111)
3392 
        (unspec_volatile:SI [
3393 
          (match_operand:DI 0 "general_operand" "x")
3394 
          (match_operand:DI 1 "general_operand" "x")
3395 
        ] 2650))
3396 
   (set (reg:SI 110)
3397 
        (unspec_volatile:SI [
3398 
          (match_dup 0)
3399 
          (match_dup 1)
3400 
        ] 2652))
3401 
   (set (reg:SI 109)
3402 
        (unspec_volatile:SI [
3403 
          (match_dup 0)
3404 
          (match_dup 1)
3405 
        ] 2654))
3406 
   (set (reg:SI 108)
3407 
        (unspec_volatile:SI [
3408 
          (match_dup 0)
3409 
          (match_dup 1)
3410 
        ] 2656))
3411 
   (set (reg:SI 107)
3412 
        (unspec_volatile:SI [
3413 
          (match_dup 0)
3414 
          (match_dup 1)
3415 
        ] 2658))
3416 
   (set (reg:SI 106)
3417 
        (unspec_volatile:SI [
3418 
          (match_dup 0)
3419 
          (match_dup 1)
3420 
        ] 2660))
3421 
   (set (reg:SI 105)
3422 
        (unspec_volatile:SI [
3423 
          (match_dup 0)
3424 
          (match_dup 1)
3425 
        ] 2662))
3426 
   (set (reg:SI 104)
3427 
        (unspec_volatile:SI [
3428 
          (match_dup 0)
3429 
          (match_dup 1)
3430 
        ] 2664))]
3431 
  "CGEN_ENABLE_INSN_P (87)"
3432 
  "cpssda1u.b\\t%0,%1"
3433 
  [(set_attr "may_trap" "no")
3434 
   (set_attr "latency" "0")
3435 
   (set_attr "length" "4")
3436 
   (set_attr "slot" "cop")
3437 
   (set_attr "slots" "p1")
3438 
   (set_attr "stall" "none")])
3439 
 
3440 
 
3441 
(define_insn "cgen_intrinsic_cpssqa1_b_C3"
3442 
  [(set (reg:SI 111)
3443 
        (unspec_volatile:SI [
3444 
          (match_operand:DI 0 "general_operand" "x")
3445 
          (match_operand:DI 1 "general_operand" "x")
3446 
        ] 2666))
3447 
   (set (reg:SI 110)
3448 
        (unspec_volatile:SI [
3449 
          (match_dup 0)
3450 
          (match_dup 1)
3451 
        ] 2668))
3452 
   (set (reg:SI 109)
3453 
        (unspec_volatile:SI [
3454 
          (match_dup 0)
3455 
          (match_dup 1)
3456 
        ] 2670))
3457 
   (set (reg:SI 108)
3458 
        (unspec_volatile:SI [
3459 
          (match_dup 0)
3460 
          (match_dup 1)
3461 
        ] 2672))
3462 
   (set (reg:SI 107)
3463 
        (unspec_volatile:SI [
3464 
          (match_dup 0)
3465 
          (match_dup 1)
3466 
        ] 2674))
3467 
   (set (reg:SI 106)
3468 
        (unspec_volatile:SI [
3469 
          (match_dup 0)
3470 
          (match_dup 1)
3471 
        ] 2676))
3472 
   (set (reg:SI 105)
3473 
        (unspec_volatile:SI [
3474 
          (match_dup 0)
3475 
          (match_dup 1)
3476 
        ] 2678))
3477 
   (set (reg:SI 104)
3478 
        (unspec_volatile:SI [
3479 
          (match_dup 0)
3480 
          (match_dup 1)
3481 
        ] 2680))]
3482 
  "CGEN_ENABLE_INSN_P (88)"
3483 
  "cpssqa1.b\\t%0,%1"
3484 
  [(set_attr "may_trap" "no")
3485 
   (set_attr "latency" "0")
3486 
   (set_attr "length" "4")
3487 
   (set_attr "slot" "cop")
3488 
   (set_attr "slots" "c3")
3489 
   (set_attr "stall" "none")])
3490 
 
3491 
 
3492 
(define_insn "cgen_intrinsic_cpssqa1_b_P1"
3493 
  [(set (reg:SI 111)
3494 
        (unspec_volatile:SI [
3495 
          (match_operand:DI 0 "general_operand" "x")
3496 
          (match_operand:DI 1 "general_operand" "x")
3497 
        ] 2666))
3498 
   (set (reg:SI 110)
3499 
        (unspec_volatile:SI [
3500 
          (match_dup 0)
3501 
          (match_dup 1)
3502 
        ] 2668))
3503 
   (set (reg:SI 109)
3504 
        (unspec_volatile:SI [
3505 
          (match_dup 0)
3506 
          (match_dup 1)
3507 
        ] 2670))
3508 
   (set (reg:SI 108)
3509 
        (unspec_volatile:SI [
3510 
          (match_dup 0)
3511 
          (match_dup 1)
3512 
        ] 2672))
3513 
   (set (reg:SI 107)
3514 
        (unspec_volatile:SI [
3515 
          (match_dup 0)
3516 
          (match_dup 1)
3517 
        ] 2674))
3518 
   (set (reg:SI 106)
3519 
        (unspec_volatile:SI [
3520 
          (match_dup 0)
3521 
          (match_dup 1)
3522 
        ] 2676))
3523 
   (set (reg:SI 105)
3524 
        (unspec_volatile:SI [
3525 
          (match_dup 0)
3526 
          (match_dup 1)
3527 
        ] 2678))
3528 
   (set (reg:SI 104)
3529 
        (unspec_volatile:SI [
3530 
          (match_dup 0)
3531 
          (match_dup 1)
3532 
        ] 2680))]
3533 
  "CGEN_ENABLE_INSN_P (89)"
3534 
  "cpssqa1.b\\t%0,%1"
3535 
  [(set_attr "may_trap" "no")
3536 
   (set_attr "latency" "0")
3537 
   (set_attr "length" "4")
3538 
   (set_attr "slot" "cop")
3539 
   (set_attr "slots" "p1")
3540 
   (set_attr "stall" "none")])
3541 
 
3542 
 
3543 
(define_insn "cgen_intrinsic_cpssqa1u_b_C3"
3544 
  [(set (reg:SI 111)
3545 
        (unspec_volatile:SI [
3546 
          (match_operand:DI 0 "general_operand" "x")
3547 
          (match_operand:DI 1 "general_operand" "x")
3548 
        ] 2682))
3549 
   (set (reg:SI 110)
3550 
        (unspec_volatile:SI [
3551 
          (match_dup 0)
3552 
          (match_dup 1)
3553 
        ] 2684))
3554 
   (set (reg:SI 109)
3555 
        (unspec_volatile:SI [
3556 
          (match_dup 0)
3557 
          (match_dup 1)
3558 
        ] 2686))
3559 
   (set (reg:SI 108)
3560 
        (unspec_volatile:SI [
3561 
          (match_dup 0)
3562 
          (match_dup 1)
3563 
        ] 2688))
3564 
   (set (reg:SI 107)
3565 
        (unspec_volatile:SI [
3566 
          (match_dup 0)
3567 
          (match_dup 1)
3568 
        ] 2690))
3569 
   (set (reg:SI 106)
3570 
        (unspec_volatile:SI [
3571 
          (match_dup 0)
3572 
          (match_dup 1)
3573 
        ] 2692))
3574 
   (set (reg:SI 105)
3575 
        (unspec_volatile:SI [
3576 
          (match_dup 0)
3577 
          (match_dup 1)
3578 
        ] 2694))
3579 
   (set (reg:SI 104)
3580 
        (unspec_volatile:SI [
3581 
          (match_dup 0)
3582 
          (match_dup 1)
3583 
        ] 2696))]
3584 
  "CGEN_ENABLE_INSN_P (90)"
3585 
  "cpssqa1u.b\\t%0,%1"
3586 
  [(set_attr "may_trap" "no")
3587 
   (set_attr "latency" "0")
3588 
   (set_attr "length" "4")
3589 
   (set_attr "slot" "cop")
3590 
   (set_attr "slots" "c3")
3591 
   (set_attr "stall" "none")])
3592 
 
3593 
 
3594 
(define_insn "cgen_intrinsic_cpssqa1u_b_P1"
3595 
  [(set (reg:SI 111)
3596 
        (unspec_volatile:SI [
3597 
          (match_operand:DI 0 "general_operand" "x")
3598 
          (match_operand:DI 1 "general_operand" "x")
3599 
        ] 2682))
3600 
   (set (reg:SI 110)
3601 
        (unspec_volatile:SI [
3602 
          (match_dup 0)
3603 
          (match_dup 1)
3604 
        ] 2684))
3605 
   (set (reg:SI 109)
3606 
        (unspec_volatile:SI [
3607 
          (match_dup 0)
3608 
          (match_dup 1)
3609 
        ] 2686))
3610 
   (set (reg:SI 108)
3611 
        (unspec_volatile:SI [
3612 
          (match_dup 0)
3613 
          (match_dup 1)
3614 
        ] 2688))
3615 
   (set (reg:SI 107)
3616 
        (unspec_volatile:SI [
3617 
          (match_dup 0)
3618 
          (match_dup 1)
3619 
        ] 2690))
3620 
   (set (reg:SI 106)
3621 
        (unspec_volatile:SI [
3622 
          (match_dup 0)
3623 
          (match_dup 1)
3624 
        ] 2692))
3625 
   (set (reg:SI 105)
3626 
        (unspec_volatile:SI [
3627 
          (match_dup 0)
3628 
          (match_dup 1)
3629 
        ] 2694))
3630 
   (set (reg:SI 104)
3631 
        (unspec_volatile:SI [
3632 
          (match_dup 0)
3633 
          (match_dup 1)
3634 
        ] 2696))]
3635 
  "CGEN_ENABLE_INSN_P (91)"
3636 
  "cpssqa1u.b\\t%0,%1"
3637 
  [(set_attr "may_trap" "no")
3638 
   (set_attr "latency" "0")
3639 
   (set_attr "length" "4")
3640 
   (set_attr "slot" "cop")
3641 
   (set_attr "slots" "p1")
3642 
   (set_attr "stall" "none")])
3643 
 
3644 
 
3645 
(define_insn "cgen_intrinsic_cpfmadila1_h_P1"
3646 
  [(set (reg:SI 87)
3647 
        (unspec_volatile:SI [
3648 
          (match_operand:DI 0 "general_operand" "x")
3649 
          (match_operand:DI 1 "general_operand" "x")
3650 
          (match_operand:SI 2 "cgen_h_uint_3a1_immediate" "")
3651 
          (match_operand:SI 3 "cgen_h_sint_8a1_immediate" "")
3652 
        ] 1000))
3653 
   (set (reg:SI 107)
3654 
        (unspec_volatile:SI [
3655 
          (match_dup 0)
3656 
          (match_dup 1)
3657 
          (match_dup 2)
3658 
          (match_dup 3)
3659 
        ] 1002))
3660 
   (set (reg:SI 106)
3661 
        (unspec_volatile:SI [
3662 
          (match_dup 0)
3663 
          (match_dup 1)
3664 
          (match_dup 2)
3665 
          (match_dup 3)
3666 
        ] 1004))
3667 
   (set (reg:SI 105)
3668 
        (unspec_volatile:SI [
3669 
          (match_dup 0)
3670 
          (match_dup 1)
3671 
          (match_dup 2)
3672 
          (match_dup 3)
3673 
        ] 1006))
3674 
   (set (reg:SI 104)
3675 
        (unspec_volatile:SI [
3676 
          (match_dup 0)
3677 
          (match_dup 1)
3678 
          (match_dup 2)
3679 
          (match_dup 3)
3680 
        ] 1008))]
3681 
  "CGEN_ENABLE_INSN_P (92)"
3682 
  "cpfmadila1.h\\t%0,%1,%2,%3"
3683 
  [(set_attr "may_trap" "no")
3684 
   (set_attr "latency" "0")
3685 
   (set_attr "length" "4")
3686 
   (set_attr "slot" "cop")
3687 
   (set_attr "slots" "p1")
3688 
   (set_attr "stall" "none")])
3689 
 
3690 
 
3691 
(define_insn "cgen_intrinsic_cpfmadiua1_h_P1"
3692 
  [(set (reg:SI 87)
3693 
        (unspec_volatile:SI [
3694 
          (match_operand:DI 0 "general_operand" "x")
3695 
          (match_operand:DI 1 "general_operand" "x")
3696 
          (match_operand:SI 2 "cgen_h_uint_3a1_immediate" "")
3697 
          (match_operand:SI 3 "cgen_h_sint_8a1_immediate" "")
3698 
        ] 1010))
3699 
   (set (reg:SI 111)
3700 
        (unspec_volatile:SI [
3701 
          (match_dup 0)
3702 
          (match_dup 1)
3703 
          (match_dup 2)
3704 
          (match_dup 3)
3705 
        ] 1012))
3706 
   (set (reg:SI 110)
3707 
        (unspec_volatile:SI [
3708 
          (match_dup 0)
3709 
          (match_dup 1)
3710 
          (match_dup 2)
3711 
          (match_dup 3)
3712 
        ] 1014))
3713 
   (set (reg:SI 109)
3714 
        (unspec_volatile:SI [
3715 
          (match_dup 0)
3716 
          (match_dup 1)
3717 
          (match_dup 2)
3718 
          (match_dup 3)
3719 
        ] 1016))
3720 
   (set (reg:SI 108)
3721 
        (unspec_volatile:SI [
3722 
          (match_dup 0)
3723 
          (match_dup 1)
3724 
          (match_dup 2)
3725 
          (match_dup 3)
3726 
        ] 1018))]
3727 
  "CGEN_ENABLE_INSN_P (93)"
3728 
  "cpfmadiua1.h\\t%0,%1,%2,%3"
3729 
  [(set_attr "may_trap" "no")
3730 
   (set_attr "latency" "0")
3731 
   (set_attr "length" "4")
3732 
   (set_attr "slot" "cop")
3733 
   (set_attr "slots" "p1")
3734 
   (set_attr "stall" "none")])
3735 
 
3736 
 
3737 
(define_insn "cgen_intrinsic_cpfmadia1_b_P1"
3738 
  [(set (reg:SI 87)
3739 
        (unspec_volatile:SI [
3740 
          (match_operand:DI 0 "general_operand" "x")
3741 
          (match_operand:DI 1 "general_operand" "x")
3742 
          (match_operand:SI 2 "cgen_h_uint_3a1_immediate" "")
3743 
          (match_operand:SI 3 "cgen_h_sint_8a1_immediate" "")
3744 
        ] 1020))
3745 
   (set (reg:SI 111)
3746 
        (unspec_volatile:SI [
3747 
          (match_dup 0)
3748 
          (match_dup 1)
3749 
          (match_dup 2)
3750 
          (match_dup 3)
3751 
        ] 1022))
3752 
   (set (reg:SI 110)
3753 
        (unspec_volatile:SI [
3754 
          (match_dup 0)
3755 
          (match_dup 1)
3756 
          (match_dup 2)
3757 
          (match_dup 3)
3758 
        ] 1024))
3759 
   (set (reg:SI 109)
3760 
        (unspec_volatile:SI [
3761 
          (match_dup 0)
3762 
          (match_dup 1)
3763 
          (match_dup 2)
3764 
          (match_dup 3)
3765 
        ] 1026))
3766 
   (set (reg:SI 108)
3767 
        (unspec_volatile:SI [
3768 
          (match_dup 0)
3769 
          (match_dup 1)
3770 
          (match_dup 2)
3771 
          (match_dup 3)
3772 
        ] 1028))
3773 
   (set (reg:SI 107)
3774 
        (unspec_volatile:SI [
3775 
          (match_dup 0)
3776 
          (match_dup 1)
3777 
          (match_dup 2)
3778 
          (match_dup 3)
3779 
        ] 1030))
3780 
   (set (reg:SI 106)
3781 
        (unspec_volatile:SI [
3782 
          (match_dup 0)
3783 
          (match_dup 1)
3784 
          (match_dup 2)
3785 
          (match_dup 3)
3786 
        ] 1032))
3787 
   (set (reg:SI 105)
3788 
        (unspec_volatile:SI [
3789 
          (match_dup 0)
3790 
          (match_dup 1)
3791 
          (match_dup 2)
3792 
          (match_dup 3)
3793 
        ] 1034))
3794 
   (set (reg:SI 104)
3795 
        (unspec_volatile:SI [
3796 
          (match_dup 0)
3797 
          (match_dup 1)
3798 
          (match_dup 2)
3799 
          (match_dup 3)
3800 
        ] 1036))]
3801 
  "CGEN_ENABLE_INSN_P (94)"
3802 
  "cpfmadia1.b\\t%0,%1,%2,%3"
3803 
  [(set_attr "may_trap" "no")
3804 
   (set_attr "latency" "0")
3805 
   (set_attr "length" "4")
3806 
   (set_attr "slot" "cop")
3807 
   (set_attr "slots" "p1")
3808 
   (set_attr "stall" "none")])
3809 
 
3810 
 
3811 
(define_insn "cgen_intrinsic_cpfmadia1u_b_P1"
3812 
  [(set (reg:SI 87)
3813 
        (unspec_volatile:SI [
3814 
          (match_operand:DI 0 "general_operand" "x")
3815 
          (match_operand:DI 1 "general_operand" "x")
3816 
          (match_operand:SI 2 "cgen_h_uint_3a1_immediate" "")
3817 
          (match_operand:SI 3 "cgen_h_sint_8a1_immediate" "")
3818 
        ] 1038))
3819 
   (set (reg:SI 111)
3820 
        (unspec_volatile:SI [
3821 
          (match_dup 0)
3822 
          (match_dup 1)
3823 
          (match_dup 2)
3824 
          (match_dup 3)
3825 
        ] 1040))
3826 
   (set (reg:SI 110)
3827 
        (unspec_volatile:SI [
3828 
          (match_dup 0)
3829 
          (match_dup 1)
3830 
          (match_dup 2)
3831 
          (match_dup 3)
3832 
        ] 1042))
3833 
   (set (reg:SI 109)
3834 
        (unspec_volatile:SI [
3835 
          (match_dup 0)
3836 
          (match_dup 1)
3837 
          (match_dup 2)
3838 
          (match_dup 3)
3839 
        ] 1044))
3840 
   (set (reg:SI 108)
3841 
        (unspec_volatile:SI [
3842 
          (match_dup 0)
3843 
          (match_dup 1)
3844 
          (match_dup 2)
3845 
          (match_dup 3)
3846 
        ] 1046))
3847 
   (set (reg:SI 107)
3848 
        (unspec_volatile:SI [
3849 
          (match_dup 0)
3850 
          (match_dup 1)
3851 
          (match_dup 2)
3852 
          (match_dup 3)
3853 
        ] 1048))
3854 
   (set (reg:SI 106)
3855 
        (unspec_volatile:SI [
3856 
          (match_dup 0)
3857 
          (match_dup 1)
3858 
          (match_dup 2)
3859 
          (match_dup 3)
3860 
        ] 1050))
3861 
   (set (reg:SI 105)
3862 
        (unspec_volatile:SI [
3863 
          (match_dup 0)
3864 
          (match_dup 1)
3865 
          (match_dup 2)
3866 
          (match_dup 3)
3867 
        ] 1052))
3868 
   (set (reg:SI 104)
3869 
        (unspec_volatile:SI [
3870 
          (match_dup 0)
3871 
          (match_dup 1)
3872 
          (match_dup 2)
3873 
          (match_dup 3)
3874 
        ] 1054))]
3875 
  "CGEN_ENABLE_INSN_P (95)"
3876 
  "cpfmadia1u.b\\t%0,%1,%2,%3"
3877 
  [(set_attr "may_trap" "no")
3878 
   (set_attr "latency" "0")
3879 
   (set_attr "length" "4")
3880 
   (set_attr "slot" "cop")
3881 
   (set_attr "slots" "p1")
3882 
   (set_attr "stall" "none")])
3883 
 
3884 
 
3885 
(define_insn "cgen_intrinsic_cpfmulila1_h_P1"
3886 
  [(set (reg:SI 107)
3887 
        (unspec_volatile:SI [
3888 
          (match_operand:DI 0 "general_operand" "x")
3889 
          (match_operand:DI 1 "general_operand" "x")
3890 
          (match_operand:SI 2 "cgen_h_uint_3a1_immediate" "")
3891 
          (match_operand:SI 3 "cgen_h_sint_8a1_immediate" "")
3892 
        ] 1056))
3893 
   (set (reg:SI 106)
3894 
        (unspec_volatile:SI [
3895 
          (match_dup 0)
3896 
          (match_dup 1)
3897 
          (match_dup 2)
3898 
          (match_dup 3)
3899 
        ] 1058))
3900 
   (set (reg:SI 105)
3901 
        (unspec_volatile:SI [
3902 
          (match_dup 0)
3903 
          (match_dup 1)
3904 
          (match_dup 2)
3905 
          (match_dup 3)
3906 
        ] 1060))
3907 
   (set (reg:SI 104)
3908 
        (unspec_volatile:SI [
3909 
          (match_dup 0)
3910 
          (match_dup 1)
3911 
          (match_dup 2)
3912 
          (match_dup 3)
3913 
        ] 1062))]
3914 
  "CGEN_ENABLE_INSN_P (96)"
3915 
  "cpfmulila1.h\\t%0,%1,%2,%3"
3916 
  [(set_attr "may_trap" "no")
3917 
   (set_attr "latency" "0")
3918 
   (set_attr "length" "4")
3919 
   (set_attr "slot" "cop")
3920 
   (set_attr "slots" "p1")
3921 
   (set_attr "stall" "none")])
3922 
 
3923 
 
3924 
(define_insn "cgen_intrinsic_cpfmuliua1_h_P1"
3925 
  [(set (reg:SI 111)
3926 
        (unspec_volatile:SI [
3927 
          (match_operand:DI 0 "general_operand" "x")
3928 
          (match_operand:DI 1 "general_operand" "x")
3929 
          (match_operand:SI 2 "cgen_h_uint_3a1_immediate" "")
3930 
          (match_operand:SI 3 "cgen_h_sint_8a1_immediate" "")
3931 
        ] 1064))
3932 
   (set (reg:SI 110)
3933 
        (unspec_volatile:SI [
3934 
          (match_dup 0)
3935 
          (match_dup 1)
3936 
          (match_dup 2)
3937 
          (match_dup 3)
3938 
        ] 1066))
3939 
   (set (reg:SI 109)
3940 
        (unspec_volatile:SI [
3941 
          (match_dup 0)
3942 
          (match_dup 1)
3943 
          (match_dup 2)
3944 
          (match_dup 3)
3945 
        ] 1068))
3946 
   (set (reg:SI 108)
3947 
        (unspec_volatile:SI [
3948 
          (match_dup 0)
3949 
          (match_dup 1)
3950 
          (match_dup 2)
3951 
          (match_dup 3)
3952 
        ] 1070))]
3953 
  "CGEN_ENABLE_INSN_P (97)"
3954 
  "cpfmuliua1.h\\t%0,%1,%2,%3"
3955 
  [(set_attr "may_trap" "no")
3956 
   (set_attr "latency" "0")
3957 
   (set_attr "length" "4")
3958 
   (set_attr "slot" "cop")
3959 
   (set_attr "slots" "p1")
3960 
   (set_attr "stall" "none")])
3961 
 
3962 
 
3963 
(define_insn "cgen_intrinsic_cpfmulia1_b_P1"
3964 
  [(set (reg:SI 111)
3965 
        (unspec_volatile:SI [
3966 
          (match_operand:DI 0 "general_operand" "x")
3967 
          (match_operand:DI 1 "general_operand" "x")
3968 
          (match_operand:SI 2 "cgen_h_uint_3a1_immediate" "")
3969 
          (match_operand:SI 3 "cgen_h_sint_8a1_immediate" "")
3970 
        ] 1072))
3971 
   (set (reg:SI 110)
3972 
        (unspec_volatile:SI [
3973 
          (match_dup 0)
3974 
          (match_dup 1)
3975 
          (match_dup 2)
3976 
          (match_dup 3)
3977 
        ] 1074))
3978 
   (set (reg:SI 109)
3979 
        (unspec_volatile:SI [
3980 
          (match_dup 0)
3981 
          (match_dup 1)
3982 
          (match_dup 2)
3983 
          (match_dup 3)
3984 
        ] 1076))
3985 
   (set (reg:SI 108)
3986 
        (unspec_volatile:SI [
3987 
          (match_dup 0)
3988 
          (match_dup 1)
3989 
          (match_dup 2)
3990 
          (match_dup 3)
3991 
        ] 1078))
3992 
   (set (reg:SI 107)
3993 
        (unspec_volatile:SI [
3994 
          (match_dup 0)
3995 
          (match_dup 1)
3996 
          (match_dup 2)
3997 
          (match_dup 3)
3998 
        ] 1080))
3999 
   (set (reg:SI 106)
4000 
        (unspec_volatile:SI [
4001 
          (match_dup 0)
4002 
          (match_dup 1)
4003 
          (match_dup 2)
4004 
          (match_dup 3)
4005 
        ] 1082))
4006 
   (set (reg:SI 105)
4007 
        (unspec_volatile:SI [
4008 
          (match_dup 0)
4009 
          (match_dup 1)
4010 
          (match_dup 2)
4011 
          (match_dup 3)
4012 
        ] 1084))
4013 
   (set (reg:SI 104)
4014 
        (unspec_volatile:SI [
4015 
          (match_dup 0)
4016 
          (match_dup 1)
4017 
          (match_dup 2)
4018 
          (match_dup 3)
4019 
        ] 1086))]
4020 
  "CGEN_ENABLE_INSN_P (98)"
4021 
  "cpfmulia1.b\\t%0,%1,%2,%3"
4022 
  [(set_attr "may_trap" "no")
4023 
   (set_attr "latency" "0")
4024 
   (set_attr "length" "4")
4025 
   (set_attr "slot" "cop")
4026 
   (set_attr "slots" "p1")
4027 
   (set_attr "stall" "none")])
4028 
 
4029 
 
4030 
(define_insn "cgen_intrinsic_cpfmulia1u_b_P1"
4031 
  [(set (reg:SI 111)
4032 
        (unspec_volatile:SI [
4033 
          (match_operand:DI 0 "general_operand" "x")
4034 
          (match_operand:DI 1 "general_operand" "x")
4035 
          (match_operand:SI 2 "cgen_h_uint_3a1_immediate" "")
4036 
          (match_operand:SI 3 "cgen_h_sint_8a1_immediate" "")
4037 
        ] 1088))
4038 
   (set (reg:SI 110)
4039 
        (unspec_volatile:SI [
4040 
          (match_dup 0)
4041 
          (match_dup 1)
4042 
          (match_dup 2)
4043 
          (match_dup 3)
4044 
        ] 1090))
4045 
   (set (reg:SI 109)
4046 
        (unspec_volatile:SI [
4047 
          (match_dup 0)
4048 
          (match_dup 1)
4049 
          (match_dup 2)
4050 
          (match_dup 3)
4051 
        ] 1092))
4052 
   (set (reg:SI 108)
4053 
        (unspec_volatile:SI [
4054 
          (match_dup 0)
4055 
          (match_dup 1)
4056 
          (match_dup 2)
4057 
          (match_dup 3)
4058 
        ] 1094))
4059 
   (set (reg:SI 107)
4060 
        (unspec_volatile:SI [
4061 
          (match_dup 0)
4062 
          (match_dup 1)
4063 
          (match_dup 2)
4064 
          (match_dup 3)
4065 
        ] 1096))
4066 
   (set (reg:SI 106)
4067 
        (unspec_volatile:SI [
4068 
          (match_dup 0)
4069 
          (match_dup 1)
4070 
          (match_dup 2)
4071 
          (match_dup 3)
4072 
        ] 1098))
4073 
   (set (reg:SI 105)
4074 
        (unspec_volatile:SI [
4075 
          (match_dup 0)
4076 
          (match_dup 1)
4077 
          (match_dup 2)
4078 
          (match_dup 3)
4079 
        ] 1100))
4080 
   (set (reg:SI 104)
4081 
        (unspec_volatile:SI [
4082 
          (match_dup 0)
4083 
          (match_dup 1)
4084 
          (match_dup 2)
4085 
          (match_dup 3)
4086 
        ] 1102))]
4087 
  "CGEN_ENABLE_INSN_P (99)"
4088 
  "cpfmulia1u.b\\t%0,%1,%2,%3"
4089 
  [(set_attr "may_trap" "no")
4090 
   (set_attr "latency" "0")
4091 
   (set_attr "length" "4")
4092 
   (set_attr "slot" "cop")
4093 
   (set_attr "slots" "p1")
4094 
   (set_attr "stall" "none")])
4095 
 
4096 
 
4097 
(define_insn "cgen_intrinsic_cpamadila1_h_P1"
4098 
  [(set (reg:SI 87)
4099 
        (unspec_volatile:SI [
4100 
          (match_operand:DI 0 "general_operand" "x")
4101 
          (match_operand:DI 1 "general_operand" "x")
4102 
          (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
4103 
        ] 1104))
4104 
   (set (reg:SI 107)
4105 
        (unspec_volatile:SI [
4106 
          (match_dup 0)
4107 
          (match_dup 1)
4108 
          (match_dup 2)
4109 
        ] 1106))
4110 
   (set (reg:SI 106)
4111 
        (unspec_volatile:SI [
4112 
          (match_dup 0)
4113 
          (match_dup 1)
4114 
          (match_dup 2)
4115 
        ] 1108))
4116 
   (set (reg:SI 105)
4117 
        (unspec_volatile:SI [
4118 
          (match_dup 0)
4119 
          (match_dup 1)
4120 
          (match_dup 2)
4121 
        ] 1110))
4122 
   (set (reg:SI 104)
4123 
        (unspec_volatile:SI [
4124 
          (match_dup 0)
4125 
          (match_dup 1)
4126 
          (match_dup 2)
4127 
        ] 1112))]
4128 
  "CGEN_ENABLE_INSN_P (100)"
4129 
  "cpamadila1.h\\t%0,%1,%2"
4130 
  [(set_attr "may_trap" "no")
4131 
   (set_attr "latency" "0")
4132 
   (set_attr "length" "4")
4133 
   (set_attr "slot" "cop")
4134 
   (set_attr "slots" "p1")
4135 
   (set_attr "stall" "none")])
4136 
 
4137 
 
4138 
(define_insn "cgen_intrinsic_cpamadiua1_h_P1"
4139 
  [(set (reg:SI 87)
4140 
        (unspec_volatile:SI [
4141 
          (match_operand:DI 0 "general_operand" "x")
4142 
          (match_operand:DI 1 "general_operand" "x")
4143 
          (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
4144 
        ] 1114))
4145 
   (set (reg:SI 111)
4146 
        (unspec_volatile:SI [
4147 
          (match_dup 0)
4148 
          (match_dup 1)
4149 
          (match_dup 2)
4150 
        ] 1116))
4151 
   (set (reg:SI 110)
4152 
        (unspec_volatile:SI [
4153 
          (match_dup 0)
4154 
          (match_dup 1)
4155 
          (match_dup 2)
4156 
        ] 1118))
4157 
   (set (reg:SI 109)
4158 
        (unspec_volatile:SI [
4159 
          (match_dup 0)
4160 
          (match_dup 1)
4161 
          (match_dup 2)
4162 
        ] 1120))
4163 
   (set (reg:SI 108)
4164 
        (unspec_volatile:SI [
4165 
          (match_dup 0)
4166 
          (match_dup 1)
4167 
          (match_dup 2)
4168 
        ] 1122))]
4169 
  "CGEN_ENABLE_INSN_P (101)"
4170 
  "cpamadiua1.h\\t%0,%1,%2"
4171 
  [(set_attr "may_trap" "no")
4172 
   (set_attr "latency" "0")
4173 
   (set_attr "length" "4")
4174 
   (set_attr "slot" "cop")
4175 
   (set_attr "slots" "p1")
4176 
   (set_attr "stall" "none")])
4177 
 
4178 
 
4179 
(define_insn "cgen_intrinsic_cpamadia1_b_P1"
4180 
  [(set (reg:SI 87)
4181 
        (unspec_volatile:SI [
4182 
          (match_operand:DI 0 "general_operand" "x")
4183 
          (match_operand:DI 1 "general_operand" "x")
4184 
          (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
4185 
        ] 1124))
4186 
   (set (reg:SI 111)
4187 
        (unspec_volatile:SI [
4188 
          (match_dup 0)
4189 
          (match_dup 1)
4190 
          (match_dup 2)
4191 
        ] 1126))
4192 
   (set (reg:SI 110)
4193 
        (unspec_volatile:SI [
4194 
          (match_dup 0)
4195 
          (match_dup 1)
4196 
          (match_dup 2)
4197 
        ] 1128))
4198 
   (set (reg:SI 109)
4199 
        (unspec_volatile:SI [
4200 
          (match_dup 0)
4201 
          (match_dup 1)
4202 
          (match_dup 2)
4203 
        ] 1130))
4204 
   (set (reg:SI 108)
4205 
        (unspec_volatile:SI [
4206 
          (match_dup 0)
4207 
          (match_dup 1)
4208 
          (match_dup 2)
4209 
        ] 1132))
4210 
   (set (reg:SI 107)
4211 
        (unspec_volatile:SI [
4212 
          (match_dup 0)
4213 
          (match_dup 1)
4214 
          (match_dup 2)
4215 
        ] 1134))
4216 
   (set (reg:SI 106)
4217 
        (unspec_volatile:SI [
4218 
          (match_dup 0)
4219 
          (match_dup 1)
4220 
          (match_dup 2)
4221 
        ] 1136))
4222 
   (set (reg:SI 105)
4223 
        (unspec_volatile:SI [
4224 
          (match_dup 0)
4225 
          (match_dup 1)
4226 
          (match_dup 2)
4227 
        ] 1138))
4228 
   (set (reg:SI 104)
4229 
        (unspec_volatile:SI [
4230 
          (match_dup 0)
4231 
          (match_dup 1)
4232 
          (match_dup 2)
4233 
        ] 1140))]
4234 
  "CGEN_ENABLE_INSN_P (102)"
4235 
  "cpamadia1.b\\t%0,%1,%2"
4236 
  [(set_attr "may_trap" "no")
4237 
   (set_attr "latency" "0")
4238 
   (set_attr "length" "4")
4239 
   (set_attr "slot" "cop")
4240 
   (set_attr "slots" "p1")
4241 
   (set_attr "stall" "none")])
4242 
 
4243 
 
4244 
(define_insn "cgen_intrinsic_cpamadia1u_b_P1"
4245 
  [(set (reg:SI 87)
4246 
        (unspec_volatile:SI [
4247 
          (match_operand:DI 0 "general_operand" "x")
4248 
          (match_operand:DI 1 "general_operand" "x")
4249 
          (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
4250 
        ] 1142))
4251 
   (set (reg:SI 111)
4252 
        (unspec_volatile:SI [
4253 
          (match_dup 0)
4254 
          (match_dup 1)
4255 
          (match_dup 2)
4256 
        ] 1144))
4257 
   (set (reg:SI 110)
4258 
        (unspec_volatile:SI [
4259 
          (match_dup 0)
4260 
          (match_dup 1)
4261 
          (match_dup 2)
4262 
        ] 1146))
4263 
   (set (reg:SI 109)
4264 
        (unspec_volatile:SI [
4265 
          (match_dup 0)
4266 
          (match_dup 1)
4267 
          (match_dup 2)
4268 
        ] 1148))
4269 
   (set (reg:SI 108)
4270 
        (unspec_volatile:SI [
4271 
          (match_dup 0)
4272 
          (match_dup 1)
4273 
          (match_dup 2)
4274 
        ] 1150))
4275 
   (set (reg:SI 107)
4276 
        (unspec_volatile:SI [
4277 
          (match_dup 0)
4278 
          (match_dup 1)
4279 
          (match_dup 2)
4280 
        ] 1152))
4281 
   (set (reg:SI 106)
4282 
        (unspec_volatile:SI [
4283 
          (match_dup 0)
4284 
          (match_dup 1)
4285 
          (match_dup 2)
4286 
        ] 1154))
4287 
   (set (reg:SI 105)
4288 
        (unspec_volatile:SI [
4289 
          (match_dup 0)
4290 
          (match_dup 1)
4291 
          (match_dup 2)
4292 
        ] 1156))
4293 
   (set (reg:SI 104)
4294 
        (unspec_volatile:SI [
4295 
          (match_dup 0)
4296 
          (match_dup 1)
4297 
          (match_dup 2)
4298 
        ] 1158))]
4299 
  "CGEN_ENABLE_INSN_P (103)"
4300 
  "cpamadia1u.b\\t%0,%1,%2"
4301 
  [(set_attr "may_trap" "no")
4302 
   (set_attr "latency" "0")
4303 
   (set_attr "length" "4")
4304 
   (set_attr "slot" "cop")
4305 
   (set_attr "slots" "p1")
4306 
   (set_attr "stall" "none")])
4307 
 
4308 
 
4309 
(define_insn "cgen_intrinsic_cpamulila1_h_P1"
4310 
  [(set (reg:SI 107)
4311 
        (unspec_volatile:SI [
4312 
          (match_operand:DI 0 "general_operand" "x")
4313 
          (match_operand:DI 1 "general_operand" "x")
4314 
          (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
4315 
        ] 1160))
4316 
   (set (reg:SI 106)
4317 
        (unspec_volatile:SI [
4318 
          (match_dup 0)
4319 
          (match_dup 1)
4320 
          (match_dup 2)
4321 
        ] 1162))
4322 
   (set (reg:SI 105)
4323 
        (unspec_volatile:SI [
4324 
          (match_dup 0)
4325 
          (match_dup 1)
4326 
          (match_dup 2)
4327 
        ] 1164))
4328 
   (set (reg:SI 104)
4329 
        (unspec_volatile:SI [
4330 
          (match_dup 0)
4331 
          (match_dup 1)
4332 
          (match_dup 2)
4333 
        ] 1166))]
4334 
  "CGEN_ENABLE_INSN_P (104)"
4335 
  "cpamulila1.h\\t%0,%1,%2"
4336 
  [(set_attr "may_trap" "no")
4337 
   (set_attr "latency" "0")
4338 
   (set_attr "length" "4")
4339 
   (set_attr "slot" "cop")
4340 
   (set_attr "slots" "p1")
4341 
   (set_attr "stall" "none")])
4342 
 
4343 
 
4344 
(define_insn "cgen_intrinsic_cpamuliua1_h_P1"
4345 
  [(set (reg:SI 111)
4346 
        (unspec_volatile:SI [
4347 
          (match_operand:DI 0 "general_operand" "x")
4348 
          (match_operand:DI 1 "general_operand" "x")
4349 
          (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
4350 
        ] 1168))
4351 
   (set (reg:SI 110)
4352 
        (unspec_volatile:SI [
4353 
          (match_dup 0)
4354 
          (match_dup 1)
4355 
          (match_dup 2)
4356 
        ] 1170))
4357 
   (set (reg:SI 109)
4358 
        (unspec_volatile:SI [
4359 
          (match_dup 0)
4360 
          (match_dup 1)
4361 
          (match_dup 2)
4362 
        ] 1172))
4363 
   (set (reg:SI 108)
4364 
        (unspec_volatile:SI [
4365 
          (match_dup 0)
4366 
          (match_dup 1)
4367 
          (match_dup 2)
4368 
        ] 1174))]
4369 
  "CGEN_ENABLE_INSN_P (105)"
4370 
  "cpamuliua1.h\\t%0,%1,%2"
4371 
  [(set_attr "may_trap" "no")
4372 
   (set_attr "latency" "0")
4373 
   (set_attr "length" "4")
4374 
   (set_attr "slot" "cop")
4375 
   (set_attr "slots" "p1")
4376 
   (set_attr "stall" "none")])
4377 
 
4378 
 
4379 
(define_insn "cgen_intrinsic_cpamulia1_b_P1"
4380 
  [(set (reg:SI 111)
4381 
        (unspec_volatile:SI [
4382 
          (match_operand:DI 0 "general_operand" "x")
4383 
          (match_operand:DI 1 "general_operand" "x")
4384 
          (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
4385 
        ] 1176))
4386 
   (set (reg:SI 110)
4387 
        (unspec_volatile:SI [
4388 
          (match_dup 0)
4389 
          (match_dup 1)
4390 
          (match_dup 2)
4391 
        ] 1178))
4392 
   (set (reg:SI 109)
4393 
        (unspec_volatile:SI [
4394 
          (match_dup 0)
4395 
          (match_dup 1)
4396 
          (match_dup 2)
4397 
        ] 1180))
4398 
   (set (reg:SI 108)
4399 
        (unspec_volatile:SI [
4400 
          (match_dup 0)
4401 
          (match_dup 1)
4402 
          (match_dup 2)
4403 
        ] 1182))
4404 
   (set (reg:SI 107)
4405 
        (unspec_volatile:SI [
4406 
          (match_dup 0)
4407 
          (match_dup 1)
4408 
          (match_dup 2)
4409 
        ] 1184))
4410 
   (set (reg:SI 106)
4411 
        (unspec_volatile:SI [
4412 
          (match_dup 0)
4413 
          (match_dup 1)
4414 
          (match_dup 2)
4415 
        ] 1186))
4416 
   (set (reg:SI 105)
4417 
        (unspec_volatile:SI [
4418 
          (match_dup 0)
4419 
          (match_dup 1)
4420 
          (match_dup 2)
4421 
        ] 1188))
4422 
   (set (reg:SI 104)
4423 
        (unspec_volatile:SI [
4424 
          (match_dup 0)
4425 
          (match_dup 1)
4426 
          (match_dup 2)
4427 
        ] 1190))]
4428 
  "CGEN_ENABLE_INSN_P (106)"
4429 
  "cpamulia1.b\\t%0,%1,%2"
4430 
  [(set_attr "may_trap" "no")
4431 
   (set_attr "latency" "0")
4432 
   (set_attr "length" "4")
4433 
   (set_attr "slot" "cop")
4434 
   (set_attr "slots" "p1")
4435 
   (set_attr "stall" "none")])
4436 
 
4437 
 
4438 
(define_insn "cgen_intrinsic_cpamulia1u_b_P1"
4439 
  [(set (reg:SI 111)
4440 
        (unspec_volatile:SI [
4441 
          (match_operand:DI 0 "general_operand" "x")
4442 
          (match_operand:DI 1 "general_operand" "x")
4443 
          (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
4444 
        ] 1192))
4445 
   (set (reg:SI 110)
4446 
        (unspec_volatile:SI [
4447 
          (match_dup 0)
4448 
          (match_dup 1)
4449 
          (match_dup 2)
4450 
        ] 1194))
4451 
   (set (reg:SI 109)
4452 
        (unspec_volatile:SI [
4453 
          (match_dup 0)
4454 
          (match_dup 1)
4455 
          (match_dup 2)
4456 
        ] 1196))
4457 
   (set (reg:SI 108)
4458 
        (unspec_volatile:SI [
4459 
          (match_dup 0)
4460 
          (match_dup 1)
4461 
          (match_dup 2)
4462 
        ] 1198))
4463 
   (set (reg:SI 107)
4464 
        (unspec_volatile:SI [
4465 
          (match_dup 0)
4466 
          (match_dup 1)
4467 
          (match_dup 2)
4468 
        ] 1200))
4469 
   (set (reg:SI 106)
4470 
        (unspec_volatile:SI [
4471 
          (match_dup 0)
4472 
          (match_dup 1)
4473 
          (match_dup 2)
4474 
        ] 1202))
4475 
   (set (reg:SI 105)
4476 
        (unspec_volatile:SI [
4477 
          (match_dup 0)
4478 
          (match_dup 1)
4479 
          (match_dup 2)
4480 
        ] 1204))
4481 
   (set (reg:SI 104)
4482 
        (unspec_volatile:SI [
4483 
          (match_dup 0)
4484 
          (match_dup 1)
4485 
          (match_dup 2)
4486 
        ] 1206))]
4487 
  "CGEN_ENABLE_INSN_P (107)"
4488 
  "cpamulia1u.b\\t%0,%1,%2"
4489 
  [(set_attr "may_trap" "no")
4490 
   (set_attr "latency" "0")
4491 
   (set_attr "length" "4")
4492 
   (set_attr "slot" "cop")
4493 
   (set_attr "slots" "p1")
4494 
   (set_attr "stall" "none")])
4495 
 
4496 
 
4497 
(define_insn "cgen_intrinsic_cpfmadila1s1_h_P1"
4498 
  [(set (reg:SI 87)
4499 
        (unspec_volatile:SI [
4500 
          (match_operand:DI 0 "general_operand" "x")
4501 
          (match_operand:DI 1 "general_operand" "x")
4502 
          (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
4503 
        ] 1208))
4504 
   (set (reg:SI 107)
4505 
        (unspec_volatile:SI [
4506 
          (match_dup 0)
4507 
          (match_dup 1)
4508 
          (match_dup 2)
4509 
        ] 1210))
4510 
   (set (reg:SI 106)
4511 
        (unspec_volatile:SI [
4512 
          (match_dup 0)
4513 
          (match_dup 1)
4514 
          (match_dup 2)
4515 
        ] 1212))
4516 
   (set (reg:SI 105)
4517 
        (unspec_volatile:SI [
4518 
          (match_dup 0)
4519 
          (match_dup 1)
4520 
          (match_dup 2)
4521 
        ] 1214))
4522 
   (set (reg:SI 104)
4523 
        (unspec_volatile:SI [
4524 
          (match_dup 0)
4525 
          (match_dup 1)
4526 
          (match_dup 2)
4527 
        ] 1216))]
4528 
  "CGEN_ENABLE_INSN_P (108)"
4529 
  "cpfmadila1s1.h\\t%0,%1,%2"
4530 
  [(set_attr "may_trap" "no")
4531 
   (set_attr "latency" "0")
4532 
   (set_attr "length" "4")
4533 
   (set_attr "slot" "cop")
4534 
   (set_attr "slots" "p1")
4535 
   (set_attr "stall" "none")])
4536 
 
4537 
 
4538 
(define_insn "cgen_intrinsic_cpfmadiua1s1_h_P1"
4539 
  [(set (reg:SI 87)
4540 
        (unspec_volatile:SI [
4541 
          (match_operand:DI 0 "general_operand" "x")
4542 
          (match_operand:DI 1 "general_operand" "x")
4543 
          (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
4544 
        ] 1218))
4545 
   (set (reg:SI 111)
4546 
        (unspec_volatile:SI [
4547 
          (match_dup 0)
4548 
          (match_dup 1)
4549 
          (match_dup 2)
4550 
        ] 1220))
4551 
   (set (reg:SI 110)
4552 
        (unspec_volatile:SI [
4553 
          (match_dup 0)
4554 
          (match_dup 1)
4555 
          (match_dup 2)
4556 
        ] 1222))
4557 
   (set (reg:SI 109)
4558 
        (unspec_volatile:SI [
4559 
          (match_dup 0)
4560 
          (match_dup 1)
4561 
          (match_dup 2)
4562 
        ] 1224))
4563 
   (set (reg:SI 108)
4564 
        (unspec_volatile:SI [
4565 
          (match_dup 0)
4566 
          (match_dup 1)
4567 
          (match_dup 2)
4568 
        ] 1226))]
4569 
  "CGEN_ENABLE_INSN_P (109)"
4570 
  "cpfmadiua1s1.h\\t%0,%1,%2"
4571 
  [(set_attr "may_trap" "no")
4572 
   (set_attr "latency" "0")
4573 
   (set_attr "length" "4")
4574 
   (set_attr "slot" "cop")
4575 
   (set_attr "slots" "p1")
4576 
   (set_attr "stall" "none")])
4577 
 
4578 
 
4579 
(define_insn "cgen_intrinsic_cpfmadia1s1_b_P1"
4580 
  [(set (reg:SI 87)
4581 
        (unspec_volatile:SI [
4582 
          (match_operand:DI 0 "general_operand" "x")
4583 
          (match_operand:DI 1 "general_operand" "x")
4584 
          (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
4585 
        ] 1228))
4586 
   (set (reg:SI 111)
4587 
        (unspec_volatile:SI [
4588 
          (match_dup 0)
4589 
          (match_dup 1)
4590 
          (match_dup 2)
4591 
        ] 1230))
4592 
   (set (reg:SI 110)
4593 
        (unspec_volatile:SI [
4594 
          (match_dup 0)
4595 
          (match_dup 1)
4596 
          (match_dup 2)
4597 
        ] 1232))
4598 
   (set (reg:SI 109)
4599 
        (unspec_volatile:SI [
4600 
          (match_dup 0)
4601 
          (match_dup 1)
4602 
          (match_dup 2)
4603 
        ] 1234))
4604 
   (set (reg:SI 108)
4605 
        (unspec_volatile:SI [
4606 
          (match_dup 0)
4607 
          (match_dup 1)
4608 
          (match_dup 2)
4609 
        ] 1236))
4610 
   (set (reg:SI 107)
4611 
        (unspec_volatile:SI [
4612 
          (match_dup 0)
4613 
          (match_dup 1)
4614 
          (match_dup 2)
4615 
        ] 1238))
4616 
   (set (reg:SI 106)
4617 
        (unspec_volatile:SI [
4618 
          (match_dup 0)
4619 
          (match_dup 1)
4620 
          (match_dup 2)
4621 
        ] 1240))
4622 
   (set (reg:SI 105)
4623 
        (unspec_volatile:SI [
4624 
          (match_dup 0)
4625 
          (match_dup 1)
4626 
          (match_dup 2)
4627 
        ] 1242))
4628 
   (set (reg:SI 104)
4629 
        (unspec_volatile:SI [
4630 
          (match_dup 0)
4631 
          (match_dup 1)
4632 
          (match_dup 2)
4633 
        ] 1244))]
4634 
  "CGEN_ENABLE_INSN_P (110)"
4635 
  "cpfmadia1s1.b\\t%0,%1,%2"
4636 
  [(set_attr "may_trap" "no")
4637 
   (set_attr "latency" "0")
4638 
   (set_attr "length" "4")
4639 
   (set_attr "slot" "cop")
4640 
   (set_attr "slots" "p1")
4641 
   (set_attr "stall" "none")])
4642 
 
4643 
 
4644 
(define_insn "cgen_intrinsic_cpfmadia1s1u_b_P1"
4645 
  [(set (reg:SI 87)
4646 
        (unspec_volatile:SI [
4647 
          (match_operand:DI 0 "general_operand" "x")
4648 
          (match_operand:DI 1 "general_operand" "x")
4649 
          (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
4650 
        ] 1246))
4651 
   (set (reg:SI 111)
4652 
        (unspec_volatile:SI [
4653 
          (match_dup 0)
4654 
          (match_dup 1)
4655 
          (match_dup 2)
4656 
        ] 1248))
4657 
   (set (reg:SI 110)
4658 
        (unspec_volatile:SI [
4659 
          (match_dup 0)
4660 
          (match_dup 1)
4661 
          (match_dup 2)
4662 
        ] 1250))
4663 
   (set (reg:SI 109)
4664 
        (unspec_volatile:SI [
4665 
          (match_dup 0)
4666 
          (match_dup 1)
4667 
          (match_dup 2)
4668 
        ] 1252))
4669 
   (set (reg:SI 108)
4670 
        (unspec_volatile:SI [
4671 
          (match_dup 0)
4672 
          (match_dup 1)
4673 
          (match_dup 2)
4674 
        ] 1254))
4675 
   (set (reg:SI 107)
4676 
        (unspec_volatile:SI [
4677 
          (match_dup 0)
4678 
          (match_dup 1)
4679 
          (match_dup 2)
4680 
        ] 1256))
4681 
   (set (reg:SI 106)
4682 
        (unspec_volatile:SI [
4683 
          (match_dup 0)
4684 
          (match_dup 1)
4685 
          (match_dup 2)
4686 
        ] 1258))
4687 
   (set (reg:SI 105)
4688 
        (unspec_volatile:SI [
4689 
          (match_dup 0)
4690 
          (match_dup 1)
4691 
          (match_dup 2)
4692 
        ] 1260))
4693 
   (set (reg:SI 104)
4694 
        (unspec_volatile:SI [
4695 
          (match_dup 0)
4696 
          (match_dup 1)
4697 
          (match_dup 2)
4698 
        ] 1262))]
4699 
  "CGEN_ENABLE_INSN_P (111)"
4700 
  "cpfmadia1s1u.b\\t%0,%1,%2"
4701 
  [(set_attr "may_trap" "no")
4702 
   (set_attr "latency" "0")
4703 
   (set_attr "length" "4")
4704 
   (set_attr "slot" "cop")
4705 
   (set_attr "slots" "p1")
4706 
   (set_attr "stall" "none")])
4707 
 
4708 
 
4709 
(define_insn "cgen_intrinsic_cpfmulila1s1_h_P1"
4710 
  [(set (reg:SI 107)
4711 
        (unspec_volatile:SI [
4712 
          (match_operand:DI 0 "general_operand" "x")
4713 
          (match_operand:DI 1 "general_operand" "x")
4714 
          (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
4715 
        ] 1264))
4716 
   (set (reg:SI 106)
4717 
        (unspec_volatile:SI [
4718 
          (match_dup 0)
4719 
          (match_dup 1)
4720 
          (match_dup 2)
4721 
        ] 1266))
4722 
   (set (reg:SI 105)
4723 
        (unspec_volatile:SI [
4724 
          (match_dup 0)
4725 
          (match_dup 1)
4726 
          (match_dup 2)
4727 
        ] 1268))
4728 
   (set (reg:SI 104)
4729 
        (unspec_volatile:SI [
4730 
          (match_dup 0)
4731 
          (match_dup 1)
4732 
          (match_dup 2)
4733 
        ] 1270))]
4734 
  "CGEN_ENABLE_INSN_P (112)"
4735 
  "cpfmulila1s1.h\\t%0,%1,%2"
4736 
  [(set_attr "may_trap" "no")
4737 
   (set_attr "latency" "0")
4738 
   (set_attr "length" "4")
4739 
   (set_attr "slot" "cop")
4740 
   (set_attr "slots" "p1")
4741 
   (set_attr "stall" "none")])
4742 
 
4743 
 
4744 
(define_insn "cgen_intrinsic_cpfmuliua1s1_h_P1"
4745 
  [(set (reg:SI 111)
4746 
        (unspec_volatile:SI [
4747 
          (match_operand:DI 0 "general_operand" "x")
4748 
          (match_operand:DI 1 "general_operand" "x")
4749 
          (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
4750 
        ] 1272))
4751 
   (set (reg:SI 110)
4752 
        (unspec_volatile:SI [
4753 
          (match_dup 0)
4754 
          (match_dup 1)
4755 
          (match_dup 2)
4756 
        ] 1274))
4757 
   (set (reg:SI 109)
4758 
        (unspec_volatile:SI [
4759 
          (match_dup 0)
4760 
          (match_dup 1)
4761 
          (match_dup 2)
4762 
        ] 1276))
4763 
   (set (reg:SI 108)
4764 
        (unspec_volatile:SI [
4765 
          (match_dup 0)
4766 
          (match_dup 1)
4767 
          (match_dup 2)
4768 
        ] 1278))]
4769 
  "CGEN_ENABLE_INSN_P (113)"
4770 
  "cpfmuliua1s1.h\\t%0,%1,%2"
4771 
  [(set_attr "may_trap" "no")
4772 
   (set_attr "latency" "0")
4773 
   (set_attr "length" "4")
4774 
   (set_attr "slot" "cop")
4775 
   (set_attr "slots" "p1")
4776 
   (set_attr "stall" "none")])
4777 
 
4778 
 
4779 
(define_insn "cgen_intrinsic_cpfmulia1s1_b_P1"
4780 
  [(set (reg:SI 111)
4781 
        (unspec_volatile:SI [
4782 
          (match_operand:DI 0 "general_operand" "x")
4783 
          (match_operand:DI 1 "general_operand" "x")
4784 
          (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
4785 
        ] 1280))
4786 
   (set (reg:SI 110)
4787 
        (unspec_volatile:SI [
4788 
          (match_dup 0)
4789 
          (match_dup 1)
4790 
          (match_dup 2)
4791 
        ] 1282))
4792 
   (set (reg:SI 109)
4793 
        (unspec_volatile:SI [
4794 
          (match_dup 0)
4795 
          (match_dup 1)
4796 
          (match_dup 2)
4797 
        ] 1284))
4798 
   (set (reg:SI 108)
4799 
        (unspec_volatile:SI [
4800 
          (match_dup 0)
4801 
          (match_dup 1)
4802 
          (match_dup 2)
4803 
        ] 1286))
4804 
   (set (reg:SI 107)
4805 
        (unspec_volatile:SI [
4806 
          (match_dup 0)
4807 
          (match_dup 1)
4808 
          (match_dup 2)
4809 
        ] 1288))
4810 
   (set (reg:SI 106)
4811 
        (unspec_volatile:SI [
4812 
          (match_dup 0)
4813 
          (match_dup 1)
4814 
          (match_dup 2)
4815 
        ] 1290))
4816 
   (set (reg:SI 105)
4817 
        (unspec_volatile:SI [
4818 
          (match_dup 0)
4819 
          (match_dup 1)
4820 
          (match_dup 2)
4821 
        ] 1292))
4822 
   (set (reg:SI 104)
4823 
        (unspec_volatile:SI [
4824 
          (match_dup 0)
4825 
          (match_dup 1)
4826 
          (match_dup 2)
4827 
        ] 1294))]
4828 
  "CGEN_ENABLE_INSN_P (114)"
4829 
  "cpfmulia1s1.b\\t%0,%1,%2"
4830 
  [(set_attr "may_trap" "no")
4831 
   (set_attr "latency" "0")
4832 
   (set_attr "length" "4")
4833 
   (set_attr "slot" "cop")
4834 
   (set_attr "slots" "p1")
4835 
   (set_attr "stall" "none")])
4836 
 
4837 
 
4838 
(define_insn "cgen_intrinsic_cpfmulia1s1u_b_P1"
4839 
  [(set (reg:SI 111)
4840 
        (unspec_volatile:SI [
4841 
          (match_operand:DI 0 "general_operand" "x")
4842 
          (match_operand:DI 1 "general_operand" "x")
4843 
          (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
4844 
        ] 1296))
4845 
   (set (reg:SI 110)
4846 
        (unspec_volatile:SI [
4847 
          (match_dup 0)
4848 
          (match_dup 1)
4849 
          (match_dup 2)
4850 
        ] 1298))
4851 
   (set (reg:SI 109)
4852 
        (unspec_volatile:SI [
4853 
          (match_dup 0)
4854 
          (match_dup 1)
4855 
          (match_dup 2)
4856 
        ] 1300))
4857 
   (set (reg:SI 108)
4858 
        (unspec_volatile:SI [
4859 
          (match_dup 0)
4860 
          (match_dup 1)
4861 
          (match_dup 2)
4862 
        ] 1302))
4863 
   (set (reg:SI 107)
4864 
        (unspec_volatile:SI [
4865 
          (match_dup 0)
4866 
          (match_dup 1)
4867 
          (match_dup 2)
4868 
        ] 1304))
4869 
   (set (reg:SI 106)
4870 
        (unspec_volatile:SI [
4871 
          (match_dup 0)
4872 
          (match_dup 1)
4873 
          (match_dup 2)
4874 
        ] 1306))
4875 
   (set (reg:SI 105)
4876 
        (unspec_volatile:SI [
4877 
          (match_dup 0)
4878 
          (match_dup 1)
4879 
          (match_dup 2)
4880 
        ] 1308))
4881 
   (set (reg:SI 104)
4882 
        (unspec_volatile:SI [
4883 
          (match_dup 0)
4884 
          (match_dup 1)
4885 
          (match_dup 2)
4886 
        ] 1310))]
4887 
  "CGEN_ENABLE_INSN_P (115)"
4888 
  "cpfmulia1s1u.b\\t%0,%1,%2"
4889 
  [(set_attr "may_trap" "no")
4890 
   (set_attr "latency" "0")
4891 
   (set_attr "length" "4")
4892 
   (set_attr "slot" "cop")
4893 
   (set_attr "slots" "p1")
4894 
   (set_attr "stall" "none")])
4895 
 
4896 
 
4897 
(define_insn "cgen_intrinsic_cpfmadila1s0_h_P1"
4898 
  [(set (reg:SI 87)
4899 
        (unspec_volatile:SI [
4900 
          (match_operand:DI 0 "general_operand" "x")
4901 
          (match_operand:DI 1 "general_operand" "x")
4902 
          (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
4903 
        ] 1312))
4904 
   (set (reg:SI 107)
4905 
        (unspec_volatile:SI [
4906 
          (match_dup 0)
4907 
          (match_dup 1)
4908 
          (match_dup 2)
4909 
        ] 1314))
4910 
   (set (reg:SI 106)
4911 
        (unspec_volatile:SI [
4912 
          (match_dup 0)
4913 
          (match_dup 1)
4914 
          (match_dup 2)
4915 
        ] 1316))
4916 
   (set (reg:SI 105)
4917 
        (unspec_volatile:SI [
4918 
          (match_dup 0)
4919 
          (match_dup 1)
4920 
          (match_dup 2)
4921 
        ] 1318))
4922 
   (set (reg:SI 104)
4923 
        (unspec_volatile:SI [
4924 
          (match_dup 0)
4925 
          (match_dup 1)
4926 
          (match_dup 2)
4927 
        ] 1320))]
4928 
  "CGEN_ENABLE_INSN_P (116)"
4929 
  "cpfmadila1s0.h\\t%0,%1,%2"
4930 
  [(set_attr "may_trap" "no")
4931 
   (set_attr "latency" "0")
4932 
   (set_attr "length" "4")
4933 
   (set_attr "slot" "cop")
4934 
   (set_attr "slots" "p1")
4935 
   (set_attr "stall" "none")])
4936 
 
4937 
 
4938 
(define_insn "cgen_intrinsic_cpfmadiua1s0_h_P1"
4939 
  [(set (reg:SI 87)
4940 
        (unspec_volatile:SI [
4941 
          (match_operand:DI 0 "general_operand" "x")
4942 
          (match_operand:DI 1 "general_operand" "x")
4943 
          (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
4944 
        ] 1322))
4945 
   (set (reg:SI 111)
4946 
        (unspec_volatile:SI [
4947 
          (match_dup 0)
4948 
          (match_dup 1)
4949 
          (match_dup 2)
4950 
        ] 1324))
4951 
   (set (reg:SI 110)
4952 
        (unspec_volatile:SI [
4953 
          (match_dup 0)
4954 
          (match_dup 1)
4955 
          (match_dup 2)
4956 
        ] 1326))
4957 
   (set (reg:SI 109)
4958 
        (unspec_volatile:SI [
4959 
          (match_dup 0)
4960 
          (match_dup 1)
4961 
          (match_dup 2)
4962 
        ] 1328))
4963 
   (set (reg:SI 108)
4964 
        (unspec_volatile:SI [
4965 
          (match_dup 0)
4966 
          (match_dup 1)
4967 
          (match_dup 2)
4968 
        ] 1330))]
4969 
  "CGEN_ENABLE_INSN_P (117)"
4970 
  "cpfmadiua1s0.h\\t%0,%1,%2"
4971 
  [(set_attr "may_trap" "no")
4972 
   (set_attr "latency" "0")
4973 
   (set_attr "length" "4")
4974 
   (set_attr "slot" "cop")
4975 
   (set_attr "slots" "p1")
4976 
   (set_attr "stall" "none")])
4977 
 
4978 
 
4979 
(define_insn "cgen_intrinsic_cpfmadia1s0_b_P1"
4980 
  [(set (reg:SI 87)
4981 
        (unspec_volatile:SI [
4982 
          (match_operand:DI 0 "general_operand" "x")
4983 
          (match_operand:DI 1 "general_operand" "x")
4984 
          (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
4985 
        ] 1332))
4986 
   (set (reg:SI 111)
4987 
        (unspec_volatile:SI [
4988 
          (match_dup 0)
4989 
          (match_dup 1)
4990 
          (match_dup 2)
4991 
        ] 1334))
4992 
   (set (reg:SI 110)
4993 
        (unspec_volatile:SI [
4994 
          (match_dup 0)
4995 
          (match_dup 1)
4996 
          (match_dup 2)
4997 
        ] 1336))
4998 
   (set (reg:SI 109)
4999 
        (unspec_volatile:SI [
5000 
          (match_dup 0)
5001 
          (match_dup 1)
5002 
          (match_dup 2)
5003 
        ] 1338))
5004 
   (set (reg:SI 108)
5005 
        (unspec_volatile:SI [
5006 
          (match_dup 0)
5007 
          (match_dup 1)
5008 
          (match_dup 2)
5009 
        ] 1340))
5010 
   (set (reg:SI 107)
5011 
        (unspec_volatile:SI [
5012 
          (match_dup 0)
5013 
          (match_dup 1)
5014 
          (match_dup 2)
5015 
        ] 1342))
5016 
   (set (reg:SI 106)
5017 
        (unspec_volatile:SI [
5018 
          (match_dup 0)
5019 
          (match_dup 1)
5020 
          (match_dup 2)
5021 
        ] 1344))
5022 
   (set (reg:SI 105)
5023 
        (unspec_volatile:SI [
5024 
          (match_dup 0)
5025 
          (match_dup 1)
5026 
          (match_dup 2)
5027 
        ] 1346))
5028 
   (set (reg:SI 104)
5029 
        (unspec_volatile:SI [
5030 
          (match_dup 0)
5031 
          (match_dup 1)
5032 
          (match_dup 2)
5033 
        ] 1348))]
5034 
  "CGEN_ENABLE_INSN_P (118)"
5035 
  "cpfmadia1s0.b\\t%0,%1,%2"
5036 
  [(set_attr "may_trap" "no")
5037 
   (set_attr "latency" "0")
5038 
   (set_attr "length" "4")
5039 
   (set_attr "slot" "cop")
5040 
   (set_attr "slots" "p1")
5041 
   (set_attr "stall" "none")])
5042 
 
5043 
 
5044 
(define_insn "cgen_intrinsic_cpfmadia1s0u_b_P1"
5045 
  [(set (reg:SI 87)
5046 
        (unspec_volatile:SI [
5047 
          (match_operand:DI 0 "general_operand" "x")
5048 
          (match_operand:DI 1 "general_operand" "x")
5049 
          (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
5050 
        ] 1350))
5051 
   (set (reg:SI 111)
5052 
        (unspec_volatile:SI [
5053 
          (match_dup 0)
5054 
          (match_dup 1)
5055 
          (match_dup 2)
5056 
        ] 1352))
5057 
   (set (reg:SI 110)
5058 
        (unspec_volatile:SI [
5059 
          (match_dup 0)
5060 
          (match_dup 1)
5061 
          (match_dup 2)
5062 
        ] 1354))
5063 
   (set (reg:SI 109)
5064 
        (unspec_volatile:SI [
5065 
          (match_dup 0)
5066 
          (match_dup 1)
5067 
          (match_dup 2)
5068 
        ] 1356))
5069 
   (set (reg:SI 108)
5070 
        (unspec_volatile:SI [
5071 
          (match_dup 0)
5072 
          (match_dup 1)
5073 
          (match_dup 2)
5074 
        ] 1358))
5075 
   (set (reg:SI 107)
5076 
        (unspec_volatile:SI [
5077 
          (match_dup 0)
5078 
          (match_dup 1)
5079 
          (match_dup 2)
5080 
        ] 1360))
5081 
   (set (reg:SI 106)
5082 
        (unspec_volatile:SI [
5083 
          (match_dup 0)
5084 
          (match_dup 1)
5085 
          (match_dup 2)
5086 
        ] 1362))
5087 
   (set (reg:SI 105)
5088 
        (unspec_volatile:SI [
5089 
          (match_dup 0)
5090 
          (match_dup 1)
5091 
          (match_dup 2)
5092 
        ] 1364))
5093 
   (set (reg:SI 104)
5094 
        (unspec_volatile:SI [
5095 
          (match_dup 0)
5096 
          (match_dup 1)
5097 
          (match_dup 2)
5098 
        ] 1366))]
5099 
  "CGEN_ENABLE_INSN_P (119)"
5100 
  "cpfmadia1s0u.b\\t%0,%1,%2"
5101 
  [(set_attr "may_trap" "no")
5102 
   (set_attr "latency" "0")
5103 
   (set_attr "length" "4")
5104 
   (set_attr "slot" "cop")
5105 
   (set_attr "slots" "p1")
5106 
   (set_attr "stall" "none")])
5107 
 
5108 
 
5109 
(define_insn "cgen_intrinsic_cpfmulila1s0_h_P1"
5110 
  [(set (reg:SI 107)
5111 
        (unspec_volatile:SI [
5112 
          (match_operand:DI 0 "general_operand" "x")
5113 
          (match_operand:DI 1 "general_operand" "x")
5114 
          (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
5115 
        ] 1368))
5116 
   (set (reg:SI 106)
5117 
        (unspec_volatile:SI [
5118 
          (match_dup 0)
5119 
          (match_dup 1)
5120 
          (match_dup 2)
5121 
        ] 1370))
5122 
   (set (reg:SI 105)
5123 
        (unspec_volatile:SI [
5124 
          (match_dup 0)
5125 
          (match_dup 1)
5126 
          (match_dup 2)
5127 
        ] 1372))
5128 
   (set (reg:SI 104)
5129 
        (unspec_volatile:SI [
5130 
          (match_dup 0)
5131 
          (match_dup 1)
5132 
          (match_dup 2)
5133 
        ] 1374))]
5134 
  "CGEN_ENABLE_INSN_P (120)"
5135 
  "cpfmulila1s0.h\\t%0,%1,%2"
5136 
  [(set_attr "may_trap" "no")
5137 
   (set_attr "latency" "0")
5138 
   (set_attr "length" "4")
5139 
   (set_attr "slot" "cop")
5140 
   (set_attr "slots" "p1")
5141 
   (set_attr "stall" "none")])
5142 
 
5143 
 
5144 
(define_insn "cgen_intrinsic_cpfmuliua1s0_h_P1"
5145 
  [(set (reg:SI 111)
5146 
        (unspec_volatile:SI [
5147 
          (match_operand:DI 0 "general_operand" "x")
5148 
          (match_operand:DI 1 "general_operand" "x")
5149 
          (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
5150 
        ] 1376))
5151 
   (set (reg:SI 110)
5152 
        (unspec_volatile:SI [
5153 
          (match_dup 0)
5154 
          (match_dup 1)
5155 
          (match_dup 2)
5156 
        ] 1378))
5157 
   (set (reg:SI 109)
5158 
        (unspec_volatile:SI [
5159 
          (match_dup 0)
5160 
          (match_dup 1)
5161 
          (match_dup 2)
5162 
        ] 1380))
5163 
   (set (reg:SI 108)
5164 
        (unspec_volatile:SI [
5165 
          (match_dup 0)
5166 
          (match_dup 1)
5167 
          (match_dup 2)
5168 
        ] 1382))]
5169 
  "CGEN_ENABLE_INSN_P (121)"
5170 
  "cpfmuliua1s0.h\\t%0,%1,%2"
5171 
  [(set_attr "may_trap" "no")
5172 
   (set_attr "latency" "0")
5173 
   (set_attr "length" "4")
5174 
   (set_attr "slot" "cop")
5175 
   (set_attr "slots" "p1")
5176 
   (set_attr "stall" "none")])
5177 
 
5178 
 
5179 
(define_insn "cgen_intrinsic_cpfmulia1s0_b_P1"
5180 
  [(set (reg:SI 111)
5181 
        (unspec_volatile:SI [
5182 
          (match_operand:DI 0 "general_operand" "x")
5183 
          (match_operand:DI 1 "general_operand" "x")
5184 
          (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
5185 
        ] 1384))
5186 
   (set (reg:SI 110)
5187 
        (unspec_volatile:SI [
5188 
          (match_dup 0)
5189 
          (match_dup 1)
5190 
          (match_dup 2)
5191 
        ] 1386))
5192 
   (set (reg:SI 109)
5193 
        (unspec_volatile:SI [
5194 
          (match_dup 0)
5195 
          (match_dup 1)
5196 
          (match_dup 2)
5197 
        ] 1388))
5198 
   (set (reg:SI 108)
5199 
        (unspec_volatile:SI [
5200 
          (match_dup 0)
5201 
          (match_dup 1)
5202 
          (match_dup 2)
5203 
        ] 1390))
5204 
   (set (reg:SI 107)
5205 
        (unspec_volatile:SI [
5206 
          (match_dup 0)
5207 
          (match_dup 1)
5208 
          (match_dup 2)
5209 
        ] 1392))
5210 
   (set (reg:SI 106)
5211 
        (unspec_volatile:SI [
5212 
          (match_dup 0)
5213 
          (match_dup 1)
5214 
          (match_dup 2)
5215 
        ] 1394))
5216 
   (set (reg:SI 105)
5217 
        (unspec_volatile:SI [
5218 
          (match_dup 0)
5219 
          (match_dup 1)
5220 
          (match_dup 2)
5221 
        ] 1396))
5222 
   (set (reg:SI 104)
5223 
        (unspec_volatile:SI [
5224 
          (match_dup 0)
5225 
          (match_dup 1)
5226 
          (match_dup 2)
5227 
        ] 1398))]
5228 
  "CGEN_ENABLE_INSN_P (122)"
5229 
  "cpfmulia1s0.b\\t%0,%1,%2"
5230 
  [(set_attr "may_trap" "no")
5231 
   (set_attr "latency" "0")
5232 
   (set_attr "length" "4")
5233 
   (set_attr "slot" "cop")
5234 
   (set_attr "slots" "p1")
5235 
   (set_attr "stall" "none")])
5236 
 
5237 
 
5238 
(define_insn "cgen_intrinsic_cpfmulia1s0u_b_P1"
5239 
  [(set (reg:SI 111)
5240 
        (unspec_volatile:SI [
5241 
          (match_operand:DI 0 "general_operand" "x")
5242 
          (match_operand:DI 1 "general_operand" "x")
5243 
          (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
5244 
        ] 1400))
5245 
   (set (reg:SI 110)
5246 
        (unspec_volatile:SI [
5247 
          (match_dup 0)
5248 
          (match_dup 1)
5249 
          (match_dup 2)
5250 
        ] 1402))
5251 
   (set (reg:SI 109)
5252 
        (unspec_volatile:SI [
5253 
          (match_dup 0)
5254 
          (match_dup 1)
5255 
          (match_dup 2)
5256 
        ] 1404))
5257 
   (set (reg:SI 108)
5258 
        (unspec_volatile:SI [
5259 
          (match_dup 0)
5260 
          (match_dup 1)
5261 
          (match_dup 2)
5262 
        ] 1406))
5263 
   (set (reg:SI 107)
5264 
        (unspec_volatile:SI [
5265 
          (match_dup 0)
5266 
          (match_dup 1)
5267 
          (match_dup 2)
5268 
        ] 1408))
5269 
   (set (reg:SI 106)
5270 
        (unspec_volatile:SI [
5271 
          (match_dup 0)
5272 
          (match_dup 1)
5273 
          (match_dup 2)
5274 
        ] 1410))
5275 
   (set (reg:SI 105)
5276 
        (unspec_volatile:SI [
5277 
          (match_dup 0)
5278 
          (match_dup 1)
5279 
          (match_dup 2)
5280 
        ] 1412))
5281 
   (set (reg:SI 104)
5282 
        (unspec_volatile:SI [
5283 
          (match_dup 0)
5284 
          (match_dup 1)
5285 
          (match_dup 2)
5286 
        ] 1414))]
5287 
  "CGEN_ENABLE_INSN_P (123)"
5288 
  "cpfmulia1s0u.b\\t%0,%1,%2"
5289 
  [(set_attr "may_trap" "no")
5290 
   (set_attr "latency" "0")
5291 
   (set_attr "length" "4")
5292 
   (set_attr "slot" "cop")
5293 
   (set_attr "slots" "p1")
5294 
   (set_attr "stall" "none")])
5295 
 
5296 
 
5297 
(define_insn "cgen_intrinsic_cpsllia1_P1"
5298 
  [(set (reg:SI 111)
5299 
        (unspec_volatile:SI [
5300 
          (match_operand:SI 0 "cgen_h_uint_5a1_immediate" "")
5301 
        ] 2698))
5302 
   (set (reg:SI 110)
5303 
        (unspec_volatile:SI [
5304 
          (match_dup 0)
5305 
        ] 2700))
5306 
   (set (reg:SI 109)
5307 
        (unspec_volatile:SI [
5308 
          (match_dup 0)
5309 
        ] 2702))
5310 
   (set (reg:SI 108)
5311 
        (unspec_volatile:SI [
5312 
          (match_dup 0)
5313 
        ] 2704))
5314 
   (set (reg:SI 107)
5315 
        (unspec_volatile:SI [
5316 
          (match_dup 0)
5317 
        ] 2706))
5318 
   (set (reg:SI 106)
5319 
        (unspec_volatile:SI [
5320 
          (match_dup 0)
5321 
        ] 2708))
5322 
   (set (reg:SI 105)
5323 
        (unspec_volatile:SI [
5324 
          (match_dup 0)
5325 
        ] 2710))
5326 
   (set (reg:SI 104)
5327 
        (unspec_volatile:SI [
5328 
          (match_dup 0)
5329 
        ] 2712))]
5330 
  "CGEN_ENABLE_INSN_P (124)"
5331 
  "cpsllia1\\t%0"
5332 
  [(set_attr "may_trap" "no")
5333 
   (set_attr "latency" "0")
5334 
   (set_attr "length" "4")
5335 
   (set_attr "slot" "cop")
5336 
   (set_attr "slots" "c3")
5337 
   (set_attr "stall" "none")])
5338 
 
5339 
 
5340 
(define_insn "cgen_intrinsic_cpsllia1_1_p1"
5341 
  [(set (reg:SI 111)
5342 
        (unspec_volatile:SI [
5343 
          (match_operand:SI 0 "cgen_h_uint_5a1_immediate" "")
5344 
        ] 2698))
5345 
   (set (reg:SI 110)
5346 
        (unspec_volatile:SI [
5347 
          (match_dup 0)
5348 
        ] 2700))
5349 
   (set (reg:SI 109)
5350 
        (unspec_volatile:SI [
5351 
          (match_dup 0)
5352 
        ] 2702))
5353 
   (set (reg:SI 108)
5354 
        (unspec_volatile:SI [
5355 
          (match_dup 0)
5356 
        ] 2704))
5357 
   (set (reg:SI 107)
5358 
        (unspec_volatile:SI [
5359 
          (match_dup 0)
5360 
        ] 2706))
5361 
   (set (reg:SI 106)
5362 
        (unspec_volatile:SI [
5363 
          (match_dup 0)
5364 
        ] 2708))
5365 
   (set (reg:SI 105)
5366 
        (unspec_volatile:SI [
5367 
          (match_dup 0)
5368 
        ] 2710))
5369 
   (set (reg:SI 104)
5370 
        (unspec_volatile:SI [
5371 
          (match_dup 0)
5372 
        ] 2712))]
5373 
  "CGEN_ENABLE_INSN_P (125)"
5374 
  "cpsllia1\\t%0"
5375 
  [(set_attr "may_trap" "no")
5376 
   (set_attr "latency" "0")
5377 
   (set_attr "length" "4")
5378 
   (set_attr "slot" "cop")
5379 
   (set_attr "slots" "p1")
5380 
   (set_attr "stall" "none")])
5381 
 
5382 
 
5383 
(define_insn "cgen_intrinsic_cpsraia1_P1"
5384 
  [(set (reg:SI 111)
5385 
        (unspec_volatile:SI [
5386 
          (match_operand:SI 0 "cgen_h_uint_5a1_immediate" "")
5387 
        ] 2714))
5388 
   (set (reg:SI 110)
5389 
        (unspec_volatile:SI [
5390 
          (match_dup 0)
5391 
        ] 2716))
5392 
   (set (reg:SI 109)
5393 
        (unspec_volatile:SI [
5394 
          (match_dup 0)
5395 
        ] 2718))
5396 
   (set (reg:SI 108)
5397 
        (unspec_volatile:SI [
5398 
          (match_dup 0)
5399 
        ] 2720))
5400 
   (set (reg:SI 107)
5401 
        (unspec_volatile:SI [
5402 
          (match_dup 0)
5403 
        ] 2722))
5404 
   (set (reg:SI 106)
5405 
        (unspec_volatile:SI [
5406 
          (match_dup 0)
5407 
        ] 2724))
5408 
   (set (reg:SI 105)
5409 
        (unspec_volatile:SI [
5410 
          (match_dup 0)
5411 
        ] 2726))
5412 
   (set (reg:SI 104)
5413 
        (unspec_volatile:SI [
5414 
          (match_dup 0)
5415 
        ] 2728))]
5416 
  "CGEN_ENABLE_INSN_P (126)"
5417 
  "cpsraia1\\t%0"
5418 
  [(set_attr "may_trap" "no")
5419 
   (set_attr "latency" "0")
5420 
   (set_attr "length" "4")
5421 
   (set_attr "slot" "cop")
5422 
   (set_attr "slots" "c3")
5423 
   (set_attr "stall" "none")])
5424 
 
5425 
 
5426 
(define_insn "cgen_intrinsic_cpsraia1_1_p1"
5427 
  [(set (reg:SI 111)
5428 
        (unspec_volatile:SI [
5429 
          (match_operand:SI 0 "cgen_h_uint_5a1_immediate" "")
5430 
        ] 2714))
5431 
   (set (reg:SI 110)
5432 
        (unspec_volatile:SI [
5433 
          (match_dup 0)
5434 
        ] 2716))
5435 
   (set (reg:SI 109)
5436 
        (unspec_volatile:SI [
5437 
          (match_dup 0)
5438 
        ] 2718))
5439 
   (set (reg:SI 108)
5440 
        (unspec_volatile:SI [
5441 
          (match_dup 0)
5442 
        ] 2720))
5443 
   (set (reg:SI 107)
5444 
        (unspec_volatile:SI [
5445 
          (match_dup 0)
5446 
        ] 2722))
5447 
   (set (reg:SI 106)
5448 
        (unspec_volatile:SI [
5449 
          (match_dup 0)
5450 
        ] 2724))
5451 
   (set (reg:SI 105)
5452 
        (unspec_volatile:SI [
5453 
          (match_dup 0)
5454 
        ] 2726))
5455 
   (set (reg:SI 104)
5456 
        (unspec_volatile:SI [
5457 
          (match_dup 0)
5458 
        ] 2728))]
5459 
  "CGEN_ENABLE_INSN_P (127)"
5460 
  "cpsraia1\\t%0"
5461 
  [(set_attr "may_trap" "no")
5462 
   (set_attr "latency" "0")
5463 
   (set_attr "length" "4")
5464 
   (set_attr "slot" "cop")
5465 
   (set_attr "slots" "p1")
5466 
   (set_attr "stall" "none")])
5467 
 
5468 
 
5469 
(define_insn "cgen_intrinsic_cpsrlia1_P1"
5470 
  [(set (reg:SI 111)
5471 
        (unspec_volatile:SI [
5472 
          (match_operand:SI 0 "cgen_h_uint_5a1_immediate" "")
5473 
        ] 2730))
5474 
   (set (reg:SI 110)
5475 
        (unspec_volatile:SI [
5476 
          (match_dup 0)
5477 
        ] 2732))
5478 
   (set (reg:SI 109)
5479 
        (unspec_volatile:SI [
5480 
          (match_dup 0)
5481 
        ] 2734))
5482 
   (set (reg:SI 108)
5483 
        (unspec_volatile:SI [
5484 
          (match_dup 0)
5485 
        ] 2736))
5486 
   (set (reg:SI 107)
5487 
        (unspec_volatile:SI [
5488 
          (match_dup 0)
5489 
        ] 2738))
5490 
   (set (reg:SI 106)
5491 
        (unspec_volatile:SI [
5492 
          (match_dup 0)
5493 
        ] 2740))
5494 
   (set (reg:SI 105)
5495 
        (unspec_volatile:SI [
5496 
          (match_dup 0)
5497 
        ] 2742))
5498 
   (set (reg:SI 104)
5499 
        (unspec_volatile:SI [
5500 
          (match_dup 0)
5501 
        ] 2744))]
5502 
  "CGEN_ENABLE_INSN_P (128)"
5503 
  "cpsrlia1\\t%0"
5504 
  [(set_attr "may_trap" "no")
5505 
   (set_attr "latency" "0")
5506 
   (set_attr "length" "4")
5507 
   (set_attr "slot" "cop")
5508 
   (set_attr "slots" "c3")
5509 
   (set_attr "stall" "none")])
5510 
 
5511 
 
5512 
(define_insn "cgen_intrinsic_cpsrlia1_1_p1"
5513 
  [(set (reg:SI 111)
5514 
        (unspec_volatile:SI [
5515 
          (match_operand:SI 0 "cgen_h_uint_5a1_immediate" "")
5516 
        ] 2730))
5517 
   (set (reg:SI 110)
5518 
        (unspec_volatile:SI [
5519 
          (match_dup 0)
5520 
        ] 2732))
5521 
   (set (reg:SI 109)
5522 
        (unspec_volatile:SI [
5523 
          (match_dup 0)
5524 
        ] 2734))
5525 
   (set (reg:SI 108)
5526 
        (unspec_volatile:SI [
5527 
          (match_dup 0)
5528 
        ] 2736))
5529 
   (set (reg:SI 107)
5530 
        (unspec_volatile:SI [
5531 
          (match_dup 0)
5532 
        ] 2738))
5533 
   (set (reg:SI 106)
5534 
        (unspec_volatile:SI [
5535 
          (match_dup 0)
5536 
        ] 2740))
5537 
   (set (reg:SI 105)
5538 
        (unspec_volatile:SI [
5539 
          (match_dup 0)
5540 
        ] 2742))
5541 
   (set (reg:SI 104)
5542 
        (unspec_volatile:SI [
5543 
          (match_dup 0)
5544 
        ] 2744))]
5545 
  "CGEN_ENABLE_INSN_P (129)"
5546 
  "cpsrlia1\\t%0"
5547 
  [(set_attr "may_trap" "no")
5548 
   (set_attr "latency" "0")
5549 
   (set_attr "length" "4")
5550 
   (set_attr "slot" "cop")
5551 
   (set_attr "slots" "p1")
5552 
   (set_attr "stall" "none")])
5553 
 
5554 
 
5555 
(define_insn "cgen_intrinsic_cpslla1_C3"
5556 
  [(set (reg:SI 111)
5557 
        (unspec_volatile:SI [
5558 
          (match_operand:DI 0 "general_operand" "x")
5559 
        ] 2746))
5560 
   (set (reg:SI 110)
5561 
        (unspec_volatile:SI [
5562 
          (match_dup 0)
5563 
        ] 2748))
5564 
   (set (reg:SI 109)
5565 
        (unspec_volatile:SI [
5566 
          (match_dup 0)
5567 
        ] 2750))
5568 
   (set (reg:SI 108)
5569 
        (unspec_volatile:SI [
5570 
          (match_dup 0)
5571 
        ] 2752))
5572 
   (set (reg:SI 107)
5573 
        (unspec_volatile:SI [
5574 
          (match_dup 0)
5575 
        ] 2754))
5576 
   (set (reg:SI 106)
5577 
        (unspec_volatile:SI [
5578 
          (match_dup 0)
5579 
        ] 2756))
5580 
   (set (reg:SI 105)
5581 
        (unspec_volatile:SI [
5582 
          (match_dup 0)
5583 
        ] 2758))
5584 
   (set (reg:SI 104)
5585 
        (unspec_volatile:SI [
5586 
          (match_dup 0)
5587 
        ] 2760))]
5588 
  "CGEN_ENABLE_INSN_P (130)"
5589 
  "cpslla1\\t%0"
5590 
  [(set_attr "may_trap" "no")
5591 
   (set_attr "latency" "0")
5592 
   (set_attr "length" "4")
5593 
   (set_attr "slot" "cop")
5594 
   (set_attr "slots" "c3")
5595 
   (set_attr "stall" "none")])
5596 
 
5597 
 
5598 
(define_insn "cgen_intrinsic_cpslla1_P1"
5599 
  [(set (reg:SI 111)
5600 
        (unspec_volatile:SI [
5601 
          (match_operand:DI 0 "general_operand" "x")
5602 
        ] 2746))
5603 
   (set (reg:SI 110)
5604 
        (unspec_volatile:SI [
5605 
          (match_dup 0)
5606 
        ] 2748))
5607 
   (set (reg:SI 109)
5608 
        (unspec_volatile:SI [
5609 
          (match_dup 0)
5610 
        ] 2750))
5611 
   (set (reg:SI 108)
5612 
        (unspec_volatile:SI [
5613 
          (match_dup 0)
5614 
        ] 2752))
5615 
   (set (reg:SI 107)
5616 
        (unspec_volatile:SI [
5617 
          (match_dup 0)
5618 
        ] 2754))
5619 
   (set (reg:SI 106)
5620 
        (unspec_volatile:SI [
5621 
          (match_dup 0)
5622 
        ] 2756))
5623 
   (set (reg:SI 105)
5624 
        (unspec_volatile:SI [
5625 
          (match_dup 0)
5626 
        ] 2758))
5627 
   (set (reg:SI 104)
5628 
        (unspec_volatile:SI [
5629 
          (match_dup 0)
5630 
        ] 2760))]
5631 
  "CGEN_ENABLE_INSN_P (131)"
5632 
  "cpslla1\\t%0"
5633 
  [(set_attr "may_trap" "no")
5634 
   (set_attr "latency" "0")
5635 
   (set_attr "length" "4")
5636 
   (set_attr "slot" "cop")
5637 
   (set_attr "slots" "p1")
5638 
   (set_attr "stall" "none")])
5639 
 
5640 
 
5641 
(define_insn "cgen_intrinsic_cpsraa1_C3"
5642 
  [(set (reg:SI 111)
5643 
        (unspec_volatile:SI [
5644 
          (match_operand:DI 0 "general_operand" "x")
5645 
        ] 2762))
5646 
   (set (reg:SI 110)
5647 
        (unspec_volatile:SI [
5648 
          (match_dup 0)
5649 
        ] 2764))
5650 
   (set (reg:SI 109)
5651 
        (unspec_volatile:SI [
5652 
          (match_dup 0)
5653 
        ] 2766))
5654 
   (set (reg:SI 108)
5655 
        (unspec_volatile:SI [
5656 
          (match_dup 0)
5657 
        ] 2768))
5658 
   (set (reg:SI 107)
5659 
        (unspec_volatile:SI [
5660 
          (match_dup 0)
5661 
        ] 2770))
5662 
   (set (reg:SI 106)
5663 
        (unspec_volatile:SI [
5664 
          (match_dup 0)
5665 
        ] 2772))
5666 
   (set (reg:SI 105)
5667 
        (unspec_volatile:SI [
5668 
          (match_dup 0)
5669 
        ] 2774))
5670 
   (set (reg:SI 104)
5671 
        (unspec_volatile:SI [
5672 
          (match_dup 0)
5673 
        ] 2776))]
5674 
  "CGEN_ENABLE_INSN_P (132)"
5675 
  "cpsraa1\\t%0"
5676 
  [(set_attr "may_trap" "no")
5677 
   (set_attr "latency" "0")
5678 
   (set_attr "length" "4")
5679 
   (set_attr "slot" "cop")
5680 
   (set_attr "slots" "c3")
5681 
   (set_attr "stall" "none")])
5682 
 
5683 
 
5684 
(define_insn "cgen_intrinsic_cpsraa1_P1"
5685 
  [(set (reg:SI 111)
5686 
        (unspec_volatile:SI [
5687 
          (match_operand:DI 0 "general_operand" "x")
5688 
        ] 2762))
5689 
   (set (reg:SI 110)
5690 
        (unspec_volatile:SI [
5691 
          (match_dup 0)
5692 
        ] 2764))
5693 
   (set (reg:SI 109)
5694 
        (unspec_volatile:SI [
5695 
          (match_dup 0)
5696 
        ] 2766))
5697 
   (set (reg:SI 108)
5698 
        (unspec_volatile:SI [
5699 
          (match_dup 0)
5700 
        ] 2768))
5701 
   (set (reg:SI 107)
5702 
        (unspec_volatile:SI [
5703 
          (match_dup 0)
5704 
        ] 2770))
5705 
   (set (reg:SI 106)
5706 
        (unspec_volatile:SI [
5707 
          (match_dup 0)
5708 
        ] 2772))
5709 
   (set (reg:SI 105)
5710 
        (unspec_volatile:SI [
5711 
          (match_dup 0)
5712 
        ] 2774))
5713 
   (set (reg:SI 104)
5714 
        (unspec_volatile:SI [
5715 
          (match_dup 0)
5716 
        ] 2776))]
5717 
  "CGEN_ENABLE_INSN_P (133)"
5718 
  "cpsraa1\\t%0"
5719 
  [(set_attr "may_trap" "no")
5720 
   (set_attr "latency" "0")
5721 
   (set_attr "length" "4")
5722 
   (set_attr "slot" "cop")
5723 
   (set_attr "slots" "p1")
5724 
   (set_attr "stall" "none")])
5725 
 
5726 
 
5727 
(define_insn "cgen_intrinsic_cpsrla1_C3"
5728 
  [(set (reg:SI 111)
5729 
        (unspec_volatile:SI [
5730 
          (match_operand:DI 0 "general_operand" "x")
5731 
        ] 2778))
5732 
   (set (reg:SI 110)
5733 
        (unspec_volatile:SI [
5734 
          (match_dup 0)
5735 
        ] 2780))
5736 
   (set (reg:SI 109)
5737 
        (unspec_volatile:SI [
5738 
          (match_dup 0)
5739 
        ] 2782))
5740 
   (set (reg:SI 108)
5741 
        (unspec_volatile:SI [
5742 
          (match_dup 0)
5743 
        ] 2784))
5744 
   (set (reg:SI 107)
5745 
        (unspec_volatile:SI [
5746 
          (match_dup 0)
5747 
        ] 2786))
5748 
   (set (reg:SI 106)
5749 
        (unspec_volatile:SI [
5750 
          (match_dup 0)
5751 
        ] 2788))
5752 
   (set (reg:SI 105)
5753 
        (unspec_volatile:SI [
5754 
          (match_dup 0)
5755 
        ] 2790))
5756 
   (set (reg:SI 104)
5757 
        (unspec_volatile:SI [
5758 
          (match_dup 0)
5759 
        ] 2792))]
5760 
  "CGEN_ENABLE_INSN_P (134)"
5761 
  "cpsrla1\\t%0"
5762 
  [(set_attr "may_trap" "no")
5763 
   (set_attr "latency" "0")
5764 
   (set_attr "length" "4")
5765 
   (set_attr "slot" "cop")
5766 
   (set_attr "slots" "c3")
5767 
   (set_attr "stall" "none")])
5768 
 
5769 
 
5770 
(define_insn "cgen_intrinsic_cpsrla1_P1"
5771 
  [(set (reg:SI 111)
5772 
        (unspec_volatile:SI [
5773 
          (match_operand:DI 0 "general_operand" "x")
5774 
        ] 2778))
5775 
   (set (reg:SI 110)
5776 
        (unspec_volatile:SI [
5777 
          (match_dup 0)
5778 
        ] 2780))
5779 
   (set (reg:SI 109)
5780 
        (unspec_volatile:SI [
5781 
          (match_dup 0)
5782 
        ] 2782))
5783 
   (set (reg:SI 108)
5784 
        (unspec_volatile:SI [
5785 
          (match_dup 0)
5786 
        ] 2784))
5787 
   (set (reg:SI 107)
5788 
        (unspec_volatile:SI [
5789 
          (match_dup 0)
5790 
        ] 2786))
5791 
   (set (reg:SI 106)
5792 
        (unspec_volatile:SI [
5793 
          (match_dup 0)
5794 
        ] 2788))
5795 
   (set (reg:SI 105)
5796 
        (unspec_volatile:SI [
5797 
          (match_dup 0)
5798 
        ] 2790))
5799 
   (set (reg:SI 104)
5800 
        (unspec_volatile:SI [
5801 
          (match_dup 0)
5802 
        ] 2792))]
5803 
  "CGEN_ENABLE_INSN_P (135)"
5804 
  "cpsrla1\\t%0"
5805 
  [(set_attr "may_trap" "no")
5806 
   (set_attr "latency" "0")
5807 
   (set_attr "length" "4")
5808 
   (set_attr "slot" "cop")
5809 
   (set_attr "slots" "p1")
5810 
   (set_attr "stall" "none")])
5811 
 
5812 
 
5813 
(define_insn "cgen_intrinsic_cpacswp_P1"
5814 
  [(set (reg:SI 111)
5815 
        (unspec_volatile:SI [
5816 
          (const_int 0)
5817 
        ] 1416))
5818 
   (set (reg:SI 110)
5819 
        (unspec_volatile:SI [
5820 
          (const_int 0)
5821 
        ] 1418))
5822 
   (set (reg:SI 109)
5823 
        (unspec_volatile:SI [
5824 
          (const_int 0)
5825 
        ] 1420))
5826 
   (set (reg:SI 108)
5827 
        (unspec_volatile:SI [
5828 
          (const_int 0)
5829 
        ] 1422))
5830 
   (set (reg:SI 107)
5831 
        (unspec_volatile:SI [
5832 
          (const_int 0)
5833 
        ] 1424))
5834 
   (set (reg:SI 106)
5835 
        (unspec_volatile:SI [
5836 
          (const_int 0)
5837 
        ] 1426))
5838 
   (set (reg:SI 105)
5839 
        (unspec_volatile:SI [
5840 
          (const_int 0)
5841 
        ] 1428))
5842 
   (set (reg:SI 104)
5843 
        (unspec_volatile:SI [
5844 
          (const_int 0)
5845 
        ] 1430))
5846 
   (set (reg:SI 103)
5847 
        (unspec_volatile:SI [
5848 
          (const_int 0)
5849 
        ] 1432))
5850 
   (set (reg:SI 102)
5851 
        (unspec_volatile:SI [
5852 
          (const_int 0)
5853 
        ] 1434))
5854 
   (set (reg:SI 101)
5855 
        (unspec_volatile:SI [
5856 
          (const_int 0)
5857 
        ] 1436))
5858 
   (set (reg:SI 100)
5859 
        (unspec_volatile:SI [
5860 
          (const_int 0)
5861 
        ] 1438))
5862 
   (set (reg:SI 99)
5863 
        (unspec_volatile:SI [
5864 
          (const_int 0)
5865 
        ] 1440))
5866 
   (set (reg:SI 98)
5867 
        (unspec_volatile:SI [
5868 
          (const_int 0)
5869 
        ] 1442))
5870 
   (set (reg:SI 97)
5871 
        (unspec_volatile:SI [
5872 
          (const_int 0)
5873 
        ] 1444))
5874 
   (set (reg:SI 96)
5875 
        (unspec_volatile:SI [
5876 
          (const_int 0)
5877 
        ] 1446))]
5878 
  "CGEN_ENABLE_INSN_P (136)"
5879 
  "cpacswp"
5880 
  [(set_attr "may_trap" "no")
5881 
   (set_attr "latency" "0")
5882 
   (set_attr "length" "4")
5883 
   (set_attr "slot" "cop")
5884 
   (set_attr "slots" "p1")
5885 
   (set_attr "stall" "none")])
5886 
 
5887 
 
5888 
(define_insn "cgen_intrinsic_cpaccpa1_P1"
5889 
  [(set (reg:SI 111)
5890 
        (unspec_volatile:SI [
5891 
          (const_int 0)
5892 
        ] 1448))
5893 
   (set (reg:SI 110)
5894 
        (unspec_volatile:SI [
5895 
          (const_int 0)
5896 
        ] 1450))
5897 
   (set (reg:SI 109)
5898 
        (unspec_volatile:SI [
5899 
          (const_int 0)
5900 
        ] 1452))
5901 
   (set (reg:SI 108)
5902 
        (unspec_volatile:SI [
5903 
          (const_int 0)
5904 
        ] 1454))
5905 
   (set (reg:SI 107)
5906 
        (unspec_volatile:SI [
5907 
          (const_int 0)
5908 
        ] 1456))
5909 
   (set (reg:SI 106)
5910 
        (unspec_volatile:SI [
5911 
          (const_int 0)
5912 
        ] 1458))
5913 
   (set (reg:SI 105)
5914 
        (unspec_volatile:SI [
5915 
          (const_int 0)
5916 
        ] 1460))
5917 
   (set (reg:SI 104)
5918 
        (unspec_volatile:SI [
5919 
          (const_int 0)
5920 
        ] 1462))]
5921 
  "CGEN_ENABLE_INSN_P (137)"
5922 
  "cpaccpa1"
5923 
  [(set_attr "may_trap" "no")
5924 
   (set_attr "latency" "0")
5925 
   (set_attr "length" "4")
5926 
   (set_attr "slot" "cop")
5927 
   (set_attr "slots" "p1")
5928 
   (set_attr "stall" "none")])
5929 
 
5930 
 
5931 
(define_insn "cgen_intrinsic_cpacsuma1_P1"
5932 
  [(set (reg:SI 87)
5933 
        (unspec_volatile:SI [
5934 
          (const_int 0)
5935 
        ] 1464))
5936 
   (set (reg:SI 111)
5937 
        (unspec_volatile:SI [
5938 
          (const_int 0)
5939 
        ] 1466))
5940 
   (set (reg:SI 110)
5941 
        (unspec_volatile:SI [
5942 
          (const_int 0)
5943 
        ] 1468))
5944 
   (set (reg:SI 109)
5945 
        (unspec_volatile:SI [
5946 
          (const_int 0)
5947 
        ] 1470))
5948 
   (set (reg:SI 108)
5949 
        (unspec_volatile:SI [
5950 
          (const_int 0)
5951 
        ] 1472))
5952 
   (set (reg:SI 107)
5953 
        (unspec_volatile:SI [
5954 
          (const_int 0)
5955 
        ] 1474))
5956 
   (set (reg:SI 106)
5957 
        (unspec_volatile:SI [
5958 
          (const_int 0)
5959 
        ] 1476))
5960 
   (set (reg:SI 105)
5961 
        (unspec_volatile:SI [
5962 
          (const_int 0)
5963 
        ] 1478))
5964 
   (set (reg:SI 104)
5965 
        (unspec_volatile:SI [
5966 
          (const_int 0)
5967 
        ] 1480))]
5968 
  "CGEN_ENABLE_INSN_P (138)"
5969 
  "cpacsuma1"
5970 
  [(set_attr "may_trap" "no")
5971 
   (set_attr "latency" "0")
5972 
   (set_attr "length" "4")
5973 
   (set_attr "slot" "cop")
5974 
   (set_attr "slots" "p1")
5975 
   (set_attr "stall" "none")])
5976 
 
5977 
 
5978 
(define_insn "cgen_intrinsic_cpmovhla1_w_C3"
5979 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
5980 
        (unspec_volatile:DI [
5981 
          (const_int 0)
5982 
        ] 2794))]
5983 
  "CGEN_ENABLE_INSN_P (139)"
5984 
  "cpmovhla1.w\\t%0"
5985 
  [(set_attr "may_trap" "no")
5986 
   (set_attr "latency" "0")
5987 
   (set_attr "length" "4")
5988 
   (set_attr "slot" "cop")
5989 
   (set_attr "slots" "c3")
5990 
   (set_attr "stall" "none")])
5991 
 
5992 
 
5993 
(define_insn "cgen_intrinsic_cpmovhla1_w_P1"
5994 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
5995 
        (unspec_volatile:DI [
5996 
          (const_int 0)
5997 
        ] 2794))]
5998 
  "CGEN_ENABLE_INSN_P (140)"
5999 
  "cpmovhla1.w\\t%0"
6000 
  [(set_attr "may_trap" "no")
6001 
   (set_attr "latency" "0")
6002 
   (set_attr "length" "4")
6003 
   (set_attr "slot" "cop")
6004 
   (set_attr "slots" "p1")
6005 
   (set_attr "stall" "none")])
6006 
 
6007 
 
6008 
(define_insn "cgen_intrinsic_cpmovhua1_w_C3"
6009 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6010 
        (unspec_volatile:DI [
6011 
          (const_int 0)
6012 
        ] 2796))]
6013 
  "CGEN_ENABLE_INSN_P (141)"
6014 
  "cpmovhua1.w\\t%0"
6015 
  [(set_attr "may_trap" "no")
6016 
   (set_attr "latency" "0")
6017 
   (set_attr "length" "4")
6018 
   (set_attr "slot" "cop")
6019 
   (set_attr "slots" "c3")
6020 
   (set_attr "stall" "none")])
6021 
 
6022 
 
6023 
(define_insn "cgen_intrinsic_cpmovhua1_w_P1"
6024 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6025 
        (unspec_volatile:DI [
6026 
          (const_int 0)
6027 
        ] 2796))]
6028 
  "CGEN_ENABLE_INSN_P (142)"
6029 
  "cpmovhua1.w\\t%0"
6030 
  [(set_attr "may_trap" "no")
6031 
   (set_attr "latency" "0")
6032 
   (set_attr "length" "4")
6033 
   (set_attr "slot" "cop")
6034 
   (set_attr "slots" "p1")
6035 
   (set_attr "stall" "none")])
6036 
 
6037 
 
6038 
(define_insn "cgen_intrinsic_cppackla1_w_C3"
6039 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6040 
        (unspec_volatile:DI [
6041 
          (const_int 0)
6042 
        ] 2798))]
6043 
  "CGEN_ENABLE_INSN_P (143)"
6044 
  "cppackla1.w\\t%0"
6045 
  [(set_attr "may_trap" "no")
6046 
   (set_attr "latency" "0")
6047 
   (set_attr "length" "4")
6048 
   (set_attr "slot" "cop")
6049 
   (set_attr "slots" "c3")
6050 
   (set_attr "stall" "none")])
6051 
 
6052 
 
6053 
(define_insn "cgen_intrinsic_cppackla1_w_P1"
6054 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6055 
        (unspec_volatile:DI [
6056 
          (const_int 0)
6057 
        ] 2798))]
6058 
  "CGEN_ENABLE_INSN_P (144)"
6059 
  "cppackla1.w\\t%0"
6060 
  [(set_attr "may_trap" "no")
6061 
   (set_attr "latency" "0")
6062 
   (set_attr "length" "4")
6063 
   (set_attr "slot" "cop")
6064 
   (set_attr "slots" "p1")
6065 
   (set_attr "stall" "none")])
6066 
 
6067 
 
6068 
(define_insn "cgen_intrinsic_cppackua1_w_C3"
6069 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6070 
        (unspec_volatile:DI [
6071 
          (const_int 0)
6072 
        ] 2800))]
6073 
  "CGEN_ENABLE_INSN_P (145)"
6074 
  "cppackua1.w\\t%0"
6075 
  [(set_attr "may_trap" "no")
6076 
   (set_attr "latency" "0")
6077 
   (set_attr "length" "4")
6078 
   (set_attr "slot" "cop")
6079 
   (set_attr "slots" "c3")
6080 
   (set_attr "stall" "none")])
6081 
 
6082 
 
6083 
(define_insn "cgen_intrinsic_cppackua1_w_P1"
6084 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6085 
        (unspec_volatile:DI [
6086 
          (const_int 0)
6087 
        ] 2800))]
6088 
  "CGEN_ENABLE_INSN_P (146)"
6089 
  "cppackua1.w\\t%0"
6090 
  [(set_attr "may_trap" "no")
6091 
   (set_attr "latency" "0")
6092 
   (set_attr "length" "4")
6093 
   (set_attr "slot" "cop")
6094 
   (set_attr "slots" "p1")
6095 
   (set_attr "stall" "none")])
6096 
 
6097 
 
6098 
(define_insn "cgen_intrinsic_cppackla1_h_C3"
6099 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6100 
        (unspec_volatile:DI [
6101 
          (const_int 0)
6102 
        ] 2802))]
6103 
  "CGEN_ENABLE_INSN_P (147)"
6104 
  "cppackla1.h\\t%0"
6105 
  [(set_attr "may_trap" "no")
6106 
   (set_attr "latency" "0")
6107 
   (set_attr "length" "4")
6108 
   (set_attr "slot" "cop")
6109 
   (set_attr "slots" "c3")
6110 
   (set_attr "stall" "none")])
6111 
 
6112 
 
6113 
(define_insn "cgen_intrinsic_cppackla1_h_P1"
6114 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6115 
        (unspec_volatile:DI [
6116 
          (const_int 0)
6117 
        ] 2802))]
6118 
  "CGEN_ENABLE_INSN_P (148)"
6119 
  "cppackla1.h\\t%0"
6120 
  [(set_attr "may_trap" "no")
6121 
   (set_attr "latency" "0")
6122 
   (set_attr "length" "4")
6123 
   (set_attr "slot" "cop")
6124 
   (set_attr "slots" "p1")
6125 
   (set_attr "stall" "none")])
6126 
 
6127 
 
6128 
(define_insn "cgen_intrinsic_cppackua1_h_C3"
6129 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6130 
        (unspec_volatile:DI [
6131 
          (const_int 0)
6132 
        ] 2804))]
6133 
  "CGEN_ENABLE_INSN_P (149)"
6134 
  "cppackua1.h\\t%0"
6135 
  [(set_attr "may_trap" "no")
6136 
   (set_attr "latency" "0")
6137 
   (set_attr "length" "4")
6138 
   (set_attr "slot" "cop")
6139 
   (set_attr "slots" "c3")
6140 
   (set_attr "stall" "none")])
6141 
 
6142 
 
6143 
(define_insn "cgen_intrinsic_cppackua1_h_P1"
6144 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6145 
        (unspec_volatile:DI [
6146 
          (const_int 0)
6147 
        ] 2804))]
6148 
  "CGEN_ENABLE_INSN_P (150)"
6149 
  "cppackua1.h\\t%0"
6150 
  [(set_attr "may_trap" "no")
6151 
   (set_attr "latency" "0")
6152 
   (set_attr "length" "4")
6153 
   (set_attr "slot" "cop")
6154 
   (set_attr "slots" "p1")
6155 
   (set_attr "stall" "none")])
6156 
 
6157 
 
6158 
(define_insn "cgen_intrinsic_cppacka1_b_C3"
6159 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6160 
        (unspec_volatile:DI [
6161 
          (const_int 0)
6162 
        ] 2806))]
6163 
  "CGEN_ENABLE_INSN_P (151)"
6164 
  "cppacka1.b\\t%0"
6165 
  [(set_attr "may_trap" "no")
6166 
   (set_attr "latency" "0")
6167 
   (set_attr "length" "4")
6168 
   (set_attr "slot" "cop")
6169 
   (set_attr "slots" "c3")
6170 
   (set_attr "stall" "none")])
6171 
 
6172 
 
6173 
(define_insn "cgen_intrinsic_cppacka1_b_P1"
6174 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6175 
        (unspec_volatile:DI [
6176 
          (const_int 0)
6177 
        ] 2806))]
6178 
  "CGEN_ENABLE_INSN_P (152)"
6179 
  "cppacka1.b\\t%0"
6180 
  [(set_attr "may_trap" "no")
6181 
   (set_attr "latency" "0")
6182 
   (set_attr "length" "4")
6183 
   (set_attr "slot" "cop")
6184 
   (set_attr "slots" "p1")
6185 
   (set_attr "stall" "none")])
6186 
 
6187 
 
6188 
(define_insn "cgen_intrinsic_cppacka1u_b_C3"
6189 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6190 
        (unspec_volatile:DI [
6191 
          (const_int 0)
6192 
        ] 2808))]
6193 
  "CGEN_ENABLE_INSN_P (153)"
6194 
  "cppacka1u.b\\t%0"
6195 
  [(set_attr "may_trap" "no")
6196 
   (set_attr "latency" "0")
6197 
   (set_attr "length" "4")
6198 
   (set_attr "slot" "cop")
6199 
   (set_attr "slots" "c3")
6200 
   (set_attr "stall" "none")])
6201 
 
6202 
 
6203 
(define_insn "cgen_intrinsic_cppacka1u_b_P1"
6204 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6205 
        (unspec_volatile:DI [
6206 
          (const_int 0)
6207 
        ] 2808))]
6208 
  "CGEN_ENABLE_INSN_P (154)"
6209 
  "cppacka1u.b\\t%0"
6210 
  [(set_attr "may_trap" "no")
6211 
   (set_attr "latency" "0")
6212 
   (set_attr "length" "4")
6213 
   (set_attr "slot" "cop")
6214 
   (set_attr "slots" "p1")
6215 
   (set_attr "stall" "none")])
6216 
 
6217 
 
6218 
(define_insn "cgen_intrinsic_cpmovlla1_w_C3"
6219 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6220 
        (unspec_volatile:DI [
6221 
          (const_int 0)
6222 
        ] 2810))]
6223 
  "CGEN_ENABLE_INSN_P (155)"
6224 
  "cpmovlla1.w\\t%0"
6225 
  [(set_attr "may_trap" "no")
6226 
   (set_attr "latency" "0")
6227 
   (set_attr "length" "4")
6228 
   (set_attr "slot" "cop")
6229 
   (set_attr "slots" "c3")
6230 
   (set_attr "stall" "none")])
6231 
 
6232 
 
6233 
(define_insn "cgen_intrinsic_cpmovlla1_w_P1"
6234 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6235 
        (unspec_volatile:DI [
6236 
          (const_int 0)
6237 
        ] 2810))]
6238 
  "CGEN_ENABLE_INSN_P (156)"
6239 
  "cpmovlla1.w\\t%0"
6240 
  [(set_attr "may_trap" "no")
6241 
   (set_attr "latency" "0")
6242 
   (set_attr "length" "4")
6243 
   (set_attr "slot" "cop")
6244 
   (set_attr "slots" "p1")
6245 
   (set_attr "stall" "none")])
6246 
 
6247 
 
6248 
(define_insn "cgen_intrinsic_cpmovlua1_w_C3"
6249 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6250 
        (unspec_volatile:DI [
6251 
          (const_int 0)
6252 
        ] 2812))]
6253 
  "CGEN_ENABLE_INSN_P (157)"
6254 
  "cpmovlua1.w\\t%0"
6255 
  [(set_attr "may_trap" "no")
6256 
   (set_attr "latency" "0")
6257 
   (set_attr "length" "4")
6258 
   (set_attr "slot" "cop")
6259 
   (set_attr "slots" "c3")
6260 
   (set_attr "stall" "none")])
6261 
 
6262 
 
6263 
(define_insn "cgen_intrinsic_cpmovlua1_w_P1"
6264 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6265 
        (unspec_volatile:DI [
6266 
          (const_int 0)
6267 
        ] 2812))]
6268 
  "CGEN_ENABLE_INSN_P (158)"
6269 
  "cpmovlua1.w\\t%0"
6270 
  [(set_attr "may_trap" "no")
6271 
   (set_attr "latency" "0")
6272 
   (set_attr "length" "4")
6273 
   (set_attr "slot" "cop")
6274 
   (set_attr "slots" "p1")
6275 
   (set_attr "stall" "none")])
6276 
 
6277 
 
6278 
(define_insn "cgen_intrinsic_cpmovula1_w_C3"
6279 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6280 
        (unspec_volatile:DI [
6281 
          (const_int 0)
6282 
        ] 2814))]
6283 
  "CGEN_ENABLE_INSN_P (159)"
6284 
  "cpmovula1.w\\t%0"
6285 
  [(set_attr "may_trap" "no")
6286 
   (set_attr "latency" "0")
6287 
   (set_attr "length" "4")
6288 
   (set_attr "slot" "cop")
6289 
   (set_attr "slots" "c3")
6290 
   (set_attr "stall" "none")])
6291 
 
6292 
 
6293 
(define_insn "cgen_intrinsic_cpmovula1_w_P1"
6294 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6295 
        (unspec_volatile:DI [
6296 
          (const_int 0)
6297 
        ] 2814))]
6298 
  "CGEN_ENABLE_INSN_P (160)"
6299 
  "cpmovula1.w\\t%0"
6300 
  [(set_attr "may_trap" "no")
6301 
   (set_attr "latency" "0")
6302 
   (set_attr "length" "4")
6303 
   (set_attr "slot" "cop")
6304 
   (set_attr "slots" "p1")
6305 
   (set_attr "stall" "none")])
6306 
 
6307 
 
6308 
(define_insn "cgen_intrinsic_cpmovuua1_w_C3"
6309 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6310 
        (unspec_volatile:DI [
6311 
          (const_int 0)
6312 
        ] 2816))]
6313 
  "CGEN_ENABLE_INSN_P (161)"
6314 
  "cpmovuua1.w\\t%0"
6315 
  [(set_attr "may_trap" "no")
6316 
   (set_attr "latency" "0")
6317 
   (set_attr "length" "4")
6318 
   (set_attr "slot" "cop")
6319 
   (set_attr "slots" "c3")
6320 
   (set_attr "stall" "none")])
6321 
 
6322 
 
6323 
(define_insn "cgen_intrinsic_cpmovuua1_w_P1"
6324 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6325 
        (unspec_volatile:DI [
6326 
          (const_int 0)
6327 
        ] 2816))]
6328 
  "CGEN_ENABLE_INSN_P (162)"
6329 
  "cpmovuua1.w\\t%0"
6330 
  [(set_attr "may_trap" "no")
6331 
   (set_attr "latency" "0")
6332 
   (set_attr "length" "4")
6333 
   (set_attr "slot" "cop")
6334 
   (set_attr "slots" "p1")
6335 
   (set_attr "stall" "none")])
6336 
 
6337 
 
6338 
(define_insn "cgen_intrinsic_cpmovla1_h_C3"
6339 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6340 
        (unspec_volatile:DI [
6341 
          (const_int 0)
6342 
        ] 2818))]
6343 
  "CGEN_ENABLE_INSN_P (163)"
6344 
  "cpmovla1.h\\t%0"
6345 
  [(set_attr "may_trap" "no")
6346 
   (set_attr "latency" "0")
6347 
   (set_attr "length" "4")
6348 
   (set_attr "slot" "cop")
6349 
   (set_attr "slots" "c3")
6350 
   (set_attr "stall" "none")])
6351 
 
6352 
 
6353 
(define_insn "cgen_intrinsic_cpmovla1_h_P1"
6354 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6355 
        (unspec_volatile:DI [
6356 
          (const_int 0)
6357 
        ] 2818))]
6358 
  "CGEN_ENABLE_INSN_P (164)"
6359 
  "cpmovla1.h\\t%0"
6360 
  [(set_attr "may_trap" "no")
6361 
   (set_attr "latency" "0")
6362 
   (set_attr "length" "4")
6363 
   (set_attr "slot" "cop")
6364 
   (set_attr "slots" "p1")
6365 
   (set_attr "stall" "none")])
6366 
 
6367 
 
6368 
(define_insn "cgen_intrinsic_cpmovua1_h_C3"
6369 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6370 
        (unspec_volatile:DI [
6371 
          (const_int 0)
6372 
        ] 2820))]
6373 
  "CGEN_ENABLE_INSN_P (165)"
6374 
  "cpmovua1.h\\t%0"
6375 
  [(set_attr "may_trap" "no")
6376 
   (set_attr "latency" "0")
6377 
   (set_attr "length" "4")
6378 
   (set_attr "slot" "cop")
6379 
   (set_attr "slots" "c3")
6380 
   (set_attr "stall" "none")])
6381 
 
6382 
 
6383 
(define_insn "cgen_intrinsic_cpmovua1_h_P1"
6384 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6385 
        (unspec_volatile:DI [
6386 
          (const_int 0)
6387 
        ] 2820))]
6388 
  "CGEN_ENABLE_INSN_P (166)"
6389 
  "cpmovua1.h\\t%0"
6390 
  [(set_attr "may_trap" "no")
6391 
   (set_attr "latency" "0")
6392 
   (set_attr "length" "4")
6393 
   (set_attr "slot" "cop")
6394 
   (set_attr "slots" "p1")
6395 
   (set_attr "stall" "none")])
6396 
 
6397 
 
6398 
(define_insn "cgen_intrinsic_cpmova1_b_C3"
6399 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6400 
        (unspec_volatile:DI [
6401 
          (const_int 0)
6402 
        ] 2822))]
6403 
  "CGEN_ENABLE_INSN_P (167)"
6404 
  "cpmova1.b\\t%0"
6405 
  [(set_attr "may_trap" "no")
6406 
   (set_attr "latency" "0")
6407 
   (set_attr "length" "4")
6408 
   (set_attr "slot" "cop")
6409 
   (set_attr "slots" "c3")
6410 
   (set_attr "stall" "none")])
6411 
 
6412 
 
6413 
(define_insn "cgen_intrinsic_cpmova1_b_P1"
6414 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6415 
        (unspec_volatile:DI [
6416 
          (const_int 0)
6417 
        ] 2822))]
6418 
  "CGEN_ENABLE_INSN_P (168)"
6419 
  "cpmova1.b\\t%0"
6420 
  [(set_attr "may_trap" "no")
6421 
   (set_attr "latency" "0")
6422 
   (set_attr "length" "4")
6423 
   (set_attr "slot" "cop")
6424 
   (set_attr "slots" "p1")
6425 
   (set_attr "stall" "none")])
6426 
 
6427 
 
6428 
(define_insn "cgen_intrinsic_cpsetla1_w_C3"
6429 
  [(set (reg:SI 107)
6430 
        (unspec_volatile:SI [
6431 
          (match_operand:DI 0 "general_operand" "x")
6432 
          (match_operand:DI 1 "general_operand" "x")
6433 
        ] 2824))
6434 
   (set (reg:SI 106)
6435 
        (unspec_volatile:SI [
6436 
          (match_dup 0)
6437 
          (match_dup 1)
6438 
        ] 2826))
6439 
   (set (reg:SI 105)
6440 
        (unspec_volatile:SI [
6441 
          (match_dup 0)
6442 
          (match_dup 1)
6443 
        ] 2828))
6444 
   (set (reg:SI 104)
6445 
        (unspec_volatile:SI [
6446 
          (match_dup 0)
6447 
          (match_dup 1)
6448 
        ] 2830))]
6449 
  "CGEN_ENABLE_INSN_P (169)"
6450 
  "cpsetla1.w\\t%0,%1"
6451 
  [(set_attr "may_trap" "no")
6452 
   (set_attr "latency" "0")
6453 
   (set_attr "length" "4")
6454 
   (set_attr "slot" "cop")
6455 
   (set_attr "slots" "c3")
6456 
   (set_attr "stall" "none")])
6457 
 
6458 
 
6459 
(define_insn "cgen_intrinsic_cpsetla1_w_P1"
6460 
  [(set (reg:SI 107)
6461 
        (unspec_volatile:SI [
6462 
          (match_operand:DI 0 "general_operand" "x")
6463 
          (match_operand:DI 1 "general_operand" "x")
6464 
        ] 2824))
6465 
   (set (reg:SI 106)
6466 
        (unspec_volatile:SI [
6467 
          (match_dup 0)
6468 
          (match_dup 1)
6469 
        ] 2826))
6470 
   (set (reg:SI 105)
6471 
        (unspec_volatile:SI [
6472 
          (match_dup 0)
6473 
          (match_dup 1)
6474 
        ] 2828))
6475 
   (set (reg:SI 104)
6476 
        (unspec_volatile:SI [
6477 
          (match_dup 0)
6478 
          (match_dup 1)
6479 
        ] 2830))]
6480 
  "CGEN_ENABLE_INSN_P (170)"
6481 
  "cpsetla1.w\\t%0,%1"
6482 
  [(set_attr "may_trap" "no")
6483 
   (set_attr "latency" "0")
6484 
   (set_attr "length" "4")
6485 
   (set_attr "slot" "cop")
6486 
   (set_attr "slots" "p1")
6487 
   (set_attr "stall" "none")])
6488 
 
6489 
 
6490 
(define_insn "cgen_intrinsic_cpsetua1_w_C3"
6491 
  [(set (reg:SI 111)
6492 
        (unspec_volatile:SI [
6493 
          (match_operand:DI 0 "general_operand" "x")
6494 
          (match_operand:DI 1 "general_operand" "x")
6495 
        ] 2832))
6496 
   (set (reg:SI 110)
6497 
        (unspec_volatile:SI [
6498 
          (match_dup 0)
6499 
          (match_dup 1)
6500 
        ] 2834))
6501 
   (set (reg:SI 109)
6502 
        (unspec_volatile:SI [
6503 
          (match_dup 0)
6504 
          (match_dup 1)
6505 
        ] 2836))
6506 
   (set (reg:SI 108)
6507 
        (unspec_volatile:SI [
6508 
          (match_dup 0)
6509 
          (match_dup 1)
6510 
        ] 2838))]
6511 
  "CGEN_ENABLE_INSN_P (171)"
6512 
  "cpsetua1.w\\t%0,%1"
6513 
  [(set_attr "may_trap" "no")
6514 
   (set_attr "latency" "0")
6515 
   (set_attr "length" "4")
6516 
   (set_attr "slot" "cop")
6517 
   (set_attr "slots" "c3")
6518 
   (set_attr "stall" "none")])
6519 
 
6520 
 
6521 
(define_insn "cgen_intrinsic_cpsetua1_w_P1"
6522 
  [(set (reg:SI 111)
6523 
        (unspec_volatile:SI [
6524 
          (match_operand:DI 0 "general_operand" "x")
6525 
          (match_operand:DI 1 "general_operand" "x")
6526 
        ] 2832))
6527 
   (set (reg:SI 110)
6528 
        (unspec_volatile:SI [
6529 
          (match_dup 0)
6530 
          (match_dup 1)
6531 
        ] 2834))
6532 
   (set (reg:SI 109)
6533 
        (unspec_volatile:SI [
6534 
          (match_dup 0)
6535 
          (match_dup 1)
6536 
        ] 2836))
6537 
   (set (reg:SI 108)
6538 
        (unspec_volatile:SI [
6539 
          (match_dup 0)
6540 
          (match_dup 1)
6541 
        ] 2838))]
6542 
  "CGEN_ENABLE_INSN_P (172)"
6543 
  "cpsetua1.w\\t%0,%1"
6544 
  [(set_attr "may_trap" "no")
6545 
   (set_attr "latency" "0")
6546 
   (set_attr "length" "4")
6547 
   (set_attr "slot" "cop")
6548 
   (set_attr "slots" "p1")
6549 
   (set_attr "stall" "none")])
6550 
 
6551 
 
6552 
(define_insn "cgen_intrinsic_cpseta1_h_C3"
6553 
  [(set (reg:SI 111)
6554 
        (unspec_volatile:SI [
6555 
          (match_operand:DI 0 "general_operand" "x")
6556 
          (match_operand:DI 1 "general_operand" "x")
6557 
        ] 2840))
6558 
   (set (reg:SI 110)
6559 
        (unspec_volatile:SI [
6560 
          (match_dup 0)
6561 
          (match_dup 1)
6562 
        ] 2842))
6563 
   (set (reg:SI 109)
6564 
        (unspec_volatile:SI [
6565 
          (match_dup 0)
6566 
          (match_dup 1)
6567 
        ] 2844))
6568 
   (set (reg:SI 108)
6569 
        (unspec_volatile:SI [
6570 
          (match_dup 0)
6571 
          (match_dup 1)
6572 
        ] 2846))
6573 
   (set (reg:SI 107)
6574 
        (unspec_volatile:SI [
6575 
          (match_dup 0)
6576 
          (match_dup 1)
6577 
        ] 2848))
6578 
   (set (reg:SI 106)
6579 
        (unspec_volatile:SI [
6580 
          (match_dup 0)
6581 
          (match_dup 1)
6582 
        ] 2850))
6583 
   (set (reg:SI 105)
6584 
        (unspec_volatile:SI [
6585 
          (match_dup 0)
6586 
          (match_dup 1)
6587 
        ] 2852))
6588 
   (set (reg:SI 104)
6589 
        (unspec_volatile:SI [
6590 
          (match_dup 0)
6591 
          (match_dup 1)
6592 
        ] 2854))]
6593 
  "CGEN_ENABLE_INSN_P (173)"
6594 
  "cpseta1.h\\t%0,%1"
6595 
  [(set_attr "may_trap" "no")
6596 
   (set_attr "latency" "0")
6597 
   (set_attr "length" "4")
6598 
   (set_attr "slot" "cop")
6599 
   (set_attr "slots" "c3")
6600 
   (set_attr "stall" "none")])
6601 
 
6602 
 
6603 
(define_insn "cgen_intrinsic_cpseta1_h_P1"
6604 
  [(set (reg:SI 111)
6605 
        (unspec_volatile:SI [
6606 
          (match_operand:DI 0 "general_operand" "x")
6607 
          (match_operand:DI 1 "general_operand" "x")
6608 
        ] 2840))
6609 
   (set (reg:SI 110)
6610 
        (unspec_volatile:SI [
6611 
          (match_dup 0)
6612 
          (match_dup 1)
6613 
        ] 2842))
6614 
   (set (reg:SI 109)
6615 
        (unspec_volatile:SI [
6616 
          (match_dup 0)
6617 
          (match_dup 1)
6618 
        ] 2844))
6619 
   (set (reg:SI 108)
6620 
        (unspec_volatile:SI [
6621 
          (match_dup 0)
6622 
          (match_dup 1)
6623 
        ] 2846))
6624 
   (set (reg:SI 107)
6625 
        (unspec_volatile:SI [
6626 
          (match_dup 0)
6627 
          (match_dup 1)
6628 
        ] 2848))
6629 
   (set (reg:SI 106)
6630 
        (unspec_volatile:SI [
6631 
          (match_dup 0)
6632 
          (match_dup 1)
6633 
        ] 2850))
6634 
   (set (reg:SI 105)
6635 
        (unspec_volatile:SI [
6636 
          (match_dup 0)
6637 
          (match_dup 1)
6638 
        ] 2852))
6639 
   (set (reg:SI 104)
6640 
        (unspec_volatile:SI [
6641 
          (match_dup 0)
6642 
          (match_dup 1)
6643 
        ] 2854))]
6644 
  "CGEN_ENABLE_INSN_P (174)"
6645 
  "cpseta1.h\\t%0,%1"
6646 
  [(set_attr "may_trap" "no")
6647 
   (set_attr "latency" "0")
6648 
   (set_attr "length" "4")
6649 
   (set_attr "slot" "cop")
6650 
   (set_attr "slots" "p1")
6651 
   (set_attr "stall" "none")])
6652 
 
6653 
 
6654 
(define_insn "cgen_intrinsic_cpsadla1_h_C3"
6655 
  [(set (reg:SI 87)
6656 
        (unspec_volatile:SI [
6657 
          (match_operand:DI 0 "general_operand" "x")
6658 
          (match_operand:DI 1 "general_operand" "x")
6659 
        ] 2856))
6660 
   (set (reg:SI 107)
6661 
        (unspec_volatile:SI [
6662 
          (match_dup 0)
6663 
          (match_dup 1)
6664 
        ] 2858))
6665 
   (set (reg:SI 106)
6666 
        (unspec_volatile:SI [
6667 
          (match_dup 0)
6668 
          (match_dup 1)
6669 
        ] 2860))
6670 
   (set (reg:SI 105)
6671 
        (unspec_volatile:SI [
6672 
          (match_dup 0)
6673 
          (match_dup 1)
6674 
        ] 2862))
6675 
   (set (reg:SI 104)
6676 
        (unspec_volatile:SI [
6677 
          (match_dup 0)
6678 
          (match_dup 1)
6679 
        ] 2864))]
6680 
  "CGEN_ENABLE_INSN_P (175)"
6681 
  "cpsadla1.h\\t%0,%1"
6682 
  [(set_attr "may_trap" "no")
6683 
   (set_attr "latency" "0")
6684 
   (set_attr "length" "4")
6685 
   (set_attr "slot" "cop")
6686 
   (set_attr "slots" "c3")
6687 
   (set_attr "stall" "none")])
6688 
 
6689 
 
6690 
(define_insn "cgen_intrinsic_cpsadla1_h_P1"
6691 
  [(set (reg:SI 87)
6692 
        (unspec_volatile:SI [
6693 
          (match_operand:DI 0 "general_operand" "x")
6694 
          (match_operand:DI 1 "general_operand" "x")
6695 
        ] 2856))
6696 
   (set (reg:SI 107)
6697 
        (unspec_volatile:SI [
6698 
          (match_dup 0)
6699 
          (match_dup 1)
6700 
        ] 2858))
6701 
   (set (reg:SI 106)
6702 
        (unspec_volatile:SI [
6703 
          (match_dup 0)
6704 
          (match_dup 1)
6705 
        ] 2860))
6706 
   (set (reg:SI 105)
6707 
        (unspec_volatile:SI [
6708 
          (match_dup 0)
6709 
          (match_dup 1)
6710 
        ] 2862))
6711 
   (set (reg:SI 104)
6712 
        (unspec_volatile:SI [
6713 
          (match_dup 0)
6714 
          (match_dup 1)
6715 
        ] 2864))]
6716 
  "CGEN_ENABLE_INSN_P (176)"
6717 
  "cpsadla1.h\\t%0,%1"
6718 
  [(set_attr "may_trap" "no")
6719 
   (set_attr "latency" "0")
6720 
   (set_attr "length" "4")
6721 
   (set_attr "slot" "cop")
6722 
   (set_attr "slots" "p1")
6723 
   (set_attr "stall" "none")])
6724 
 
6725 
 
6726 
(define_insn "cgen_intrinsic_cpsadua1_h_C3"
6727 
  [(set (reg:SI 87)
6728 
        (unspec_volatile:SI [
6729 
          (match_operand:DI 0 "general_operand" "x")
6730 
          (match_operand:DI 1 "general_operand" "x")
6731 
        ] 2866))
6732 
   (set (reg:SI 111)
6733 
        (unspec_volatile:SI [
6734 
          (match_dup 0)
6735 
          (match_dup 1)
6736 
        ] 2868))
6737 
   (set (reg:SI 110)
6738 
        (unspec_volatile:SI [
6739 
          (match_dup 0)
6740 
          (match_dup 1)
6741 
        ] 2870))
6742 
   (set (reg:SI 109)
6743 
        (unspec_volatile:SI [
6744 
          (match_dup 0)
6745 
          (match_dup 1)
6746 
        ] 2872))
6747 
   (set (reg:SI 108)
6748 
        (unspec_volatile:SI [
6749 
          (match_dup 0)
6750 
          (match_dup 1)
6751 
        ] 2874))]
6752 
  "CGEN_ENABLE_INSN_P (177)"
6753 
  "cpsadua1.h\\t%0,%1"
6754 
  [(set_attr "may_trap" "no")
6755 
   (set_attr "latency" "0")
6756 
   (set_attr "length" "4")
6757 
   (set_attr "slot" "cop")
6758 
   (set_attr "slots" "c3")
6759 
   (set_attr "stall" "none")])
6760 
 
6761 
 
6762 
(define_insn "cgen_intrinsic_cpsadua1_h_P1"
6763 
  [(set (reg:SI 87)
6764 
        (unspec_volatile:SI [
6765 
          (match_operand:DI 0 "general_operand" "x")
6766 
          (match_operand:DI 1 "general_operand" "x")
6767 
        ] 2866))
6768 
   (set (reg:SI 111)
6769 
        (unspec_volatile:SI [
6770 
          (match_dup 0)
6771 
          (match_dup 1)
6772 
        ] 2868))
6773 
   (set (reg:SI 110)
6774 
        (unspec_volatile:SI [
6775 
          (match_dup 0)
6776 
          (match_dup 1)
6777 
        ] 2870))
6778 
   (set (reg:SI 109)
6779 
        (unspec_volatile:SI [
6780 
          (match_dup 0)
6781 
          (match_dup 1)
6782 
        ] 2872))
6783 
   (set (reg:SI 108)
6784 
        (unspec_volatile:SI [
6785 
          (match_dup 0)
6786 
          (match_dup 1)
6787 
        ] 2874))]
6788 
  "CGEN_ENABLE_INSN_P (178)"
6789 
  "cpsadua1.h\\t%0,%1"
6790 
  [(set_attr "may_trap" "no")
6791 
   (set_attr "latency" "0")
6792 
   (set_attr "length" "4")
6793 
   (set_attr "slot" "cop")
6794 
   (set_attr "slots" "p1")
6795 
   (set_attr "stall" "none")])
6796 
 
6797 
 
6798 
(define_insn "cgen_intrinsic_cpsada1_b_C3"
6799 
  [(set (reg:SI 87)
6800 
        (unspec_volatile:SI [
6801 
          (match_operand:DI 0 "general_operand" "x")
6802 
          (match_operand:DI 1 "general_operand" "x")
6803 
        ] 2876))
6804 
   (set (reg:SI 111)
6805 
        (unspec_volatile:SI [
6806 
          (match_dup 0)
6807 
          (match_dup 1)
6808 
        ] 2878))
6809 
   (set (reg:SI 110)
6810 
        (unspec_volatile:SI [
6811 
          (match_dup 0)
6812 
          (match_dup 1)
6813 
        ] 2880))
6814 
   (set (reg:SI 109)
6815 
        (unspec_volatile:SI [
6816 
          (match_dup 0)
6817 
          (match_dup 1)
6818 
        ] 2882))
6819 
   (set (reg:SI 108)
6820 
        (unspec_volatile:SI [
6821 
          (match_dup 0)
6822 
          (match_dup 1)
6823 
        ] 2884))
6824 
   (set (reg:SI 107)
6825 
        (unspec_volatile:SI [
6826 
          (match_dup 0)
6827 
          (match_dup 1)
6828 
        ] 2886))
6829 
   (set (reg:SI 106)
6830 
        (unspec_volatile:SI [
6831 
          (match_dup 0)
6832 
          (match_dup 1)
6833 
        ] 2888))
6834 
   (set (reg:SI 105)
6835 
        (unspec_volatile:SI [
6836 
          (match_dup 0)
6837 
          (match_dup 1)
6838 
        ] 2890))
6839 
   (set (reg:SI 104)
6840 
        (unspec_volatile:SI [
6841 
          (match_dup 0)
6842 
          (match_dup 1)
6843 
        ] 2892))]
6844 
  "CGEN_ENABLE_INSN_P (179)"
6845 
  "cpsada1.b\\t%0,%1"
6846 
  [(set_attr "may_trap" "no")
6847 
   (set_attr "latency" "0")
6848 
   (set_attr "length" "4")
6849 
   (set_attr "slot" "cop")
6850 
   (set_attr "slots" "c3")
6851 
   (set_attr "stall" "none")])
6852 
 
6853 
 
6854 
(define_insn "cgen_intrinsic_cpsada1_b_P1"
6855 
  [(set (reg:SI 87)
6856 
        (unspec_volatile:SI [
6857 
          (match_operand:DI 0 "general_operand" "x")
6858 
          (match_operand:DI 1 "general_operand" "x")
6859 
        ] 2876))
6860 
   (set (reg:SI 111)
6861 
        (unspec_volatile:SI [
6862 
          (match_dup 0)
6863 
          (match_dup 1)
6864 
        ] 2878))
6865 
   (set (reg:SI 110)
6866 
        (unspec_volatile:SI [
6867 
          (match_dup 0)
6868 
          (match_dup 1)
6869 
        ] 2880))
6870 
   (set (reg:SI 109)
6871 
        (unspec_volatile:SI [
6872 
          (match_dup 0)
6873 
          (match_dup 1)
6874 
        ] 2882))
6875 
   (set (reg:SI 108)
6876 
        (unspec_volatile:SI [
6877 
          (match_dup 0)
6878 
          (match_dup 1)
6879 
        ] 2884))
6880 
   (set (reg:SI 107)
6881 
        (unspec_volatile:SI [
6882 
          (match_dup 0)
6883 
          (match_dup 1)
6884 
        ] 2886))
6885 
   (set (reg:SI 106)
6886 
        (unspec_volatile:SI [
6887 
          (match_dup 0)
6888 
          (match_dup 1)
6889 
        ] 2888))
6890 
   (set (reg:SI 105)
6891 
        (unspec_volatile:SI [
6892 
          (match_dup 0)
6893 
          (match_dup 1)
6894 
        ] 2890))
6895 
   (set (reg:SI 104)
6896 
        (unspec_volatile:SI [
6897 
          (match_dup 0)
6898 
          (match_dup 1)
6899 
        ] 2892))]
6900 
  "CGEN_ENABLE_INSN_P (180)"
6901 
  "cpsada1.b\\t%0,%1"
6902 
  [(set_attr "may_trap" "no")
6903 
   (set_attr "latency" "0")
6904 
   (set_attr "length" "4")
6905 
   (set_attr "slot" "cop")
6906 
   (set_attr "slots" "p1")
6907 
   (set_attr "stall" "none")])
6908 
 
6909 
 
6910 
(define_insn "cgen_intrinsic_cpsada1u_b_C3"
6911 
  [(set (reg:SI 87)
6912 
        (unspec_volatile:SI [
6913 
          (match_operand:DI 0 "general_operand" "x")
6914 
          (match_operand:DI 1 "general_operand" "x")
6915 
        ] 2894))
6916 
   (set (reg:SI 111)
6917 
        (unspec_volatile:SI [
6918 
          (match_dup 0)
6919 
          (match_dup 1)
6920 
        ] 2896))
6921 
   (set (reg:SI 110)
6922 
        (unspec_volatile:SI [
6923 
          (match_dup 0)
6924 
          (match_dup 1)
6925 
        ] 2898))
6926 
   (set (reg:SI 109)
6927 
        (unspec_volatile:SI [
6928 
          (match_dup 0)
6929 
          (match_dup 1)
6930 
        ] 2900))
6931 
   (set (reg:SI 108)
6932 
        (unspec_volatile:SI [
6933 
          (match_dup 0)
6934 
          (match_dup 1)
6935 
        ] 2902))
6936 
   (set (reg:SI 107)
6937 
        (unspec_volatile:SI [
6938 
          (match_dup 0)
6939 
          (match_dup 1)
6940 
        ] 2904))
6941 
   (set (reg:SI 106)
6942 
        (unspec_volatile:SI [
6943 
          (match_dup 0)
6944 
          (match_dup 1)
6945 
        ] 2906))
6946 
   (set (reg:SI 105)
6947 
        (unspec_volatile:SI [
6948 
          (match_dup 0)
6949 
          (match_dup 1)
6950 
        ] 2908))
6951 
   (set (reg:SI 104)
6952 
        (unspec_volatile:SI [
6953 
          (match_dup 0)
6954 
          (match_dup 1)
6955 
        ] 2910))]
6956 
  "CGEN_ENABLE_INSN_P (181)"
6957 
  "cpsada1u.b\\t%0,%1"
6958 
  [(set_attr "may_trap" "no")
6959 
   (set_attr "latency" "0")
6960 
   (set_attr "length" "4")
6961 
   (set_attr "slot" "cop")
6962 
   (set_attr "slots" "c3")
6963 
   (set_attr "stall" "none")])
6964 
 
6965 
 
6966 
(define_insn "cgen_intrinsic_cpsada1u_b_P1"
6967 
  [(set (reg:SI 87)
6968 
        (unspec_volatile:SI [
6969 
          (match_operand:DI 0 "general_operand" "x")
6970 
          (match_operand:DI 1 "general_operand" "x")
6971 
        ] 2894))
6972 
   (set (reg:SI 111)
6973 
        (unspec_volatile:SI [
6974 
          (match_dup 0)
6975 
          (match_dup 1)
6976 
        ] 2896))
6977 
   (set (reg:SI 110)
6978 
        (unspec_volatile:SI [
6979 
          (match_dup 0)
6980 
          (match_dup 1)
6981 
        ] 2898))
6982 
   (set (reg:SI 109)
6983 
        (unspec_volatile:SI [
6984 
          (match_dup 0)
6985 
          (match_dup 1)
6986 
        ] 2900))
6987 
   (set (reg:SI 108)
6988 
        (unspec_volatile:SI [
6989 
          (match_dup 0)
6990 
          (match_dup 1)
6991 
        ] 2902))
6992 
   (set (reg:SI 107)
6993 
        (unspec_volatile:SI [
6994 
          (match_dup 0)
6995 
          (match_dup 1)
6996 
        ] 2904))
6997 
   (set (reg:SI 106)
6998 
        (unspec_volatile:SI [
6999 
          (match_dup 0)
7000 
          (match_dup 1)
7001 
        ] 2906))
7002 
   (set (reg:SI 105)
7003 
        (unspec_volatile:SI [
7004 
          (match_dup 0)
7005 
          (match_dup 1)
7006 
        ] 2908))
7007 
   (set (reg:SI 104)
7008 
        (unspec_volatile:SI [
7009 
          (match_dup 0)
7010 
          (match_dup 1)
7011 
        ] 2910))]
7012 
  "CGEN_ENABLE_INSN_P (182)"
7013 
  "cpsada1u.b\\t%0,%1"
7014 
  [(set_attr "may_trap" "no")
7015 
   (set_attr "latency" "0")
7016 
   (set_attr "length" "4")
7017 
   (set_attr "slot" "cop")
7018 
   (set_attr "slots" "p1")
7019 
   (set_attr "stall" "none")])
7020 
 
7021 
 
7022 
(define_insn "cgen_intrinsic_cpabsla1_h_C3"
7023 
  [(set (reg:SI 107)
7024 
        (unspec_volatile:SI [
7025 
          (match_operand:DI 0 "general_operand" "x")
7026 
          (match_operand:DI 1 "general_operand" "x")
7027 
        ] 2912))
7028 
   (set (reg:SI 106)
7029 
        (unspec_volatile:SI [
7030 
          (match_dup 0)
7031 
          (match_dup 1)
7032 
        ] 2914))
7033 
   (set (reg:SI 105)
7034 
        (unspec_volatile:SI [
7035 
          (match_dup 0)
7036 
          (match_dup 1)
7037 
        ] 2916))
7038 
   (set (reg:SI 104)
7039 
        (unspec_volatile:SI [
7040 
          (match_dup 0)
7041 
          (match_dup 1)
7042 
        ] 2918))]
7043 
  "CGEN_ENABLE_INSN_P (183)"
7044 
  "cpabsla1.h\\t%0,%1"
7045 
  [(set_attr "may_trap" "no")
7046 
   (set_attr "latency" "0")
7047 
   (set_attr "length" "4")
7048 
   (set_attr "slot" "cop")
7049 
   (set_attr "slots" "c3")
7050 
   (set_attr "stall" "none")])
7051 
 
7052 
 
7053 
(define_insn "cgen_intrinsic_cpabsla1_h_P1"
7054 
  [(set (reg:SI 107)
7055 
        (unspec_volatile:SI [
7056 
          (match_operand:DI 0 "general_operand" "x")
7057 
          (match_operand:DI 1 "general_operand" "x")
7058 
        ] 2912))
7059 
   (set (reg:SI 106)
7060 
        (unspec_volatile:SI [
7061 
          (match_dup 0)
7062 
          (match_dup 1)
7063 
        ] 2914))
7064 
   (set (reg:SI 105)
7065 
        (unspec_volatile:SI [
7066 
          (match_dup 0)
7067 
          (match_dup 1)
7068 
        ] 2916))
7069 
   (set (reg:SI 104)
7070 
        (unspec_volatile:SI [
7071 
          (match_dup 0)
7072 
          (match_dup 1)
7073 
        ] 2918))]
7074 
  "CGEN_ENABLE_INSN_P (184)"
7075 
  "cpabsla1.h\\t%0,%1"
7076 
  [(set_attr "may_trap" "no")
7077 
   (set_attr "latency" "0")
7078 
   (set_attr "length" "4")
7079 
   (set_attr "slot" "cop")
7080 
   (set_attr "slots" "p1")
7081 
   (set_attr "stall" "none")])
7082 
 
7083 
 
7084 
(define_insn "cgen_intrinsic_cpabsua1_h_C3"
7085 
  [(set (reg:SI 111)
7086 
        (unspec_volatile:SI [
7087 
          (match_operand:DI 0 "general_operand" "x")
7088 
          (match_operand:DI 1 "general_operand" "x")
7089 
        ] 2920))
7090 
   (set (reg:SI 110)
7091 
        (unspec_volatile:SI [
7092 
          (match_dup 0)
7093 
          (match_dup 1)
7094 
        ] 2922))
7095 
   (set (reg:SI 109)
7096 
        (unspec_volatile:SI [
7097 
          (match_dup 0)
7098 
          (match_dup 1)
7099 
        ] 2924))
7100 
   (set (reg:SI 108)
7101 
        (unspec_volatile:SI [
7102 
          (match_dup 0)
7103 
          (match_dup 1)
7104 
        ] 2926))]
7105 
  "CGEN_ENABLE_INSN_P (185)"
7106 
  "cpabsua1.h\\t%0,%1"
7107 
  [(set_attr "may_trap" "no")
7108 
   (set_attr "latency" "0")
7109 
   (set_attr "length" "4")
7110 
   (set_attr "slot" "cop")
7111 
   (set_attr "slots" "c3")
7112 
   (set_attr "stall" "none")])
7113 
 
7114 
 
7115 
(define_insn "cgen_intrinsic_cpabsua1_h_P1"
7116 
  [(set (reg:SI 111)
7117 
        (unspec_volatile:SI [
7118 
          (match_operand:DI 0 "general_operand" "x")
7119 
          (match_operand:DI 1 "general_operand" "x")
7120 
        ] 2920))
7121 
   (set (reg:SI 110)
7122 
        (unspec_volatile:SI [
7123 
          (match_dup 0)
7124 
          (match_dup 1)
7125 
        ] 2922))
7126 
   (set (reg:SI 109)
7127 
        (unspec_volatile:SI [
7128 
          (match_dup 0)
7129 
          (match_dup 1)
7130 
        ] 2924))
7131 
   (set (reg:SI 108)
7132 
        (unspec_volatile:SI [
7133 
          (match_dup 0)
7134 
          (match_dup 1)
7135 
        ] 2926))]
7136 
  "CGEN_ENABLE_INSN_P (186)"
7137 
  "cpabsua1.h\\t%0,%1"
7138 
  [(set_attr "may_trap" "no")
7139 
   (set_attr "latency" "0")
7140 
   (set_attr "length" "4")
7141 
   (set_attr "slot" "cop")
7142 
   (set_attr "slots" "p1")
7143 
   (set_attr "stall" "none")])
7144 
 
7145 
 
7146 
(define_insn "cgen_intrinsic_cpabsa1_b_C3"
7147 
  [(set (reg:SI 111)
7148 
        (unspec_volatile:SI [
7149 
          (match_operand:DI 0 "general_operand" "x")
7150 
          (match_operand:DI 1 "general_operand" "x")
7151 
        ] 2928))
7152 
   (set (reg:SI 110)
7153 
        (unspec_volatile:SI [
7154 
          (match_dup 0)
7155 
          (match_dup 1)
7156 
        ] 2930))
7157 
   (set (reg:SI 109)
7158 
        (unspec_volatile:SI [
7159 
          (match_dup 0)
7160 
          (match_dup 1)
7161 
        ] 2932))
7162 
   (set (reg:SI 108)
7163 
        (unspec_volatile:SI [
7164 
          (match_dup 0)
7165 
          (match_dup 1)
7166 
        ] 2934))
7167 
   (set (reg:SI 107)
7168 
        (unspec_volatile:SI [
7169 
          (match_dup 0)
7170 
          (match_dup 1)
7171 
        ] 2936))
7172 
   (set (reg:SI 106)
7173 
        (unspec_volatile:SI [
7174 
          (match_dup 0)
7175 
          (match_dup 1)
7176 
        ] 2938))
7177 
   (set (reg:SI 105)
7178 
        (unspec_volatile:SI [
7179 
          (match_dup 0)
7180 
          (match_dup 1)
7181 
        ] 2940))
7182 
   (set (reg:SI 104)
7183 
        (unspec_volatile:SI [
7184 
          (match_dup 0)
7185 
          (match_dup 1)
7186 
        ] 2942))]
7187 
  "CGEN_ENABLE_INSN_P (187)"
7188 
  "cpabsa1.b\\t%0,%1"
7189 
  [(set_attr "may_trap" "no")
7190 
   (set_attr "latency" "0")
7191 
   (set_attr "length" "4")
7192 
   (set_attr "slot" "cop")
7193 
   (set_attr "slots" "c3")
7194 
   (set_attr "stall" "none")])
7195 
 
7196 
 
7197 
(define_insn "cgen_intrinsic_cpabsa1_b_P1"
7198 
  [(set (reg:SI 111)
7199 
        (unspec_volatile:SI [
7200 
          (match_operand:DI 0 "general_operand" "x")
7201 
          (match_operand:DI 1 "general_operand" "x")
7202 
        ] 2928))
7203 
   (set (reg:SI 110)
7204 
        (unspec_volatile:SI [
7205 
          (match_dup 0)
7206 
          (match_dup 1)
7207 
        ] 2930))
7208 
   (set (reg:SI 109)
7209 
        (unspec_volatile:SI [
7210 
          (match_dup 0)
7211 
          (match_dup 1)
7212 
        ] 2932))
7213 
   (set (reg:SI 108)
7214 
        (unspec_volatile:SI [
7215 
          (match_dup 0)
7216 
          (match_dup 1)
7217 
        ] 2934))
7218 
   (set (reg:SI 107)
7219 
        (unspec_volatile:SI [
7220 
          (match_dup 0)
7221 
          (match_dup 1)
7222 
        ] 2936))
7223 
   (set (reg:SI 106)
7224 
        (unspec_volatile:SI [
7225 
          (match_dup 0)
7226 
          (match_dup 1)
7227 
        ] 2938))
7228 
   (set (reg:SI 105)
7229 
        (unspec_volatile:SI [
7230 
          (match_dup 0)
7231 
          (match_dup 1)
7232 
        ] 2940))
7233 
   (set (reg:SI 104)
7234 
        (unspec_volatile:SI [
7235 
          (match_dup 0)
7236 
          (match_dup 1)
7237 
        ] 2942))]
7238 
  "CGEN_ENABLE_INSN_P (188)"
7239 
  "cpabsa1.b\\t%0,%1"
7240 
  [(set_attr "may_trap" "no")
7241 
   (set_attr "latency" "0")
7242 
   (set_attr "length" "4")
7243 
   (set_attr "slot" "cop")
7244 
   (set_attr "slots" "p1")
7245 
   (set_attr "stall" "none")])
7246 
 
7247 
 
7248 
(define_insn "cgen_intrinsic_cpabsa1u_b_C3"
7249 
  [(set (reg:SI 111)
7250 
        (unspec_volatile:SI [
7251 
          (match_operand:DI 0 "general_operand" "x")
7252 
          (match_operand:DI 1 "general_operand" "x")
7253 
        ] 2944))
7254 
   (set (reg:SI 110)
7255 
        (unspec_volatile:SI [
7256 
          (match_dup 0)
7257 
          (match_dup 1)
7258 
        ] 2946))
7259 
   (set (reg:SI 109)
7260 
        (unspec_volatile:SI [
7261 
          (match_dup 0)
7262 
          (match_dup 1)
7263 
        ] 2948))
7264 
   (set (reg:SI 108)
7265 
        (unspec_volatile:SI [
7266 
          (match_dup 0)
7267 
          (match_dup 1)
7268 
        ] 2950))
7269 
   (set (reg:SI 107)
7270 
        (unspec_volatile:SI [
7271 
          (match_dup 0)
7272 
          (match_dup 1)
7273 
        ] 2952))
7274 
   (set (reg:SI 106)
7275 
        (unspec_volatile:SI [
7276 
          (match_dup 0)
7277 
          (match_dup 1)
7278 
        ] 2954))
7279 
   (set (reg:SI 105)
7280 
        (unspec_volatile:SI [
7281 
          (match_dup 0)
7282 
          (match_dup 1)
7283 
        ] 2956))
7284 
   (set (reg:SI 104)
7285 
        (unspec_volatile:SI [
7286 
          (match_dup 0)
7287 
          (match_dup 1)
7288 
        ] 2958))]
7289 
  "CGEN_ENABLE_INSN_P (189)"
7290 
  "cpabsa1u.b\\t%0,%1"
7291 
  [(set_attr "may_trap" "no")
7292 
   (set_attr "latency" "0")
7293 
   (set_attr "length" "4")
7294 
   (set_attr "slot" "cop")
7295 
   (set_attr "slots" "c3")
7296 
   (set_attr "stall" "none")])
7297 
 
7298 
 
7299 
(define_insn "cgen_intrinsic_cpabsa1u_b_P1"
7300 
  [(set (reg:SI 111)
7301 
        (unspec_volatile:SI [
7302 
          (match_operand:DI 0 "general_operand" "x")
7303 
          (match_operand:DI 1 "general_operand" "x")
7304 
        ] 2944))
7305 
   (set (reg:SI 110)
7306 
        (unspec_volatile:SI [
7307 
          (match_dup 0)
7308 
          (match_dup 1)
7309 
        ] 2946))
7310 
   (set (reg:SI 109)
7311 
        (unspec_volatile:SI [
7312 
          (match_dup 0)
7313 
          (match_dup 1)
7314 
        ] 2948))
7315 
   (set (reg:SI 108)
7316 
        (unspec_volatile:SI [
7317 
          (match_dup 0)
7318 
          (match_dup 1)
7319 
        ] 2950))
7320 
   (set (reg:SI 107)
7321 
        (unspec_volatile:SI [
7322 
          (match_dup 0)
7323 
          (match_dup 1)
7324 
        ] 2952))
7325 
   (set (reg:SI 106)
7326 
        (unspec_volatile:SI [
7327 
          (match_dup 0)
7328 
          (match_dup 1)
7329 
        ] 2954))
7330 
   (set (reg:SI 105)
7331 
        (unspec_volatile:SI [
7332 
          (match_dup 0)
7333 
          (match_dup 1)
7334 
        ] 2956))
7335 
   (set (reg:SI 104)
7336 
        (unspec_volatile:SI [
7337 
          (match_dup 0)
7338 
          (match_dup 1)
7339 
        ] 2958))]
7340 
  "CGEN_ENABLE_INSN_P (190)"
7341 
  "cpabsa1u.b\\t%0,%1"
7342 
  [(set_attr "may_trap" "no")
7343 
   (set_attr "latency" "0")
7344 
   (set_attr "length" "4")
7345 
   (set_attr "slot" "cop")
7346 
   (set_attr "slots" "p1")
7347 
   (set_attr "stall" "none")])
7348 
 
7349 
 
7350 
(define_insn "cgen_intrinsic_cpsubacla1_h_C3"
7351 
  [(set (reg:SI 87)
7352 
        (unspec_volatile:SI [
7353 
          (match_operand:DI 0 "general_operand" "x")
7354 
          (match_operand:DI 1 "general_operand" "x")
7355 
        ] 2960))
7356 
   (set (reg:SI 107)
7357 
        (unspec_volatile:SI [
7358 
          (match_dup 0)
7359 
          (match_dup 1)
7360 
        ] 2962))
7361 
   (set (reg:SI 106)
7362 
        (unspec_volatile:SI [
7363 
          (match_dup 0)
7364 
          (match_dup 1)
7365 
        ] 2964))
7366 
   (set (reg:SI 105)
7367 
        (unspec_volatile:SI [
7368 
          (match_dup 0)
7369 
          (match_dup 1)
7370 
        ] 2966))
7371 
   (set (reg:SI 104)
7372 
        (unspec_volatile:SI [
7373 
          (match_dup 0)
7374 
          (match_dup 1)
7375 
        ] 2968))]
7376 
  "CGEN_ENABLE_INSN_P (191)"
7377 
  "cpsubacla1.h\\t%0,%1"
7378 
  [(set_attr "may_trap" "no")
7379 
   (set_attr "latency" "0")
7380 
   (set_attr "length" "4")
7381 
   (set_attr "slot" "cop")
7382 
   (set_attr "slots" "c3")
7383 
   (set_attr "stall" "none")])
7384 
 
7385 
 
7386 
(define_insn "cgen_intrinsic_cpsubacla1_h_P1"
7387 
  [(set (reg:SI 87)
7388 
        (unspec_volatile:SI [
7389 
          (match_operand:DI 0 "general_operand" "x")
7390 
          (match_operand:DI 1 "general_operand" "x")
7391 
        ] 2960))
7392 
   (set (reg:SI 107)
7393 
        (unspec_volatile:SI [
7394 
          (match_dup 0)
7395 
          (match_dup 1)
7396 
        ] 2962))
7397 
   (set (reg:SI 106)
7398 
        (unspec_volatile:SI [
7399 
          (match_dup 0)
7400 
          (match_dup 1)
7401 
        ] 2964))
7402 
   (set (reg:SI 105)
7403 
        (unspec_volatile:SI [
7404 
          (match_dup 0)
7405 
          (match_dup 1)
7406 
        ] 2966))
7407 
   (set (reg:SI 104)
7408 
        (unspec_volatile:SI [
7409 
          (match_dup 0)
7410 
          (match_dup 1)
7411 
        ] 2968))]
7412 
  "CGEN_ENABLE_INSN_P (192)"
7413 
  "cpsubacla1.h\\t%0,%1"
7414 
  [(set_attr "may_trap" "no")
7415 
   (set_attr "latency" "0")
7416 
   (set_attr "length" "4")
7417 
   (set_attr "slot" "cop")
7418 
   (set_attr "slots" "p1")
7419 
   (set_attr "stall" "none")])
7420 
 
7421 
 
7422 
(define_insn "cgen_intrinsic_cpsubacua1_h_C3"
7423 
  [(set (reg:SI 87)
7424 
        (unspec_volatile:SI [
7425 
          (match_operand:DI 0 "general_operand" "x")
7426 
          (match_operand:DI 1 "general_operand" "x")
7427 
        ] 2970))
7428 
   (set (reg:SI 111)
7429 
        (unspec_volatile:SI [
7430 
          (match_dup 0)
7431 
          (match_dup 1)
7432 
        ] 2972))
7433 
   (set (reg:SI 110)
7434 
        (unspec_volatile:SI [
7435 
          (match_dup 0)
7436 
          (match_dup 1)
7437 
        ] 2974))
7438 
   (set (reg:SI 109)
7439 
        (unspec_volatile:SI [
7440 
          (match_dup 0)
7441 
          (match_dup 1)
7442 
        ] 2976))
7443 
   (set (reg:SI 108)
7444 
        (unspec_volatile:SI [
7445 
          (match_dup 0)
7446 
          (match_dup 1)
7447 
        ] 2978))]
7448 
  "CGEN_ENABLE_INSN_P (193)"
7449 
  "cpsubacua1.h\\t%0,%1"
7450 
  [(set_attr "may_trap" "no")
7451 
   (set_attr "latency" "0")
7452 
   (set_attr "length" "4")
7453 
   (set_attr "slot" "cop")
7454 
   (set_attr "slots" "c3")
7455 
   (set_attr "stall" "none")])
7456 
 
7457 
 
7458 
(define_insn "cgen_intrinsic_cpsubacua1_h_P1"
7459 
  [(set (reg:SI 87)
7460 
        (unspec_volatile:SI [
7461 
          (match_operand:DI 0 "general_operand" "x")
7462 
          (match_operand:DI 1 "general_operand" "x")
7463 
        ] 2970))
7464 
   (set (reg:SI 111)
7465 
        (unspec_volatile:SI [
7466 
          (match_dup 0)
7467 
          (match_dup 1)
7468 
        ] 2972))
7469 
   (set (reg:SI 110)
7470 
        (unspec_volatile:SI [
7471 
          (match_dup 0)
7472 
          (match_dup 1)
7473 
        ] 2974))
7474 
   (set (reg:SI 109)
7475 
        (unspec_volatile:SI [
7476 
          (match_dup 0)
7477 
          (match_dup 1)
7478 
        ] 2976))
7479 
   (set (reg:SI 108)
7480 
        (unspec_volatile:SI [
7481 
          (match_dup 0)
7482 
          (match_dup 1)
7483 
        ] 2978))]
7484 
  "CGEN_ENABLE_INSN_P (194)"
7485 
  "cpsubacua1.h\\t%0,%1"
7486 
  [(set_attr "may_trap" "no")
7487 
   (set_attr "latency" "0")
7488 
   (set_attr "length" "4")
7489 
   (set_attr "slot" "cop")
7490 
   (set_attr "slots" "p1")
7491 
   (set_attr "stall" "none")])
7492 
 
7493 
 
7494 
(define_insn "cgen_intrinsic_cpsubaca1_b_C3"
7495 
  [(set (reg:SI 87)
7496 
        (unspec_volatile:SI [
7497 
          (match_operand:DI 0 "general_operand" "x")
7498 
          (match_operand:DI 1 "general_operand" "x")
7499 
        ] 2980))
7500 
   (set (reg:SI 111)
7501 
        (unspec_volatile:SI [
7502 
          (match_dup 0)
7503 
          (match_dup 1)
7504 
        ] 2982))
7505 
   (set (reg:SI 110)
7506 
        (unspec_volatile:SI [
7507 
          (match_dup 0)
7508 
          (match_dup 1)
7509 
        ] 2984))
7510 
   (set (reg:SI 109)
7511 
        (unspec_volatile:SI [
7512 
          (match_dup 0)
7513 
          (match_dup 1)
7514 
        ] 2986))
7515 
   (set (reg:SI 108)
7516 
        (unspec_volatile:SI [
7517 
          (match_dup 0)
7518 
          (match_dup 1)
7519 
        ] 2988))
7520 
   (set (reg:SI 107)
7521 
        (unspec_volatile:SI [
7522 
          (match_dup 0)
7523 
          (match_dup 1)
7524 
        ] 2990))
7525 
   (set (reg:SI 106)
7526 
        (unspec_volatile:SI [
7527 
          (match_dup 0)
7528 
          (match_dup 1)
7529 
        ] 2992))
7530 
   (set (reg:SI 105)
7531 
        (unspec_volatile:SI [
7532 
          (match_dup 0)
7533 
          (match_dup 1)
7534 
        ] 2994))
7535 
   (set (reg:SI 104)
7536 
        (unspec_volatile:SI [
7537 
          (match_dup 0)
7538 
          (match_dup 1)
7539 
        ] 2996))]
7540 
  "CGEN_ENABLE_INSN_P (195)"
7541 
  "cpsubaca1.b\\t%0,%1"
7542 
  [(set_attr "may_trap" "no")
7543 
   (set_attr "latency" "0")
7544 
   (set_attr "length" "4")
7545 
   (set_attr "slot" "cop")
7546 
   (set_attr "slots" "c3")
7547 
   (set_attr "stall" "none")])
7548 
 
7549 
 
7550 
(define_insn "cgen_intrinsic_cpsubaca1_b_P1"
7551 
  [(set (reg:SI 87)
7552 
        (unspec_volatile:SI [
7553 
          (match_operand:DI 0 "general_operand" "x")
7554 
          (match_operand:DI 1 "general_operand" "x")
7555 
        ] 2980))
7556 
   (set (reg:SI 111)
7557 
        (unspec_volatile:SI [
7558 
          (match_dup 0)
7559 
          (match_dup 1)
7560 
        ] 2982))
7561 
   (set (reg:SI 110)
7562 
        (unspec_volatile:SI [
7563 
          (match_dup 0)
7564 
          (match_dup 1)
7565 
        ] 2984))
7566 
   (set (reg:SI 109)
7567 
        (unspec_volatile:SI [
7568 
          (match_dup 0)
7569 
          (match_dup 1)
7570 
        ] 2986))
7571 
   (set (reg:SI 108)
7572 
        (unspec_volatile:SI [
7573 
          (match_dup 0)
7574 
          (match_dup 1)
7575 
        ] 2988))
7576 
   (set (reg:SI 107)
7577 
        (unspec_volatile:SI [
7578 
          (match_dup 0)
7579 
          (match_dup 1)
7580 
        ] 2990))
7581 
   (set (reg:SI 106)
7582 
        (unspec_volatile:SI [
7583 
          (match_dup 0)
7584 
          (match_dup 1)
7585 
        ] 2992))
7586 
   (set (reg:SI 105)
7587 
        (unspec_volatile:SI [
7588 
          (match_dup 0)
7589 
          (match_dup 1)
7590 
        ] 2994))
7591 
   (set (reg:SI 104)
7592 
        (unspec_volatile:SI [
7593 
          (match_dup 0)
7594 
          (match_dup 1)
7595 
        ] 2996))]
7596 
  "CGEN_ENABLE_INSN_P (196)"
7597 
  "cpsubaca1.b\\t%0,%1"
7598 
  [(set_attr "may_trap" "no")
7599 
   (set_attr "latency" "0")
7600 
   (set_attr "length" "4")
7601 
   (set_attr "slot" "cop")
7602 
   (set_attr "slots" "p1")
7603 
   (set_attr "stall" "none")])
7604 
 
7605 
 
7606 
(define_insn "cgen_intrinsic_cpsubaca1u_b_C3"
7607 
  [(set (reg:SI 87)
7608 
        (unspec_volatile:SI [
7609 
          (match_operand:DI 0 "general_operand" "x")
7610 
          (match_operand:DI 1 "general_operand" "x")
7611 
        ] 2998))
7612 
   (set (reg:SI 111)
7613 
        (unspec_volatile:SI [
7614 
          (match_dup 0)
7615 
          (match_dup 1)
7616 
        ] 3000))
7617 
   (set (reg:SI 110)
7618 
        (unspec_volatile:SI [
7619 
          (match_dup 0)
7620 
          (match_dup 1)
7621 
        ] 3002))
7622 
   (set (reg:SI 109)
7623 
        (unspec_volatile:SI [
7624 
          (match_dup 0)
7625 
          (match_dup 1)
7626 
        ] 3004))
7627 
   (set (reg:SI 108)
7628 
        (unspec_volatile:SI [
7629 
          (match_dup 0)
7630 
          (match_dup 1)
7631 
        ] 3006))
7632 
   (set (reg:SI 107)
7633 
        (unspec_volatile:SI [
7634 
          (match_dup 0)
7635 
          (match_dup 1)
7636 
        ] 3008))
7637 
   (set (reg:SI 106)
7638 
        (unspec_volatile:SI [
7639 
          (match_dup 0)
7640 
          (match_dup 1)
7641 
        ] 3010))
7642 
   (set (reg:SI 105)
7643 
        (unspec_volatile:SI [
7644 
          (match_dup 0)
7645 
          (match_dup 1)
7646 
        ] 3012))
7647 
   (set (reg:SI 104)
7648 
        (unspec_volatile:SI [
7649 
          (match_dup 0)
7650 
          (match_dup 1)
7651 
        ] 3014))]
7652 
  "CGEN_ENABLE_INSN_P (197)"
7653 
  "cpsubaca1u.b\\t%0,%1"
7654 
  [(set_attr "may_trap" "no")
7655 
   (set_attr "latency" "0")
7656 
   (set_attr "length" "4")
7657 
   (set_attr "slot" "cop")
7658 
   (set_attr "slots" "c3")
7659 
   (set_attr "stall" "none")])
7660 
 
7661 
 
7662 
(define_insn "cgen_intrinsic_cpsubaca1u_b_P1"
7663 
  [(set (reg:SI 87)
7664 
        (unspec_volatile:SI [
7665 
          (match_operand:DI 0 "general_operand" "x")
7666 
          (match_operand:DI 1 "general_operand" "x")
7667 
        ] 2998))
7668 
   (set (reg:SI 111)
7669 
        (unspec_volatile:SI [
7670 
          (match_dup 0)
7671 
          (match_dup 1)
7672 
        ] 3000))
7673 
   (set (reg:SI 110)
7674 
        (unspec_volatile:SI [
7675 
          (match_dup 0)
7676 
          (match_dup 1)
7677 
        ] 3002))
7678 
   (set (reg:SI 109)
7679 
        (unspec_volatile:SI [
7680 
          (match_dup 0)
7681 
          (match_dup 1)
7682 
        ] 3004))
7683 
   (set (reg:SI 108)
7684 
        (unspec_volatile:SI [
7685 
          (match_dup 0)
7686 
          (match_dup 1)
7687 
        ] 3006))
7688 
   (set (reg:SI 107)
7689 
        (unspec_volatile:SI [
7690 
          (match_dup 0)
7691 
          (match_dup 1)
7692 
        ] 3008))
7693 
   (set (reg:SI 106)
7694 
        (unspec_volatile:SI [
7695 
          (match_dup 0)
7696 
          (match_dup 1)
7697 
        ] 3010))
7698 
   (set (reg:SI 105)
7699 
        (unspec_volatile:SI [
7700 
          (match_dup 0)
7701 
          (match_dup 1)
7702 
        ] 3012))
7703 
   (set (reg:SI 104)
7704 
        (unspec_volatile:SI [
7705 
          (match_dup 0)
7706 
          (match_dup 1)
7707 
        ] 3014))]
7708 
  "CGEN_ENABLE_INSN_P (198)"
7709 
  "cpsubaca1u.b\\t%0,%1"
7710 
  [(set_attr "may_trap" "no")
7711 
   (set_attr "latency" "0")
7712 
   (set_attr "length" "4")
7713 
   (set_attr "slot" "cop")
7714 
   (set_attr "slots" "p1")
7715 
   (set_attr "stall" "none")])
7716 
 
7717 
 
7718 
(define_insn "cgen_intrinsic_cpsubla1_h_C3"
7719 
  [(set (reg:SI 107)
7720 
        (unspec_volatile:SI [
7721 
          (match_operand:DI 0 "general_operand" "x")
7722 
          (match_operand:DI 1 "general_operand" "x")
7723 
        ] 3016))
7724 
   (set (reg:SI 106)
7725 
        (unspec_volatile:SI [
7726 
          (match_dup 0)
7727 
          (match_dup 1)
7728 
        ] 3018))
7729 
   (set (reg:SI 105)
7730 
        (unspec_volatile:SI [
7731 
          (match_dup 0)
7732 
          (match_dup 1)
7733 
        ] 3020))
7734 
   (set (reg:SI 104)
7735 
        (unspec_volatile:SI [
7736 
          (match_dup 0)
7737 
          (match_dup 1)
7738 
        ] 3022))]
7739 
  "CGEN_ENABLE_INSN_P (199)"
7740 
  "cpsubla1.h\\t%0,%1"
7741 
  [(set_attr "may_trap" "no")
7742 
   (set_attr "latency" "0")
7743 
   (set_attr "length" "4")
7744 
   (set_attr "slot" "cop")
7745 
   (set_attr "slots" "c3")
7746 
   (set_attr "stall" "none")])
7747 
 
7748 
 
7749 
(define_insn "cgen_intrinsic_cpsubla1_h_P1"
7750 
  [(set (reg:SI 107)
7751 
        (unspec_volatile:SI [
7752 
          (match_operand:DI 0 "general_operand" "x")
7753 
          (match_operand:DI 1 "general_operand" "x")
7754 
        ] 3016))
7755 
   (set (reg:SI 106)
7756 
        (unspec_volatile:SI [
7757 
          (match_dup 0)
7758 
          (match_dup 1)
7759 
        ] 3018))
7760 
   (set (reg:SI 105)
7761 
        (unspec_volatile:SI [
7762 
          (match_dup 0)
7763 
          (match_dup 1)
7764 
        ] 3020))
7765 
   (set (reg:SI 104)
7766 
        (unspec_volatile:SI [
7767 
          (match_dup 0)
7768 
          (match_dup 1)
7769 
        ] 3022))]
7770 
  "CGEN_ENABLE_INSN_P (200)"
7771 
  "cpsubla1.h\\t%0,%1"
7772 
  [(set_attr "may_trap" "no")
7773 
   (set_attr "latency" "0")
7774 
   (set_attr "length" "4")
7775 
   (set_attr "slot" "cop")
7776 
   (set_attr "slots" "p1")
7777 
   (set_attr "stall" "none")])
7778 
 
7779 
 
7780 
(define_insn "cgen_intrinsic_cpsubua1_h_C3"
7781 
  [(set (reg:SI 111)
7782 
        (unspec_volatile:SI [
7783 
          (match_operand:DI 0 "general_operand" "x")
7784 
          (match_operand:DI 1 "general_operand" "x")
7785 
        ] 3024))
7786 
   (set (reg:SI 110)
7787 
        (unspec_volatile:SI [
7788 
          (match_dup 0)
7789 
          (match_dup 1)
7790 
        ] 3026))
7791 
   (set (reg:SI 109)
7792 
        (unspec_volatile:SI [
7793 
          (match_dup 0)
7794 
          (match_dup 1)
7795 
        ] 3028))
7796 
   (set (reg:SI 108)
7797 
        (unspec_volatile:SI [
7798 
          (match_dup 0)
7799 
          (match_dup 1)
7800 
        ] 3030))]
7801 
  "CGEN_ENABLE_INSN_P (201)"
7802 
  "cpsubua1.h\\t%0,%1"
7803 
  [(set_attr "may_trap" "no")
7804 
   (set_attr "latency" "0")
7805 
   (set_attr "length" "4")
7806 
   (set_attr "slot" "cop")
7807 
   (set_attr "slots" "c3")
7808 
   (set_attr "stall" "none")])
7809 
 
7810 
 
7811 
(define_insn "cgen_intrinsic_cpsubua1_h_P1"
7812 
  [(set (reg:SI 111)
7813 
        (unspec_volatile:SI [
7814 
          (match_operand:DI 0 "general_operand" "x")
7815 
          (match_operand:DI 1 "general_operand" "x")
7816 
        ] 3024))
7817 
   (set (reg:SI 110)
7818 
        (unspec_volatile:SI [
7819 
          (match_dup 0)
7820 
          (match_dup 1)
7821 
        ] 3026))
7822 
   (set (reg:SI 109)
7823 
        (unspec_volatile:SI [
7824 
          (match_dup 0)
7825 
          (match_dup 1)
7826 
        ] 3028))
7827 
   (set (reg:SI 108)
7828 
        (unspec_volatile:SI [
7829 
          (match_dup 0)
7830 
          (match_dup 1)
7831 
        ] 3030))]
7832 
  "CGEN_ENABLE_INSN_P (202)"
7833 
  "cpsubua1.h\\t%0,%1"
7834 
  [(set_attr "may_trap" "no")
7835 
   (set_attr "latency" "0")
7836 
   (set_attr "length" "4")
7837 
   (set_attr "slot" "cop")
7838 
   (set_attr "slots" "p1")
7839 
   (set_attr "stall" "none")])
7840 
 
7841 
 
7842 
(define_insn "cgen_intrinsic_cpsuba1_b_C3"
7843 
  [(set (reg:SI 111)
7844 
        (unspec_volatile:SI [
7845 
          (match_operand:DI 0 "general_operand" "x")
7846 
          (match_operand:DI 1 "general_operand" "x")
7847 
        ] 3032))
7848 
   (set (reg:SI 110)
7849 
        (unspec_volatile:SI [
7850 
          (match_dup 0)
7851 
          (match_dup 1)
7852 
        ] 3034))
7853 
   (set (reg:SI 109)
7854 
        (unspec_volatile:SI [
7855 
          (match_dup 0)
7856 
          (match_dup 1)
7857 
        ] 3036))
7858 
   (set (reg:SI 108)
7859 
        (unspec_volatile:SI [
7860 
          (match_dup 0)
7861 
          (match_dup 1)
7862 
        ] 3038))
7863 
   (set (reg:SI 107)
7864 
        (unspec_volatile:SI [
7865 
          (match_dup 0)
7866 
          (match_dup 1)
7867 
        ] 3040))
7868 
   (set (reg:SI 106)
7869 
        (unspec_volatile:SI [
7870 
          (match_dup 0)
7871 
          (match_dup 1)
7872 
        ] 3042))
7873 
   (set (reg:SI 105)
7874 
        (unspec_volatile:SI [
7875 
          (match_dup 0)
7876 
          (match_dup 1)
7877 
        ] 3044))
7878 
   (set (reg:SI 104)
7879 
        (unspec_volatile:SI [
7880 
          (match_dup 0)
7881 
          (match_dup 1)
7882 
        ] 3046))]
7883 
  "CGEN_ENABLE_INSN_P (203)"
7884 
  "cpsuba1.b\\t%0,%1"
7885 
  [(set_attr "may_trap" "no")
7886 
   (set_attr "latency" "0")
7887 
   (set_attr "length" "4")
7888 
   (set_attr "slot" "cop")
7889 
   (set_attr "slots" "c3")
7890 
   (set_attr "stall" "none")])
7891 
 
7892 
 
7893 
(define_insn "cgen_intrinsic_cpsuba1_b_P1"
7894 
  [(set (reg:SI 111)
7895 
        (unspec_volatile:SI [
7896 
          (match_operand:DI 0 "general_operand" "x")
7897 
          (match_operand:DI 1 "general_operand" "x")
7898 
        ] 3032))
7899 
   (set (reg:SI 110)
7900 
        (unspec_volatile:SI [
7901 
          (match_dup 0)
7902 
          (match_dup 1)
7903 
        ] 3034))
7904 
   (set (reg:SI 109)
7905 
        (unspec_volatile:SI [
7906 
          (match_dup 0)
7907 
          (match_dup 1)
7908 
        ] 3036))
7909 
   (set (reg:SI 108)
7910 
        (unspec_volatile:SI [
7911 
          (match_dup 0)
7912 
          (match_dup 1)
7913 
        ] 3038))
7914 
   (set (reg:SI 107)
7915 
        (unspec_volatile:SI [
7916 
          (match_dup 0)
7917 
          (match_dup 1)
7918 
        ] 3040))
7919 
   (set (reg:SI 106)
7920 
        (unspec_volatile:SI [
7921 
          (match_dup 0)
7922 
          (match_dup 1)
7923 
        ] 3042))
7924 
   (set (reg:SI 105)
7925 
        (unspec_volatile:SI [
7926 
          (match_dup 0)
7927 
          (match_dup 1)
7928 
        ] 3044))
7929 
   (set (reg:SI 104)
7930 
        (unspec_volatile:SI [
7931 
          (match_dup 0)
7932 
          (match_dup 1)
7933 
        ] 3046))]
7934 
  "CGEN_ENABLE_INSN_P (204)"
7935 
  "cpsuba1.b\\t%0,%1"
7936 
  [(set_attr "may_trap" "no")
7937 
   (set_attr "latency" "0")
7938 
   (set_attr "length" "4")
7939 
   (set_attr "slot" "cop")
7940 
   (set_attr "slots" "p1")
7941 
   (set_attr "stall" "none")])
7942 
 
7943 
 
7944 
(define_insn "cgen_intrinsic_cpsuba1u_b_C3"
7945 
  [(set (reg:SI 111)
7946 
        (unspec_volatile:SI [
7947 
          (match_operand:DI 0 "general_operand" "x")
7948 
          (match_operand:DI 1 "general_operand" "x")
7949 
        ] 3048))
7950 
   (set (reg:SI 110)
7951 
        (unspec_volatile:SI [
7952 
          (match_dup 0)
7953 
          (match_dup 1)
7954 
        ] 3050))
7955 
   (set (reg:SI 109)
7956 
        (unspec_volatile:SI [
7957 
          (match_dup 0)
7958 
          (match_dup 1)
7959 
        ] 3052))
7960 
   (set (reg:SI 108)
7961 
        (unspec_volatile:SI [
7962 
          (match_dup 0)
7963 
          (match_dup 1)
7964 
        ] 3054))
7965 
   (set (reg:SI 107)
7966 
        (unspec_volatile:SI [
7967 
          (match_dup 0)
7968 
          (match_dup 1)
7969 
        ] 3056))
7970 
   (set (reg:SI 106)
7971 
        (unspec_volatile:SI [
7972 
          (match_dup 0)
7973 
          (match_dup 1)
7974 
        ] 3058))
7975 
   (set (reg:SI 105)
7976 
        (unspec_volatile:SI [
7977 
          (match_dup 0)
7978 
          (match_dup 1)
7979 
        ] 3060))
7980 
   (set (reg:SI 104)
7981 
        (unspec_volatile:SI [
7982 
          (match_dup 0)
7983 
          (match_dup 1)
7984 
        ] 3062))]
7985 
  "CGEN_ENABLE_INSN_P (205)"
7986 
  "cpsuba1u.b\\t%0,%1"
7987 
  [(set_attr "may_trap" "no")
7988 
   (set_attr "latency" "0")
7989 
   (set_attr "length" "4")
7990 
   (set_attr "slot" "cop")
7991 
   (set_attr "slots" "c3")
7992 
   (set_attr "stall" "none")])
7993 
 
7994 
 
7995 
(define_insn "cgen_intrinsic_cpsuba1u_b_P1"
7996 
  [(set (reg:SI 111)
7997 
        (unspec_volatile:SI [
7998 
          (match_operand:DI 0 "general_operand" "x")
7999 
          (match_operand:DI 1 "general_operand" "x")
8000 
        ] 3048))
8001 
   (set (reg:SI 110)
8002 
        (unspec_volatile:SI [
8003 
          (match_dup 0)
8004 
          (match_dup 1)
8005 
        ] 3050))
8006 
   (set (reg:SI 109)
8007 
        (unspec_volatile:SI [
8008 
          (match_dup 0)
8009 
          (match_dup 1)
8010 
        ] 3052))
8011 
   (set (reg:SI 108)
8012 
        (unspec_volatile:SI [
8013 
          (match_dup 0)
8014 
          (match_dup 1)
8015 
        ] 3054))
8016 
   (set (reg:SI 107)
8017 
        (unspec_volatile:SI [
8018 
          (match_dup 0)
8019 
          (match_dup 1)
8020 
        ] 3056))
8021 
   (set (reg:SI 106)
8022 
        (unspec_volatile:SI [
8023 
          (match_dup 0)
8024 
          (match_dup 1)
8025 
        ] 3058))
8026 
   (set (reg:SI 105)
8027 
        (unspec_volatile:SI [
8028 
          (match_dup 0)
8029 
          (match_dup 1)
8030 
        ] 3060))
8031 
   (set (reg:SI 104)
8032 
        (unspec_volatile:SI [
8033 
          (match_dup 0)
8034 
          (match_dup 1)
8035 
        ] 3062))]
8036 
  "CGEN_ENABLE_INSN_P (206)"
8037 
  "cpsuba1u.b\\t%0,%1"
8038 
  [(set_attr "may_trap" "no")
8039 
   (set_attr "latency" "0")
8040 
   (set_attr "length" "4")
8041 
   (set_attr "slot" "cop")
8042 
   (set_attr "slots" "p1")
8043 
   (set_attr "stall" "none")])
8044 
 
8045 
 
8046 
(define_insn "cgen_intrinsic_cpaddacla1_h_C3"
8047 
  [(set (reg:SI 87)
8048 
        (unspec_volatile:SI [
8049 
          (match_operand:DI 0 "general_operand" "x")
8050 
          (match_operand:DI 1 "general_operand" "x")
8051 
        ] 3064))
8052 
   (set (reg:SI 107)
8053 
        (unspec_volatile:SI [
8054 
          (match_dup 0)
8055 
          (match_dup 1)
8056 
        ] 3066))
8057 
   (set (reg:SI 106)
8058 
        (unspec_volatile:SI [
8059 
          (match_dup 0)
8060 
          (match_dup 1)
8061 
        ] 3068))
8062 
   (set (reg:SI 105)
8063 
        (unspec_volatile:SI [
8064 
          (match_dup 0)
8065 
          (match_dup 1)
8066 
        ] 3070))
8067 
   (set (reg:SI 104)
8068 
        (unspec_volatile:SI [
8069 
          (match_dup 0)
8070 
          (match_dup 1)
8071 
        ] 3072))]
8072 
  "CGEN_ENABLE_INSN_P (207)"
8073 
  "cpaddacla1.h\\t%0,%1"
8074 
  [(set_attr "may_trap" "no")
8075 
   (set_attr "latency" "0")
8076 
   (set_attr "length" "4")
8077 
   (set_attr "slot" "cop")
8078 
   (set_attr "slots" "c3")
8079 
   (set_attr "stall" "none")])
8080 
 
8081 
 
8082 
(define_insn "cgen_intrinsic_cpaddacla1_h_P1"
8083 
  [(set (reg:SI 87)
8084 
        (unspec_volatile:SI [
8085 
          (match_operand:DI 0 "general_operand" "x")
8086 
          (match_operand:DI 1 "general_operand" "x")
8087 
        ] 3064))
8088 
   (set (reg:SI 107)
8089 
        (unspec_volatile:SI [
8090 
          (match_dup 0)
8091 
          (match_dup 1)
8092 
        ] 3066))
8093 
   (set (reg:SI 106)
8094 
        (unspec_volatile:SI [
8095 
          (match_dup 0)
8096 
          (match_dup 1)
8097 
        ] 3068))
8098 
   (set (reg:SI 105)
8099 
        (unspec_volatile:SI [
8100 
          (match_dup 0)
8101 
          (match_dup 1)
8102 
        ] 3070))
8103 
   (set (reg:SI 104)
8104 
        (unspec_volatile:SI [
8105 
          (match_dup 0)
8106 
          (match_dup 1)
8107 
        ] 3072))]
8108 
  "CGEN_ENABLE_INSN_P (208)"
8109 
  "cpaddacla1.h\\t%0,%1"
8110 
  [(set_attr "may_trap" "no")
8111 
   (set_attr "latency" "0")
8112 
   (set_attr "length" "4")
8113 
   (set_attr "slot" "cop")
8114 
   (set_attr "slots" "p1")
8115 
   (set_attr "stall" "none")])
8116 
 
8117 
 
8118 
(define_insn "cgen_intrinsic_cpaddacua1_h_C3"
8119 
  [(set (reg:SI 87)
8120 
        (unspec_volatile:SI [
8121 
          (match_operand:DI 0 "general_operand" "x")
8122 
          (match_operand:DI 1 "general_operand" "x")
8123 
        ] 3074))
8124 
   (set (reg:SI 111)
8125 
        (unspec_volatile:SI [
8126 
          (match_dup 0)
8127 
          (match_dup 1)
8128 
        ] 3076))
8129 
   (set (reg:SI 110)
8130 
        (unspec_volatile:SI [
8131 
          (match_dup 0)
8132 
          (match_dup 1)
8133 
        ] 3078))
8134 
   (set (reg:SI 109)
8135 
        (unspec_volatile:SI [
8136 
          (match_dup 0)
8137 
          (match_dup 1)
8138 
        ] 3080))
8139 
   (set (reg:SI 108)
8140 
        (unspec_volatile:SI [
8141 
          (match_dup 0)
8142 
          (match_dup 1)
8143 
        ] 3082))]
8144 
  "CGEN_ENABLE_INSN_P (209)"
8145 
  "cpaddacua1.h\\t%0,%1"
8146 
  [(set_attr "may_trap" "no")
8147 
   (set_attr "latency" "0")
8148 
   (set_attr "length" "4")
8149 
   (set_attr "slot" "cop")
8150 
   (set_attr "slots" "c3")
8151 
   (set_attr "stall" "none")])
8152 
 
8153 
 
8154 
(define_insn "cgen_intrinsic_cpaddacua1_h_P1"
8155 
  [(set (reg:SI 87)
8156 
        (unspec_volatile:SI [
8157 
          (match_operand:DI 0 "general_operand" "x")
8158 
          (match_operand:DI 1 "general_operand" "x")
8159 
        ] 3074))
8160 
   (set (reg:SI 111)
8161 
        (unspec_volatile:SI [
8162 
          (match_dup 0)
8163 
          (match_dup 1)
8164 
        ] 3076))
8165 
   (set (reg:SI 110)
8166 
        (unspec_volatile:SI [
8167 
          (match_dup 0)
8168 
          (match_dup 1)
8169 
        ] 3078))
8170 
   (set (reg:SI 109)
8171 
        (unspec_volatile:SI [
8172 
          (match_dup 0)
8173 
          (match_dup 1)
8174 
        ] 3080))
8175 
   (set (reg:SI 108)
8176 
        (unspec_volatile:SI [
8177 
          (match_dup 0)
8178 
          (match_dup 1)
8179 
        ] 3082))]
8180 
  "CGEN_ENABLE_INSN_P (210)"
8181 
  "cpaddacua1.h\\t%0,%1"
8182 
  [(set_attr "may_trap" "no")
8183 
   (set_attr "latency" "0")
8184 
   (set_attr "length" "4")
8185 
   (set_attr "slot" "cop")
8186 
   (set_attr "slots" "p1")
8187 
   (set_attr "stall" "none")])
8188 
 
8189 
 
8190 
(define_insn "cgen_intrinsic_cpaddaca1_b_C3"
8191 
  [(set (reg:SI 87)
8192 
        (unspec_volatile:SI [
8193 
          (match_operand:DI 0 "general_operand" "x")
8194 
          (match_operand:DI 1 "general_operand" "x")
8195 
        ] 3084))
8196 
   (set (reg:SI 111)
8197 
        (unspec_volatile:SI [
8198 
          (match_dup 0)
8199 
          (match_dup 1)
8200 
        ] 3086))
8201 
   (set (reg:SI 110)
8202 
        (unspec_volatile:SI [
8203 
          (match_dup 0)
8204 
          (match_dup 1)
8205 
        ] 3088))
8206 
   (set (reg:SI 109)
8207 
        (unspec_volatile:SI [
8208 
          (match_dup 0)
8209 
          (match_dup 1)
8210 
        ] 3090))
8211 
   (set (reg:SI 108)
8212 
        (unspec_volatile:SI [
8213 
          (match_dup 0)
8214 
          (match_dup 1)
8215 
        ] 3092))
8216 
   (set (reg:SI 107)
8217 
        (unspec_volatile:SI [
8218 
          (match_dup 0)
8219 
          (match_dup 1)
8220 
        ] 3094))
8221 
   (set (reg:SI 106)
8222 
        (unspec_volatile:SI [
8223 
          (match_dup 0)
8224 
          (match_dup 1)
8225 
        ] 3096))
8226 
   (set (reg:SI 105)
8227 
        (unspec_volatile:SI [
8228 
          (match_dup 0)
8229 
          (match_dup 1)
8230 
        ] 3098))
8231 
   (set (reg:SI 104)
8232 
        (unspec_volatile:SI [
8233 
          (match_dup 0)
8234 
          (match_dup 1)
8235 
        ] 3100))]
8236 
  "CGEN_ENABLE_INSN_P (211)"
8237 
  "cpaddaca1.b\\t%0,%1"
8238 
  [(set_attr "may_trap" "no")
8239 
   (set_attr "latency" "0")
8240 
   (set_attr "length" "4")
8241 
   (set_attr "slot" "cop")
8242 
   (set_attr "slots" "c3")
8243 
   (set_attr "stall" "none")])
8244 
 
8245 
 
8246 
(define_insn "cgen_intrinsic_cpaddaca1_b_P1"
8247 
  [(set (reg:SI 87)
8248 
        (unspec_volatile:SI [
8249 
          (match_operand:DI 0 "general_operand" "x")
8250 
          (match_operand:DI 1 "general_operand" "x")
8251 
        ] 3084))
8252 
   (set (reg:SI 111)
8253 
        (unspec_volatile:SI [
8254 
          (match_dup 0)
8255 
          (match_dup 1)
8256 
        ] 3086))
8257 
   (set (reg:SI 110)
8258 
        (unspec_volatile:SI [
8259 
          (match_dup 0)
8260 
          (match_dup 1)
8261 
        ] 3088))
8262 
   (set (reg:SI 109)
8263 
        (unspec_volatile:SI [
8264 
          (match_dup 0)
8265 
          (match_dup 1)
8266 
        ] 3090))
8267 
   (set (reg:SI 108)
8268 
        (unspec_volatile:SI [
8269 
          (match_dup 0)
8270 
          (match_dup 1)
8271 
        ] 3092))
8272 
   (set (reg:SI 107)
8273 
        (unspec_volatile:SI [
8274 
          (match_dup 0)
8275 
          (match_dup 1)
8276 
        ] 3094))
8277 
   (set (reg:SI 106)
8278 
        (unspec_volatile:SI [
8279 
          (match_dup 0)
8280 
          (match_dup 1)
8281 
        ] 3096))
8282 
   (set (reg:SI 105)
8283 
        (unspec_volatile:SI [
8284 
          (match_dup 0)
8285 
          (match_dup 1)
8286 
        ] 3098))
8287 
   (set (reg:SI 104)
8288 
        (unspec_volatile:SI [
8289 
          (match_dup 0)
8290 
          (match_dup 1)
8291 
        ] 3100))]
8292 
  "CGEN_ENABLE_INSN_P (212)"
8293 
  "cpaddaca1.b\\t%0,%1"
8294 
  [(set_attr "may_trap" "no")
8295 
   (set_attr "latency" "0")
8296 
   (set_attr "length" "4")
8297 
   (set_attr "slot" "cop")
8298 
   (set_attr "slots" "p1")
8299 
   (set_attr "stall" "none")])
8300 
 
8301 
 
8302 
(define_insn "cgen_intrinsic_cpaddaca1u_b_C3"
8303 
  [(set (reg:SI 87)
8304 
        (unspec_volatile:SI [
8305 
          (match_operand:DI 0 "general_operand" "x")
8306 
          (match_operand:DI 1 "general_operand" "x")
8307 
        ] 3102))
8308 
   (set (reg:SI 111)
8309 
        (unspec_volatile:SI [
8310 
          (match_dup 0)
8311 
          (match_dup 1)
8312 
        ] 3104))
8313 
   (set (reg:SI 110)
8314 
        (unspec_volatile:SI [
8315 
          (match_dup 0)
8316 
          (match_dup 1)
8317 
        ] 3106))
8318 
   (set (reg:SI 109)
8319 
        (unspec_volatile:SI [
8320 
          (match_dup 0)
8321 
          (match_dup 1)
8322 
        ] 3108))
8323 
   (set (reg:SI 108)
8324 
        (unspec_volatile:SI [
8325 
          (match_dup 0)
8326 
          (match_dup 1)
8327 
        ] 3110))
8328 
   (set (reg:SI 107)
8329 
        (unspec_volatile:SI [
8330 
          (match_dup 0)
8331 
          (match_dup 1)
8332 
        ] 3112))
8333 
   (set (reg:SI 106)
8334 
        (unspec_volatile:SI [
8335 
          (match_dup 0)
8336 
          (match_dup 1)
8337 
        ] 3114))
8338 
   (set (reg:SI 105)
8339 
        (unspec_volatile:SI [
8340 
          (match_dup 0)
8341 
          (match_dup 1)
8342 
        ] 3116))
8343 
   (set (reg:SI 104)
8344 
        (unspec_volatile:SI [
8345 
          (match_dup 0)
8346 
          (match_dup 1)
8347 
        ] 3118))]
8348 
  "CGEN_ENABLE_INSN_P (213)"
8349 
  "cpaddaca1u.b\\t%0,%1"
8350 
  [(set_attr "may_trap" "no")
8351 
   (set_attr "latency" "0")
8352 
   (set_attr "length" "4")
8353 
   (set_attr "slot" "cop")
8354 
   (set_attr "slots" "c3")
8355 
   (set_attr "stall" "none")])
8356 
 
8357 
 
8358 
(define_insn "cgen_intrinsic_cpaddaca1u_b_P1"
8359 
  [(set (reg:SI 87)
8360 
        (unspec_volatile:SI [
8361 
          (match_operand:DI 0 "general_operand" "x")
8362 
          (match_operand:DI 1 "general_operand" "x")
8363 
        ] 3102))
8364 
   (set (reg:SI 111)
8365 
        (unspec_volatile:SI [
8366 
          (match_dup 0)
8367 
          (match_dup 1)
8368 
        ] 3104))
8369 
   (set (reg:SI 110)
8370 
        (unspec_volatile:SI [
8371 
          (match_dup 0)
8372 
          (match_dup 1)
8373 
        ] 3106))
8374 
   (set (reg:SI 109)
8375 
        (unspec_volatile:SI [
8376 
          (match_dup 0)
8377 
          (match_dup 1)
8378 
        ] 3108))
8379 
   (set (reg:SI 108)
8380 
        (unspec_volatile:SI [
8381 
          (match_dup 0)
8382 
          (match_dup 1)
8383 
        ] 3110))
8384 
   (set (reg:SI 107)
8385 
        (unspec_volatile:SI [
8386 
          (match_dup 0)
8387 
          (match_dup 1)
8388 
        ] 3112))
8389 
   (set (reg:SI 106)
8390 
        (unspec_volatile:SI [
8391 
          (match_dup 0)
8392 
          (match_dup 1)
8393 
        ] 3114))
8394 
   (set (reg:SI 105)
8395 
        (unspec_volatile:SI [
8396 
          (match_dup 0)
8397 
          (match_dup 1)
8398 
        ] 3116))
8399 
   (set (reg:SI 104)
8400 
        (unspec_volatile:SI [
8401 
          (match_dup 0)
8402 
          (match_dup 1)
8403 
        ] 3118))]
8404 
  "CGEN_ENABLE_INSN_P (214)"
8405 
  "cpaddaca1u.b\\t%0,%1"
8406 
  [(set_attr "may_trap" "no")
8407 
   (set_attr "latency" "0")
8408 
   (set_attr "length" "4")
8409 
   (set_attr "slot" "cop")
8410 
   (set_attr "slots" "p1")
8411 
   (set_attr "stall" "none")])
8412 
 
8413 
 
8414 
(define_insn "cgen_intrinsic_cpaddla1_h_C3"
8415 
  [(set (reg:SI 107)
8416 
        (unspec_volatile:SI [
8417 
          (match_operand:DI 0 "general_operand" "x")
8418 
          (match_operand:DI 1 "general_operand" "x")
8419 
        ] 3120))
8420 
   (set (reg:SI 106)
8421 
        (unspec_volatile:SI [
8422 
          (match_dup 0)
8423 
          (match_dup 1)
8424 
        ] 3122))
8425 
   (set (reg:SI 105)
8426 
        (unspec_volatile:SI [
8427 
          (match_dup 0)
8428 
          (match_dup 1)
8429 
        ] 3124))
8430 
   (set (reg:SI 104)
8431 
        (unspec_volatile:SI [
8432 
          (match_dup 0)
8433 
          (match_dup 1)
8434 
        ] 3126))]
8435 
  "CGEN_ENABLE_INSN_P (215)"
8436 
  "cpaddla1.h\\t%0,%1"
8437 
  [(set_attr "may_trap" "no")
8438 
   (set_attr "latency" "0")
8439 
   (set_attr "length" "4")
8440 
   (set_attr "slot" "cop")
8441 
   (set_attr "slots" "c3")
8442 
   (set_attr "stall" "none")])
8443 
 
8444 
 
8445 
(define_insn "cgen_intrinsic_cpaddla1_h_P1"
8446 
  [(set (reg:SI 107)
8447 
        (unspec_volatile:SI [
8448 
          (match_operand:DI 0 "general_operand" "x")
8449 
          (match_operand:DI 1 "general_operand" "x")
8450 
        ] 3120))
8451 
   (set (reg:SI 106)
8452 
        (unspec_volatile:SI [
8453 
          (match_dup 0)
8454 
          (match_dup 1)
8455 
        ] 3122))
8456 
   (set (reg:SI 105)
8457 
        (unspec_volatile:SI [
8458 
          (match_dup 0)
8459 
          (match_dup 1)
8460 
        ] 3124))
8461 
   (set (reg:SI 104)
8462 
        (unspec_volatile:SI [
8463 
          (match_dup 0)
8464 
          (match_dup 1)
8465 
        ] 3126))]
8466 
  "CGEN_ENABLE_INSN_P (216)"
8467 
  "cpaddla1.h\\t%0,%1"
8468 
  [(set_attr "may_trap" "no")
8469 
   (set_attr "latency" "0")
8470 
   (set_attr "length" "4")
8471 
   (set_attr "slot" "cop")
8472 
   (set_attr "slots" "p1")
8473 
   (set_attr "stall" "none")])
8474 
 
8475 
 
8476 
(define_insn "cgen_intrinsic_cpaddua1_h_C3"
8477 
  [(set (reg:SI 111)
8478 
        (unspec_volatile:SI [
8479 
          (match_operand:DI 0 "general_operand" "x")
8480 
          (match_operand:DI 1 "general_operand" "x")
8481 
        ] 3128))
8482 
   (set (reg:SI 110)
8483 
        (unspec_volatile:SI [
8484 
          (match_dup 0)
8485 
          (match_dup 1)
8486 
        ] 3130))
8487 
   (set (reg:SI 109)
8488 
        (unspec_volatile:SI [
8489 
          (match_dup 0)
8490 
          (match_dup 1)
8491 
        ] 3132))
8492 
   (set (reg:SI 108)
8493 
        (unspec_volatile:SI [
8494 
          (match_dup 0)
8495 
          (match_dup 1)
8496 
        ] 3134))]
8497 
  "CGEN_ENABLE_INSN_P (217)"
8498 
  "cpaddua1.h\\t%0,%1"
8499 
  [(set_attr "may_trap" "no")
8500 
   (set_attr "latency" "0")
8501 
   (set_attr "length" "4")
8502 
   (set_attr "slot" "cop")
8503 
   (set_attr "slots" "c3")
8504 
   (set_attr "stall" "none")])
8505 
 
8506 
 
8507 
(define_insn "cgen_intrinsic_cpaddua1_h_P1"
8508 
  [(set (reg:SI 111)
8509 
        (unspec_volatile:SI [
8510 
          (match_operand:DI 0 "general_operand" "x")
8511 
          (match_operand:DI 1 "general_operand" "x")
8512 
        ] 3128))
8513 
   (set (reg:SI 110)
8514 
        (unspec_volatile:SI [
8515 
          (match_dup 0)
8516 
          (match_dup 1)
8517 
        ] 3130))
8518 
   (set (reg:SI 109)
8519 
        (unspec_volatile:SI [
8520 
          (match_dup 0)
8521 
          (match_dup 1)
8522 
        ] 3132))
8523 
   (set (reg:SI 108)
8524 
        (unspec_volatile:SI [
8525 
          (match_dup 0)
8526 
          (match_dup 1)
8527 
        ] 3134))]
8528 
  "CGEN_ENABLE_INSN_P (218)"
8529 
  "cpaddua1.h\\t%0,%1"
8530 
  [(set_attr "may_trap" "no")
8531 
   (set_attr "latency" "0")
8532 
   (set_attr "length" "4")
8533 
   (set_attr "slot" "cop")
8534 
   (set_attr "slots" "p1")
8535 
   (set_attr "stall" "none")])
8536 
 
8537 
 
8538 
(define_insn "cgen_intrinsic_cpadda1_b_C3"
8539 
  [(set (reg:SI 111)
8540 
        (unspec_volatile:SI [
8541 
          (match_operand:DI 0 "general_operand" "x")
8542 
          (match_operand:DI 1 "general_operand" "x")
8543 
        ] 3136))
8544 
   (set (reg:SI 110)
8545 
        (unspec_volatile:SI [
8546 
          (match_dup 0)
8547 
          (match_dup 1)
8548 
        ] 3138))
8549 
   (set (reg:SI 109)
8550 
        (unspec_volatile:SI [
8551 
          (match_dup 0)
8552 
          (match_dup 1)
8553 
        ] 3140))
8554 
   (set (reg:SI 108)
8555 
        (unspec_volatile:SI [
8556 
          (match_dup 0)
8557 
          (match_dup 1)
8558 
        ] 3142))
8559 
   (set (reg:SI 107)
8560 
        (unspec_volatile:SI [
8561 
          (match_dup 0)
8562 
          (match_dup 1)
8563 
        ] 3144))
8564 
   (set (reg:SI 106)
8565 
        (unspec_volatile:SI [
8566 
          (match_dup 0)
8567 
          (match_dup 1)
8568 
        ] 3146))
8569 
   (set (reg:SI 105)
8570 
        (unspec_volatile:SI [
8571 
          (match_dup 0)
8572 
          (match_dup 1)
8573 
        ] 3148))
8574 
   (set (reg:SI 104)
8575 
        (unspec_volatile:SI [
8576 
          (match_dup 0)
8577 
          (match_dup 1)
8578 
        ] 3150))]
8579 
  "CGEN_ENABLE_INSN_P (219)"
8580 
  "cpadda1.b\\t%0,%1"
8581 
  [(set_attr "may_trap" "no")
8582 
   (set_attr "latency" "0")
8583 
   (set_attr "length" "4")
8584 
   (set_attr "slot" "cop")
8585 
   (set_attr "slots" "c3")
8586 
   (set_attr "stall" "none")])
8587 
 
8588 
 
8589 
(define_insn "cgen_intrinsic_cpadda1_b_P1"
8590 
  [(set (reg:SI 111)
8591 
        (unspec_volatile:SI [
8592 
          (match_operand:DI 0 "general_operand" "x")
8593 
          (match_operand:DI 1 "general_operand" "x")
8594 
        ] 3136))
8595 
   (set (reg:SI 110)
8596 
        (unspec_volatile:SI [
8597 
          (match_dup 0)
8598 
          (match_dup 1)
8599 
        ] 3138))
8600 
   (set (reg:SI 109)
8601 
        (unspec_volatile:SI [
8602 
          (match_dup 0)
8603 
          (match_dup 1)
8604 
        ] 3140))
8605 
   (set (reg:SI 108)
8606 
        (unspec_volatile:SI [
8607 
          (match_dup 0)
8608 
          (match_dup 1)
8609 
        ] 3142))
8610 
   (set (reg:SI 107)
8611 
        (unspec_volatile:SI [
8612 
          (match_dup 0)
8613 
          (match_dup 1)
8614 
        ] 3144))
8615 
   (set (reg:SI 106)
8616 
        (unspec_volatile:SI [
8617 
          (match_dup 0)
8618 
          (match_dup 1)
8619 
        ] 3146))
8620 
   (set (reg:SI 105)
8621 
        (unspec_volatile:SI [
8622 
          (match_dup 0)
8623 
          (match_dup 1)
8624 
        ] 3148))
8625 
   (set (reg:SI 104)
8626 
        (unspec_volatile:SI [
8627 
          (match_dup 0)
8628 
          (match_dup 1)
8629 
        ] 3150))]
8630 
  "CGEN_ENABLE_INSN_P (220)"
8631 
  "cpadda1.b\\t%0,%1"
8632 
  [(set_attr "may_trap" "no")
8633 
   (set_attr "latency" "0")
8634 
   (set_attr "length" "4")
8635 
   (set_attr "slot" "cop")
8636 
   (set_attr "slots" "p1")
8637 
   (set_attr "stall" "none")])
8638 
 
8639 
 
8640 
(define_insn "cgen_intrinsic_cpadda1u_b_C3"
8641 
  [(set (reg:SI 111)
8642 
        (unspec_volatile:SI [
8643 
          (match_operand:DI 0 "general_operand" "x")
8644 
          (match_operand:DI 1 "general_operand" "x")
8645 
        ] 3152))
8646 
   (set (reg:SI 110)
8647 
        (unspec_volatile:SI [
8648 
          (match_dup 0)
8649 
          (match_dup 1)
8650 
        ] 3154))
8651 
   (set (reg:SI 109)
8652 
        (unspec_volatile:SI [
8653 
          (match_dup 0)
8654 
          (match_dup 1)
8655 
        ] 3156))
8656 
   (set (reg:SI 108)
8657 
        (unspec_volatile:SI [
8658 
          (match_dup 0)
8659 
          (match_dup 1)
8660 
        ] 3158))
8661 
   (set (reg:SI 107)
8662 
        (unspec_volatile:SI [
8663 
          (match_dup 0)
8664 
          (match_dup 1)
8665 
        ] 3160))
8666 
   (set (reg:SI 106)
8667 
        (unspec_volatile:SI [
8668 
          (match_dup 0)
8669 
          (match_dup 1)
8670 
        ] 3162))
8671 
   (set (reg:SI 105)
8672 
        (unspec_volatile:SI [
8673 
          (match_dup 0)
8674 
          (match_dup 1)
8675 
        ] 3164))
8676 
   (set (reg:SI 104)
8677 
        (unspec_volatile:SI [
8678 
          (match_dup 0)
8679 
          (match_dup 1)
8680 
        ] 3166))]
8681 
  "CGEN_ENABLE_INSN_P (221)"
8682 
  "cpadda1u.b\\t%0,%1"
8683 
  [(set_attr "may_trap" "no")
8684 
   (set_attr "latency" "0")
8685 
   (set_attr "length" "4")
8686 
   (set_attr "slot" "cop")
8687 
   (set_attr "slots" "c3")
8688 
   (set_attr "stall" "none")])
8689 
 
8690 
 
8691 
(define_insn "cgen_intrinsic_cpadda1u_b_P1"
8692 
  [(set (reg:SI 111)
8693 
        (unspec_volatile:SI [
8694 
          (match_operand:DI 0 "general_operand" "x")
8695 
          (match_operand:DI 1 "general_operand" "x")
8696 
        ] 3152))
8697 
   (set (reg:SI 110)
8698 
        (unspec_volatile:SI [
8699 
          (match_dup 0)
8700 
          (match_dup 1)
8701 
        ] 3154))
8702 
   (set (reg:SI 109)
8703 
        (unspec_volatile:SI [
8704 
          (match_dup 0)
8705 
          (match_dup 1)
8706 
        ] 3156))
8707 
   (set (reg:SI 108)
8708 
        (unspec_volatile:SI [
8709 
          (match_dup 0)
8710 
          (match_dup 1)
8711 
        ] 3158))
8712 
   (set (reg:SI 107)
8713 
        (unspec_volatile:SI [
8714 
          (match_dup 0)
8715 
          (match_dup 1)
8716 
        ] 3160))
8717 
   (set (reg:SI 106)
8718 
        (unspec_volatile:SI [
8719 
          (match_dup 0)
8720 
          (match_dup 1)
8721 
        ] 3162))
8722 
   (set (reg:SI 105)
8723 
        (unspec_volatile:SI [
8724 
          (match_dup 0)
8725 
          (match_dup 1)
8726 
        ] 3164))
8727 
   (set (reg:SI 104)
8728 
        (unspec_volatile:SI [
8729 
          (match_dup 0)
8730 
          (match_dup 1)
8731 
        ] 3166))]
8732 
  "CGEN_ENABLE_INSN_P (222)"
8733 
  "cpadda1u.b\\t%0,%1"
8734 
  [(set_attr "may_trap" "no")
8735 
   (set_attr "latency" "0")
8736 
   (set_attr "length" "4")
8737 
   (set_attr "slot" "cop")
8738 
   (set_attr "slots" "p1")
8739 
   (set_attr "stall" "none")])
8740 
 
8741 
 
8742 
(define_insn "cgen_intrinsic_cpmovi_b_C3"
8743 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
8744 
        (unspec:DI [
8745 
          (match_operand:DI 1 "cgen_h_sint_8a1_immediate" "")
8746 
        ] 3180))]
8747 
  "CGEN_ENABLE_INSN_P (223)"
8748 
  "cpmovi.b\\t%0,%1"
8749 
  [(set_attr "may_trap" "no")
8750 
   (set_attr "latency" "0")
8751 
   (set_attr "length" "4")
8752 
   (set_attr "slot" "cop")
8753 
   (set_attr "slots" "c3")
8754 
   (set_attr "stall" "none")])
8755 
 
8756 
 
8757 
(define_insn "cgen_intrinsic_cpmovi_b_P0S_P1"
8758 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
8759 
        (unspec:DI [
8760 
          (match_operand:DI 1 "cgen_h_sint_8a1_immediate" "")
8761 
        ] 3180))]
8762 
  "CGEN_ENABLE_INSN_P (224)"
8763 
  "cpmovi.b\\t%0,%1"
8764 
  [(set_attr "may_trap" "no")
8765 
   (set_attr "latency" "0")
8766 
   (set_attr "length" "4")
8767 
   (set_attr "slot" "cop")
8768 
   (set_attr "slots" "p0s_p1")
8769 
   (set_attr "stall" "none")])
8770 
 
8771 
 
8772 
(define_insn "cgen_intrinsic_c1nop_P1"
8773 
  [(unspec_volatile [
8774 
     (const_int 0)
8775 
   ] 1482)]
8776 
  "CGEN_ENABLE_INSN_P (225)"
8777 
  "c1nop"
8778 
  [(set_attr "may_trap" "no")
8779 
   (set_attr "latency" "0")
8780 
   (set_attr "length" "4")
8781 
   (set_attr "slot" "cop")
8782 
   (set_attr "slots" "p1")
8783 
   (set_attr "stall" "none")])
8784 
 
8785 
 
8786 
(define_insn "cgen_intrinsic_cdmovi_C3"
8787 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
8788 
        (unspec:DI [
8789 
          (match_operand:DI 1 "cgen_h_sint_8a1_immediate" "")
8790 
        ] 3168))]
8791 
  "CGEN_ENABLE_INSN_P (226)"
8792 
  "cdmovi\\t%0,%1"
8793 
  [(set_attr "may_trap" "no")
8794 
   (set_attr "latency" "0")
8795 
   (set_attr "length" "4")
8796 
   (set_attr "slot" "cop")
8797 
   (set_attr "slots" "c3")
8798 
   (set_attr "stall" "none")])
8799 
 
8800 
 
8801 
(define_insn "cgen_intrinsic_cdmovi_P0_P1"
8802 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
8803 
        (unspec:DI [
8804 
          (match_operand:DI 1 "cgen_h_sint_16a1_immediate" "")
8805 
        ] 3168))]
8806 
  "CGEN_ENABLE_INSN_P (227)"
8807 
  "cdmovi\\t%0,%1"
8808 
  [(set_attr "may_trap" "no")
8809 
   (set_attr "latency" "0")
8810 
   (set_attr "length" "4")
8811 
   (set_attr "slot" "cop")
8812 
   (set_attr "slots" "p0_p1")
8813 
   (set_attr "stall" "none")])
8814 
 
8815 
 
8816 
(define_insn "cgen_intrinsic_cdmoviu_C3"
8817 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
8818 
        (unspec:DI [
8819 
          (match_operand:DI 1 "cgen_h_uint_8a1_immediate" "")
8820 
        ] 3170))]
8821 
  "CGEN_ENABLE_INSN_P (228)"
8822 
  "cdmoviu\\t%0,%1"
8823 
  [(set_attr "may_trap" "no")
8824 
   (set_attr "latency" "0")
8825 
   (set_attr "length" "4")
8826 
   (set_attr "slot" "cop")
8827 
   (set_attr "slots" "c3")
8828 
   (set_attr "stall" "none")])
8829 
 
8830 
 
8831 
(define_insn "cgen_intrinsic_cdmoviu_P0_P1"
8832 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
8833 
        (unspec:DI [
8834 
          (match_operand:DI 1 "cgen_h_uint_16a1_immediate" "")
8835 
        ] 3170))]
8836 
  "CGEN_ENABLE_INSN_P (229)"
8837 
  "cdmoviu\\t%0,%1"
8838 
  [(set_attr "may_trap" "no")
8839 
   (set_attr "latency" "0")
8840 
   (set_attr "length" "4")
8841 
   (set_attr "slot" "cop")
8842 
   (set_attr "slots" "p0_p1")
8843 
   (set_attr "stall" "none")])
8844 
 
8845 
 
8846 
(define_insn "cgen_intrinsic_cpmovi_w_C3"
8847 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
8848 
        (unspec:DI [
8849 
          (match_operand:DI 1 "cgen_h_sint_8a1_immediate" "")
8850 
        ] 3172))]
8851 
  "CGEN_ENABLE_INSN_P (230)"
8852 
  "cpmovi.w\\t%0,%1"
8853 
  [(set_attr "may_trap" "no")
8854 
   (set_attr "latency" "0")
8855 
   (set_attr "length" "4")
8856 
   (set_attr "slot" "cop")
8857 
   (set_attr "slots" "c3")
8858 
   (set_attr "stall" "none")])
8859 
 
8860 
 
8861 
(define_insn "cgen_intrinsic_cpmovi_w_P0_P1"
8862 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
8863 
        (unspec:DI [
8864 
          (match_operand:DI 1 "cgen_h_sint_16a1_immediate" "")
8865 
        ] 3172))]
8866 
  "CGEN_ENABLE_INSN_P (231)"
8867 
  "cpmovi.w\\t%0,%1"
8868 
  [(set_attr "may_trap" "no")
8869 
   (set_attr "latency" "0")
8870 
   (set_attr "length" "4")
8871 
   (set_attr "slot" "cop")
8872 
   (set_attr "slots" "p0_p1")
8873 
   (set_attr "stall" "none")])
8874 
 
8875 
 
8876 
(define_insn "cgen_intrinsic_cpmoviu_w_C3"
8877 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
8878 
        (unspec:DI [
8879 
          (match_operand:DI 1 "cgen_h_uint_8a1_immediate" "")
8880 
        ] 3174))]
8881 
  "CGEN_ENABLE_INSN_P (232)"
8882 
  "cpmoviu.w\\t%0,%1"
8883 
  [(set_attr "may_trap" "no")
8884 
   (set_attr "latency" "0")
8885 
   (set_attr "length" "4")
8886 
   (set_attr "slot" "cop")
8887 
   (set_attr "slots" "c3")
8888 
   (set_attr "stall" "none")])
8889 
 
8890 
 
8891 
(define_insn "cgen_intrinsic_cpmoviu_w_P0_P1"
8892 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
8893 
        (unspec:DI [
8894 
          (match_operand:DI 1 "cgen_h_uint_16a1_immediate" "")
8895 
        ] 3174))]
8896 
  "CGEN_ENABLE_INSN_P (233)"
8897 
  "cpmoviu.w\\t%0,%1"
8898 
  [(set_attr "may_trap" "no")
8899 
   (set_attr "latency" "0")
8900 
   (set_attr "length" "4")
8901 
   (set_attr "slot" "cop")
8902 
   (set_attr "slots" "p0_p1")
8903 
   (set_attr "stall" "none")])
8904 
 
8905 
 
8906 
(define_insn "cgen_intrinsic_cpmovi_h_C3"
8907 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
8908 
        (unspec:DI [
8909 
          (match_operand:DI 1 "cgen_h_sint_8a1_immediate" "")
8910 
        ] 3176))]
8911 
  "CGEN_ENABLE_INSN_P (234)"
8912 
  "cpmovi.h\\t%0,%1"
8913 
  [(set_attr "may_trap" "no")
8914 
   (set_attr "latency" "0")
8915 
   (set_attr "length" "4")
8916 
   (set_attr "slot" "cop")
8917 
   (set_attr "slots" "c3")
8918 
   (set_attr "stall" "none")])
8919 
 
8920 
 
8921 
(define_insn "cgen_intrinsic_cpmovi_h_P0_P1"
8922 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
8923 
        (unspec:DI [
8924 
          (match_operand:DI 1 "cgen_h_sint_16a1_immediate" "")
8925 
        ] 3176))]
8926 
  "CGEN_ENABLE_INSN_P (235)"
8927 
  "cpmovi.h\\t%0,%1"
8928 
  [(set_attr "may_trap" "no")
8929 
   (set_attr "latency" "0")
8930 
   (set_attr "length" "4")
8931 
   (set_attr "slot" "cop")
8932 
   (set_attr "slots" "p0_p1")
8933 
   (set_attr "stall" "none")])
8934 
 
8935 
 
8936 
(define_insn "cgen_intrinsic_cdclipi3_C3"
8937 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
8938 
        (unspec:DI [
8939 
          (match_operand:DI 1 "general_operand" "x")
8940 
          (match_operand:DI 2 "cgen_h_uint_6a1_immediate" "")
8941 
        ] 3182))]
8942 
  "CGEN_ENABLE_INSN_P (236)"
8943 
  "cdclipi3\\t%0,%1,%2"
8944 
  [(set_attr "may_trap" "no")
8945 
   (set_attr "latency" "0")
8946 
   (set_attr "length" "4")
8947 
   (set_attr "slot" "cop")
8948 
   (set_attr "slots" "c3")
8949 
   (set_attr "stall" "none")])
8950 
 
8951 
 
8952 
(define_insn "cgen_intrinsic_cdclipi3_P0_P1"
8953 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
8954 
        (unspec:DI [
8955 
          (match_operand:DI 1 "general_operand" "x")
8956 
          (match_operand:DI 2 "cgen_h_uint_6a1_immediate" "")
8957 
        ] 3182))]
8958 
  "CGEN_ENABLE_INSN_P (237)"
8959 
  "cdclipi3\\t%0,%1,%2"
8960 
  [(set_attr "may_trap" "no")
8961 
   (set_attr "latency" "0")
8962 
   (set_attr "length" "4")
8963 
   (set_attr "slot" "cop")
8964 
   (set_attr "slots" "p0_p1")
8965 
   (set_attr "stall" "none")])
8966 
 
8967 
 
8968 
(define_insn "cgen_intrinsic_cdclipiu3_C3"
8969 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
8970 
        (unspec:DI [
8971 
          (match_operand:DI 1 "general_operand" "x")
8972 
          (match_operand:DI 2 "cgen_h_uint_6a1_immediate" "")
8973 
        ] 3184))]
8974 
  "CGEN_ENABLE_INSN_P (238)"
8975 
  "cdclipiu3\\t%0,%1,%2"
8976 
  [(set_attr "may_trap" "no")
8977 
   (set_attr "latency" "0")
8978 
   (set_attr "length" "4")
8979 
   (set_attr "slot" "cop")
8980 
   (set_attr "slots" "c3")
8981 
   (set_attr "stall" "none")])
8982 
 
8983 
 
8984 
(define_insn "cgen_intrinsic_cdclipiu3_P0_P1"
8985 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
8986 
        (unspec:DI [
8987 
          (match_operand:DI 1 "general_operand" "x")
8988 
          (match_operand:DI 2 "cgen_h_uint_6a1_immediate" "")
8989 
        ] 3184))]
8990 
  "CGEN_ENABLE_INSN_P (239)"
8991 
  "cdclipiu3\\t%0,%1,%2"
8992 
  [(set_attr "may_trap" "no")
8993 
   (set_attr "latency" "0")
8994 
   (set_attr "length" "4")
8995 
   (set_attr "slot" "cop")
8996 
   (set_attr "slots" "p0_p1")
8997 
   (set_attr "stall" "none")])
8998 
 
8999 
 
9000 
(define_insn "cgen_intrinsic_cpclipi3_w_C3"
9001 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9002 
        (unspec:DI [
9003 
          (match_operand:DI 1 "general_operand" "x")
9004 
          (match_operand:DI 2 "cgen_h_uint_5a1_immediate" "")
9005 
        ] 3186))]
9006 
  "CGEN_ENABLE_INSN_P (240)"
9007 
  "cpclipi3.w\\t%0,%1,%2"
9008 
  [(set_attr "may_trap" "no")
9009 
   (set_attr "latency" "0")
9010 
   (set_attr "length" "4")
9011 
   (set_attr "slot" "cop")
9012 
   (set_attr "slots" "c3")
9013 
   (set_attr "stall" "none")])
9014 
 
9015 
 
9016 
(define_insn "cgen_intrinsic_cpclipi3_w_P0_P1"
9017 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9018 
        (unspec:DI [
9019 
          (match_operand:DI 1 "general_operand" "x")
9020 
          (match_operand:DI 2 "cgen_h_uint_5a1_immediate" "")
9021 
        ] 3186))]
9022 
  "CGEN_ENABLE_INSN_P (241)"
9023 
  "cpclipi3.w\\t%0,%1,%2"
9024 
  [(set_attr "may_trap" "no")
9025 
   (set_attr "latency" "0")
9026 
   (set_attr "length" "4")
9027 
   (set_attr "slot" "cop")
9028 
   (set_attr "slots" "p0_p1")
9029 
   (set_attr "stall" "none")])
9030 
 
9031 
 
9032 
(define_insn "cgen_intrinsic_cpclipiu3_w_C3"
9033 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9034 
        (unspec:DI [
9035 
          (match_operand:DI 1 "general_operand" "x")
9036 
          (match_operand:DI 2 "cgen_h_uint_5a1_immediate" "")
9037 
        ] 3188))]
9038 
  "CGEN_ENABLE_INSN_P (242)"
9039 
  "cpclipiu3.w\\t%0,%1,%2"
9040 
  [(set_attr "may_trap" "no")
9041 
   (set_attr "latency" "0")
9042 
   (set_attr "length" "4")
9043 
   (set_attr "slot" "cop")
9044 
   (set_attr "slots" "c3")
9045 
   (set_attr "stall" "none")])
9046 
 
9047 
 
9048 
(define_insn "cgen_intrinsic_cpclipiu3_w_P0_P1"
9049 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9050 
        (unspec:DI [
9051 
          (match_operand:DI 1 "general_operand" "x")
9052 
          (match_operand:DI 2 "cgen_h_uint_5a1_immediate" "")
9053 
        ] 3188))]
9054 
  "CGEN_ENABLE_INSN_P (243)"
9055 
  "cpclipiu3.w\\t%0,%1,%2"
9056 
  [(set_attr "may_trap" "no")
9057 
   (set_attr "latency" "0")
9058 
   (set_attr "length" "4")
9059 
   (set_attr "slot" "cop")
9060 
   (set_attr "slots" "p0_p1")
9061 
   (set_attr "stall" "none")])
9062 
 
9063 
 
9064 
(define_insn "cgen_intrinsic_cpslai3_w_C3"
9065 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9066 
        (unspec_volatile:DI [
9067 
          (match_operand:DI 1 "general_operand" "x")
9068 
          (match_operand:DI 2 "cgen_h_uint_5a1_immediate" "")
9069 
        ] 3190))]
9070 
  "CGEN_ENABLE_INSN_P (244)"
9071 
  "cpslai3.w\\t%0,%1,%2"
9072 
  [(set_attr "may_trap" "no")
9073 
   (set_attr "latency" "0")
9074 
   (set_attr "length" "4")
9075 
   (set_attr "slot" "cop")
9076 
   (set_attr "slots" "c3")
9077 
   (set_attr "stall" "none")])
9078 
 
9079 
 
9080 
(define_insn "cgen_intrinsic_cpslai3_w_P0_P1"
9081 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9082 
        (unspec_volatile:DI [
9083 
          (match_operand:DI 1 "general_operand" "x")
9084 
          (match_operand:DI 2 "cgen_h_uint_5a1_immediate" "")
9085 
        ] 3190))]
9086 
  "CGEN_ENABLE_INSN_P (245)"
9087 
  "cpslai3.w\\t%0,%1,%2"
9088 
  [(set_attr "may_trap" "no")
9089 
   (set_attr "latency" "0")
9090 
   (set_attr "length" "4")
9091 
   (set_attr "slot" "cop")
9092 
   (set_attr "slots" "p0_p1")
9093 
   (set_attr "stall" "none")])
9094 
 
9095 
 
9096 
(define_insn "cgen_intrinsic_cpslai3_h_C3"
9097 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9098 
        (unspec_volatile:DI [
9099 
          (match_operand:DI 1 "general_operand" "x")
9100 
          (match_operand:DI 2 "cgen_h_uint_4a1_immediate" "")
9101 
        ] 3192))]
9102 
  "CGEN_ENABLE_INSN_P (246)"
9103 
  "cpslai3.h\\t%0,%1,%2"
9104 
  [(set_attr "may_trap" "no")
9105 
   (set_attr "latency" "0")
9106 
   (set_attr "length" "4")
9107 
   (set_attr "slot" "cop")
9108 
   (set_attr "slots" "c3")
9109 
   (set_attr "stall" "none")])
9110 
 
9111 
 
9112 
(define_insn "cgen_intrinsic_cpslai3_h_P0_P1"
9113 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9114 
        (unspec_volatile:DI [
9115 
          (match_operand:DI 1 "general_operand" "x")
9116 
          (match_operand:DI 2 "cgen_h_uint_4a1_immediate" "")
9117 
        ] 3192))]
9118 
  "CGEN_ENABLE_INSN_P (247)"
9119 
  "cpslai3.h\\t%0,%1,%2"
9120 
  [(set_attr "may_trap" "no")
9121 
   (set_attr "latency" "0")
9122 
   (set_attr "length" "4")
9123 
   (set_attr "slot" "cop")
9124 
   (set_attr "slots" "p0_p1")
9125 
   (set_attr "stall" "none")])
9126 
 
9127 
 
9128 
(define_insn "cgen_intrinsic_cdslli3_C3"
9129 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9130 
        (unspec:DI [
9131 
          (match_operand:DI 1 "general_operand" "x")
9132 
          (match_operand:DI 2 "cgen_h_uint_6a1_immediate" "")
9133 
        ] 3194))]
9134 
  "CGEN_ENABLE_INSN_P (248)"
9135 
  "cdslli3\\t%0,%1,%2"
9136 
  [(set_attr "may_trap" "no")
9137 
   (set_attr "latency" "0")
9138 
   (set_attr "length" "4")
9139 
   (set_attr "slot" "cop")
9140 
   (set_attr "slots" "c3")
9141 
   (set_attr "stall" "none")])
9142 
 
9143 
 
9144 
(define_insn "cgen_intrinsic_cdslli3_P0_P1"
9145 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9146 
        (unspec:DI [
9147 
          (match_operand:DI 1 "general_operand" "x")
9148 
          (match_operand:DI 2 "cgen_h_uint_6a1_immediate" "")
9149 
        ] 3194))]
9150 
  "CGEN_ENABLE_INSN_P (249)"
9151 
  "cdslli3\\t%0,%1,%2"
9152 
  [(set_attr "may_trap" "no")
9153 
   (set_attr "latency" "0")
9154 
   (set_attr "length" "4")
9155 
   (set_attr "slot" "cop")
9156 
   (set_attr "slots" "p0_p1")
9157 
   (set_attr "stall" "none")])
9158 
 
9159 
 
9160 
(define_insn "cgen_intrinsic_cpslli3_w_C3"
9161 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9162 
        (unspec:DI [
9163 
          (match_operand:DI 1 "general_operand" "x")
9164 
          (match_operand:DI 2 "cgen_h_uint_5a1_immediate" "")
9165 
        ] 3196))]
9166 
  "CGEN_ENABLE_INSN_P (250)"
9167 
  "cpslli3.w\\t%0,%1,%2"
9168 
  [(set_attr "may_trap" "no")
9169 
   (set_attr "latency" "0")
9170 
   (set_attr "length" "4")
9171 
   (set_attr "slot" "cop")
9172 
   (set_attr "slots" "c3")
9173 
   (set_attr "stall" "none")])
9174 
 
9175 
 
9176 
(define_insn "cgen_intrinsic_cpslli3_w_P0_P1"
9177 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9178 
        (unspec:DI [
9179 
          (match_operand:DI 1 "general_operand" "x")
9180 
          (match_operand:DI 2 "cgen_h_uint_5a1_immediate" "")
9181 
        ] 3196))]
9182 
  "CGEN_ENABLE_INSN_P (251)"
9183 
  "cpslli3.w\\t%0,%1,%2"
9184 
  [(set_attr "may_trap" "no")
9185 
   (set_attr "latency" "0")
9186 
   (set_attr "length" "4")
9187 
   (set_attr "slot" "cop")
9188 
   (set_attr "slots" "p0_p1")
9189 
   (set_attr "stall" "none")])
9190 
 
9191 
 
9192 
(define_insn "cgen_intrinsic_cpslli3_h_C3"
9193 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9194 
        (unspec:DI [
9195 
          (match_operand:DI 1 "general_operand" "x")
9196 
          (match_operand:DI 2 "cgen_h_uint_4a1_immediate" "")
9197 
        ] 3198))]
9198 
  "CGEN_ENABLE_INSN_P (252)"
9199 
  "cpslli3.h\\t%0,%1,%2"
9200 
  [(set_attr "may_trap" "no")
9201 
   (set_attr "latency" "0")
9202 
   (set_attr "length" "4")
9203 
   (set_attr "slot" "cop")
9204 
   (set_attr "slots" "c3")
9205 
   (set_attr "stall" "none")])
9206 
 
9207 
 
9208 
(define_insn "cgen_intrinsic_cpslli3_h_P0_P1"
9209 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9210 
        (unspec:DI [
9211 
          (match_operand:DI 1 "general_operand" "x")
9212 
          (match_operand:DI 2 "cgen_h_uint_4a1_immediate" "")
9213 
        ] 3198))]
9214 
  "CGEN_ENABLE_INSN_P (253)"
9215 
  "cpslli3.h\\t%0,%1,%2"
9216 
  [(set_attr "may_trap" "no")
9217 
   (set_attr "latency" "0")
9218 
   (set_attr "length" "4")
9219 
   (set_attr "slot" "cop")
9220 
   (set_attr "slots" "p0_p1")
9221 
   (set_attr "stall" "none")])
9222 
 
9223 
 
9224 
(define_insn "cgen_intrinsic_cpslli3_b_C3"
9225 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9226 
        (unspec:DI [
9227 
          (match_operand:DI 1 "general_operand" "x")
9228 
          (match_operand:DI 2 "cgen_h_uint_3a1_immediate" "")
9229 
        ] 3200))]
9230 
  "CGEN_ENABLE_INSN_P (254)"
9231 
  "cpslli3.b\\t%0,%1,%2"
9232 
  [(set_attr "may_trap" "no")
9233 
   (set_attr "latency" "0")
9234 
   (set_attr "length" "4")
9235 
   (set_attr "slot" "cop")
9236 
   (set_attr "slots" "c3")
9237 
   (set_attr "stall" "none")])
9238 
 
9239 
 
9240 
(define_insn "cgen_intrinsic_cpslli3_b_P0_P1"
9241 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9242 
        (unspec:DI [
9243 
          (match_operand:DI 1 "general_operand" "x")
9244 
          (match_operand:DI 2 "cgen_h_uint_3a1_immediate" "")
9245 
        ] 3200))]
9246 
  "CGEN_ENABLE_INSN_P (255)"
9247 
  "cpslli3.b\\t%0,%1,%2"
9248 
  [(set_attr "may_trap" "no")
9249 
   (set_attr "latency" "0")
9250 
   (set_attr "length" "4")
9251 
   (set_attr "slot" "cop")
9252 
   (set_attr "slots" "p0_p1")
9253 
   (set_attr "stall" "none")])
9254 
 
9255 
 
9256 
(define_insn "cgen_intrinsic_cdsrai3_C3"
9257 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9258 
        (unspec:DI [
9259 
          (match_operand:DI 1 "general_operand" "x")
9260 
          (match_operand:DI 2 "cgen_h_uint_6a1_immediate" "")
9261 
        ] 3202))]
9262 
  "CGEN_ENABLE_INSN_P (256)"
9263 
  "cdsrai3\\t%0,%1,%2"
9264 
  [(set_attr "may_trap" "no")
9265 
   (set_attr "latency" "0")
9266 
   (set_attr "length" "4")
9267 
   (set_attr "slot" "cop")
9268 
   (set_attr "slots" "c3")
9269 
   (set_attr "stall" "none")])
9270 
 
9271 
 
9272 
(define_insn "cgen_intrinsic_cdsrai3_P0_P1"
9273 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9274 
        (unspec:DI [
9275 
          (match_operand:DI 1 "general_operand" "x")
9276 
          (match_operand:DI 2 "cgen_h_uint_6a1_immediate" "")
9277 
        ] 3202))]
9278 
  "CGEN_ENABLE_INSN_P (257)"
9279 
  "cdsrai3\\t%0,%1,%2"
9280 
  [(set_attr "may_trap" "no")
9281 
   (set_attr "latency" "0")
9282 
   (set_attr "length" "4")
9283 
   (set_attr "slot" "cop")
9284 
   (set_attr "slots" "p0_p1")
9285 
   (set_attr "stall" "none")])
9286 
 
9287 
 
9288 
(define_insn "cgen_intrinsic_cpsrai3_w_C3"
9289 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9290 
        (unspec:DI [
9291 
          (match_operand:DI 1 "general_operand" "x")
9292 
          (match_operand:DI 2 "cgen_h_uint_5a1_immediate" "")
9293 
        ] 3204))]
9294 
  "CGEN_ENABLE_INSN_P (258)"
9295 
  "cpsrai3.w\\t%0,%1,%2"
9296 
  [(set_attr "may_trap" "no")
9297 
   (set_attr "latency" "0")
9298 
   (set_attr "length" "4")
9299 
   (set_attr "slot" "cop")
9300 
   (set_attr "slots" "c3")
9301 
   (set_attr "stall" "none")])
9302 
 
9303 
 
9304 
(define_insn "cgen_intrinsic_cpsrai3_w_P0_P1"
9305 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9306 
        (unspec:DI [
9307 
          (match_operand:DI 1 "general_operand" "x")
9308 
          (match_operand:DI 2 "cgen_h_uint_5a1_immediate" "")
9309 
        ] 3204))]
9310 
  "CGEN_ENABLE_INSN_P (259)"
9311 
  "cpsrai3.w\\t%0,%1,%2"
9312 
  [(set_attr "may_trap" "no")
9313 
   (set_attr "latency" "0")
9314 
   (set_attr "length" "4")
9315 
   (set_attr "slot" "cop")
9316 
   (set_attr "slots" "p0_p1")
9317 
   (set_attr "stall" "none")])
9318 
 
9319 
 
9320 
(define_insn "cgen_intrinsic_cpsrai3_h_C3"
9321 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9322 
        (unspec:DI [
9323 
          (match_operand:DI 1 "general_operand" "x")
9324 
          (match_operand:DI 2 "cgen_h_uint_4a1_immediate" "")
9325 
        ] 3206))]
9326 
  "CGEN_ENABLE_INSN_P (260)"
9327 
  "cpsrai3.h\\t%0,%1,%2"
9328 
  [(set_attr "may_trap" "no")
9329 
   (set_attr "latency" "0")
9330 
   (set_attr "length" "4")
9331 
   (set_attr "slot" "cop")
9332 
   (set_attr "slots" "c3")
9333 
   (set_attr "stall" "none")])
9334 
 
9335 
 
9336 
(define_insn "cgen_intrinsic_cpsrai3_h_P0_P1"
9337 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9338 
        (unspec:DI [
9339 
          (match_operand:DI 1 "general_operand" "x")
9340 
          (match_operand:DI 2 "cgen_h_uint_4a1_immediate" "")
9341 
        ] 3206))]
9342 
  "CGEN_ENABLE_INSN_P (261)"
9343 
  "cpsrai3.h\\t%0,%1,%2"
9344 
  [(set_attr "may_trap" "no")
9345 
   (set_attr "latency" "0")
9346 
   (set_attr "length" "4")
9347 
   (set_attr "slot" "cop")
9348 
   (set_attr "slots" "p0_p1")
9349 
   (set_attr "stall" "none")])
9350 
 
9351 
 
9352 
(define_insn "cgen_intrinsic_cpsrai3_b_C3"
9353 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9354 
        (unspec:DI [
9355 
          (match_operand:DI 1 "general_operand" "x")
9356 
          (match_operand:DI 2 "cgen_h_uint_3a1_immediate" "")
9357 
        ] 3208))]
9358 
  "CGEN_ENABLE_INSN_P (262)"
9359 
  "cpsrai3.b\\t%0,%1,%2"
9360 
  [(set_attr "may_trap" "no")
9361 
   (set_attr "latency" "0")
9362 
   (set_attr "length" "4")
9363 
   (set_attr "slot" "cop")
9364 
   (set_attr "slots" "c3")
9365 
   (set_attr "stall" "none")])
9366 
 
9367 
 
9368 
(define_insn "cgen_intrinsic_cpsrai3_b_P0_P1"
9369 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9370 
        (unspec:DI [
9371 
          (match_operand:DI 1 "general_operand" "x")
9372 
          (match_operand:DI 2 "cgen_h_uint_3a1_immediate" "")
9373 
        ] 3208))]
9374 
  "CGEN_ENABLE_INSN_P (263)"
9375 
  "cpsrai3.b\\t%0,%1,%2"
9376 
  [(set_attr "may_trap" "no")
9377 
   (set_attr "latency" "0")
9378 
   (set_attr "length" "4")
9379 
   (set_attr "slot" "cop")
9380 
   (set_attr "slots" "p0_p1")
9381 
   (set_attr "stall" "none")])
9382 
 
9383 
 
9384 
(define_insn "cgen_intrinsic_cdsrli3_C3"
9385 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9386 
        (unspec:DI [
9387 
          (match_operand:DI 1 "general_operand" "x")
9388 
          (match_operand:DI 2 "cgen_h_uint_6a1_immediate" "")
9389 
        ] 3210))]
9390 
  "CGEN_ENABLE_INSN_P (264)"
9391 
  "cdsrli3\\t%0,%1,%2"
9392 
  [(set_attr "may_trap" "no")
9393 
   (set_attr "latency" "0")
9394 
   (set_attr "length" "4")
9395 
   (set_attr "slot" "cop")
9396 
   (set_attr "slots" "c3")
9397 
   (set_attr "stall" "none")])
9398 
 
9399 
 
9400 
(define_insn "cgen_intrinsic_cdsrli3_P0_P1"
9401 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9402 
        (unspec:DI [
9403 
          (match_operand:DI 1 "general_operand" "x")
9404 
          (match_operand:DI 2 "cgen_h_uint_6a1_immediate" "")
9405 
        ] 3210))]
9406 
  "CGEN_ENABLE_INSN_P (265)"
9407 
  "cdsrli3\\t%0,%1,%2"
9408 
  [(set_attr "may_trap" "no")
9409 
   (set_attr "latency" "0")
9410 
   (set_attr "length" "4")
9411 
   (set_attr "slot" "cop")
9412 
   (set_attr "slots" "p0_p1")
9413 
   (set_attr "stall" "none")])
9414 
 
9415 
 
9416 
(define_insn "cgen_intrinsic_cpsrli3_w_C3"
9417 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9418 
        (unspec:DI [
9419 
          (match_operand:DI 1 "general_operand" "x")
9420 
          (match_operand:DI 2 "cgen_h_uint_5a1_immediate" "")
9421 
        ] 3212))]
9422 
  "CGEN_ENABLE_INSN_P (266)"
9423 
  "cpsrli3.w\\t%0,%1,%2"
9424 
  [(set_attr "may_trap" "no")
9425 
   (set_attr "latency" "0")
9426 
   (set_attr "length" "4")
9427 
   (set_attr "slot" "cop")
9428 
   (set_attr "slots" "c3")
9429 
   (set_attr "stall" "none")])
9430 
 
9431 
 
9432 
(define_insn "cgen_intrinsic_cpsrli3_w_P0_P1"
9433 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9434 
        (unspec:DI [
9435 
          (match_operand:DI 1 "general_operand" "x")
9436 
          (match_operand:DI 2 "cgen_h_uint_5a1_immediate" "")
9437 
        ] 3212))]
9438 
  "CGEN_ENABLE_INSN_P (267)"
9439 
  "cpsrli3.w\\t%0,%1,%2"
9440 
  [(set_attr "may_trap" "no")
9441 
   (set_attr "latency" "0")
9442 
   (set_attr "length" "4")
9443 
   (set_attr "slot" "cop")
9444 
   (set_attr "slots" "p0_p1")
9445 
   (set_attr "stall" "none")])
9446 
 
9447 
 
9448 
(define_insn "cgen_intrinsic_cpsrli3_h_C3"
9449 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9450 
        (unspec:DI [
9451 
          (match_operand:DI 1 "general_operand" "x")
9452 
          (match_operand:DI 2 "cgen_h_uint_4a1_immediate" "")
9453 
        ] 3214))]
9454 
  "CGEN_ENABLE_INSN_P (268)"
9455 
  "cpsrli3.h\\t%0,%1,%2"
9456 
  [(set_attr "may_trap" "no")
9457 
   (set_attr "latency" "0")
9458 
   (set_attr "length" "4")
9459 
   (set_attr "slot" "cop")
9460 
   (set_attr "slots" "c3")
9461 
   (set_attr "stall" "none")])
9462 
 
9463 
 
9464 
(define_insn "cgen_intrinsic_cpsrli3_h_P0_P1"
9465 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9466 
        (unspec:DI [
9467 
          (match_operand:DI 1 "general_operand" "x")
9468 
          (match_operand:DI 2 "cgen_h_uint_4a1_immediate" "")
9469 
        ] 3214))]
9470 
  "CGEN_ENABLE_INSN_P (269)"
9471 
  "cpsrli3.h\\t%0,%1,%2"
9472 
  [(set_attr "may_trap" "no")
9473 
   (set_attr "latency" "0")
9474 
   (set_attr "length" "4")
9475 
   (set_attr "slot" "cop")
9476 
   (set_attr "slots" "p0_p1")
9477 
   (set_attr "stall" "none")])
9478 
 
9479 
 
9480 
(define_insn "cgen_intrinsic_cpsrli3_b_C3"
9481 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9482 
        (unspec:DI [
9483 
          (match_operand:DI 1 "general_operand" "x")
9484 
          (match_operand:DI 2 "cgen_h_uint_3a1_immediate" "")
9485 
        ] 3216))]
9486 
  "CGEN_ENABLE_INSN_P (270)"
9487 
  "cpsrli3.b\\t%0,%1,%2"
9488 
  [(set_attr "may_trap" "no")
9489 
   (set_attr "latency" "0")
9490 
   (set_attr "length" "4")
9491 
   (set_attr "slot" "cop")
9492 
   (set_attr "slots" "c3")
9493 
   (set_attr "stall" "none")])
9494 
 
9495 
 
9496 
(define_insn "cgen_intrinsic_cpsrli3_b_P0_P1"
9497 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9498 
        (unspec:DI [
9499 
          (match_operand:DI 1 "general_operand" "x")
9500 
          (match_operand:DI 2 "cgen_h_uint_3a1_immediate" "")
9501 
        ] 3216))]
9502 
  "CGEN_ENABLE_INSN_P (271)"
9503 
  "cpsrli3.b\\t%0,%1,%2"
9504 
  [(set_attr "may_trap" "no")
9505 
   (set_attr "latency" "0")
9506 
   (set_attr "length" "4")
9507 
   (set_attr "slot" "cop")
9508 
   (set_attr "slots" "p0_p1")
9509 
   (set_attr "stall" "none")])
9510 
 
9511 
 
9512 
(define_insn "cgen_intrinsic_cpsla3_w_C3"
9513 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9514 
        (unspec_volatile:DI [
9515 
          (match_operand:DI 1 "general_operand" "x")
9516 
          (match_operand:DI 2 "general_operand" "x")
9517 
        ] 3460))]
9518 
  "CGEN_ENABLE_INSN_P (272)"
9519 
  "cpsla3.w\\t%0,%1,%2"
9520 
  [(set_attr "may_trap" "no")
9521 
   (set_attr "latency" "0")
9522 
   (set_attr "length" "4")
9523 
   (set_attr "slot" "cop")
9524 
   (set_attr "slots" "c3")
9525 
   (set_attr "stall" "none")])
9526 
 
9527 
 
9528 
(define_insn "cgen_intrinsic_cpsla3_w_P0_P1"
9529 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9530 
        (unspec_volatile:DI [
9531 
          (match_operand:DI 1 "general_operand" "x")
9532 
          (match_operand:DI 2 "general_operand" "x")
9533 
        ] 3460))]
9534 
  "CGEN_ENABLE_INSN_P (273)"
9535 
  "cpsla3.w\\t%0,%1,%2"
9536 
  [(set_attr "may_trap" "no")
9537 
   (set_attr "latency" "0")
9538 
   (set_attr "length" "4")
9539 
   (set_attr "slot" "cop")
9540 
   (set_attr "slots" "p0_p1")
9541 
   (set_attr "stall" "none")])
9542 
 
9543 
 
9544 
(define_insn "cgen_intrinsic_cpsla3_h_C3"
9545 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9546 
        (unspec_volatile:DI [
9547 
          (match_operand:DI 1 "general_operand" "x")
9548 
          (match_operand:DI 2 "general_operand" "x")
9549 
        ] 3462))]
9550 
  "CGEN_ENABLE_INSN_P (274)"
9551 
  "cpsla3.h\\t%0,%1,%2"
9552 
  [(set_attr "may_trap" "no")
9553 
   (set_attr "latency" "0")
9554 
   (set_attr "length" "4")
9555 
   (set_attr "slot" "cop")
9556 
   (set_attr "slots" "c3")
9557 
   (set_attr "stall" "none")])
9558 
 
9559 
 
9560 
(define_insn "cgen_intrinsic_cpsla3_h_P0_P1"
9561 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9562 
        (unspec_volatile:DI [
9563 
          (match_operand:DI 1 "general_operand" "x")
9564 
          (match_operand:DI 2 "general_operand" "x")
9565 
        ] 3462))]
9566 
  "CGEN_ENABLE_INSN_P (275)"
9567 
  "cpsla3.h\\t%0,%1,%2"
9568 
  [(set_attr "may_trap" "no")
9569 
   (set_attr "latency" "0")
9570 
   (set_attr "length" "4")
9571 
   (set_attr "slot" "cop")
9572 
   (set_attr "slots" "p0_p1")
9573 
   (set_attr "stall" "none")])
9574 
 
9575 
 
9576 
(define_insn "cgen_intrinsic_cdsll3_C3"
9577 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9578 
        (unspec:DI [
9579 
          (match_operand:DI 1 "general_operand" "x")
9580 
          (match_operand:DI 2 "general_operand" "x")
9581 
        ] 3464))]
9582 
  "CGEN_ENABLE_INSN_P (276)"
9583 
  "cdsll3\\t%0,%1,%2"
9584 
  [(set_attr "may_trap" "no")
9585 
   (set_attr "latency" "0")
9586 
   (set_attr "length" "4")
9587 
   (set_attr "slot" "cop")
9588 
   (set_attr "slots" "c3")
9589 
   (set_attr "stall" "none")])
9590 
 
9591 
 
9592 
(define_insn "cgen_intrinsic_cdsll3_P0_P1"
9593 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9594 
        (unspec:DI [
9595 
          (match_operand:DI 1 "general_operand" "x")
9596 
          (match_operand:DI 2 "general_operand" "x")
9597 
        ] 3464))]
9598 
  "CGEN_ENABLE_INSN_P (277)"
9599 
  "cdsll3\\t%0,%1,%2"
9600 
  [(set_attr "may_trap" "no")
9601 
   (set_attr "latency" "0")
9602 
   (set_attr "length" "4")
9603 
   (set_attr "slot" "cop")
9604 
   (set_attr "slots" "p0_p1")
9605 
   (set_attr "stall" "none")])
9606 
 
9607 
 
9608 
(define_insn "cgen_intrinsic_cpssll3_w_C3"
9609 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9610 
        (unspec:DI [
9611 
          (match_operand:DI 1 "general_operand" "x")
9612 
          (match_operand:DI 2 "general_operand" "x")
9613 
        ] 3466))]
9614 
  "CGEN_ENABLE_INSN_P (278)"
9615 
  "cpssll3.w\\t%0,%1,%2"
9616 
  [(set_attr "may_trap" "no")
9617 
   (set_attr "latency" "0")
9618 
   (set_attr "length" "4")
9619 
   (set_attr "slot" "cop")
9620 
   (set_attr "slots" "c3")
9621 
   (set_attr "stall" "none")])
9622 
 
9623 
 
9624 
(define_insn "cgen_intrinsic_cpssll3_w_P0_P1"
9625 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9626 
        (unspec:DI [
9627 
          (match_operand:DI 1 "general_operand" "x")
9628 
          (match_operand:DI 2 "general_operand" "x")
9629 
        ] 3466))]
9630 
  "CGEN_ENABLE_INSN_P (279)"
9631 
  "cpssll3.w\\t%0,%1,%2"
9632 
  [(set_attr "may_trap" "no")
9633 
   (set_attr "latency" "0")
9634 
   (set_attr "length" "4")
9635 
   (set_attr "slot" "cop")
9636 
   (set_attr "slots" "p0_p1")
9637 
   (set_attr "stall" "none")])
9638 
 
9639 
 
9640 
(define_insn "cgen_intrinsic_cpsll3_w_C3"
9641 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9642 
        (unspec:DI [
9643 
          (match_operand:DI 1 "general_operand" "x")
9644 
          (match_operand:DI 2 "general_operand" "x")
9645 
        ] 3468))]
9646 
  "CGEN_ENABLE_INSN_P (280)"
9647 
  "cpsll3.w\\t%0,%1,%2"
9648 
  [(set_attr "may_trap" "no")
9649 
   (set_attr "latency" "0")
9650 
   (set_attr "length" "4")
9651 
   (set_attr "slot" "cop")
9652 
   (set_attr "slots" "c3")
9653 
   (set_attr "stall" "none")])
9654 
 
9655 
 
9656 
(define_insn "cgen_intrinsic_cpsll3_w_P0_P1"
9657 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9658 
        (unspec:DI [
9659 
          (match_operand:DI 1 "general_operand" "x")
9660 
          (match_operand:DI 2 "general_operand" "x")
9661 
        ] 3468))]
9662 
  "CGEN_ENABLE_INSN_P (281)"
9663 
  "cpsll3.w\\t%0,%1,%2"
9664 
  [(set_attr "may_trap" "no")
9665 
   (set_attr "latency" "0")
9666 
   (set_attr "length" "4")
9667 
   (set_attr "slot" "cop")
9668 
   (set_attr "slots" "p0_p1")
9669 
   (set_attr "stall" "none")])
9670 
 
9671 
 
9672 
(define_insn "cgen_intrinsic_cpssll3_h_C3"
9673 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9674 
        (unspec:DI [
9675 
          (match_operand:DI 1 "general_operand" "x")
9676 
          (match_operand:DI 2 "general_operand" "x")
9677 
        ] 3470))]
9678 
  "CGEN_ENABLE_INSN_P (282)"
9679 
  "cpssll3.h\\t%0,%1,%2"
9680 
  [(set_attr "may_trap" "no")
9681 
   (set_attr "latency" "0")
9682 
   (set_attr "length" "4")
9683 
   (set_attr "slot" "cop")
9684 
   (set_attr "slots" "c3")
9685 
   (set_attr "stall" "none")])
9686 
 
9687 
 
9688 
(define_insn "cgen_intrinsic_cpssll3_h_P0_P1"
9689 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9690 
        (unspec:DI [
9691 
          (match_operand:DI 1 "general_operand" "x")
9692 
          (match_operand:DI 2 "general_operand" "x")
9693 
        ] 3470))]
9694 
  "CGEN_ENABLE_INSN_P (283)"
9695 
  "cpssll3.h\\t%0,%1,%2"
9696 
  [(set_attr "may_trap" "no")
9697 
   (set_attr "latency" "0")
9698 
   (set_attr "length" "4")
9699 
   (set_attr "slot" "cop")
9700 
   (set_attr "slots" "p0_p1")
9701 
   (set_attr "stall" "none")])
9702 
 
9703 
 
9704 
(define_insn "cgen_intrinsic_cpsll3_h_C3"
9705 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9706 
        (unspec:DI [
9707 
          (match_operand:DI 1 "general_operand" "x")
9708 
          (match_operand:DI 2 "general_operand" "x")
9709 
        ] 3472))]
9710 
  "CGEN_ENABLE_INSN_P (284)"
9711 
  "cpsll3.h\\t%0,%1,%2"
9712 
  [(set_attr "may_trap" "no")
9713 
   (set_attr "latency" "0")
9714 
   (set_attr "length" "4")
9715 
   (set_attr "slot" "cop")
9716 
   (set_attr "slots" "c3")
9717 
   (set_attr "stall" "none")])
9718 
 
9719 
 
9720 
(define_insn "cgen_intrinsic_cpsll3_h_P0_P1"
9721 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9722 
        (unspec:DI [
9723 
          (match_operand:DI 1 "general_operand" "x")
9724 
          (match_operand:DI 2 "general_operand" "x")
9725 
        ] 3472))]
9726 
  "CGEN_ENABLE_INSN_P (285)"
9727 
  "cpsll3.h\\t%0,%1,%2"
9728 
  [(set_attr "may_trap" "no")
9729 
   (set_attr "latency" "0")
9730 
   (set_attr "length" "4")
9731 
   (set_attr "slot" "cop")
9732 
   (set_attr "slots" "p0_p1")
9733 
   (set_attr "stall" "none")])
9734 
 
9735 
 
9736 
(define_insn "cgen_intrinsic_cpssll3_b_C3"
9737 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9738 
        (unspec:DI [
9739 
          (match_operand:DI 1 "general_operand" "x")
9740 
          (match_operand:DI 2 "general_operand" "x")
9741 
        ] 3474))]
9742 
  "CGEN_ENABLE_INSN_P (286)"
9743 
  "cpssll3.b\\t%0,%1,%2"
9744 
  [(set_attr "may_trap" "no")
9745 
   (set_attr "latency" "0")
9746 
   (set_attr "length" "4")
9747 
   (set_attr "slot" "cop")
9748 
   (set_attr "slots" "c3")
9749 
   (set_attr "stall" "none")])
9750 
 
9751 
 
9752 
(define_insn "cgen_intrinsic_cpssll3_b_P0_P1"
9753 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9754 
        (unspec:DI [
9755 
          (match_operand:DI 1 "general_operand" "x")
9756 
          (match_operand:DI 2 "general_operand" "x")
9757 
        ] 3474))]
9758 
  "CGEN_ENABLE_INSN_P (287)"
9759 
  "cpssll3.b\\t%0,%1,%2"
9760 
  [(set_attr "may_trap" "no")
9761 
   (set_attr "latency" "0")
9762 
   (set_attr "length" "4")
9763 
   (set_attr "slot" "cop")
9764 
   (set_attr "slots" "p0_p1")
9765 
   (set_attr "stall" "none")])
9766 
 
9767 
 
9768 
(define_insn "cgen_intrinsic_cpsll3_b_C3"
9769 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9770 
        (unspec:DI [
9771 
          (match_operand:DI 1 "general_operand" "x")
9772 
          (match_operand:DI 2 "general_operand" "x")
9773 
        ] 3476))]
9774 
  "CGEN_ENABLE_INSN_P (288)"
9775 
  "cpsll3.b\\t%0,%1,%2"
9776 
  [(set_attr "may_trap" "no")
9777 
   (set_attr "latency" "0")
9778 
   (set_attr "length" "4")
9779 
   (set_attr "slot" "cop")
9780 
   (set_attr "slots" "c3")
9781 
   (set_attr "stall" "none")])
9782 
 
9783 
 
9784 
(define_insn "cgen_intrinsic_cpsll3_b_P0_P1"
9785 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9786 
        (unspec:DI [
9787 
          (match_operand:DI 1 "general_operand" "x")
9788 
          (match_operand:DI 2 "general_operand" "x")
9789 
        ] 3476))]
9790 
  "CGEN_ENABLE_INSN_P (289)"
9791 
  "cpsll3.b\\t%0,%1,%2"
9792 
  [(set_attr "may_trap" "no")
9793 
   (set_attr "latency" "0")
9794 
   (set_attr "length" "4")
9795 
   (set_attr "slot" "cop")
9796 
   (set_attr "slots" "p0_p1")
9797 
   (set_attr "stall" "none")])
9798 
 
9799 
 
9800 
(define_insn "cgen_intrinsic_cdsra3_C3"
9801 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9802 
        (unspec:DI [
9803 
          (match_operand:DI 1 "general_operand" "x")
9804 
          (match_operand:DI 2 "general_operand" "x")
9805 
        ] 3478))]
9806 
  "CGEN_ENABLE_INSN_P (290)"
9807 
  "cdsra3\\t%0,%1,%2"
9808 
  [(set_attr "may_trap" "no")
9809 
   (set_attr "latency" "0")
9810 
   (set_attr "length" "4")
9811 
   (set_attr "slot" "cop")
9812 
   (set_attr "slots" "c3")
9813 
   (set_attr "stall" "none")])
9814 
 
9815 
 
9816 
(define_insn "cgen_intrinsic_cdsra3_P0_P1"
9817 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9818 
        (unspec:DI [
9819 
          (match_operand:DI 1 "general_operand" "x")
9820 
          (match_operand:DI 2 "general_operand" "x")
9821 
        ] 3478))]
9822 
  "CGEN_ENABLE_INSN_P (291)"
9823 
  "cdsra3\\t%0,%1,%2"
9824 
  [(set_attr "may_trap" "no")
9825 
   (set_attr "latency" "0")
9826 
   (set_attr "length" "4")
9827 
   (set_attr "slot" "cop")
9828 
   (set_attr "slots" "p0_p1")
9829 
   (set_attr "stall" "none")])
9830 
 
9831 
 
9832 
(define_insn "cgen_intrinsic_cpssra3_w_C3"
9833 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9834 
        (unspec:DI [
9835 
          (match_operand:DI 1 "general_operand" "x")
9836 
          (match_operand:DI 2 "general_operand" "x")
9837 
        ] 3480))]
9838 
  "CGEN_ENABLE_INSN_P (292)"
9839 
  "cpssra3.w\\t%0,%1,%2"
9840 
  [(set_attr "may_trap" "no")
9841 
   (set_attr "latency" "0")
9842 
   (set_attr "length" "4")
9843 
   (set_attr "slot" "cop")
9844 
   (set_attr "slots" "c3")
9845 
   (set_attr "stall" "none")])
9846 
 
9847 
 
9848 
(define_insn "cgen_intrinsic_cpssra3_w_P0_P1"
9849 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9850 
        (unspec:DI [
9851 
          (match_operand:DI 1 "general_operand" "x")
9852 
          (match_operand:DI 2 "general_operand" "x")
9853 
        ] 3480))]
9854 
  "CGEN_ENABLE_INSN_P (293)"
9855 
  "cpssra3.w\\t%0,%1,%2"
9856 
  [(set_attr "may_trap" "no")
9857 
   (set_attr "latency" "0")
9858 
   (set_attr "length" "4")
9859 
   (set_attr "slot" "cop")
9860 
   (set_attr "slots" "p0_p1")
9861 
   (set_attr "stall" "none")])
9862 
 
9863 
 
9864 
(define_insn "cgen_intrinsic_cpsra3_w_C3"
9865 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9866 
        (unspec:DI [
9867 
          (match_operand:DI 1 "general_operand" "x")
9868 
          (match_operand:DI 2 "general_operand" "x")
9869 
        ] 3482))]
9870 
  "CGEN_ENABLE_INSN_P (294)"
9871 
  "cpsra3.w\\t%0,%1,%2"
9872 
  [(set_attr "may_trap" "no")
9873 
   (set_attr "latency" "0")
9874 
   (set_attr "length" "4")
9875 
   (set_attr "slot" "cop")
9876 
   (set_attr "slots" "c3")
9877 
   (set_attr "stall" "none")])
9878 
 
9879 
 
9880 
(define_insn "cgen_intrinsic_cpsra3_w_P0_P1"
9881 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9882 
        (unspec:DI [
9883 
          (match_operand:DI 1 "general_operand" "x")
9884 
          (match_operand:DI 2 "general_operand" "x")
9885 
        ] 3482))]
9886 
  "CGEN_ENABLE_INSN_P (295)"
9887 
  "cpsra3.w\\t%0,%1,%2"
9888 
  [(set_attr "may_trap" "no")
9889 
   (set_attr "latency" "0")
9890 
   (set_attr "length" "4")
9891 
   (set_attr "slot" "cop")
9892 
   (set_attr "slots" "p0_p1")
9893 
   (set_attr "stall" "none")])
9894 
 
9895 
 
9896 
(define_insn "cgen_intrinsic_cpssra3_h_C3"
9897 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9898 
        (unspec:DI [
9899 
          (match_operand:DI 1 "general_operand" "x")
9900 
          (match_operand:DI 2 "general_operand" "x")
9901 
        ] 3484))]
9902 
  "CGEN_ENABLE_INSN_P (296)"
9903 
  "cpssra3.h\\t%0,%1,%2"
9904 
  [(set_attr "may_trap" "no")
9905 
   (set_attr "latency" "0")
9906 
   (set_attr "length" "4")
9907 
   (set_attr "slot" "cop")
9908 
   (set_attr "slots" "c3")
9909 
   (set_attr "stall" "none")])
9910 
 
9911 
 
9912 
(define_insn "cgen_intrinsic_cpssra3_h_P0_P1"
9913 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9914 
        (unspec:DI [
9915 
          (match_operand:DI 1 "general_operand" "x")
9916 
          (match_operand:DI 2 "general_operand" "x")
9917 
        ] 3484))]
9918 
  "CGEN_ENABLE_INSN_P (297)"
9919 
  "cpssra3.h\\t%0,%1,%2"
9920 
  [(set_attr "may_trap" "no")
9921 
   (set_attr "latency" "0")
9922 
   (set_attr "length" "4")
9923 
   (set_attr "slot" "cop")
9924 
   (set_attr "slots" "p0_p1")
9925 
   (set_attr "stall" "none")])
9926 
 
9927 
 
9928 
(define_insn "cgen_intrinsic_cpsra3_h_C3"
9929 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9930 
        (unspec:DI [
9931 
          (match_operand:DI 1 "general_operand" "x")
9932 
          (match_operand:DI 2 "general_operand" "x")
9933 
        ] 3486))]
9934 
  "CGEN_ENABLE_INSN_P (298)"
9935 
  "cpsra3.h\\t%0,%1,%2"
9936 
  [(set_attr "may_trap" "no")
9937 
   (set_attr "latency" "0")
9938 
   (set_attr "length" "4")
9939 
   (set_attr "slot" "cop")
9940 
   (set_attr "slots" "c3")
9941 
   (set_attr "stall" "none")])
9942 
 
9943 
 
9944 
(define_insn "cgen_intrinsic_cpsra3_h_P0_P1"
9945 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9946 
        (unspec:DI [
9947 
          (match_operand:DI 1 "general_operand" "x")
9948 
          (match_operand:DI 2 "general_operand" "x")
9949 
        ] 3486))]
9950 
  "CGEN_ENABLE_INSN_P (299)"
9951 
  "cpsra3.h\\t%0,%1,%2"
9952 
  [(set_attr "may_trap" "no")
9953 
   (set_attr "latency" "0")
9954 
   (set_attr "length" "4")
9955 
   (set_attr "slot" "cop")
9956 
   (set_attr "slots" "p0_p1")
9957 
   (set_attr "stall" "none")])
9958 
 
9959 
 
9960 
(define_insn "cgen_intrinsic_cpssra3_b_C3"
9961 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9962 
        (unspec:DI [
9963 
          (match_operand:DI 1 "general_operand" "x")
9964 
          (match_operand:DI 2 "general_operand" "x")
9965 
        ] 3488))]
9966 
  "CGEN_ENABLE_INSN_P (300)"
9967 
  "cpssra3.b\\t%0,%1,%2"
9968 
  [(set_attr "may_trap" "no")
9969 
   (set_attr "latency" "0")
9970 
   (set_attr "length" "4")
9971 
   (set_attr "slot" "cop")
9972 
   (set_attr "slots" "c3")
9973 
   (set_attr "stall" "none")])
9974 
 
9975 
 
9976 
(define_insn "cgen_intrinsic_cpssra3_b_P0_P1"
9977 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9978 
        (unspec:DI [
9979 
          (match_operand:DI 1 "general_operand" "x")
9980 
          (match_operand:DI 2 "general_operand" "x")
9981 
        ] 3488))]
9982 
  "CGEN_ENABLE_INSN_P (301)"
9983 
  "cpssra3.b\\t%0,%1,%2"
9984 
  [(set_attr "may_trap" "no")
9985 
   (set_attr "latency" "0")
9986 
   (set_attr "length" "4")
9987 
   (set_attr "slot" "cop")
9988 
   (set_attr "slots" "p0_p1")
9989 
   (set_attr "stall" "none")])
9990 
 
9991 
 
9992 
(define_insn "cgen_intrinsic_cpsra3_b_C3"
9993 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9994 
        (unspec:DI [
9995 
          (match_operand:DI 1 "general_operand" "x")
9996 
          (match_operand:DI 2 "general_operand" "x")
9997 
        ] 3490))]
9998 
  "CGEN_ENABLE_INSN_P (302)"
9999 
  "cpsra3.b\\t%0,%1,%2"
10000 
  [(set_attr "may_trap" "no")
10001 
   (set_attr "latency" "0")
10002 
   (set_attr "length" "4")
10003 
   (set_attr "slot" "cop")
10004 
   (set_attr "slots" "c3")
10005 
   (set_attr "stall" "none")])
10006 
 
10007 
 
10008 
(define_insn "cgen_intrinsic_cpsra3_b_P0_P1"
10009 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10010 
        (unspec:DI [
10011 
          (match_operand:DI 1 "general_operand" "x")
10012 
          (match_operand:DI 2 "general_operand" "x")
10013 
        ] 3490))]
10014 
  "CGEN_ENABLE_INSN_P (303)"
10015 
  "cpsra3.b\\t%0,%1,%2"
10016 
  [(set_attr "may_trap" "no")
10017 
   (set_attr "latency" "0")
10018 
   (set_attr "length" "4")
10019 
   (set_attr "slot" "cop")
10020 
   (set_attr "slots" "p0_p1")
10021 
   (set_attr "stall" "none")])
10022 
 
10023 
 
10024 
(define_insn "cgen_intrinsic_cdsrl3_C3"
10025 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10026 
        (unspec:DI [
10027 
          (match_operand:DI 1 "general_operand" "x")
10028 
          (match_operand:DI 2 "general_operand" "x")
10029 
        ] 3492))]
10030 
  "CGEN_ENABLE_INSN_P (304)"
10031 
  "cdsrl3\\t%0,%1,%2"
10032 
  [(set_attr "may_trap" "no")
10033 
   (set_attr "latency" "0")
10034 
   (set_attr "length" "4")
10035 
   (set_attr "slot" "cop")
10036 
   (set_attr "slots" "c3")
10037 
   (set_attr "stall" "none")])
10038 
 
10039 
 
10040 
(define_insn "cgen_intrinsic_cdsrl3_P0_P1"
10041 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10042 
        (unspec:DI [
10043 
          (match_operand:DI 1 "general_operand" "x")
10044 
          (match_operand:DI 2 "general_operand" "x")
10045 
        ] 3492))]
10046 
  "CGEN_ENABLE_INSN_P (305)"
10047 
  "cdsrl3\\t%0,%1,%2"
10048 
  [(set_attr "may_trap" "no")
10049 
   (set_attr "latency" "0")
10050 
   (set_attr "length" "4")
10051 
   (set_attr "slot" "cop")
10052 
   (set_attr "slots" "p0_p1")
10053 
   (set_attr "stall" "none")])
10054 
 
10055 
 
10056 
(define_insn "cgen_intrinsic_cpssrl3_w_C3"
10057 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10058 
        (unspec:DI [
10059 
          (match_operand:DI 1 "general_operand" "x")
10060 
          (match_operand:DI 2 "general_operand" "x")
10061 
        ] 3494))]
10062 
  "CGEN_ENABLE_INSN_P (306)"
10063 
  "cpssrl3.w\\t%0,%1,%2"
10064 
  [(set_attr "may_trap" "no")
10065 
   (set_attr "latency" "0")
10066 
   (set_attr "length" "4")
10067 
   (set_attr "slot" "cop")
10068 
   (set_attr "slots" "c3")
10069 
   (set_attr "stall" "none")])
10070 
 
10071 
 
10072 
(define_insn "cgen_intrinsic_cpssrl3_w_P0_P1"
10073 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10074 
        (unspec:DI [
10075 
          (match_operand:DI 1 "general_operand" "x")
10076 
          (match_operand:DI 2 "general_operand" "x")
10077 
        ] 3494))]
10078 
  "CGEN_ENABLE_INSN_P (307)"
10079 
  "cpssrl3.w\\t%0,%1,%2"
10080 
  [(set_attr "may_trap" "no")
10081 
   (set_attr "latency" "0")
10082 
   (set_attr "length" "4")
10083 
   (set_attr "slot" "cop")
10084 
   (set_attr "slots" "p0_p1")
10085 
   (set_attr "stall" "none")])
10086 
 
10087 
 
10088 
(define_insn "cgen_intrinsic_cpsrl3_w_C3"
10089 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10090 
        (unspec:DI [
10091 
          (match_operand:DI 1 "general_operand" "x")
10092 
          (match_operand:DI 2 "general_operand" "x")
10093 
        ] 3496))]
10094 
  "CGEN_ENABLE_INSN_P (308)"
10095 
  "cpsrl3.w\\t%0,%1,%2"
10096 
  [(set_attr "may_trap" "no")
10097 
   (set_attr "latency" "0")
10098 
   (set_attr "length" "4")
10099 
   (set_attr "slot" "cop")
10100 
   (set_attr "slots" "c3")
10101 
   (set_attr "stall" "none")])
10102 
 
10103 
 
10104 
(define_insn "cgen_intrinsic_cpsrl3_w_P0_P1"
10105 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10106 
        (unspec:DI [
10107 
          (match_operand:DI 1 "general_operand" "x")
10108 
          (match_operand:DI 2 "general_operand" "x")
10109 
        ] 3496))]
10110 
  "CGEN_ENABLE_INSN_P (309)"
10111 
  "cpsrl3.w\\t%0,%1,%2"
10112 
  [(set_attr "may_trap" "no")
10113 
   (set_attr "latency" "0")
10114 
   (set_attr "length" "4")
10115 
   (set_attr "slot" "cop")
10116 
   (set_attr "slots" "p0_p1")
10117 
   (set_attr "stall" "none")])
10118 
 
10119 
 
10120 
(define_insn "cgen_intrinsic_cpssrl3_h_C3"
10121 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10122 
        (unspec:DI [
10123 
          (match_operand:DI 1 "general_operand" "x")
10124 
          (match_operand:DI 2 "general_operand" "x")
10125 
        ] 3498))]
10126 
  "CGEN_ENABLE_INSN_P (310)"
10127 
  "cpssrl3.h\\t%0,%1,%2"
10128 
  [(set_attr "may_trap" "no")
10129 
   (set_attr "latency" "0")
10130 
   (set_attr "length" "4")
10131 
   (set_attr "slot" "cop")
10132 
   (set_attr "slots" "c3")
10133 
   (set_attr "stall" "none")])
10134 
 
10135 
 
10136 
(define_insn "cgen_intrinsic_cpssrl3_h_P0_P1"
10137 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10138 
        (unspec:DI [
10139 
          (match_operand:DI 1 "general_operand" "x")
10140 
          (match_operand:DI 2 "general_operand" "x")
10141 
        ] 3498))]
10142 
  "CGEN_ENABLE_INSN_P (311)"
10143 
  "cpssrl3.h\\t%0,%1,%2"
10144 
  [(set_attr "may_trap" "no")
10145 
   (set_attr "latency" "0")
10146 
   (set_attr "length" "4")
10147 
   (set_attr "slot" "cop")
10148 
   (set_attr "slots" "p0_p1")
10149 
   (set_attr "stall" "none")])
10150 
 
10151 
 
10152 
(define_insn "cgen_intrinsic_cpsrl3_h_C3"
10153 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10154 
        (unspec:DI [
10155 
          (match_operand:DI 1 "general_operand" "x")
10156 
          (match_operand:DI 2 "general_operand" "x")
10157 
        ] 3500))]
10158 
  "CGEN_ENABLE_INSN_P (312)"
10159 
  "cpsrl3.h\\t%0,%1,%2"
10160 
  [(set_attr "may_trap" "no")
10161 
   (set_attr "latency" "0")
10162 
   (set_attr "length" "4")
10163 
   (set_attr "slot" "cop")
10164 
   (set_attr "slots" "c3")
10165 
   (set_attr "stall" "none")])
10166 
 
10167 
 
10168 
(define_insn "cgen_intrinsic_cpsrl3_h_P0_P1"
10169 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10170 
        (unspec:DI [
10171 
          (match_operand:DI 1 "general_operand" "x")
10172 
          (match_operand:DI 2 "general_operand" "x")
10173 
        ] 3500))]
10174 
  "CGEN_ENABLE_INSN_P (313)"
10175 
  "cpsrl3.h\\t%0,%1,%2"
10176 
  [(set_attr "may_trap" "no")
10177 
   (set_attr "latency" "0")
10178 
   (set_attr "length" "4")
10179 
   (set_attr "slot" "cop")
10180 
   (set_attr "slots" "p0_p1")
10181 
   (set_attr "stall" "none")])
10182 
 
10183 
 
10184 
(define_insn "cgen_intrinsic_cpssrl3_b_C3"
10185 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10186 
        (unspec:DI [
10187 
          (match_operand:DI 1 "general_operand" "x")
10188 
          (match_operand:DI 2 "general_operand" "x")
10189 
        ] 3502))]
10190 
  "CGEN_ENABLE_INSN_P (314)"
10191 
  "cpssrl3.b\\t%0,%1,%2"
10192 
  [(set_attr "may_trap" "no")
10193 
   (set_attr "latency" "0")
10194 
   (set_attr "length" "4")
10195 
   (set_attr "slot" "cop")
10196 
   (set_attr "slots" "c3")
10197 
   (set_attr "stall" "none")])
10198 
 
10199 
 
10200 
(define_insn "cgen_intrinsic_cpssrl3_b_P0_P1"
10201 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10202 
        (unspec:DI [
10203 
          (match_operand:DI 1 "general_operand" "x")
10204 
          (match_operand:DI 2 "general_operand" "x")
10205 
        ] 3502))]
10206 
  "CGEN_ENABLE_INSN_P (315)"
10207 
  "cpssrl3.b\\t%0,%1,%2"
10208 
  [(set_attr "may_trap" "no")
10209 
   (set_attr "latency" "0")
10210 
   (set_attr "length" "4")
10211 
   (set_attr "slot" "cop")
10212 
   (set_attr "slots" "p0_p1")
10213 
   (set_attr "stall" "none")])
10214 
 
10215 
 
10216 
(define_insn "cgen_intrinsic_cpsrl3_b_C3"
10217 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10218 
        (unspec:DI [
10219 
          (match_operand:DI 1 "general_operand" "x")
10220 
          (match_operand:DI 2 "general_operand" "x")
10221 
        ] 3504))]
10222 
  "CGEN_ENABLE_INSN_P (316)"
10223 
  "cpsrl3.b\\t%0,%1,%2"
10224 
  [(set_attr "may_trap" "no")
10225 
   (set_attr "latency" "0")
10226 
   (set_attr "length" "4")
10227 
   (set_attr "slot" "cop")
10228 
   (set_attr "slots" "c3")
10229 
   (set_attr "stall" "none")])
10230 
 
10231 
 
10232 
(define_insn "cgen_intrinsic_cpsrl3_b_P0_P1"
10233 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10234 
        (unspec:DI [
10235 
          (match_operand:DI 1 "general_operand" "x")
10236 
          (match_operand:DI 2 "general_operand" "x")
10237 
        ] 3504))]
10238 
  "CGEN_ENABLE_INSN_P (317)"
10239 
  "cpsrl3.b\\t%0,%1,%2"
10240 
  [(set_attr "may_trap" "no")
10241 
   (set_attr "latency" "0")
10242 
   (set_attr "length" "4")
10243 
   (set_attr "slot" "cop")
10244 
   (set_attr "slots" "p0_p1")
10245 
   (set_attr "stall" "none")])
10246 
 
10247 
 
10248 
(define_insn "cgen_intrinsic_cpmin3_w_C3"
10249 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10250 
        (unspec:DI [
10251 
          (match_operand:DI 1 "general_operand" "x")
10252 
          (match_operand:DI 2 "general_operand" "x")
10253 
        ] 3390))]
10254 
  "CGEN_ENABLE_INSN_P (318)"
10255 
  "cpmin3.w\\t%0,%1,%2"
10256 
  [(set_attr "may_trap" "no")
10257 
   (set_attr "latency" "0")
10258 
   (set_attr "length" "4")
10259 
   (set_attr "slot" "cop")
10260 
   (set_attr "slots" "c3")
10261 
   (set_attr "stall" "none")])
10262 
 
10263 
 
10264 
(define_insn "cgen_intrinsic_cpmin3_w_P0_P1"
10265 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10266 
        (unspec:DI [
10267 
          (match_operand:DI 1 "general_operand" "x")
10268 
          (match_operand:DI 2 "general_operand" "x")
10269 
        ] 3390))]
10270 
  "CGEN_ENABLE_INSN_P (319)"
10271 
  "cpmin3.w\\t%0,%1,%2"
10272 
  [(set_attr "may_trap" "no")
10273 
   (set_attr "latency" "0")
10274 
   (set_attr "length" "4")
10275 
   (set_attr "slot" "cop")
10276 
   (set_attr "slots" "p0_p1")
10277 
   (set_attr "stall" "none")])
10278 
 
10279 
 
10280 
(define_insn "cgen_intrinsic_cpminu3_w_C3"
10281 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10282 
        (unspec:DI [
10283 
          (match_operand:DI 1 "general_operand" "x")
10284 
          (match_operand:DI 2 "general_operand" "x")
10285 
        ] 3392))]
10286 
  "CGEN_ENABLE_INSN_P (320)"
10287 
  "cpminu3.w\\t%0,%1,%2"
10288 
  [(set_attr "may_trap" "no")
10289 
   (set_attr "latency" "0")
10290 
   (set_attr "length" "4")
10291 
   (set_attr "slot" "cop")
10292 
   (set_attr "slots" "c3")
10293 
   (set_attr "stall" "none")])
10294 
 
10295 
 
10296 
(define_insn "cgen_intrinsic_cpminu3_w_P0_P1"
10297 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10298 
        (unspec:DI [
10299 
          (match_operand:DI 1 "general_operand" "x")
10300 
          (match_operand:DI 2 "general_operand" "x")
10301 
        ] 3392))]
10302 
  "CGEN_ENABLE_INSN_P (321)"
10303 
  "cpminu3.w\\t%0,%1,%2"
10304 
  [(set_attr "may_trap" "no")
10305 
   (set_attr "latency" "0")
10306 
   (set_attr "length" "4")
10307 
   (set_attr "slot" "cop")
10308 
   (set_attr "slots" "p0_p1")
10309 
   (set_attr "stall" "none")])
10310 
 
10311 
 
10312 
(define_insn "cgen_intrinsic_cpmin3_h_C3"
10313 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10314 
        (unspec:DI [
10315 
          (match_operand:DI 1 "general_operand" "x")
10316 
          (match_operand:DI 2 "general_operand" "x")
10317 
        ] 3394))]
10318 
  "CGEN_ENABLE_INSN_P (322)"
10319 
  "cpmin3.h\\t%0,%1,%2"
10320 
  [(set_attr "may_trap" "no")
10321 
   (set_attr "latency" "0")
10322 
   (set_attr "length" "4")
10323 
   (set_attr "slot" "cop")
10324 
   (set_attr "slots" "c3")
10325 
   (set_attr "stall" "none")])
10326 
 
10327 
 
10328 
(define_insn "cgen_intrinsic_cpmin3_h_P0_P1"
10329 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10330 
        (unspec:DI [
10331 
          (match_operand:DI 1 "general_operand" "x")
10332 
          (match_operand:DI 2 "general_operand" "x")
10333 
        ] 3394))]
10334 
  "CGEN_ENABLE_INSN_P (323)"
10335 
  "cpmin3.h\\t%0,%1,%2"
10336 
  [(set_attr "may_trap" "no")
10337 
   (set_attr "latency" "0")
10338 
   (set_attr "length" "4")
10339 
   (set_attr "slot" "cop")
10340 
   (set_attr "slots" "p0_p1")
10341 
   (set_attr "stall" "none")])
10342 
 
10343 
 
10344 
(define_insn "cgen_intrinsic_cpmin3_b_C3"
10345 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10346 
        (unspec:DI [
10347 
          (match_operand:DI 1 "general_operand" "x")
10348 
          (match_operand:DI 2 "general_operand" "x")
10349 
        ] 3396))]
10350 
  "CGEN_ENABLE_INSN_P (324)"
10351 
  "cpmin3.b\\t%0,%1,%2"
10352 
  [(set_attr "may_trap" "no")
10353 
   (set_attr "latency" "0")
10354 
   (set_attr "length" "4")
10355 
   (set_attr "slot" "cop")
10356 
   (set_attr "slots" "c3")
10357 
   (set_attr "stall" "none")])
10358 
 
10359 
 
10360 
(define_insn "cgen_intrinsic_cpmin3_b_P0_P1"
10361 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10362 
        (unspec:DI [
10363 
          (match_operand:DI 1 "general_operand" "x")
10364 
          (match_operand:DI 2 "general_operand" "x")
10365 
        ] 3396))]
10366 
  "CGEN_ENABLE_INSN_P (325)"
10367 
  "cpmin3.b\\t%0,%1,%2"
10368 
  [(set_attr "may_trap" "no")
10369 
   (set_attr "latency" "0")
10370 
   (set_attr "length" "4")
10371 
   (set_attr "slot" "cop")
10372 
   (set_attr "slots" "p0_p1")
10373 
   (set_attr "stall" "none")])
10374 
 
10375 
 
10376 
(define_insn "cgen_intrinsic_cpminu3_b_C3"
10377 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10378 
        (unspec:DI [
10379 
          (match_operand:DI 1 "general_operand" "x")
10380 
          (match_operand:DI 2 "general_operand" "x")
10381 
        ] 3398))]
10382 
  "CGEN_ENABLE_INSN_P (326)"
10383 
  "cpminu3.b\\t%0,%1,%2"
10384 
  [(set_attr "may_trap" "no")
10385 
   (set_attr "latency" "0")
10386 
   (set_attr "length" "4")
10387 
   (set_attr "slot" "cop")
10388 
   (set_attr "slots" "c3")
10389 
   (set_attr "stall" "none")])
10390 
 
10391 
 
10392 
(define_insn "cgen_intrinsic_cpminu3_b_P0_P1"
10393 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10394 
        (unspec:DI [
10395 
          (match_operand:DI 1 "general_operand" "x")
10396 
          (match_operand:DI 2 "general_operand" "x")
10397 
        ] 3398))]
10398 
  "CGEN_ENABLE_INSN_P (327)"
10399 
  "cpminu3.b\\t%0,%1,%2"
10400 
  [(set_attr "may_trap" "no")
10401 
   (set_attr "latency" "0")
10402 
   (set_attr "length" "4")
10403 
   (set_attr "slot" "cop")
10404 
   (set_attr "slots" "p0_p1")
10405 
   (set_attr "stall" "none")])
10406 
 
10407 
 
10408 
(define_insn "cgen_intrinsic_cpmax3_w_C3"
10409 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10410 
        (unspec:DI [
10411 
          (match_operand:DI 1 "general_operand" "x")
10412 
          (match_operand:DI 2 "general_operand" "x")
10413 
        ] 3400))]
10414 
  "CGEN_ENABLE_INSN_P (328)"
10415 
  "cpmax3.w\\t%0,%1,%2"
10416 
  [(set_attr "may_trap" "no")
10417 
   (set_attr "latency" "0")
10418 
   (set_attr "length" "4")
10419 
   (set_attr "slot" "cop")
10420 
   (set_attr "slots" "c3")
10421 
   (set_attr "stall" "none")])
10422 
 
10423 
 
10424 
(define_insn "cgen_intrinsic_cpmax3_w_P0_P1"
10425 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10426 
        (unspec:DI [
10427 
          (match_operand:DI 1 "general_operand" "x")
10428 
          (match_operand:DI 2 "general_operand" "x")
10429 
        ] 3400))]
10430 
  "CGEN_ENABLE_INSN_P (329)"
10431 
  "cpmax3.w\\t%0,%1,%2"
10432 
  [(set_attr "may_trap" "no")
10433 
   (set_attr "latency" "0")
10434 
   (set_attr "length" "4")
10435 
   (set_attr "slot" "cop")
10436 
   (set_attr "slots" "p0_p1")
10437 
   (set_attr "stall" "none")])
10438 
 
10439 
 
10440 
(define_insn "cgen_intrinsic_cpmaxu3_w_C3"
10441 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10442 
        (unspec:DI [
10443 
          (match_operand:DI 1 "general_operand" "x")
10444 
          (match_operand:DI 2 "general_operand" "x")
10445 
        ] 3402))]
10446 
  "CGEN_ENABLE_INSN_P (330)"
10447 
  "cpmaxu3.w\\t%0,%1,%2"
10448 
  [(set_attr "may_trap" "no")
10449 
   (set_attr "latency" "0")
10450 
   (set_attr "length" "4")
10451 
   (set_attr "slot" "cop")
10452 
   (set_attr "slots" "c3")
10453 
   (set_attr "stall" "none")])
10454 
 
10455 
 
10456 
(define_insn "cgen_intrinsic_cpmaxu3_w_P0_P1"
10457 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10458 
        (unspec:DI [
10459 
          (match_operand:DI 1 "general_operand" "x")
10460 
          (match_operand:DI 2 "general_operand" "x")
10461 
        ] 3402))]
10462 
  "CGEN_ENABLE_INSN_P (331)"
10463 
  "cpmaxu3.w\\t%0,%1,%2"
10464 
  [(set_attr "may_trap" "no")
10465 
   (set_attr "latency" "0")
10466 
   (set_attr "length" "4")
10467 
   (set_attr "slot" "cop")
10468 
   (set_attr "slots" "p0_p1")
10469 
   (set_attr "stall" "none")])
10470 
 
10471 
 
10472 
(define_insn "cgen_intrinsic_cpmax3_h_C3"
10473 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10474 
        (unspec:DI [
10475 
          (match_operand:DI 1 "general_operand" "x")
10476 
          (match_operand:DI 2 "general_operand" "x")
10477 
        ] 3404))]
10478 
  "CGEN_ENABLE_INSN_P (332)"
10479 
  "cpmax3.h\\t%0,%1,%2"
10480 
  [(set_attr "may_trap" "no")
10481 
   (set_attr "latency" "0")
10482 
   (set_attr "length" "4")
10483 
   (set_attr "slot" "cop")
10484 
   (set_attr "slots" "c3")
10485 
   (set_attr "stall" "none")])
10486 
 
10487 
 
10488 
(define_insn "cgen_intrinsic_cpmax3_h_P0_P1"
10489 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10490 
        (unspec:DI [
10491 
          (match_operand:DI 1 "general_operand" "x")
10492 
          (match_operand:DI 2 "general_operand" "x")
10493 
        ] 3404))]
10494 
  "CGEN_ENABLE_INSN_P (333)"
10495 
  "cpmax3.h\\t%0,%1,%2"
10496 
  [(set_attr "may_trap" "no")
10497 
   (set_attr "latency" "0")
10498 
   (set_attr "length" "4")
10499 
   (set_attr "slot" "cop")
10500 
   (set_attr "slots" "p0_p1")
10501 
   (set_attr "stall" "none")])
10502 
 
10503 
 
10504 
(define_insn "cgen_intrinsic_cpmax3_b_C3"
10505 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10506 
        (unspec:DI [
10507 
          (match_operand:DI 1 "general_operand" "x")
10508 
          (match_operand:DI 2 "general_operand" "x")
10509 
        ] 3406))]
10510 
  "CGEN_ENABLE_INSN_P (334)"
10511 
  "cpmax3.b\\t%0,%1,%2"
10512 
  [(set_attr "may_trap" "no")
10513 
   (set_attr "latency" "0")
10514 
   (set_attr "length" "4")
10515 
   (set_attr "slot" "cop")
10516 
   (set_attr "slots" "c3")
10517 
   (set_attr "stall" "none")])
10518 
 
10519 
 
10520 
(define_insn "cgen_intrinsic_cpmax3_b_P0_P1"
10521 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10522 
        (unspec:DI [
10523 
          (match_operand:DI 1 "general_operand" "x")
10524 
          (match_operand:DI 2 "general_operand" "x")
10525 
        ] 3406))]
10526 
  "CGEN_ENABLE_INSN_P (335)"
10527 
  "cpmax3.b\\t%0,%1,%2"
10528 
  [(set_attr "may_trap" "no")
10529 
   (set_attr "latency" "0")
10530 
   (set_attr "length" "4")
10531 
   (set_attr "slot" "cop")
10532 
   (set_attr "slots" "p0_p1")
10533 
   (set_attr "stall" "none")])
10534 
 
10535 
 
10536 
(define_insn "cgen_intrinsic_cpmaxu3_b_C3"
10537 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10538 
        (unspec:DI [
10539 
          (match_operand:DI 1 "general_operand" "x")
10540 
          (match_operand:DI 2 "general_operand" "x")
10541 
        ] 3408))]
10542 
  "CGEN_ENABLE_INSN_P (336)"
10543 
  "cpmaxu3.b\\t%0,%1,%2"
10544 
  [(set_attr "may_trap" "no")
10545 
   (set_attr "latency" "0")
10546 
   (set_attr "length" "4")
10547 
   (set_attr "slot" "cop")
10548 
   (set_attr "slots" "c3")
10549 
   (set_attr "stall" "none")])
10550 
 
10551 
 
10552 
(define_insn "cgen_intrinsic_cpmaxu3_b_P0_P1"
10553 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10554 
        (unspec:DI [
10555 
          (match_operand:DI 1 "general_operand" "x")
10556 
          (match_operand:DI 2 "general_operand" "x")
10557 
        ] 3408))]
10558 
  "CGEN_ENABLE_INSN_P (337)"
10559 
  "cpmaxu3.b\\t%0,%1,%2"
10560 
  [(set_attr "may_trap" "no")
10561 
   (set_attr "latency" "0")
10562 
   (set_attr "length" "4")
10563 
   (set_attr "slot" "cop")
10564 
   (set_attr "slots" "p0_p1")
10565 
   (set_attr "stall" "none")])
10566 
 
10567 
 
10568 
(define_insn "cgen_intrinsic_cppack_h_C3"
10569 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10570 
        (unspec:DI [
10571 
          (match_operand:DI 1 "general_operand" "x")
10572 
          (match_operand:DI 2 "general_operand" "x")
10573 
        ] 3506))]
10574 
  "CGEN_ENABLE_INSN_P (338)"
10575 
  "cppack.h\\t%0,%1,%2"
10576 
  [(set_attr "may_trap" "no")
10577 
   (set_attr "latency" "0")
10578 
   (set_attr "length" "4")
10579 
   (set_attr "slot" "cop")
10580 
   (set_attr "slots" "c3")
10581 
   (set_attr "stall" "none")])
10582 
 
10583 
 
10584 
(define_insn "cgen_intrinsic_cppack_h_P0_P1"
10585 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10586 
        (unspec:DI [
10587 
          (match_operand:DI 1 "general_operand" "x")
10588 
          (match_operand:DI 2 "general_operand" "x")
10589 
        ] 3506))]
10590 
  "CGEN_ENABLE_INSN_P (339)"
10591 
  "cppack.h\\t%0,%1,%2"
10592 
  [(set_attr "may_trap" "no")
10593 
   (set_attr "latency" "0")
10594 
   (set_attr "length" "4")
10595 
   (set_attr "slot" "cop")
10596 
   (set_attr "slots" "p0_p1")
10597 
   (set_attr "stall" "none")])
10598 
 
10599 
 
10600 
(define_insn "cgen_intrinsic_cppack_b_C3"
10601 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10602 
        (unspec:DI [
10603 
          (match_operand:DI 1 "general_operand" "x")
10604 
          (match_operand:DI 2 "general_operand" "x")
10605 
        ] 3508))]
10606 
  "CGEN_ENABLE_INSN_P (340)"
10607 
  "cppack.b\\t%0,%1,%2"
10608 
  [(set_attr "may_trap" "no")
10609 
   (set_attr "latency" "0")
10610 
   (set_attr "length" "4")
10611 
   (set_attr "slot" "cop")
10612 
   (set_attr "slots" "c3")
10613 
   (set_attr "stall" "none")])
10614 
 
10615 
 
10616 
(define_insn "cgen_intrinsic_cppack_b_P0_P1"
10617 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10618 
        (unspec:DI [
10619 
          (match_operand:DI 1 "general_operand" "x")
10620 
          (match_operand:DI 2 "general_operand" "x")
10621 
        ] 3508))]
10622 
  "CGEN_ENABLE_INSN_P (341)"
10623 
  "cppack.b\\t%0,%1,%2"
10624 
  [(set_attr "may_trap" "no")
10625 
   (set_attr "latency" "0")
10626 
   (set_attr "length" "4")
10627 
   (set_attr "slot" "cop")
10628 
   (set_attr "slots" "p0_p1")
10629 
   (set_attr "stall" "none")])
10630 
 
10631 
 
10632 
(define_insn "cgen_intrinsic_cppacku_b_C3"
10633 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10634 
        (unspec:DI [
10635 
          (match_operand:DI 1 "general_operand" "x")
10636 
          (match_operand:DI 2 "general_operand" "x")
10637 
        ] 3510))]
10638 
  "CGEN_ENABLE_INSN_P (342)"
10639 
  "cppacku.b\\t%0,%1,%2"
10640 
  [(set_attr "may_trap" "no")
10641 
   (set_attr "latency" "0")
10642 
   (set_attr "length" "4")
10643 
   (set_attr "slot" "cop")
10644 
   (set_attr "slots" "c3")
10645 
   (set_attr "stall" "none")])
10646 
 
10647 
 
10648 
(define_insn "cgen_intrinsic_cppacku_b_P0_P1"
10649 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10650 
        (unspec:DI [
10651 
          (match_operand:DI 1 "general_operand" "x")
10652 
          (match_operand:DI 2 "general_operand" "x")
10653 
        ] 3510))]
10654 
  "CGEN_ENABLE_INSN_P (343)"
10655 
  "cppacku.b\\t%0,%1,%2"
10656 
  [(set_attr "may_trap" "no")
10657 
   (set_attr "latency" "0")
10658 
   (set_attr "length" "4")
10659 
   (set_attr "slot" "cop")
10660 
   (set_attr "slots" "p0_p1")
10661 
   (set_attr "stall" "none")])
10662 
 
10663 
 
10664 
(define_insn "cgen_intrinsic_cpxor3_C3"
10665 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10666 
        (unspec:DI [
10667 
          (match_operand:DI 1 "general_operand" "x")
10668 
          (match_operand:DI 2 "general_operand" "x")
10669 
        ] 3532))]
10670 
  "CGEN_ENABLE_INSN_P (344)"
10671 
  "cpxor3\\t%0,%1,%2"
10672 
  [(set_attr "may_trap" "no")
10673 
   (set_attr "latency" "0")
10674 
   (set_attr "length" "4")
10675 
   (set_attr "slot" "cop")
10676 
   (set_attr "slots" "c3")
10677 
   (set_attr "stall" "none")])
10678 
 
10679 
 
10680 
(define_insn "cgen_intrinsic_cpxor3_P0_P1"
10681 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10682 
        (unspec:DI [
10683 
          (match_operand:DI 1 "general_operand" "x")
10684 
          (match_operand:DI 2 "general_operand" "x")
10685 
        ] 3532))]
10686 
  "CGEN_ENABLE_INSN_P (345)"
10687 
  "cpxor3\\t%0,%1,%2"
10688 
  [(set_attr "may_trap" "no")
10689 
   (set_attr "latency" "0")
10690 
   (set_attr "length" "4")
10691 
   (set_attr "slot" "cop")
10692 
   (set_attr "slots" "p0_p1")
10693 
   (set_attr "stall" "none")])
10694 
 
10695 
 
10696 
(define_insn "cgen_intrinsic_cpnor3_C3"
10697 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10698 
        (unspec:DI [
10699 
          (match_operand:DI 1 "general_operand" "x")
10700 
          (match_operand:DI 2 "general_operand" "x")
10701 
        ] 3534))]
10702 
  "CGEN_ENABLE_INSN_P (346)"
10703 
  "cpnor3\\t%0,%1,%2"
10704 
  [(set_attr "may_trap" "no")
10705 
   (set_attr "latency" "0")
10706 
   (set_attr "length" "4")
10707 
   (set_attr "slot" "cop")
10708 
   (set_attr "slots" "c3")
10709 
   (set_attr "stall" "none")])
10710 
 
10711 
 
10712 
(define_insn "cgen_intrinsic_cpnor3_P0_P1"
10713 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10714 
        (unspec:DI [
10715 
          (match_operand:DI 1 "general_operand" "x")
10716 
          (match_operand:DI 2 "general_operand" "x")
10717 
        ] 3534))]
10718 
  "CGEN_ENABLE_INSN_P (347)"
10719 
  "cpnor3\\t%0,%1,%2"
10720 
  [(set_attr "may_trap" "no")
10721 
   (set_attr "latency" "0")
10722 
   (set_attr "length" "4")
10723 
   (set_attr "slot" "cop")
10724 
   (set_attr "slots" "p0_p1")
10725 
   (set_attr "stall" "none")])
10726 
 
10727 
 
10728 
(define_insn "cgen_intrinsic_cpor3_C3"
10729 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10730 
        (unspec:DI [
10731 
          (match_operand:DI 1 "general_operand" "x")
10732 
          (match_operand:DI 2 "general_operand" "x")
10733 
        ] 3536))]
10734 
  "CGEN_ENABLE_INSN_P (348)"
10735 
  "cpor3\\t%0,%1,%2"
10736 
  [(set_attr "may_trap" "no")
10737 
   (set_attr "latency" "0")
10738 
   (set_attr "length" "4")
10739 
   (set_attr "slot" "cop")
10740 
   (set_attr "slots" "c3")
10741 
   (set_attr "stall" "none")])
10742 
 
10743 
 
10744 
(define_insn "cgen_intrinsic_cpor3_P0_P1"
10745 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10746 
        (unspec:DI [
10747 
          (match_operand:DI 1 "general_operand" "x")
10748 
          (match_operand:DI 2 "general_operand" "x")
10749 
        ] 3536))]
10750 
  "CGEN_ENABLE_INSN_P (349)"
10751 
  "cpor3\\t%0,%1,%2"
10752 
  [(set_attr "may_trap" "no")
10753 
   (set_attr "latency" "0")
10754 
   (set_attr "length" "4")
10755 
   (set_attr "slot" "cop")
10756 
   (set_attr "slots" "p0_p1")
10757 
   (set_attr "stall" "none")])
10758 
 
10759 
 
10760 
(define_insn "cgen_intrinsic_cpand3_C3"
10761 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10762 
        (unspec:DI [
10763 
          (match_operand:DI 1 "general_operand" "x")
10764 
          (match_operand:DI 2 "general_operand" "x")
10765 
        ] 3538))]
10766 
  "CGEN_ENABLE_INSN_P (350)"
10767 
  "cpand3\\t%0,%1,%2"
10768 
  [(set_attr "may_trap" "no")
10769 
   (set_attr "latency" "0")
10770 
   (set_attr "length" "4")
10771 
   (set_attr "slot" "cop")
10772 
   (set_attr "slots" "c3")
10773 
   (set_attr "stall" "none")])
10774 
 
10775 
 
10776 
(define_insn "cgen_intrinsic_cpand3_P0_P1"
10777 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10778 
        (unspec:DI [
10779 
          (match_operand:DI 1 "general_operand" "x")
10780 
          (match_operand:DI 2 "general_operand" "x")
10781 
        ] 3538))]
10782 
  "CGEN_ENABLE_INSN_P (351)"
10783 
  "cpand3\\t%0,%1,%2"
10784 
  [(set_attr "may_trap" "no")
10785 
   (set_attr "latency" "0")
10786 
   (set_attr "length" "4")
10787 
   (set_attr "slot" "cop")
10788 
   (set_attr "slots" "p0_p1")
10789 
   (set_attr "stall" "none")])
10790 
 
10791 
 
10792 
(define_insn "cgen_intrinsic_cpabs3_h_C3"
10793 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10794 
        (unspec:DI [
10795 
          (match_operand:DI 1 "general_operand" "x")
10796 
          (match_operand:DI 2 "general_operand" "x")
10797 
        ] 3410))]
10798 
  "CGEN_ENABLE_INSN_P (352)"
10799 
  "cpabs3.h\\t%0,%1,%2"
10800 
  [(set_attr "may_trap" "no")
10801 
   (set_attr "latency" "0")
10802 
   (set_attr "length" "4")
10803 
   (set_attr "slot" "cop")
10804 
   (set_attr "slots" "c3")
10805 
   (set_attr "stall" "none")])
10806 
 
10807 
 
10808 
(define_insn "cgen_intrinsic_cpabs3_h_P0_P1"
10809 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10810 
        (unspec:DI [
10811 
          (match_operand:DI 1 "general_operand" "x")
10812 
          (match_operand:DI 2 "general_operand" "x")
10813 
        ] 3410))]
10814 
  "CGEN_ENABLE_INSN_P (353)"
10815 
  "cpabs3.h\\t%0,%1,%2"
10816 
  [(set_attr "may_trap" "no")
10817 
   (set_attr "latency" "0")
10818 
   (set_attr "length" "4")
10819 
   (set_attr "slot" "cop")
10820 
   (set_attr "slots" "p0_p1")
10821 
   (set_attr "stall" "none")])
10822 
 
10823 
 
10824 
(define_insn "cgen_intrinsic_cpabs3_b_C3"
10825 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10826 
        (unspec:DI [
10827 
          (match_operand:DI 1 "general_operand" "x")
10828 
          (match_operand:DI 2 "general_operand" "x")
10829 
        ] 3412))]
10830 
  "CGEN_ENABLE_INSN_P (354)"
10831 
  "cpabs3.b\\t%0,%1,%2"
10832 
  [(set_attr "may_trap" "no")
10833 
   (set_attr "latency" "0")
10834 
   (set_attr "length" "4")
10835 
   (set_attr "slot" "cop")
10836 
   (set_attr "slots" "c3")
10837 
   (set_attr "stall" "none")])
10838 
 
10839 
 
10840 
(define_insn "cgen_intrinsic_cpabs3_b_P0_P1"
10841 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10842 
        (unspec:DI [
10843 
          (match_operand:DI 1 "general_operand" "x")
10844 
          (match_operand:DI 2 "general_operand" "x")
10845 
        ] 3412))]
10846 
  "CGEN_ENABLE_INSN_P (355)"
10847 
  "cpabs3.b\\t%0,%1,%2"
10848 
  [(set_attr "may_trap" "no")
10849 
   (set_attr "latency" "0")
10850 
   (set_attr "length" "4")
10851 
   (set_attr "slot" "cop")
10852 
   (set_attr "slots" "p0_p1")
10853 
   (set_attr "stall" "none")])
10854 
 
10855 
 
10856 
(define_insn "cgen_intrinsic_cpabsu3_b_C3"
10857 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10858 
        (unspec:DI [
10859 
          (match_operand:DI 1 "general_operand" "x")
10860 
          (match_operand:DI 2 "general_operand" "x")
10861 
        ] 3414))]
10862 
  "CGEN_ENABLE_INSN_P (356)"
10863 
  "cpabsu3.b\\t%0,%1,%2"
10864 
  [(set_attr "may_trap" "no")
10865 
   (set_attr "latency" "0")
10866 
   (set_attr "length" "4")
10867 
   (set_attr "slot" "cop")
10868 
   (set_attr "slots" "c3")
10869 
   (set_attr "stall" "none")])
10870 
 
10871 
 
10872 
(define_insn "cgen_intrinsic_cpabsu3_b_P0_P1"
10873 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10874 
        (unspec:DI [
10875 
          (match_operand:DI 1 "general_operand" "x")
10876 
          (match_operand:DI 2 "general_operand" "x")
10877 
        ] 3414))]
10878 
  "CGEN_ENABLE_INSN_P (357)"
10879 
  "cpabsu3.b\\t%0,%1,%2"
10880 
  [(set_attr "may_trap" "no")
10881 
   (set_attr "latency" "0")
10882 
   (set_attr "length" "4")
10883 
   (set_attr "slot" "cop")
10884 
   (set_attr "slots" "p0_p1")
10885 
   (set_attr "stall" "none")])
10886 
 
10887 
 
10888 
(define_insn "cgen_intrinsic_cpaddsr3_w_C3"
10889 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10890 
        (unspec:DI [
10891 
          (match_operand:DI 1 "general_operand" "x")
10892 
          (match_operand:DI 2 "general_operand" "x")
10893 
        ] 3416))]
10894 
  "CGEN_ENABLE_INSN_P (358)"
10895 
  "cpaddsr3.w\\t%0,%1,%2"
10896 
  [(set_attr "may_trap" "no")
10897 
   (set_attr "latency" "0")
10898 
   (set_attr "length" "4")
10899 
   (set_attr "slot" "cop")
10900 
   (set_attr "slots" "c3")
10901 
   (set_attr "stall" "none")])
10902 
 
10903 
 
10904 
(define_insn "cgen_intrinsic_cpaddsr3_w_P0_P1"
10905 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10906 
        (unspec:DI [
10907 
          (match_operand:DI 1 "general_operand" "x")
10908 
          (match_operand:DI 2 "general_operand" "x")
10909 
        ] 3416))]
10910 
  "CGEN_ENABLE_INSN_P (359)"
10911 
  "cpaddsr3.w\\t%0,%1,%2"
10912 
  [(set_attr "may_trap" "no")
10913 
   (set_attr "latency" "0")
10914 
   (set_attr "length" "4")
10915 
   (set_attr "slot" "cop")
10916 
   (set_attr "slots" "p0_p1")
10917 
   (set_attr "stall" "none")])
10918 
 
10919 
 
10920 
(define_insn "cgen_intrinsic_cpaddsr3_h_C3"
10921 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10922 
        (unspec:DI [
10923 
          (match_operand:DI 1 "general_operand" "x")
10924 
          (match_operand:DI 2 "general_operand" "x")
10925 
        ] 3418))]
10926 
  "CGEN_ENABLE_INSN_P (360)"
10927 
  "cpaddsr3.h\\t%0,%1,%2"
10928 
  [(set_attr "may_trap" "no")
10929 
   (set_attr "latency" "0")
10930 
   (set_attr "length" "4")
10931 
   (set_attr "slot" "cop")
10932 
   (set_attr "slots" "c3")
10933 
   (set_attr "stall" "none")])
10934 
 
10935 
 
10936 
(define_insn "cgen_intrinsic_cpaddsr3_h_P0_P1"
10937 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10938 
        (unspec:DI [
10939 
          (match_operand:DI 1 "general_operand" "x")
10940 
          (match_operand:DI 2 "general_operand" "x")
10941 
        ] 3418))]
10942 
  "CGEN_ENABLE_INSN_P (361)"
10943 
  "cpaddsr3.h\\t%0,%1,%2"
10944 
  [(set_attr "may_trap" "no")
10945 
   (set_attr "latency" "0")
10946 
   (set_attr "length" "4")
10947 
   (set_attr "slot" "cop")
10948 
   (set_attr "slots" "p0_p1")
10949 
   (set_attr "stall" "none")])
10950 
 
10951 
 
10952 
(define_insn "cgen_intrinsic_cpaddsr3_b_C3"
10953 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10954 
        (unspec:DI [
10955 
          (match_operand:DI 1 "general_operand" "x")
10956 
          (match_operand:DI 2 "general_operand" "x")
10957 
        ] 3420))]
10958 
  "CGEN_ENABLE_INSN_P (362)"
10959 
  "cpaddsr3.b\\t%0,%1,%2"
10960 
  [(set_attr "may_trap" "no")
10961 
   (set_attr "latency" "0")
10962 
   (set_attr "length" "4")
10963 
   (set_attr "slot" "cop")
10964 
   (set_attr "slots" "c3")
10965 
   (set_attr "stall" "none")])
10966 
 
10967 
 
10968 
(define_insn "cgen_intrinsic_cpaddsr3_b_P0_P1"
10969 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10970 
        (unspec:DI [
10971 
          (match_operand:DI 1 "general_operand" "x")
10972 
          (match_operand:DI 2 "general_operand" "x")
10973 
        ] 3420))]
10974 
  "CGEN_ENABLE_INSN_P (363)"
10975 
  "cpaddsr3.b\\t%0,%1,%2"
10976 
  [(set_attr "may_trap" "no")
10977 
   (set_attr "latency" "0")
10978 
   (set_attr "length" "4")
10979 
   (set_attr "slot" "cop")
10980 
   (set_attr "slots" "p0_p1")
10981 
   (set_attr "stall" "none")])
10982 
 
10983 
 
10984 
(define_insn "cgen_intrinsic_cpaddsru3_b_C3"
10985 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10986 
        (unspec:DI [
10987 
          (match_operand:DI 1 "general_operand" "x")
10988 
          (match_operand:DI 2 "general_operand" "x")
10989 
        ] 3422))]
10990 
  "CGEN_ENABLE_INSN_P (364)"
10991 
  "cpaddsru3.b\\t%0,%1,%2"
10992 
  [(set_attr "may_trap" "no")
10993 
   (set_attr "latency" "0")
10994 
   (set_attr "length" "4")
10995 
   (set_attr "slot" "cop")
10996 
   (set_attr "slots" "c3")
10997 
   (set_attr "stall" "none")])
10998 
 
10999 
 
11000 
(define_insn "cgen_intrinsic_cpaddsru3_b_P0_P1"
11001 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11002 
        (unspec:DI [
11003 
          (match_operand:DI 1 "general_operand" "x")
11004 
          (match_operand:DI 2 "general_operand" "x")
11005 
        ] 3422))]
11006 
  "CGEN_ENABLE_INSN_P (365)"
11007 
  "cpaddsru3.b\\t%0,%1,%2"
11008 
  [(set_attr "may_trap" "no")
11009 
   (set_attr "latency" "0")
11010 
   (set_attr "length" "4")
11011 
   (set_attr "slot" "cop")
11012 
   (set_attr "slots" "p0_p1")
11013 
   (set_attr "stall" "none")])
11014 
 
11015 
 
11016 
(define_insn "cgen_intrinsic_cpave3_w_C3"
11017 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11018 
        (unspec:DI [
11019 
          (match_operand:DI 1 "general_operand" "x")
11020 
          (match_operand:DI 2 "general_operand" "x")
11021 
        ] 3424))]
11022 
  "CGEN_ENABLE_INSN_P (366)"
11023 
  "cpave3.w\\t%0,%1,%2"
11024 
  [(set_attr "may_trap" "no")
11025 
   (set_attr "latency" "0")
11026 
   (set_attr "length" "4")
11027 
   (set_attr "slot" "cop")
11028 
   (set_attr "slots" "c3")
11029 
   (set_attr "stall" "none")])
11030 
 
11031 
 
11032 
(define_insn "cgen_intrinsic_cpave3_w_P0_P1"
11033 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11034 
        (unspec:DI [
11035 
          (match_operand:DI 1 "general_operand" "x")
11036 
          (match_operand:DI 2 "general_operand" "x")
11037 
        ] 3424))]
11038 
  "CGEN_ENABLE_INSN_P (367)"
11039 
  "cpave3.w\\t%0,%1,%2"
11040 
  [(set_attr "may_trap" "no")
11041 
   (set_attr "latency" "0")
11042 
   (set_attr "length" "4")
11043 
   (set_attr "slot" "cop")
11044 
   (set_attr "slots" "p0_p1")
11045 
   (set_attr "stall" "none")])
11046 
 
11047 
 
11048 
(define_insn "cgen_intrinsic_cpave3_h_C3"
11049 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11050 
        (unspec:DI [
11051 
          (match_operand:DI 1 "general_operand" "x")
11052 
          (match_operand:DI 2 "general_operand" "x")
11053 
        ] 3426))]
11054 
  "CGEN_ENABLE_INSN_P (368)"
11055 
  "cpave3.h\\t%0,%1,%2"
11056 
  [(set_attr "may_trap" "no")
11057 
   (set_attr "latency" "0")
11058 
   (set_attr "length" "4")
11059 
   (set_attr "slot" "cop")
11060 
   (set_attr "slots" "c3")
11061 
   (set_attr "stall" "none")])
11062 
 
11063 
 
11064 
(define_insn "cgen_intrinsic_cpave3_h_P0_P1"
11065 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11066 
        (unspec:DI [
11067 
          (match_operand:DI 1 "general_operand" "x")
11068 
          (match_operand:DI 2 "general_operand" "x")
11069 
        ] 3426))]
11070 
  "CGEN_ENABLE_INSN_P (369)"
11071 
  "cpave3.h\\t%0,%1,%2"
11072 
  [(set_attr "may_trap" "no")
11073 
   (set_attr "latency" "0")
11074 
   (set_attr "length" "4")
11075 
   (set_attr "slot" "cop")
11076 
   (set_attr "slots" "p0_p1")
11077 
   (set_attr "stall" "none")])
11078 
 
11079 
 
11080 
(define_insn "cgen_intrinsic_cpave3_b_C3"
11081 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11082 
        (unspec:DI [
11083 
          (match_operand:DI 1 "general_operand" "x")
11084 
          (match_operand:DI 2 "general_operand" "x")
11085 
        ] 3428))]
11086 
  "CGEN_ENABLE_INSN_P (370)"
11087 
  "cpave3.b\\t%0,%1,%2"
11088 
  [(set_attr "may_trap" "no")
11089 
   (set_attr "latency" "0")
11090 
   (set_attr "length" "4")
11091 
   (set_attr "slot" "cop")
11092 
   (set_attr "slots" "c3")
11093 
   (set_attr "stall" "none")])
11094 
 
11095 
 
11096 
(define_insn "cgen_intrinsic_cpave3_b_P0_P1"
11097 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11098 
        (unspec:DI [
11099 
          (match_operand:DI 1 "general_operand" "x")
11100 
          (match_operand:DI 2 "general_operand" "x")
11101 
        ] 3428))]
11102 
  "CGEN_ENABLE_INSN_P (371)"
11103 
  "cpave3.b\\t%0,%1,%2"
11104 
  [(set_attr "may_trap" "no")
11105 
   (set_attr "latency" "0")
11106 
   (set_attr "length" "4")
11107 
   (set_attr "slot" "cop")
11108 
   (set_attr "slots" "p0_p1")
11109 
   (set_attr "stall" "none")])
11110 
 
11111 
 
11112 
(define_insn "cgen_intrinsic_cpaveu3_b_C3"
11113 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11114 
        (unspec:DI [
11115 
          (match_operand:DI 1 "general_operand" "x")
11116 
          (match_operand:DI 2 "general_operand" "x")
11117 
        ] 3430))]
11118 
  "CGEN_ENABLE_INSN_P (372)"
11119 
  "cpaveu3.b\\t%0,%1,%2"
11120 
  [(set_attr "may_trap" "no")
11121 
   (set_attr "latency" "0")
11122 
   (set_attr "length" "4")
11123 
   (set_attr "slot" "cop")
11124 
   (set_attr "slots" "c3")
11125 
   (set_attr "stall" "none")])
11126 
 
11127 
 
11128 
(define_insn "cgen_intrinsic_cpaveu3_b_P0_P1"
11129 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11130 
        (unspec:DI [
11131 
          (match_operand:DI 1 "general_operand" "x")
11132 
          (match_operand:DI 2 "general_operand" "x")
11133 
        ] 3430))]
11134 
  "CGEN_ENABLE_INSN_P (373)"
11135 
  "cpaveu3.b\\t%0,%1,%2"
11136 
  [(set_attr "may_trap" "no")
11137 
   (set_attr "latency" "0")
11138 
   (set_attr "length" "4")
11139 
   (set_attr "slot" "cop")
11140 
   (set_attr "slots" "p0_p1")
11141 
   (set_attr "stall" "none")])
11142 
 
11143 
 
11144 
(define_insn "cgen_intrinsic_cpextlsub3_b_C3"
11145 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11146 
        (unspec:DI [
11147 
          (match_operand:DI 1 "general_operand" "x")
11148 
          (match_operand:DI 2 "general_operand" "x")
11149 
        ] 3432))]
11150 
  "CGEN_ENABLE_INSN_P (374)"
11151 
  "cpextlsub3.b\\t%0,%1,%2"
11152 
  [(set_attr "may_trap" "no")
11153 
   (set_attr "latency" "0")
11154 
   (set_attr "length" "4")
11155 
   (set_attr "slot" "cop")
11156 
   (set_attr "slots" "c3")
11157 
   (set_attr "stall" "none")])
11158 
 
11159 
 
11160 
(define_insn "cgen_intrinsic_cpextlsub3_b_P0_P1"
11161 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11162 
        (unspec:DI [
11163 
          (match_operand:DI 1 "general_operand" "x")
11164 
          (match_operand:DI 2 "general_operand" "x")
11165 
        ] 3432))]
11166 
  "CGEN_ENABLE_INSN_P (375)"
11167 
  "cpextlsub3.b\\t%0,%1,%2"
11168 
  [(set_attr "may_trap" "no")
11169 
   (set_attr "latency" "0")
11170 
   (set_attr "length" "4")
11171 
   (set_attr "slot" "cop")
11172 
   (set_attr "slots" "p0_p1")
11173 
   (set_attr "stall" "none")])
11174 
 
11175 
 
11176 
(define_insn "cgen_intrinsic_cpextlsubu3_b_C3"
11177 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11178 
        (unspec:DI [
11179 
          (match_operand:DI 1 "general_operand" "x")
11180 
          (match_operand:DI 2 "general_operand" "x")
11181 
        ] 3434))]
11182 
  "CGEN_ENABLE_INSN_P (376)"
11183 
  "cpextlsubu3.b\\t%0,%1,%2"
11184 
  [(set_attr "may_trap" "no")
11185 
   (set_attr "latency" "0")
11186 
   (set_attr "length" "4")
11187 
   (set_attr "slot" "cop")
11188 
   (set_attr "slots" "c3")
11189 
   (set_attr "stall" "none")])
11190 
 
11191 
 
11192 
(define_insn "cgen_intrinsic_cpextlsubu3_b_P0_P1"
11193 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11194 
        (unspec:DI [
11195 
          (match_operand:DI 1 "general_operand" "x")
11196 
          (match_operand:DI 2 "general_operand" "x")
11197 
        ] 3434))]
11198 
  "CGEN_ENABLE_INSN_P (377)"
11199 
  "cpextlsubu3.b\\t%0,%1,%2"
11200 
  [(set_attr "may_trap" "no")
11201 
   (set_attr "latency" "0")
11202 
   (set_attr "length" "4")
11203 
   (set_attr "slot" "cop")
11204 
   (set_attr "slots" "p0_p1")
11205 
   (set_attr "stall" "none")])
11206 
 
11207 
 
11208 
(define_insn "cgen_intrinsic_cpextusub3_b_C3"
11209 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11210 
        (unspec:DI [
11211 
          (match_operand:DI 1 "general_operand" "x")
11212 
          (match_operand:DI 2 "general_operand" "x")
11213 
        ] 3436))]
11214 
  "CGEN_ENABLE_INSN_P (378)"
11215 
  "cpextusub3.b\\t%0,%1,%2"
11216 
  [(set_attr "may_trap" "no")
11217 
   (set_attr "latency" "0")
11218 
   (set_attr "length" "4")
11219 
   (set_attr "slot" "cop")
11220 
   (set_attr "slots" "c3")
11221 
   (set_attr "stall" "none")])
11222 
 
11223 
 
11224 
(define_insn "cgen_intrinsic_cpextusub3_b_P0_P1"
11225 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11226 
        (unspec:DI [
11227 
          (match_operand:DI 1 "general_operand" "x")
11228 
          (match_operand:DI 2 "general_operand" "x")
11229 
        ] 3436))]
11230 
  "CGEN_ENABLE_INSN_P (379)"
11231 
  "cpextusub3.b\\t%0,%1,%2"
11232 
  [(set_attr "may_trap" "no")
11233 
   (set_attr "latency" "0")
11234 
   (set_attr "length" "4")
11235 
   (set_attr "slot" "cop")
11236 
   (set_attr "slots" "p0_p1")
11237 
   (set_attr "stall" "none")])
11238 
 
11239 
 
11240 
(define_insn "cgen_intrinsic_cpextusubu3_b_C3"
11241 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11242 
        (unspec:DI [
11243 
          (match_operand:DI 1 "general_operand" "x")
11244 
          (match_operand:DI 2 "general_operand" "x")
11245 
        ] 3438))]
11246 
  "CGEN_ENABLE_INSN_P (380)"
11247 
  "cpextusubu3.b\\t%0,%1,%2"
11248 
  [(set_attr "may_trap" "no")
11249 
   (set_attr "latency" "0")
11250 
   (set_attr "length" "4")
11251 
   (set_attr "slot" "cop")
11252 
   (set_attr "slots" "c3")
11253 
   (set_attr "stall" "none")])
11254 
 
11255 
 
11256 
(define_insn "cgen_intrinsic_cpextusubu3_b_P0_P1"
11257 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11258 
        (unspec:DI [
11259 
          (match_operand:DI 1 "general_operand" "x")
11260 
          (match_operand:DI 2 "general_operand" "x")
11261 
        ] 3438))]
11262 
  "CGEN_ENABLE_INSN_P (381)"
11263 
  "cpextusubu3.b\\t%0,%1,%2"
11264 
  [(set_attr "may_trap" "no")
11265 
   (set_attr "latency" "0")
11266 
   (set_attr "length" "4")
11267 
   (set_attr "slot" "cop")
11268 
   (set_attr "slots" "p0_p1")
11269 
   (set_attr "stall" "none")])
11270 
 
11271 
 
11272 
(define_insn "cgen_intrinsic_cpextladd3_b_C3"
11273 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11274 
        (unspec:DI [
11275 
          (match_operand:DI 1 "general_operand" "x")
11276 
          (match_operand:DI 2 "general_operand" "x")
11277 
        ] 3440))]
11278 
  "CGEN_ENABLE_INSN_P (382)"
11279 
  "cpextladd3.b\\t%0,%1,%2"
11280 
  [(set_attr "may_trap" "no")
11281 
   (set_attr "latency" "0")
11282 
   (set_attr "length" "4")
11283 
   (set_attr "slot" "cop")
11284 
   (set_attr "slots" "c3")
11285 
   (set_attr "stall" "none")])
11286 
 
11287 
 
11288 
(define_insn "cgen_intrinsic_cpextladd3_b_P0_P1"
11289 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11290 
        (unspec:DI [
11291 
          (match_operand:DI 1 "general_operand" "x")
11292 
          (match_operand:DI 2 "general_operand" "x")
11293 
        ] 3440))]
11294 
  "CGEN_ENABLE_INSN_P (383)"
11295 
  "cpextladd3.b\\t%0,%1,%2"
11296 
  [(set_attr "may_trap" "no")
11297 
   (set_attr "latency" "0")
11298 
   (set_attr "length" "4")
11299 
   (set_attr "slot" "cop")
11300 
   (set_attr "slots" "p0_p1")
11301 
   (set_attr "stall" "none")])
11302 
 
11303 
 
11304 
(define_insn "cgen_intrinsic_cpextladdu3_b_C3"
11305 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11306 
        (unspec:DI [
11307 
          (match_operand:DI 1 "general_operand" "x")
11308 
          (match_operand:DI 2 "general_operand" "x")
11309 
        ] 3442))]
11310 
  "CGEN_ENABLE_INSN_P (384)"
11311 
  "cpextladdu3.b\\t%0,%1,%2"
11312 
  [(set_attr "may_trap" "no")
11313 
   (set_attr "latency" "0")
11314 
   (set_attr "length" "4")
11315 
   (set_attr "slot" "cop")
11316 
   (set_attr "slots" "c3")
11317 
   (set_attr "stall" "none")])
11318 
 
11319 
 
11320 
(define_insn "cgen_intrinsic_cpextladdu3_b_P0_P1"
11321 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11322 
        (unspec:DI [
11323 
          (match_operand:DI 1 "general_operand" "x")
11324 
          (match_operand:DI 2 "general_operand" "x")
11325 
        ] 3442))]
11326 
  "CGEN_ENABLE_INSN_P (385)"
11327 
  "cpextladdu3.b\\t%0,%1,%2"
11328 
  [(set_attr "may_trap" "no")
11329 
   (set_attr "latency" "0")
11330 
   (set_attr "length" "4")
11331 
   (set_attr "slot" "cop")
11332 
   (set_attr "slots" "p0_p1")
11333 
   (set_attr "stall" "none")])
11334 
 
11335 
 
11336 
(define_insn "cgen_intrinsic_cpextuadd3_b_C3"
11337 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11338 
        (unspec:DI [
11339 
          (match_operand:DI 1 "general_operand" "x")
11340 
          (match_operand:DI 2 "general_operand" "x")
11341 
        ] 3444))]
11342 
  "CGEN_ENABLE_INSN_P (386)"
11343 
  "cpextuadd3.b\\t%0,%1,%2"
11344 
  [(set_attr "may_trap" "no")
11345 
   (set_attr "latency" "0")
11346 
   (set_attr "length" "4")
11347 
   (set_attr "slot" "cop")
11348 
   (set_attr "slots" "c3")
11349 
   (set_attr "stall" "none")])
11350 
 
11351 
 
11352 
(define_insn "cgen_intrinsic_cpextuadd3_b_P0_P1"
11353 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11354 
        (unspec:DI [
11355 
          (match_operand:DI 1 "general_operand" "x")
11356 
          (match_operand:DI 2 "general_operand" "x")
11357 
        ] 3444))]
11358 
  "CGEN_ENABLE_INSN_P (387)"
11359 
  "cpextuadd3.b\\t%0,%1,%2"
11360 
  [(set_attr "may_trap" "no")
11361 
   (set_attr "latency" "0")
11362 
   (set_attr "length" "4")
11363 
   (set_attr "slot" "cop")
11364 
   (set_attr "slots" "p0_p1")
11365 
   (set_attr "stall" "none")])
11366 
 
11367 
 
11368 
(define_insn "cgen_intrinsic_cpextuaddu3_b_C3"
11369 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11370 
        (unspec:DI [
11371 
          (match_operand:DI 1 "general_operand" "x")
11372 
          (match_operand:DI 2 "general_operand" "x")
11373 
        ] 3446))]
11374 
  "CGEN_ENABLE_INSN_P (388)"
11375 
  "cpextuaddu3.b\\t%0,%1,%2"
11376 
  [(set_attr "may_trap" "no")
11377 
   (set_attr "latency" "0")
11378 
   (set_attr "length" "4")
11379 
   (set_attr "slot" "cop")
11380 
   (set_attr "slots" "c3")
11381 
   (set_attr "stall" "none")])
11382 
 
11383 
 
11384 
(define_insn "cgen_intrinsic_cpextuaddu3_b_P0_P1"
11385 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11386 
        (unspec:DI [
11387 
          (match_operand:DI 1 "general_operand" "x")
11388 
          (match_operand:DI 2 "general_operand" "x")
11389 
        ] 3446))]
11390 
  "CGEN_ENABLE_INSN_P (389)"
11391 
  "cpextuaddu3.b\\t%0,%1,%2"
11392 
  [(set_attr "may_trap" "no")
11393 
   (set_attr "latency" "0")
11394 
   (set_attr "length" "4")
11395 
   (set_attr "slot" "cop")
11396 
   (set_attr "slots" "p0_p1")
11397 
   (set_attr "stall" "none")])
11398 
 
11399 
 
11400 
(define_insn "cgen_intrinsic_cpssub3_w_C3"
11401 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11402 
        (unspec_volatile:DI [
11403 
          (match_operand:DI 1 "general_operand" "x")
11404 
          (match_operand:DI 2 "general_operand" "x")
11405 
        ] 3448))
11406 
   (set (reg:SI 84)
11407 
        (unspec_volatile:SI [
11408 
          (match_dup 1)
11409 
          (match_dup 2)
11410 
        ] 3450))]
11411 
  "CGEN_ENABLE_INSN_P (390)"
11412 
  "cpssub3.w\\t%0,%1,%2"
11413 
  [(set_attr "may_trap" "no")
11414 
   (set_attr "latency" "0")
11415 
   (set_attr "length" "4")
11416 
   (set_attr "slot" "cop")
11417 
   (set_attr "slots" "c3")
11418 
   (set_attr "stall" "none")])
11419 
 
11420 
 
11421 
(define_insn "cgen_intrinsic_cpssub3_w_P0_P1"
11422 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11423 
        (unspec_volatile:DI [
11424 
          (match_operand:DI 1 "general_operand" "x")
11425 
          (match_operand:DI 2 "general_operand" "x")
11426 
        ] 3448))
11427 
   (set (reg:SI 84)
11428 
        (unspec_volatile:SI [
11429 
          (match_dup 1)
11430 
          (match_dup 2)
11431 
        ] 3450))]
11432 
  "CGEN_ENABLE_INSN_P (391)"
11433 
  "cpssub3.w\\t%0,%1,%2"
11434 
  [(set_attr "may_trap" "no")
11435 
   (set_attr "latency" "0")
11436 
   (set_attr "length" "4")
11437 
   (set_attr "slot" "cop")
11438 
   (set_attr "slots" "p0_p1")
11439 
   (set_attr "stall" "none")])
11440 
 
11441 
 
11442 
(define_insn "cgen_intrinsic_cpssub3_h_C3"
11443 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11444 
        (unspec_volatile:DI [
11445 
          (match_operand:DI 1 "general_operand" "x")
11446 
          (match_operand:DI 2 "general_operand" "x")
11447 
        ] 3452))
11448 
   (set (reg:SI 84)
11449 
        (unspec_volatile:SI [
11450 
          (match_dup 1)
11451 
          (match_dup 2)
11452 
        ] 3454))]
11453 
  "CGEN_ENABLE_INSN_P (392)"
11454 
  "cpssub3.h\\t%0,%1,%2"
11455 
  [(set_attr "may_trap" "no")
11456 
   (set_attr "latency" "0")
11457 
   (set_attr "length" "4")
11458 
   (set_attr "slot" "cop")
11459 
   (set_attr "slots" "c3")
11460 
   (set_attr "stall" "none")])
11461 
 
11462 
 
11463 
(define_insn "cgen_intrinsic_cpssub3_h_P0_P1"
11464 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11465 
        (unspec_volatile:DI [
11466 
          (match_operand:DI 1 "general_operand" "x")
11467 
          (match_operand:DI 2 "general_operand" "x")
11468 
        ] 3452))
11469 
   (set (reg:SI 84)
11470 
        (unspec_volatile:SI [
11471 
          (match_dup 1)
11472 
          (match_dup 2)
11473 
        ] 3454))]
11474 
  "CGEN_ENABLE_INSN_P (393)"
11475 
  "cpssub3.h\\t%0,%1,%2"
11476 
  [(set_attr "may_trap" "no")
11477 
   (set_attr "latency" "0")
11478 
   (set_attr "length" "4")
11479 
   (set_attr "slot" "cop")
11480 
   (set_attr "slots" "p0_p1")
11481 
   (set_attr "stall" "none")])
11482 
 
11483 
 
11484 
(define_insn "cgen_intrinsic_cpsadd3_w_C3"
11485 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11486 
        (unspec_volatile:DI [
11487 
          (match_operand:DI 1 "general_operand" "x")
11488 
          (match_operand:DI 2 "general_operand" "x")
11489 
        ] 3456))]
11490 
  "CGEN_ENABLE_INSN_P (394)"
11491 
  "cpsadd3.w\\t%0,%1,%2"
11492 
  [(set_attr "may_trap" "no")
11493 
   (set_attr "latency" "0")
11494 
   (set_attr "length" "4")
11495 
   (set_attr "slot" "cop")
11496 
   (set_attr "slots" "c3")
11497 
   (set_attr "stall" "none")])
11498 
 
11499 
 
11500 
(define_insn "cgen_intrinsic_cpsadd3_w_P0_P1"
11501 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11502 
        (unspec_volatile:DI [
11503 
          (match_operand:DI 1 "general_operand" "x")
11504 
          (match_operand:DI 2 "general_operand" "x")
11505 
        ] 3456))]
11506 
  "CGEN_ENABLE_INSN_P (395)"
11507 
  "cpsadd3.w\\t%0,%1,%2"
11508 
  [(set_attr "may_trap" "no")
11509 
   (set_attr "latency" "0")
11510 
   (set_attr "length" "4")
11511 
   (set_attr "slot" "cop")
11512 
   (set_attr "slots" "p0_p1")
11513 
   (set_attr "stall" "none")])
11514 
 
11515 
 
11516 
(define_insn "cgen_intrinsic_cpsadd3_h_C3"
11517 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11518 
        (unspec_volatile:DI [
11519 
          (match_operand:DI 1 "general_operand" "x")
11520 
          (match_operand:DI 2 "general_operand" "x")
11521 
        ] 3458))]
11522 
  "CGEN_ENABLE_INSN_P (396)"
11523 
  "cpsadd3.h\\t%0,%1,%2"
11524 
  [(set_attr "may_trap" "no")
11525 
   (set_attr "latency" "0")
11526 
   (set_attr "length" "4")
11527 
   (set_attr "slot" "cop")
11528 
   (set_attr "slots" "c3")
11529 
   (set_attr "stall" "none")])
11530 
 
11531 
 
11532 
(define_insn "cgen_intrinsic_cpsadd3_h_P0_P1"
11533 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11534 
        (unspec_volatile:DI [
11535 
          (match_operand:DI 1 "general_operand" "x")
11536 
          (match_operand:DI 2 "general_operand" "x")
11537 
        ] 3458))]
11538 
  "CGEN_ENABLE_INSN_P (397)"
11539 
  "cpsadd3.h\\t%0,%1,%2"
11540 
  [(set_attr "may_trap" "no")
11541 
   (set_attr "latency" "0")
11542 
   (set_attr "length" "4")
11543 
   (set_attr "slot" "cop")
11544 
   (set_attr "slots" "p0_p1")
11545 
   (set_attr "stall" "none")])
11546 
 
11547 
 
11548 
(define_insn "cgen_intrinsic_cdsub3_C3"
11549 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11550 
        (unspec:DI [
11551 
          (match_operand:DI 1 "general_operand" "x")
11552 
          (match_operand:DI 2 "general_operand" "x")
11553 
        ] 3540))]
11554 
  "CGEN_ENABLE_INSN_P (398)"
11555 
  "cdsub3\\t%0,%1,%2"
11556 
  [(set_attr "may_trap" "no")
11557 
   (set_attr "latency" "0")
11558 
   (set_attr "length" "4")
11559 
   (set_attr "slot" "cop")
11560 
   (set_attr "slots" "c3")
11561 
   (set_attr "stall" "none")])
11562 
 
11563 
 
11564 
(define_insn "cgen_intrinsic_cdsub3_P0_P1"
11565 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11566 
        (unspec:DI [
11567 
          (match_operand:DI 1 "general_operand" "x")
11568 
          (match_operand:DI 2 "general_operand" "x")
11569 
        ] 3540))]
11570 
  "CGEN_ENABLE_INSN_P (399)"
11571 
  "cdsub3\\t%0,%1,%2"
11572 
  [(set_attr "may_trap" "no")
11573 
   (set_attr "latency" "0")
11574 
   (set_attr "length" "4")
11575 
   (set_attr "slot" "cop")
11576 
   (set_attr "slots" "p0_p1")
11577 
   (set_attr "stall" "none")])
11578 
 
11579 
 
11580 
(define_insn "cgen_intrinsic_cpsub3_w_C3"
11581 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11582 
        (unspec:DI [
11583 
          (match_operand:DI 1 "general_operand" "x")
11584 
          (match_operand:DI 2 "general_operand" "x")
11585 
        ] 3542))]
11586 
  "CGEN_ENABLE_INSN_P (400)"
11587 
  "cpsub3.w\\t%0,%1,%2"
11588 
  [(set_attr "may_trap" "no")
11589 
   (set_attr "latency" "0")
11590 
   (set_attr "length" "4")
11591 
   (set_attr "slot" "cop")
11592 
   (set_attr "slots" "c3")
11593 
   (set_attr "stall" "none")])
11594 
 
11595 
 
11596 
(define_insn "cgen_intrinsic_cpsub3_w_P0_P1"
11597 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11598 
        (unspec:DI [
11599 
          (match_operand:DI 1 "general_operand" "x")
11600 
          (match_operand:DI 2 "general_operand" "x")
11601 
        ] 3542))]
11602 
  "CGEN_ENABLE_INSN_P (401)"
11603 
  "cpsub3.w\\t%0,%1,%2"
11604 
  [(set_attr "may_trap" "no")
11605 
   (set_attr "latency" "0")
11606 
   (set_attr "length" "4")
11607 
   (set_attr "slot" "cop")
11608 
   (set_attr "slots" "p0_p1")
11609 
   (set_attr "stall" "none")])
11610 
 
11611 
 
11612 
(define_insn "cgen_intrinsic_cpsub3_h_C3"
11613 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11614 
        (unspec:DI [
11615 
          (match_operand:DI 1 "general_operand" "x")
11616 
          (match_operand:DI 2 "general_operand" "x")
11617 
        ] 3544))]
11618 
  "CGEN_ENABLE_INSN_P (402)"
11619 
  "cpsub3.h\\t%0,%1,%2"
11620 
  [(set_attr "may_trap" "no")
11621 
   (set_attr "latency" "0")
11622 
   (set_attr "length" "4")
11623 
   (set_attr "slot" "cop")
11624 
   (set_attr "slots" "c3")
11625 
   (set_attr "stall" "none")])
11626 
 
11627 
 
11628 
(define_insn "cgen_intrinsic_cpsub3_h_P0_P1"
11629 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11630 
        (unspec:DI [
11631 
          (match_operand:DI 1 "general_operand" "x")
11632 
          (match_operand:DI 2 "general_operand" "x")
11633 
        ] 3544))]
11634 
  "CGEN_ENABLE_INSN_P (403)"
11635 
  "cpsub3.h\\t%0,%1,%2"
11636 
  [(set_attr "may_trap" "no")
11637 
   (set_attr "latency" "0")
11638 
   (set_attr "length" "4")
11639 
   (set_attr "slot" "cop")
11640 
   (set_attr "slots" "p0_p1")
11641 
   (set_attr "stall" "none")])
11642 
 
11643 
 
11644 
(define_insn "cgen_intrinsic_cpsub3_b_C3"
11645 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11646 
        (unspec:DI [
11647 
          (match_operand:DI 1 "general_operand" "x")
11648 
          (match_operand:DI 2 "general_operand" "x")
11649 
        ] 3546))]
11650 
  "CGEN_ENABLE_INSN_P (404)"
11651 
  "cpsub3.b\\t%0,%1,%2"
11652 
  [(set_attr "may_trap" "no")
11653 
   (set_attr "latency" "0")
11654 
   (set_attr "length" "4")
11655 
   (set_attr "slot" "cop")
11656 
   (set_attr "slots" "c3")
11657 
   (set_attr "stall" "none")])
11658 
 
11659 
 
11660 
(define_insn "cgen_intrinsic_cpsub3_b_P0_P1"
11661 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11662 
        (unspec:DI [
11663 
          (match_operand:DI 1 "general_operand" "x")
11664 
          (match_operand:DI 2 "general_operand" "x")
11665 
        ] 3546))]
11666 
  "CGEN_ENABLE_INSN_P (405)"
11667 
  "cpsub3.b\\t%0,%1,%2"
11668 
  [(set_attr "may_trap" "no")
11669 
   (set_attr "latency" "0")
11670 
   (set_attr "length" "4")
11671 
   (set_attr "slot" "cop")
11672 
   (set_attr "slots" "p0_p1")
11673 
   (set_attr "stall" "none")])
11674 
 
11675 
 
11676 
(define_insn "cgen_intrinsic_cdadd3_C3"
11677 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11678 
        (unspec:DI [
11679 
          (match_operand:DI 1 "general_operand" "x")
11680 
          (match_operand:DI 2 "general_operand" "x")
11681 
        ] 3548))]
11682 
  "CGEN_ENABLE_INSN_P (406)"
11683 
  "cdadd3\\t%0,%1,%2"
11684 
  [(set_attr "may_trap" "no")
11685 
   (set_attr "latency" "0")
11686 
   (set_attr "length" "4")
11687 
   (set_attr "slot" "cop")
11688 
   (set_attr "slots" "c3")
11689 
   (set_attr "stall" "none")])
11690 
 
11691 
 
11692 
(define_insn "cgen_intrinsic_cdadd3_P0_P1"
11693 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11694 
        (unspec:DI [
11695 
          (match_operand:DI 1 "general_operand" "x")
11696 
          (match_operand:DI 2 "general_operand" "x")
11697 
        ] 3548))]
11698 
  "CGEN_ENABLE_INSN_P (407)"
11699 
  "cdadd3\\t%0,%1,%2"
11700 
  [(set_attr "may_trap" "no")
11701 
   (set_attr "latency" "0")
11702 
   (set_attr "length" "4")
11703 
   (set_attr "slot" "cop")
11704 
   (set_attr "slots" "p0_p1")
11705 
   (set_attr "stall" "none")])
11706 
 
11707 
 
11708 
(define_insn "cgen_intrinsic_cpocmpge_w_C3"
11709 
  [(set (reg:SI 81)
11710 
        (unspec:SI [
11711 
          (match_operand:DI 0 "general_operand" "x")
11712 
          (match_operand:DI 1 "general_operand" "x")
11713 
        ] 3218))
11714 
   (set (reg:SI 113)
11715 
        (unspec:SI [
11716 
          (match_dup 0)
11717 
          (match_dup 1)
11718 
        ] 3219))]
11719 
  "CGEN_ENABLE_INSN_P (408)"
11720 
  "cpocmpge.w\\t%0,%1"
11721 
  [(set_attr "may_trap" "no")
11722 
   (set_attr "latency" "0")
11723 
   (set_attr "length" "4")
11724 
   (set_attr "slot" "cop")
11725 
   (set_attr "slots" "c3")
11726 
   (set_attr "stall" "none")])
11727 
 
11728 
 
11729 
(define_insn "cgen_intrinsic_cpocmpge_w_P0_P1"
11730 
  [(unspec_volatile [
11731 
     (match_operand:DI 0 "general_operand" "x")
11732 
     (match_operand:DI 1 "general_operand" "x")
11733 
   ] 3218)]
11734 
  "CGEN_ENABLE_INSN_P (409)"
11735 
  "cpocmpge.w\\t%0,%1"
11736 
  [(set_attr "may_trap" "no")
11737 
   (set_attr "latency" "0")
11738 
   (set_attr "length" "4")
11739 
   (set_attr "slot" "cop")
11740 
   (set_attr "slots" "p0_p1")
11741 
   (set_attr "stall" "none")])
11742 
 
11743 
 
11744 
(define_insn "cgen_intrinsic_cpocmpgeu_w_C3"
11745 
  [(set (reg:SI 81)
11746 
        (unspec:SI [
11747 
          (match_operand:DI 0 "general_operand" "x")
11748 
          (match_operand:DI 1 "general_operand" "x")
11749 
        ] 3220))
11750 
   (set (reg:SI 113)
11751 
        (unspec:SI [
11752 
          (match_dup 0)
11753 
          (match_dup 1)
11754 
        ] 3221))]
11755 
  "CGEN_ENABLE_INSN_P (410)"
11756 
  "cpocmpgeu.w\\t%0,%1"
11757 
  [(set_attr "may_trap" "no")
11758 
   (set_attr "latency" "0")
11759 
   (set_attr "length" "4")
11760 
   (set_attr "slot" "cop")
11761 
   (set_attr "slots" "c3")
11762 
   (set_attr "stall" "none")])
11763 
 
11764 
 
11765 
(define_insn "cgen_intrinsic_cpocmpgeu_w_P0_P1"
11766 
  [(unspec_volatile [
11767 
     (match_operand:DI 0 "general_operand" "x")
11768 
     (match_operand:DI 1 "general_operand" "x")
11769 
   ] 3220)]
11770 
  "CGEN_ENABLE_INSN_P (411)"
11771 
  "cpocmpgeu.w\\t%0,%1"
11772 
  [(set_attr "may_trap" "no")
11773 
   (set_attr "latency" "0")
11774 
   (set_attr "length" "4")
11775 
   (set_attr "slot" "cop")
11776 
   (set_attr "slots" "p0_p1")
11777 
   (set_attr "stall" "none")])
11778 
 
11779 
 
11780 
(define_insn "cgen_intrinsic_cpocmpge_h_C3"
11781 
  [(set (reg:SI 81)
11782 
        (unspec:SI [
11783 
          (match_operand:DI 0 "general_operand" "x")
11784 
          (match_operand:DI 1 "general_operand" "x")
11785 
        ] 3222))
11786 
   (set (reg:SI 113)
11787 
        (unspec:SI [
11788 
          (match_dup 0)
11789 
          (match_dup 1)
11790 
        ] 3223))]
11791 
  "CGEN_ENABLE_INSN_P (412)"
11792 
  "cpocmpge.h\\t%0,%1"
11793 
  [(set_attr "may_trap" "no")
11794 
   (set_attr "latency" "0")
11795 
   (set_attr "length" "4")
11796 
   (set_attr "slot" "cop")
11797 
   (set_attr "slots" "c3")
11798 
   (set_attr "stall" "none")])
11799 
 
11800 
 
11801 
(define_insn "cgen_intrinsic_cpocmpge_h_P0_P1"
11802 
  [(unspec_volatile [
11803 
     (match_operand:DI 0 "general_operand" "x")
11804 
     (match_operand:DI 1 "general_operand" "x")
11805 
   ] 3222)]
11806 
  "CGEN_ENABLE_INSN_P (413)"
11807 
  "cpocmpge.h\\t%0,%1"
11808 
  [(set_attr "may_trap" "no")
11809 
   (set_attr "latency" "0")
11810 
   (set_attr "length" "4")
11811 
   (set_attr "slot" "cop")
11812 
   (set_attr "slots" "p0_p1")
11813 
   (set_attr "stall" "none")])
11814 
 
11815 
 
11816 
(define_insn "cgen_intrinsic_cpocmpge_b_C3"
11817 
  [(set (reg:SI 81)
11818 
        (unspec:SI [
11819 
          (match_operand:DI 0 "general_operand" "x")
11820 
          (match_operand:DI 1 "general_operand" "x")
11821 
        ] 3224))
11822 
   (set (reg:SI 113)
11823 
        (unspec:SI [
11824 
          (match_dup 0)
11825 
          (match_dup 1)
11826 
        ] 3225))]
11827 
  "CGEN_ENABLE_INSN_P (414)"
11828 
  "cpocmpge.b\\t%0,%1"
11829 
  [(set_attr "may_trap" "no")
11830 
   (set_attr "latency" "0")
11831 
   (set_attr "length" "4")
11832 
   (set_attr "slot" "cop")
11833 
   (set_attr "slots" "c3")
11834 
   (set_attr "stall" "none")])
11835 
 
11836 
 
11837 
(define_insn "cgen_intrinsic_cpocmpge_b_P0_P1"
11838 
  [(unspec_volatile [
11839 
     (match_operand:DI 0 "general_operand" "x")
11840 
     (match_operand:DI 1 "general_operand" "x")
11841 
   ] 3224)]
11842 
  "CGEN_ENABLE_INSN_P (415)"
11843 
  "cpocmpge.b\\t%0,%1"
11844 
  [(set_attr "may_trap" "no")
11845 
   (set_attr "latency" "0")
11846 
   (set_attr "length" "4")
11847 
   (set_attr "slot" "cop")
11848 
   (set_attr "slots" "p0_p1")
11849 
   (set_attr "stall" "none")])
11850 
 
11851 
 
11852 
(define_insn "cgen_intrinsic_cpocmpgeu_b_C3"
11853 
  [(set (reg:SI 81)
11854 
        (unspec:SI [
11855 
          (match_operand:DI 0 "general_operand" "x")
11856 
          (match_operand:DI 1 "general_operand" "x")
11857 
        ] 3226))
11858 
   (set (reg:SI 113)
11859 
        (unspec:SI [
11860 
          (match_dup 0)
11861 
          (match_dup 1)
11862 
        ] 3227))]
11863 
  "CGEN_ENABLE_INSN_P (416)"
11864 
  "cpocmpgeu.b\\t%0,%1"
11865 
  [(set_attr "may_trap" "no")
11866 
   (set_attr "latency" "0")
11867 
   (set_attr "length" "4")
11868 
   (set_attr "slot" "cop")
11869 
   (set_attr "slots" "c3")
11870 
   (set_attr "stall" "none")])
11871 
 
11872 
 
11873 
(define_insn "cgen_intrinsic_cpocmpgeu_b_P0_P1"
11874 
  [(unspec_volatile [
11875 
     (match_operand:DI 0 "general_operand" "x")
11876 
     (match_operand:DI 1 "general_operand" "x")
11877 
   ] 3226)]
11878 
  "CGEN_ENABLE_INSN_P (417)"
11879 
  "cpocmpgeu.b\\t%0,%1"
11880 
  [(set_attr "may_trap" "no")
11881 
   (set_attr "latency" "0")
11882 
   (set_attr "length" "4")
11883 
   (set_attr "slot" "cop")
11884 
   (set_attr "slots" "p0_p1")
11885 
   (set_attr "stall" "none")])
11886 
 
11887 
 
11888 
(define_insn "cgen_intrinsic_cpocmpgt_w_C3"
11889 
  [(set (reg:SI 81)
11890 
        (unspec:SI [
11891 
          (match_operand:DI 0 "general_operand" "x")
11892 
          (match_operand:DI 1 "general_operand" "x")
11893 
        ] 3228))
11894 
   (set (reg:SI 113)
11895 
        (unspec:SI [
11896 
          (match_dup 0)
11897 
          (match_dup 1)
11898 
        ] 3229))]
11899 
  "CGEN_ENABLE_INSN_P (418)"
11900 
  "cpocmpgt.w\\t%0,%1"
11901 
  [(set_attr "may_trap" "no")
11902 
   (set_attr "latency" "0")
11903 
   (set_attr "length" "4")
11904 
   (set_attr "slot" "cop")
11905 
   (set_attr "slots" "c3")
11906 
   (set_attr "stall" "none")])
11907 
 
11908 
 
11909 
(define_insn "cgen_intrinsic_cpocmpgt_w_P0_P1"
11910 
  [(unspec_volatile [
11911 
     (match_operand:DI 0 "general_operand" "x")
11912 
     (match_operand:DI 1 "general_operand" "x")
11913 
   ] 3228)]
11914 
  "CGEN_ENABLE_INSN_P (419)"
11915 
  "cpocmpgt.w\\t%0,%1"
11916 
  [(set_attr "may_trap" "no")
11917 
   (set_attr "latency" "0")
11918 
   (set_attr "length" "4")
11919 
   (set_attr "slot" "cop")
11920 
   (set_attr "slots" "p0_p1")
11921 
   (set_attr "stall" "none")])
11922 
 
11923 
 
11924 
(define_insn "cgen_intrinsic_cpocmpgtu_w_C3"
11925 
  [(set (reg:SI 81)
11926 
        (unspec:SI [
11927 
          (match_operand:DI 0 "general_operand" "x")
11928 
          (match_operand:DI 1 "general_operand" "x")
11929 
        ] 3230))
11930 
   (set (reg:SI 113)
11931 
        (unspec:SI [
11932 
          (match_dup 0)
11933 
          (match_dup 1)
11934 
        ] 3231))]
11935 
  "CGEN_ENABLE_INSN_P (420)"
11936 
  "cpocmpgtu.w\\t%0,%1"
11937 
  [(set_attr "may_trap" "no")
11938 
   (set_attr "latency" "0")
11939 
   (set_attr "length" "4")
11940 
   (set_attr "slot" "cop")
11941 
   (set_attr "slots" "c3")
11942 
   (set_attr "stall" "none")])
11943 
 
11944 
 
11945 
(define_insn "cgen_intrinsic_cpocmpgtu_w_P0_P1"
11946 
  [(unspec_volatile [
11947 
     (match_operand:DI 0 "general_operand" "x")
11948 
     (match_operand:DI 1 "general_operand" "x")
11949 
   ] 3230)]
11950 
  "CGEN_ENABLE_INSN_P (421)"
11951 
  "cpocmpgtu.w\\t%0,%1"
11952 
  [(set_attr "may_trap" "no")
11953 
   (set_attr "latency" "0")
11954 
   (set_attr "length" "4")
11955 
   (set_attr "slot" "cop")
11956 
   (set_attr "slots" "p0_p1")
11957 
   (set_attr "stall" "none")])
11958 
 
11959 
 
11960 
(define_insn "cgen_intrinsic_cpocmpgt_h_C3"
11961 
  [(set (reg:SI 81)
11962 
        (unspec:SI [
11963 
          (match_operand:DI 0 "general_operand" "x")
11964 
          (match_operand:DI 1 "general_operand" "x")
11965 
        ] 3232))
11966 
   (set (reg:SI 113)
11967 
        (unspec:SI [
11968 
          (match_dup 0)
11969 
          (match_dup 1)
11970 
        ] 3233))]
11971 
  "CGEN_ENABLE_INSN_P (422)"
11972 
  "cpocmpgt.h\\t%0,%1"
11973 
  [(set_attr "may_trap" "no")
11974 
   (set_attr "latency" "0")
11975 
   (set_attr "length" "4")
11976 
   (set_attr "slot" "cop")
11977 
   (set_attr "slots" "c3")
11978 
   (set_attr "stall" "none")])
11979 
 
11980 
 
11981 
(define_insn "cgen_intrinsic_cpocmpgt_h_P0_P1"
11982 
  [(unspec_volatile [
11983 
     (match_operand:DI 0 "general_operand" "x")
11984 
     (match_operand:DI 1 "general_operand" "x")
11985 
   ] 3232)]
11986 
  "CGEN_ENABLE_INSN_P (423)"
11987 
  "cpocmpgt.h\\t%0,%1"
11988 
  [(set_attr "may_trap" "no")
11989 
   (set_attr "latency" "0")
11990 
   (set_attr "length" "4")
11991 
   (set_attr "slot" "cop")
11992 
   (set_attr "slots" "p0_p1")
11993 
   (set_attr "stall" "none")])
11994 
 
11995 
 
11996 
(define_insn "cgen_intrinsic_cpocmpgt_b_C3"
11997 
  [(set (reg:SI 81)
11998 
        (unspec:SI [
11999 
          (match_operand:DI 0 "general_operand" "x")
12000 
          (match_operand:DI 1 "general_operand" "x")
12001 
        ] 3234))
12002 
   (set (reg:SI 113)
12003 
        (unspec:SI [
12004 
          (match_dup 0)
12005 
          (match_dup 1)
12006 
        ] 3235))]
12007 
  "CGEN_ENABLE_INSN_P (424)"
12008 
  "cpocmpgt.b\\t%0,%1"
12009 
  [(set_attr "may_trap" "no")
12010 
   (set_attr "latency" "0")
12011 
   (set_attr "length" "4")
12012 
   (set_attr "slot" "cop")
12013 
   (set_attr "slots" "c3")
12014 
   (set_attr "stall" "none")])
12015 
 
12016 
 
12017 
(define_insn "cgen_intrinsic_cpocmpgt_b_P0_P1"
12018 
  [(unspec_volatile [
12019 
     (match_operand:DI 0 "general_operand" "x")
12020 
     (match_operand:DI 1 "general_operand" "x")
12021 
   ] 3234)]
12022 
  "CGEN_ENABLE_INSN_P (425)"
12023 
  "cpocmpgt.b\\t%0,%1"
12024 
  [(set_attr "may_trap" "no")
12025 
   (set_attr "latency" "0")
12026 
   (set_attr "length" "4")
12027 
   (set_attr "slot" "cop")
12028 
   (set_attr "slots" "p0_p1")
12029 
   (set_attr "stall" "none")])
12030 
 
12031 
 
12032 
(define_insn "cgen_intrinsic_cpocmpgtu_b_C3"
12033 
  [(set (reg:SI 81)
12034 
        (unspec:SI [
12035 
          (match_operand:DI 0 "general_operand" "x")
12036 
          (match_operand:DI 1 "general_operand" "x")
12037 
        ] 3236))
12038 
   (set (reg:SI 113)
12039 
        (unspec:SI [
12040 
          (match_dup 0)
12041 
          (match_dup 1)
12042 
        ] 3237))]
12043 
  "CGEN_ENABLE_INSN_P (426)"
12044 
  "cpocmpgtu.b\\t%0,%1"
12045 
  [(set_attr "may_trap" "no")
12046 
   (set_attr "latency" "0")
12047 
   (set_attr "length" "4")
12048 
   (set_attr "slot" "cop")
12049 
   (set_attr "slots" "c3")
12050 
   (set_attr "stall" "none")])
12051 
 
12052 
 
12053 
(define_insn "cgen_intrinsic_cpocmpgtu_b_P0_P1"
12054 
  [(unspec_volatile [
12055 
     (match_operand:DI 0 "general_operand" "x")
12056 
     (match_operand:DI 1 "general_operand" "x")
12057 
   ] 3236)]
12058 
  "CGEN_ENABLE_INSN_P (427)"
12059 
  "cpocmpgtu.b\\t%0,%1"
12060 
  [(set_attr "may_trap" "no")
12061 
   (set_attr "latency" "0")
12062 
   (set_attr "length" "4")
12063 
   (set_attr "slot" "cop")
12064 
   (set_attr "slots" "p0_p1")
12065 
   (set_attr "stall" "none")])
12066 
 
12067 
 
12068 
(define_insn "cgen_intrinsic_cpocmpne_w_C3"
12069 
  [(set (reg:SI 81)
12070 
        (unspec:SI [
12071 
          (match_operand:DI 0 "general_operand" "x")
12072 
          (match_operand:DI 1 "general_operand" "x")
12073 
        ] 3238))
12074 
   (set (reg:SI 113)
12075 
        (unspec:SI [
12076 
          (match_dup 0)
12077 
          (match_dup 1)
12078 
        ] 3239))]
12079 
  "CGEN_ENABLE_INSN_P (428)"
12080 
  "cpocmpne.w\\t%0,%1"
12081 
  [(set_attr "may_trap" "no")
12082 
   (set_attr "latency" "0")
12083 
   (set_attr "length" "4")
12084 
   (set_attr "slot" "cop")
12085 
   (set_attr "slots" "c3")
12086 
   (set_attr "stall" "none")])
12087 
 
12088 
 
12089 
(define_insn "cgen_intrinsic_cpocmpne_w_P0_P1"
12090 
  [(unspec_volatile [
12091 
     (match_operand:DI 0 "general_operand" "x")
12092 
     (match_operand:DI 1 "general_operand" "x")
12093 
   ] 3238)]
12094 
  "CGEN_ENABLE_INSN_P (429)"
12095 
  "cpocmpne.w\\t%0,%1"
12096 
  [(set_attr "may_trap" "no")
12097 
   (set_attr "latency" "0")
12098 
   (set_attr "length" "4")
12099 
   (set_attr "slot" "cop")
12100 
   (set_attr "slots" "p0_p1")
12101 
   (set_attr "stall" "none")])
12102 
 
12103 
 
12104 
(define_insn "cgen_intrinsic_cpocmpne_h_C3"
12105 
  [(set (reg:SI 81)
12106 
        (unspec:SI [
12107 
          (match_operand:DI 0 "general_operand" "x")
12108 
          (match_operand:DI 1 "general_operand" "x")
12109 
        ] 3240))
12110 
   (set (reg:SI 113)
12111 
        (unspec:SI [
12112 
          (match_dup 0)
12113 
          (match_dup 1)
12114 
        ] 3241))]
12115 
  "CGEN_ENABLE_INSN_P (430)"
12116 
  "cpocmpne.h\\t%0,%1"
12117 
  [(set_attr "may_trap" "no")
12118 
   (set_attr "latency" "0")
12119 
   (set_attr "length" "4")
12120 
   (set_attr "slot" "cop")
12121 
   (set_attr "slots" "c3")
12122 
   (set_attr "stall" "none")])
12123 
 
12124 
 
12125 
(define_insn "cgen_intrinsic_cpocmpne_h_P0_P1"
12126 
  [(unspec_volatile [
12127 
     (match_operand:DI 0 "general_operand" "x")
12128 
     (match_operand:DI 1 "general_operand" "x")
12129 
   ] 3240)]
12130 
  "CGEN_ENABLE_INSN_P (431)"
12131 
  "cpocmpne.h\\t%0,%1"
12132 
  [(set_attr "may_trap" "no")
12133 
   (set_attr "latency" "0")
12134 
   (set_attr "length" "4")
12135 
   (set_attr "slot" "cop")
12136 
   (set_attr "slots" "p0_p1")
12137 
   (set_attr "stall" "none")])
12138 
 
12139 
 
12140 
(define_insn "cgen_intrinsic_cpocmpne_b_C3"
12141 
  [(set (reg:SI 81)
12142 
        (unspec:SI [
12143 
          (match_operand:DI 0 "general_operand" "x")
12144 
          (match_operand:DI 1 "general_operand" "x")
12145 
        ] 3242))
12146 
   (set (reg:SI 113)
12147 
        (unspec:SI [
12148 
          (match_dup 0)
12149 
          (match_dup 1)
12150 
        ] 3243))]
12151 
  "CGEN_ENABLE_INSN_P (432)"
12152 
  "cpocmpne.b\\t%0,%1"
12153 
  [(set_attr "may_trap" "no")
12154 
   (set_attr "latency" "0")
12155 
   (set_attr "length" "4")
12156 
   (set_attr "slot" "cop")
12157 
   (set_attr "slots" "c3")
12158 
   (set_attr "stall" "none")])
12159 
 
12160 
 
12161 
(define_insn "cgen_intrinsic_cpocmpne_b_P0_P1"
12162 
  [(unspec_volatile [
12163 
     (match_operand:DI 0 "general_operand" "x")
12164 
     (match_operand:DI 1 "general_operand" "x")
12165 
   ] 3242)]
12166 
  "CGEN_ENABLE_INSN_P (433)"
12167 
  "cpocmpne.b\\t%0,%1"
12168 
  [(set_attr "may_trap" "no")
12169 
   (set_attr "latency" "0")
12170 
   (set_attr "length" "4")
12171 
   (set_attr "slot" "cop")
12172 
   (set_attr "slots" "p0_p1")
12173 
   (set_attr "stall" "none")])
12174 
 
12175 
 
12176 
(define_insn "cgen_intrinsic_cpocmpeq_w_C3"
12177 
  [(set (reg:SI 81)
12178 
        (unspec:SI [
12179 
          (match_operand:DI 0 "general_operand" "x")
12180 
          (match_operand:DI 1 "general_operand" "x")
12181 
        ] 3244))
12182 
   (set (reg:SI 113)
12183 
        (unspec:SI [
12184 
          (match_dup 0)
12185 
          (match_dup 1)
12186 
        ] 3245))]
12187 
  "CGEN_ENABLE_INSN_P (434)"
12188 
  "cpocmpeq.w\\t%0,%1"
12189 
  [(set_attr "may_trap" "no")
12190 
   (set_attr "latency" "0")
12191 
   (set_attr "length" "4")
12192 
   (set_attr "slot" "cop")
12193 
   (set_attr "slots" "c3")
12194 
   (set_attr "stall" "none")])
12195 
 
12196 
 
12197 
(define_insn "cgen_intrinsic_cpocmpeq_w_P0_P1"
12198 
  [(unspec_volatile [
12199 
     (match_operand:DI 0 "general_operand" "x")
12200 
     (match_operand:DI 1 "general_operand" "x")
12201 
   ] 3244)]
12202 
  "CGEN_ENABLE_INSN_P (435)"
12203 
  "cpocmpeq.w\\t%0,%1"
12204 
  [(set_attr "may_trap" "no")
12205 
   (set_attr "latency" "0")
12206 
   (set_attr "length" "4")
12207 
   (set_attr "slot" "cop")
12208 
   (set_attr "slots" "p0_p1")
12209 
   (set_attr "stall" "none")])
12210 
 
12211 
 
12212 
(define_insn "cgen_intrinsic_cpocmpeq_h_C3"
12213 
  [(set (reg:SI 81)
12214 
        (unspec:SI [
12215 
          (match_operand:DI 0 "general_operand" "x")
12216 
          (match_operand:DI 1 "general_operand" "x")
12217 
        ] 3246))
12218 
   (set (reg:SI 113)
12219 
        (unspec:SI [
12220 
          (match_dup 0)
12221 
          (match_dup 1)
12222 
        ] 3247))]
12223 
  "CGEN_ENABLE_INSN_P (436)"
12224 
  "cpocmpeq.h\\t%0,%1"
12225 
  [(set_attr "may_trap" "no")
12226 
   (set_attr "latency" "0")
12227 
   (set_attr "length" "4")
12228 
   (set_attr "slot" "cop")
12229 
   (set_attr "slots" "c3")
12230 
   (set_attr "stall" "none")])
12231 
 
12232 
 
12233 
(define_insn "cgen_intrinsic_cpocmpeq_h_P0_P1"
12234 
  [(unspec_volatile [
12235 
     (match_operand:DI 0 "general_operand" "x")
12236 
     (match_operand:DI 1 "general_operand" "x")
12237 
   ] 3246)]
12238 
  "CGEN_ENABLE_INSN_P (437)"
12239 
  "cpocmpeq.h\\t%0,%1"
12240 
  [(set_attr "may_trap" "no")
12241 
   (set_attr "latency" "0")
12242 
   (set_attr "length" "4")
12243 
   (set_attr "slot" "cop")
12244 
   (set_attr "slots" "p0_p1")
12245 
   (set_attr "stall" "none")])
12246 
 
12247 
 
12248 
(define_insn "cgen_intrinsic_cpocmpeq_b_C3"
12249 
  [(set (reg:SI 81)
12250 
        (unspec:SI [
12251 
          (match_operand:DI 0 "general_operand" "x")
12252 
          (match_operand:DI 1 "general_operand" "x")
12253 
        ] 3248))
12254 
   (set (reg:SI 113)
12255 
        (unspec:SI [
12256 
          (match_dup 0)
12257 
          (match_dup 1)
12258 
        ] 3249))]
12259 
  "CGEN_ENABLE_INSN_P (438)"
12260 
  "cpocmpeq.b\\t%0,%1"
12261 
  [(set_attr "may_trap" "no")
12262 
   (set_attr "latency" "0")
12263 
   (set_attr "length" "4")
12264 
   (set_attr "slot" "cop")
12265 
   (set_attr "slots" "c3")
12266 
   (set_attr "stall" "none")])
12267 
 
12268 
 
12269 
(define_insn "cgen_intrinsic_cpocmpeq_b_P0_P1"
12270 
  [(unspec_volatile [
12271 
     (match_operand:DI 0 "general_operand" "x")
12272 
     (match_operand:DI 1 "general_operand" "x")
12273 
   ] 3248)]
12274 
  "CGEN_ENABLE_INSN_P (439)"
12275 
  "cpocmpeq.b\\t%0,%1"
12276 
  [(set_attr "may_trap" "no")
12277 
   (set_attr "latency" "0")
12278 
   (set_attr "length" "4")
12279 
   (set_attr "slot" "cop")
12280 
   (set_attr "slots" "p0_p1")
12281 
   (set_attr "stall" "none")])
12282 
 
12283 
 
12284 
(define_insn "cgen_intrinsic_cpacmpge_w_C3"
12285 
  [(set (reg:SI 81)
12286 
        (unspec:SI [
12287 
          (match_operand:DI 0 "general_operand" "x")
12288 
          (match_operand:DI 1 "general_operand" "x")
12289 
        ] 3250))
12290 
   (set (reg:SI 113)
12291 
        (unspec:SI [
12292 
          (match_dup 0)
12293 
          (match_dup 1)
12294 
        ] 3251))]
12295 
  "CGEN_ENABLE_INSN_P (440)"
12296 
  "cpacmpge.w\\t%0,%1"
12297 
  [(set_attr "may_trap" "no")
12298 
   (set_attr "latency" "0")
12299 
   (set_attr "length" "4")
12300 
   (set_attr "slot" "cop")
12301 
   (set_attr "slots" "c3")
12302 
   (set_attr "stall" "none")])
12303 
 
12304 
 
12305 
(define_insn "cgen_intrinsic_cpacmpge_w_P0_P1"
12306 
  [(unspec_volatile [
12307 
     (match_operand:DI 0 "general_operand" "x")
12308 
     (match_operand:DI 1 "general_operand" "x")
12309 
   ] 3250)]
12310 
  "CGEN_ENABLE_INSN_P (441)"
12311 
  "cpacmpge.w\\t%0,%1"
12312 
  [(set_attr "may_trap" "no")
12313 
   (set_attr "latency" "0")
12314 
   (set_attr "length" "4")
12315 
   (set_attr "slot" "cop")
12316 
   (set_attr "slots" "p0_p1")
12317 
   (set_attr "stall" "none")])
12318 
 
12319 
 
12320 
(define_insn "cgen_intrinsic_cpacmpgeu_w_C3"
12321 
  [(set (reg:SI 81)
12322 
        (unspec:SI [
12323 
          (match_operand:DI 0 "general_operand" "x")
12324 
          (match_operand:DI 1 "general_operand" "x")
12325 
        ] 3252))
12326 
   (set (reg:SI 113)
12327 
        (unspec:SI [
12328 
          (match_dup 0)
12329 
          (match_dup 1)
12330 
        ] 3253))]
12331 
  "CGEN_ENABLE_INSN_P (442)"
12332 
  "cpacmpgeu.w\\t%0,%1"
12333 
  [(set_attr "may_trap" "no")
12334 
   (set_attr "latency" "0")
12335 
   (set_attr "length" "4")
12336 
   (set_attr "slot" "cop")
12337 
   (set_attr "slots" "c3")
12338 
   (set_attr "stall" "none")])
12339 
 
12340 
 
12341 
(define_insn "cgen_intrinsic_cpacmpgeu_w_P0_P1"
12342 
  [(unspec_volatile [
12343 
     (match_operand:DI 0 "general_operand" "x")
12344 
     (match_operand:DI 1 "general_operand" "x")
12345 
   ] 3252)]
12346 
  "CGEN_ENABLE_INSN_P (443)"
12347 
  "cpacmpgeu.w\\t%0,%1"
12348 
  [(set_attr "may_trap" "no")
12349 
   (set_attr "latency" "0")
12350 
   (set_attr "length" "4")
12351 
   (set_attr "slot" "cop")
12352 
   (set_attr "slots" "p0_p1")
12353 
   (set_attr "stall" "none")])
12354 
 
12355 
 
12356 
(define_insn "cgen_intrinsic_cpacmpge_h_C3"
12357 
  [(set (reg:SI 81)
12358 
        (unspec:SI [
12359 
          (match_operand:DI 0 "general_operand" "x")
12360 
          (match_operand:DI 1 "general_operand" "x")
12361 
        ] 3254))
12362 
   (set (reg:SI 113)
12363 
        (unspec:SI [
12364 
          (match_dup 0)
12365 
          (match_dup 1)
12366 
        ] 3255))]
12367 
  "CGEN_ENABLE_INSN_P (444)"
12368 
  "cpacmpge.h\\t%0,%1"
12369 
  [(set_attr "may_trap" "no")
12370 
   (set_attr "latency" "0")
12371 
   (set_attr "length" "4")
12372 
   (set_attr "slot" "cop")
12373 
   (set_attr "slots" "c3")
12374 
   (set_attr "stall" "none")])
12375 
 
12376 
 
12377 
(define_insn "cgen_intrinsic_cpacmpge_h_P0_P1"
12378 
  [(unspec_volatile [
12379 
     (match_operand:DI 0 "general_operand" "x")
12380 
     (match_operand:DI 1 "general_operand" "x")
12381 
   ] 3254)]
12382 
  "CGEN_ENABLE_INSN_P (445)"
12383 
  "cpacmpge.h\\t%0,%1"
12384 
  [(set_attr "may_trap" "no")
12385 
   (set_attr "latency" "0")
12386 
   (set_attr "length" "4")
12387 
   (set_attr "slot" "cop")
12388 
   (set_attr "slots" "p0_p1")
12389 
   (set_attr "stall" "none")])
12390 
 
12391 
 
12392 
(define_insn "cgen_intrinsic_cpacmpge_b_C3"
12393 
  [(set (reg:SI 81)
12394 
        (unspec:SI [
12395 
          (match_operand:DI 0 "general_operand" "x")
12396 
          (match_operand:DI 1 "general_operand" "x")
12397 
        ] 3256))
12398 
   (set (reg:SI 113)
12399 
        (unspec:SI [
12400 
          (match_dup 0)
12401 
          (match_dup 1)
12402 
        ] 3257))]
12403 
  "CGEN_ENABLE_INSN_P (446)"
12404 
  "cpacmpge.b\\t%0,%1"
12405 
  [(set_attr "may_trap" "no")
12406 
   (set_attr "latency" "0")
12407 
   (set_attr "length" "4")
12408 
   (set_attr "slot" "cop")
12409 
   (set_attr "slots" "c3")
12410 
   (set_attr "stall" "none")])
12411 
 
12412 
 
12413 
(define_insn "cgen_intrinsic_cpacmpge_b_P0_P1"
12414 
  [(unspec_volatile [
12415 
     (match_operand:DI 0 "general_operand" "x")
12416 
     (match_operand:DI 1 "general_operand" "x")
12417 
   ] 3256)]
12418 
  "CGEN_ENABLE_INSN_P (447)"
12419 
  "cpacmpge.b\\t%0,%1"
12420 
  [(set_attr "may_trap" "no")
12421 
   (set_attr "latency" "0")
12422 
   (set_attr "length" "4")
12423 
   (set_attr "slot" "cop")
12424 
   (set_attr "slots" "p0_p1")
12425 
   (set_attr "stall" "none")])
12426 
 
12427 
 
12428 
(define_insn "cgen_intrinsic_cpacmpgeu_b_C3"
12429 
  [(set (reg:SI 81)
12430 
        (unspec:SI [
12431 
          (match_operand:DI 0 "general_operand" "x")
12432 
          (match_operand:DI 1 "general_operand" "x")
12433 
        ] 3258))
12434 
   (set (reg:SI 113)
12435 
        (unspec:SI [
12436 
          (match_dup 0)
12437 
          (match_dup 1)
12438 
        ] 3259))]
12439 
  "CGEN_ENABLE_INSN_P (448)"
12440 
  "cpacmpgeu.b\\t%0,%1"
12441 
  [(set_attr "may_trap" "no")
12442 
   (set_attr "latency" "0")
12443 
   (set_attr "length" "4")
12444 
   (set_attr "slot" "cop")
12445 
   (set_attr "slots" "c3")
12446 
   (set_attr "stall" "none")])
12447 
 
12448 
 
12449 
(define_insn "cgen_intrinsic_cpacmpgeu_b_P0_P1"
12450 
  [(unspec_volatile [
12451 
     (match_operand:DI 0 "general_operand" "x")
12452 
     (match_operand:DI 1 "general_operand" "x")
12453 
   ] 3258)]
12454 
  "CGEN_ENABLE_INSN_P (449)"
12455 
  "cpacmpgeu.b\\t%0,%1"
12456 
  [(set_attr "may_trap" "no")
12457 
   (set_attr "latency" "0")
12458 
   (set_attr "length" "4")
12459 
   (set_attr "slot" "cop")
12460 
   (set_attr "slots" "p0_p1")
12461 
   (set_attr "stall" "none")])
12462 
 
12463 
 
12464 
(define_insn "cgen_intrinsic_cpacmpgt_w_C3"
12465 
  [(set (reg:SI 81)
12466 
        (unspec:SI [
12467 
          (match_operand:DI 0 "general_operand" "x")
12468 
          (match_operand:DI 1 "general_operand" "x")
12469 
        ] 3260))
12470 
   (set (reg:SI 113)
12471 
        (unspec:SI [
12472 
          (match_dup 0)
12473 
          (match_dup 1)
12474 
        ] 3261))]
12475 
  "CGEN_ENABLE_INSN_P (450)"
12476 
  "cpacmpgt.w\\t%0,%1"
12477 
  [(set_attr "may_trap" "no")
12478 
   (set_attr "latency" "0")
12479 
   (set_attr "length" "4")
12480 
   (set_attr "slot" "cop")
12481 
   (set_attr "slots" "c3")
12482 
   (set_attr "stall" "none")])
12483 
 
12484 
 
12485 
(define_insn "cgen_intrinsic_cpacmpgt_w_P0_P1"
12486 
  [(unspec_volatile [
12487 
     (match_operand:DI 0 "general_operand" "x")
12488 
     (match_operand:DI 1 "general_operand" "x")
12489 
   ] 3260)]
12490 
  "CGEN_ENABLE_INSN_P (451)"
12491 
  "cpacmpgt.w\\t%0,%1"
12492 
  [(set_attr "may_trap" "no")
12493 
   (set_attr "latency" "0")
12494 
   (set_attr "length" "4")
12495 
   (set_attr "slot" "cop")
12496 
   (set_attr "slots" "p0_p1")
12497 
   (set_attr "stall" "none")])
12498 
 
12499 
 
12500 
(define_insn "cgen_intrinsic_cpacmpgtu_w_C3"
12501 
  [(set (reg:SI 81)
12502 
        (unspec:SI [
12503 
          (match_operand:DI 0 "general_operand" "x")
12504 
          (match_operand:DI 1 "general_operand" "x")
12505 
        ] 3262))
12506 
   (set (reg:SI 113)
12507 
        (unspec:SI [
12508 
          (match_dup 0)
12509 
          (match_dup 1)
12510 
        ] 3263))]
12511 
  "CGEN_ENABLE_INSN_P (452)"
12512 
  "cpacmpgtu.w\\t%0,%1"
12513 
  [(set_attr "may_trap" "no")
12514 
   (set_attr "latency" "0")
12515 
   (set_attr "length" "4")
12516 
   (set_attr "slot" "cop")
12517 
   (set_attr "slots" "c3")
12518 
   (set_attr "stall" "none")])
12519 
 
12520 
 
12521 
(define_insn "cgen_intrinsic_cpacmpgtu_w_P0_P1"
12522 
  [(unspec_volatile [
12523 
     (match_operand:DI 0 "general_operand" "x")
12524 
     (match_operand:DI 1 "general_operand" "x")
12525 
   ] 3262)]
12526 
  "CGEN_ENABLE_INSN_P (453)"
12527 
  "cpacmpgtu.w\\t%0,%1"
12528 
  [(set_attr "may_trap" "no")
12529 
   (set_attr "latency" "0")
12530 
   (set_attr "length" "4")
12531 
   (set_attr "slot" "cop")
12532 
   (set_attr "slots" "p0_p1")
12533 
   (set_attr "stall" "none")])
12534 
 
12535 
 
12536 
(define_insn "cgen_intrinsic_cpacmpgt_h_C3"
12537 
  [(set (reg:SI 81)
12538 
        (unspec:SI [
12539 
          (match_operand:DI 0 "general_operand" "x")
12540 
          (match_operand:DI 1 "general_operand" "x")
12541 
        ] 3264))
12542 
   (set (reg:SI 113)
12543 
        (unspec:SI [
12544 
          (match_dup 0)
12545 
          (match_dup 1)
12546 
        ] 3265))]
12547 
  "CGEN_ENABLE_INSN_P (454)"
12548 
  "cpacmpgt.h\\t%0,%1"
12549 
  [(set_attr "may_trap" "no")
12550 
   (set_attr "latency" "0")
12551 
   (set_attr "length" "4")
12552 
   (set_attr "slot" "cop")
12553 
   (set_attr "slots" "c3")
12554 
   (set_attr "stall" "none")])
12555 
 
12556 
 
12557 
(define_insn "cgen_intrinsic_cpacmpgt_h_P0_P1"
12558 
  [(unspec_volatile [
12559 
     (match_operand:DI 0 "general_operand" "x")
12560 
     (match_operand:DI 1 "general_operand" "x")
12561 
   ] 3264)]
12562 
  "CGEN_ENABLE_INSN_P (455)"
12563 
  "cpacmpgt.h\\t%0,%1"
12564 
  [(set_attr "may_trap" "no")
12565 
   (set_attr "latency" "0")
12566 
   (set_attr "length" "4")
12567 
   (set_attr "slot" "cop")
12568 
   (set_attr "slots" "p0_p1")
12569 
   (set_attr "stall" "none")])
12570 
 
12571 
 
12572 
(define_insn "cgen_intrinsic_cpacmpgt_b_C3"
12573 
  [(set (reg:SI 81)
12574 
        (unspec:SI [
12575 
          (match_operand:DI 0 "general_operand" "x")
12576 
          (match_operand:DI 1 "general_operand" "x")
12577 
        ] 3266))
12578 
   (set (reg:SI 113)
12579 
        (unspec:SI [
12580 
          (match_dup 0)
12581 
          (match_dup 1)
12582 
        ] 3267))]
12583 
  "CGEN_ENABLE_INSN_P (456)"
12584 
  "cpacmpgt.b\\t%0,%1"
12585 
  [(set_attr "may_trap" "no")
12586 
   (set_attr "latency" "0")
12587 
   (set_attr "length" "4")
12588 
   (set_attr "slot" "cop")
12589 
   (set_attr "slots" "c3")
12590 
   (set_attr "stall" "none")])
12591 
 
12592 
 
12593 
(define_insn "cgen_intrinsic_cpacmpgt_b_P0_P1"
12594 
  [(unspec_volatile [
12595 
     (match_operand:DI 0 "general_operand" "x")
12596 
     (match_operand:DI 1 "general_operand" "x")
12597 
   ] 3266)]
12598 
  "CGEN_ENABLE_INSN_P (457)"
12599 
  "cpacmpgt.b\\t%0,%1"
12600 
  [(set_attr "may_trap" "no")
12601 
   (set_attr "latency" "0")
12602 
   (set_attr "length" "4")
12603 
   (set_attr "slot" "cop")
12604 
   (set_attr "slots" "p0_p1")
12605 
   (set_attr "stall" "none")])
12606 
 
12607 
 
12608 
(define_insn "cgen_intrinsic_cpacmpgtu_b_C3"
12609 
  [(set (reg:SI 81)
12610 
        (unspec:SI [
12611 
          (match_operand:DI 0 "general_operand" "x")
12612 
          (match_operand:DI 1 "general_operand" "x")
12613 
        ] 3268))
12614 
   (set (reg:SI 113)
12615 
        (unspec:SI [
12616 
          (match_dup 0)
12617 
          (match_dup 1)
12618 
        ] 3269))]
12619 
  "CGEN_ENABLE_INSN_P (458)"
12620 
  "cpacmpgtu.b\\t%0,%1"
12621 
  [(set_attr "may_trap" "no")
12622 
   (set_attr "latency" "0")
12623 
   (set_attr "length" "4")
12624 
   (set_attr "slot" "cop")
12625 
   (set_attr "slots" "c3")
12626 
   (set_attr "stall" "none")])
12627 
 
12628 
 
12629 
(define_insn "cgen_intrinsic_cpacmpgtu_b_P0_P1"
12630 
  [(unspec_volatile [
12631 
     (match_operand:DI 0 "general_operand" "x")
12632 
     (match_operand:DI 1 "general_operand" "x")
12633 
   ] 3268)]
12634 
  "CGEN_ENABLE_INSN_P (459)"
12635 
  "cpacmpgtu.b\\t%0,%1"
12636 
  [(set_attr "may_trap" "no")
12637 
   (set_attr "latency" "0")
12638 
   (set_attr "length" "4")
12639 
   (set_attr "slot" "cop")
12640 
   (set_attr "slots" "p0_p1")
12641 
   (set_attr "stall" "none")])
12642 
 
12643 
 
12644 
(define_insn "cgen_intrinsic_cpacmpne_w_C3"
12645 
  [(set (reg:SI 81)
12646 
        (unspec:SI [
12647 
          (match_operand:DI 0 "general_operand" "x")
12648 
          (match_operand:DI 1 "general_operand" "x")
12649 
        ] 3270))
12650 
   (set (reg:SI 113)
12651 
        (unspec:SI [
12652 
          (match_dup 0)
12653 
          (match_dup 1)
12654 
        ] 3271))]
12655 
  "CGEN_ENABLE_INSN_P (460)"
12656 
  "cpacmpne.w\\t%0,%1"
12657 
  [(set_attr "may_trap" "no")
12658 
   (set_attr "latency" "0")
12659 
   (set_attr "length" "4")
12660 
   (set_attr "slot" "cop")
12661 
   (set_attr "slots" "c3")
12662 
   (set_attr "stall" "none")])
12663 
 
12664 
 
12665 
(define_insn "cgen_intrinsic_cpacmpne_w_P0_P1"
12666 
  [(unspec_volatile [
12667 
     (match_operand:DI 0 "general_operand" "x")
12668 
     (match_operand:DI 1 "general_operand" "x")
12669 
   ] 3270)]
12670 
  "CGEN_ENABLE_INSN_P (461)"
12671 
  "cpacmpne.w\\t%0,%1"
12672 
  [(set_attr "may_trap" "no")
12673 
   (set_attr "latency" "0")
12674 
   (set_attr "length" "4")
12675 
   (set_attr "slot" "cop")
12676 
   (set_attr "slots" "p0_p1")
12677 
   (set_attr "stall" "none")])
12678 
 
12679 
 
12680 
(define_insn "cgen_intrinsic_cpacmpne_h_C3"
12681 
  [(set (reg:SI 81)
12682 
        (unspec:SI [
12683 
          (match_operand:DI 0 "general_operand" "x")
12684 
          (match_operand:DI 1 "general_operand" "x")
12685 
        ] 3272))
12686 
   (set (reg:SI 113)
12687 
        (unspec:SI [
12688 
          (match_dup 0)
12689 
          (match_dup 1)
12690 
        ] 3273))]
12691 
  "CGEN_ENABLE_INSN_P (462)"
12692 
  "cpacmpne.h\\t%0,%1"
12693 
  [(set_attr "may_trap" "no")
12694 
   (set_attr "latency" "0")
12695 
   (set_attr "length" "4")
12696 
   (set_attr "slot" "cop")
12697 
   (set_attr "slots" "c3")
12698 
   (set_attr "stall" "none")])
12699 
 
12700 
 
12701 
(define_insn "cgen_intrinsic_cpacmpne_h_P0_P1"
12702 
  [(unspec_volatile [
12703 
     (match_operand:DI 0 "general_operand" "x")
12704 
     (match_operand:DI 1 "general_operand" "x")
12705 
   ] 3272)]
12706 
  "CGEN_ENABLE_INSN_P (463)"
12707 
  "cpacmpne.h\\t%0,%1"
12708 
  [(set_attr "may_trap" "no")
12709 
   (set_attr "latency" "0")
12710 
   (set_attr "length" "4")
12711 
   (set_attr "slot" "cop")
12712 
   (set_attr "slots" "p0_p1")
12713 
   (set_attr "stall" "none")])
12714 
 
12715 
 
12716 
(define_insn "cgen_intrinsic_cpacmpne_b_C3"
12717 
  [(set (reg:SI 81)
12718 
        (unspec:SI [
12719 
          (match_operand:DI 0 "general_operand" "x")
12720 
          (match_operand:DI 1 "general_operand" "x")
12721 
        ] 3274))
12722 
   (set (reg:SI 113)
12723 
        (unspec:SI [
12724 
          (match_dup 0)
12725 
          (match_dup 1)
12726 
        ] 3275))]
12727 
  "CGEN_ENABLE_INSN_P (464)"
12728 
  "cpacmpne.b\\t%0,%1"
12729 
  [(set_attr "may_trap" "no")
12730 
   (set_attr "latency" "0")
12731 
   (set_attr "length" "4")
12732 
   (set_attr "slot" "cop")
12733 
   (set_attr "slots" "c3")
12734 
   (set_attr "stall" "none")])
12735 
 
12736 
 
12737 
(define_insn "cgen_intrinsic_cpacmpne_b_P0_P1"
12738 
  [(unspec_volatile [
12739 
     (match_operand:DI 0 "general_operand" "x")
12740 
     (match_operand:DI 1 "general_operand" "x")
12741 
   ] 3274)]
12742 
  "CGEN_ENABLE_INSN_P (465)"
12743 
  "cpacmpne.b\\t%0,%1"
12744 
  [(set_attr "may_trap" "no")
12745 
   (set_attr "latency" "0")
12746 
   (set_attr "length" "4")
12747 
   (set_attr "slot" "cop")
12748 
   (set_attr "slots" "p0_p1")
12749 
   (set_attr "stall" "none")])
12750 
 
12751 
 
12752 
(define_insn "cgen_intrinsic_cpacmpeq_w_C3"
12753 
  [(set (reg:SI 81)
12754 
        (unspec:SI [
12755 
          (match_operand:DI 0 "general_operand" "x")
12756 
          (match_operand:DI 1 "general_operand" "x")
12757 
        ] 3276))
12758 
   (set (reg:SI 113)
12759 
        (unspec:SI [
12760 
          (match_dup 0)
12761 
          (match_dup 1)
12762 
        ] 3277))]
12763 
  "CGEN_ENABLE_INSN_P (466)"
12764 
  "cpacmpeq.w\\t%0,%1"
12765 
  [(set_attr "may_trap" "no")
12766 
   (set_attr "latency" "0")
12767 
   (set_attr "length" "4")
12768 
   (set_attr "slot" "cop")
12769 
   (set_attr "slots" "c3")
12770 
   (set_attr "stall" "none")])
12771 
 
12772 
 
12773 
(define_insn "cgen_intrinsic_cpacmpeq_w_P0_P1"
12774 
  [(unspec_volatile [
12775 
     (match_operand:DI 0 "general_operand" "x")
12776 
     (match_operand:DI 1 "general_operand" "x")
12777 
   ] 3276)]
12778 
  "CGEN_ENABLE_INSN_P (467)"
12779 
  "cpacmpeq.w\\t%0,%1"
12780 
  [(set_attr "may_trap" "no")
12781 
   (set_attr "latency" "0")
12782 
   (set_attr "length" "4")
12783 
   (set_attr "slot" "cop")
12784 
   (set_attr "slots" "p0_p1")
12785 
   (set_attr "stall" "none")])
12786 
 
12787 
 
12788 
(define_insn "cgen_intrinsic_cpacmpeq_h_C3"
12789 
  [(set (reg:SI 81)
12790 
        (unspec:SI [
12791 
          (match_operand:DI 0 "general_operand" "x")
12792 
          (match_operand:DI 1 "general_operand" "x")
12793 
        ] 3278))
12794 
   (set (reg:SI 113)
12795 
        (unspec:SI [
12796 
          (match_dup 0)
12797 
          (match_dup 1)
12798 
        ] 3279))]
12799 
  "CGEN_ENABLE_INSN_P (468)"
12800 
  "cpacmpeq.h\\t%0,%1"
12801 
  [(set_attr "may_trap" "no")
12802 
   (set_attr "latency" "0")
12803 
   (set_attr "length" "4")
12804 
   (set_attr "slot" "cop")
12805 
   (set_attr "slots" "c3")
12806 
   (set_attr "stall" "none")])
12807 
 
12808 
 
12809 
(define_insn "cgen_intrinsic_cpacmpeq_h_P0_P1"
12810 
  [(unspec_volatile [
12811 
     (match_operand:DI 0 "general_operand" "x")
12812 
     (match_operand:DI 1 "general_operand" "x")
12813 
   ] 3278)]
12814 
  "CGEN_ENABLE_INSN_P (469)"
12815 
  "cpacmpeq.h\\t%0,%1"
12816 
  [(set_attr "may_trap" "no")
12817 
   (set_attr "latency" "0")
12818 
   (set_attr "length" "4")
12819 
   (set_attr "slot" "cop")
12820 
   (set_attr "slots" "p0_p1")
12821 
   (set_attr "stall" "none")])
12822 
 
12823 
 
12824 
(define_insn "cgen_intrinsic_cpacmpeq_b_C3"
12825 
  [(set (reg:SI 81)
12826 
        (unspec:SI [
12827 
          (match_operand:DI 0 "general_operand" "x")
12828 
          (match_operand:DI 1 "general_operand" "x")
12829 
        ] 3280))
12830 
   (set (reg:SI 113)
12831 
        (unspec:SI [
12832 
          (match_dup 0)
12833 
          (match_dup 1)
12834 
        ] 3281))]
12835 
  "CGEN_ENABLE_INSN_P (470)"
12836 
  "cpacmpeq.b\\t%0,%1"
12837 
  [(set_attr "may_trap" "no")
12838 
   (set_attr "latency" "0")
12839 
   (set_attr "length" "4")
12840 
   (set_attr "slot" "cop")
12841 
   (set_attr "slots" "c3")
12842 
   (set_attr "stall" "none")])
12843 
 
12844 
 
12845 
(define_insn "cgen_intrinsic_cpacmpeq_b_P0_P1"
12846 
  [(unspec_volatile [
12847 
     (match_operand:DI 0 "general_operand" "x")
12848 
     (match_operand:DI 1 "general_operand" "x")
12849 
   ] 3280)]
12850 
  "CGEN_ENABLE_INSN_P (471)"
12851 
  "cpacmpeq.b\\t%0,%1"
12852 
  [(set_attr "may_trap" "no")
12853 
   (set_attr "latency" "0")
12854 
   (set_attr "length" "4")
12855 
   (set_attr "slot" "cop")
12856 
   (set_attr "slots" "p0_p1")
12857 
   (set_attr "stall" "none")])
12858 
 
12859 
 
12860 
(define_insn "cgen_intrinsic_cpfsftbi_C3"
12861 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
12862 
        (unspec:DI [
12863 
          (match_operand:DI 1 "general_operand" "x")
12864 
          (match_operand:DI 2 "general_operand" "x")
12865 
          (match_operand:DI 3 "cgen_h_uint_3a1_immediate" "")
12866 
        ] 3528))]
12867 
  "CGEN_ENABLE_INSN_P (472)"
12868 
  "cpfsftbi\\t%0,%1,%2,%3"
12869 
  [(set_attr "may_trap" "no")
12870 
   (set_attr "latency" "0")
12871 
   (set_attr "length" "4")
12872 
   (set_attr "slot" "cop")
12873 
   (set_attr "slots" "c3")
12874 
   (set_attr "stall" "none")])
12875 
 
12876 
 
12877 
(define_insn "cgen_intrinsic_cpfsftbi_P0_P1"
12878 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
12879 
        (unspec:DI [
12880 
          (match_operand:DI 1 "general_operand" "x")
12881 
          (match_operand:DI 2 "general_operand" "x")
12882 
          (match_operand:DI 3 "cgen_h_uint_3a1_immediate" "")
12883 
        ] 3528))]
12884 
  "CGEN_ENABLE_INSN_P (473)"
12885 
  "cpfsftbi\\t%0,%1,%2,%3"
12886 
  [(set_attr "may_trap" "no")
12887 
   (set_attr "latency" "0")
12888 
   (set_attr "length" "4")
12889 
   (set_attr "slot" "cop")
12890 
   (set_attr "slots" "p0_p1")
12891 
   (set_attr "stall" "none")])
12892 
 
12893 
 
12894 
(define_insn "cgen_intrinsic_cpfacla0s1_h_P0S"
12895 
  [(set (reg:SI 86)
12896 
        (unspec_volatile:SI [
12897 
          (match_operand:DI 0 "general_operand" "x")
12898 
          (match_operand:DI 1 "general_operand" "x")
12899 
        ] 1484))
12900 
   (set (reg:SI 99)
12901 
        (unspec_volatile:SI [
12902 
          (match_dup 0)
12903 
          (match_dup 1)
12904 
        ] 1486))
12905 
   (set (reg:SI 98)
12906 
        (unspec_volatile:SI [
12907 
          (match_dup 0)
12908 
          (match_dup 1)
12909 
        ] 1488))
12910 
   (set (reg:SI 97)
12911 
        (unspec_volatile:SI [
12912 
          (match_dup 0)
12913 
          (match_dup 1)
12914 
        ] 1490))
12915 
   (set (reg:SI 96)
12916 
        (unspec_volatile:SI [
12917 
          (match_dup 0)
12918 
          (match_dup 1)
12919 
        ] 1492))]
12920 
  "CGEN_ENABLE_INSN_P (474)"
12921 
  "cpfacla0s1.h\\t%0,%1"
12922 
  [(set_attr "may_trap" "no")
12923 
   (set_attr "latency" "0")
12924 
   (set_attr "length" "4")
12925 
   (set_attr "slot" "cop")
12926 
   (set_attr "slots" "p0s")
12927 
   (set_attr "stall" "none")])
12928 
 
12929 
 
12930 
(define_insn "cgen_intrinsic_cpfacua0s1_h_P0S"
12931 
  [(set (reg:SI 86)
12932 
        (unspec_volatile:SI [
12933 
          (match_operand:DI 0 "general_operand" "x")
12934 
          (match_operand:DI 1 "general_operand" "x")
12935 
        ] 1494))
12936 
   (set (reg:SI 103)
12937 
        (unspec_volatile:SI [
12938 
          (match_dup 0)
12939 
          (match_dup 1)
12940 
        ] 1496))
12941 
   (set (reg:SI 102)
12942 
        (unspec_volatile:SI [
12943 
          (match_dup 0)
12944 
          (match_dup 1)
12945 
        ] 1498))
12946 
   (set (reg:SI 101)
12947 
        (unspec_volatile:SI [
12948 
          (match_dup 0)
12949 
          (match_dup 1)
12950 
        ] 1500))
12951 
   (set (reg:SI 100)
12952 
        (unspec_volatile:SI [
12953 
          (match_dup 0)
12954 
          (match_dup 1)
12955 
        ] 1502))]
12956 
  "CGEN_ENABLE_INSN_P (475)"
12957 
  "cpfacua0s1.h\\t%0,%1"
12958 
  [(set_attr "may_trap" "no")
12959 
   (set_attr "latency" "0")
12960 
   (set_attr "length" "4")
12961 
   (set_attr "slot" "cop")
12962 
   (set_attr "slots" "p0s")
12963 
   (set_attr "stall" "none")])
12964 
 
12965 
 
12966 
(define_insn "cgen_intrinsic_cpfaca0s1_b_P0S"
12967 
  [(set (reg:SI 86)
12968 
        (unspec_volatile:SI [
12969 
          (match_operand:DI 0 "general_operand" "x")
12970 
          (match_operand:DI 1 "general_operand" "x")
12971 
        ] 1504))
12972 
   (set (reg:SI 103)
12973 
        (unspec_volatile:SI [
12974 
          (match_dup 0)
12975 
          (match_dup 1)
12976 
        ] 1506))
12977 
   (set (reg:SI 102)
12978 
        (unspec_volatile:SI [
12979 
          (match_dup 0)
12980 
          (match_dup 1)
12981 
        ] 1508))
12982 
   (set (reg:SI 101)
12983 
        (unspec_volatile:SI [
12984 
          (match_dup 0)
12985 
          (match_dup 1)
12986 
        ] 1510))
12987 
   (set (reg:SI 100)
12988 
        (unspec_volatile:SI [
12989 
          (match_dup 0)
12990 
          (match_dup 1)
12991 
        ] 1512))
12992 
   (set (reg:SI 99)
12993 
        (unspec_volatile:SI [
12994 
          (match_dup 0)
12995 
          (match_dup 1)
12996 
        ] 1514))
12997 
   (set (reg:SI 98)
12998 
        (unspec_volatile:SI [
12999 
          (match_dup 0)
13000 
          (match_dup 1)
13001 
        ] 1516))
13002 
   (set (reg:SI 97)
13003 
        (unspec_volatile:SI [
13004 
          (match_dup 0)
13005 
          (match_dup 1)
13006 
        ] 1518))
13007 
   (set (reg:SI 96)
13008 
        (unspec_volatile:SI [
13009 
          (match_dup 0)
13010 
          (match_dup 1)
13011 
        ] 1520))]
13012 
  "CGEN_ENABLE_INSN_P (476)"
13013 
  "cpfaca0s1.b\\t%0,%1"
13014 
  [(set_attr "may_trap" "no")
13015 
   (set_attr "latency" "0")
13016 
   (set_attr "length" "4")
13017 
   (set_attr "slot" "cop")
13018 
   (set_attr "slots" "p0s")
13019 
   (set_attr "stall" "none")])
13020 
 
13021 
 
13022 
(define_insn "cgen_intrinsic_cpfaca0s1u_b_P0S"
13023 
  [(set (reg:SI 86)
13024 
        (unspec_volatile:SI [
13025 
          (match_operand:DI 0 "general_operand" "x")
13026 
          (match_operand:DI 1 "general_operand" "x")
13027 
        ] 1522))
13028 
   (set (reg:SI 103)
13029 
        (unspec_volatile:SI [
13030 
          (match_dup 0)
13031 
          (match_dup 1)
13032 
        ] 1524))
13033 
   (set (reg:SI 102)
13034 
        (unspec_volatile:SI [
13035 
          (match_dup 0)
13036 
          (match_dup 1)
13037 
        ] 1526))
13038 
   (set (reg:SI 101)
13039 
        (unspec_volatile:SI [
13040 
          (match_dup 0)
13041 
          (match_dup 1)
13042 
        ] 1528))
13043 
   (set (reg:SI 100)
13044 
        (unspec_volatile:SI [
13045 
          (match_dup 0)
13046 
          (match_dup 1)
13047 
        ] 1530))
13048 
   (set (reg:SI 99)
13049 
        (unspec_volatile:SI [
13050 
          (match_dup 0)
13051 
          (match_dup 1)
13052 
        ] 1532))
13053 
   (set (reg:SI 98)
13054 
        (unspec_volatile:SI [
13055 
          (match_dup 0)
13056 
          (match_dup 1)
13057 
        ] 1534))
13058 
   (set (reg:SI 97)
13059 
        (unspec_volatile:SI [
13060 
          (match_dup 0)
13061 
          (match_dup 1)
13062 
        ] 1536))
13063 
   (set (reg:SI 96)
13064 
        (unspec_volatile:SI [
13065 
          (match_dup 0)
13066 
          (match_dup 1)
13067 
        ] 1538))]
13068 
  "CGEN_ENABLE_INSN_P (477)"
13069 
  "cpfaca0s1u.b\\t%0,%1"
13070 
  [(set_attr "may_trap" "no")
13071 
   (set_attr "latency" "0")
13072 
   (set_attr "length" "4")
13073 
   (set_attr "slot" "cop")
13074 
   (set_attr "slots" "p0s")
13075 
   (set_attr "stall" "none")])
13076 
 
13077 
 
13078 
(define_insn "cgen_intrinsic_cpfsftbla0s1_h_P0S"
13079 
  [(set (reg:SI 99)
13080 
        (unspec_volatile:SI [
13081 
          (match_operand:DI 0 "general_operand" "x")
13082 
          (match_operand:DI 1 "general_operand" "x")
13083 
        ] 1540))
13084 
   (set (reg:SI 98)
13085 
        (unspec_volatile:SI [
13086 
          (match_dup 0)
13087 
          (match_dup 1)
13088 
        ] 1542))
13089 
   (set (reg:SI 97)
13090 
        (unspec_volatile:SI [
13091 
          (match_dup 0)
13092 
          (match_dup 1)
13093 
        ] 1544))
13094 
   (set (reg:SI 96)
13095 
        (unspec_volatile:SI [
13096 
          (match_dup 0)
13097 
          (match_dup 1)
13098 
        ] 1546))]
13099 
  "CGEN_ENABLE_INSN_P (478)"
13100 
  "cpfsftbla0s1.h\\t%0,%1"
13101 
  [(set_attr "may_trap" "no")
13102 
   (set_attr "latency" "0")
13103 
   (set_attr "length" "4")
13104 
   (set_attr "slot" "cop")
13105 
   (set_attr "slots" "p0s")
13106 
   (set_attr "stall" "none")])
13107 
 
13108 
 
13109 
(define_insn "cgen_intrinsic_cpfsftbua0s1_h_P0S"
13110 
  [(set (reg:SI 103)
13111 
        (unspec_volatile:SI [
13112 
          (match_operand:DI 0 "general_operand" "x")
13113 
          (match_operand:DI 1 "general_operand" "x")
13114 
        ] 1548))
13115 
   (set (reg:SI 102)
13116 
        (unspec_volatile:SI [
13117 
          (match_dup 0)
13118 
          (match_dup 1)
13119 
        ] 1550))
13120 
   (set (reg:SI 101)
13121 
        (unspec_volatile:SI [
13122 
          (match_dup 0)
13123 
          (match_dup 1)
13124 
        ] 1552))
13125 
   (set (reg:SI 100)
13126 
        (unspec_volatile:SI [
13127 
          (match_dup 0)
13128 
          (match_dup 1)
13129 
        ] 1554))]
13130 
  "CGEN_ENABLE_INSN_P (479)"
13131 
  "cpfsftbua0s1.h\\t%0,%1"
13132 
  [(set_attr "may_trap" "no")
13133 
   (set_attr "latency" "0")
13134 
   (set_attr "length" "4")
13135 
   (set_attr "slot" "cop")
13136 
   (set_attr "slots" "p0s")
13137 
   (set_attr "stall" "none")])
13138 
 
13139 
 
13140 
(define_insn "cgen_intrinsic_cpfsftba0s1_b_P0S"
13141 
  [(set (reg:SI 103)
13142 
        (unspec_volatile:SI [
13143 
          (match_operand:DI 0 "general_operand" "x")
13144 
          (match_operand:DI 1 "general_operand" "x")
13145 
        ] 1556))
13146 
   (set (reg:SI 102)
13147 
        (unspec_volatile:SI [
13148 
          (match_dup 0)
13149 
          (match_dup 1)
13150 
        ] 1558))
13151 
   (set (reg:SI 101)
13152 
        (unspec_volatile:SI [
13153 
          (match_dup 0)
13154 
          (match_dup 1)
13155 
        ] 1560))
13156 
   (set (reg:SI 100)
13157 
        (unspec_volatile:SI [
13158 
          (match_dup 0)
13159 
          (match_dup 1)
13160 
        ] 1562))
13161 
   (set (reg:SI 99)
13162 
        (unspec_volatile:SI [
13163 
          (match_dup 0)
13164 
          (match_dup 1)
13165 
        ] 1564))
13166 
   (set (reg:SI 98)
13167 
        (unspec_volatile:SI [
13168 
          (match_dup 0)
13169 
          (match_dup 1)
13170 
        ] 1566))
13171 
   (set (reg:SI 97)
13172 
        (unspec_volatile:SI [
13173 
          (match_dup 0)
13174 
          (match_dup 1)
13175 
        ] 1568))
13176 
   (set (reg:SI 96)
13177 
        (unspec_volatile:SI [
13178 
          (match_dup 0)
13179 
          (match_dup 1)
13180 
        ] 1570))]
13181 
  "CGEN_ENABLE_INSN_P (480)"
13182 
  "cpfsftba0s1.b\\t%0,%1"
13183 
  [(set_attr "may_trap" "no")
13184 
   (set_attr "latency" "0")
13185 
   (set_attr "length" "4")
13186 
   (set_attr "slot" "cop")
13187 
   (set_attr "slots" "p0s")
13188 
   (set_attr "stall" "none")])
13189 
 
13190 
 
13191 
(define_insn "cgen_intrinsic_cpfsftba0s1u_b_P0S"
13192 
  [(set (reg:SI 103)
13193 
        (unspec_volatile:SI [
13194 
          (match_operand:DI 0 "general_operand" "x")
13195 
          (match_operand:DI 1 "general_operand" "x")
13196 
        ] 1572))
13197 
   (set (reg:SI 102)
13198 
        (unspec_volatile:SI [
13199 
          (match_dup 0)
13200 
          (match_dup 1)
13201 
        ] 1574))
13202 
   (set (reg:SI 101)
13203 
        (unspec_volatile:SI [
13204 
          (match_dup 0)
13205 
          (match_dup 1)
13206 
        ] 1576))
13207 
   (set (reg:SI 100)
13208 
        (unspec_volatile:SI [
13209 
          (match_dup 0)
13210 
          (match_dup 1)
13211 
        ] 1578))
13212 
   (set (reg:SI 99)
13213 
        (unspec_volatile:SI [
13214 
          (match_dup 0)
13215 
          (match_dup 1)
13216 
        ] 1580))
13217 
   (set (reg:SI 98)
13218 
        (unspec_volatile:SI [
13219 
          (match_dup 0)
13220 
          (match_dup 1)
13221 
        ] 1582))
13222 
   (set (reg:SI 97)
13223 
        (unspec_volatile:SI [
13224 
          (match_dup 0)
13225 
          (match_dup 1)
13226 
        ] 1584))
13227 
   (set (reg:SI 96)
13228 
        (unspec_volatile:SI [
13229 
          (match_dup 0)
13230 
          (match_dup 1)
13231 
        ] 1586))]
13232 
  "CGEN_ENABLE_INSN_P (481)"
13233 
  "cpfsftba0s1u.b\\t%0,%1"
13234 
  [(set_attr "may_trap" "no")
13235 
   (set_attr "latency" "0")
13236 
   (set_attr "length" "4")
13237 
   (set_attr "slot" "cop")
13238 
   (set_attr "slots" "p0s")
13239 
   (set_attr "stall" "none")])
13240 
 
13241 
 
13242 
(define_insn "cgen_intrinsic_cpfacla0s0_h_P0S"
13243 
  [(set (reg:SI 86)
13244 
        (unspec_volatile:SI [
13245 
          (match_operand:DI 0 "general_operand" "x")
13246 
          (match_operand:DI 1 "general_operand" "x")
13247 
        ] 1588))
13248 
   (set (reg:SI 99)
13249 
        (unspec_volatile:SI [
13250 
          (match_dup 0)
13251 
          (match_dup 1)
13252 
        ] 1590))
13253 
   (set (reg:SI 98)
13254 
        (unspec_volatile:SI [
13255 
          (match_dup 0)
13256 
          (match_dup 1)
13257 
        ] 1592))
13258 
   (set (reg:SI 97)
13259 
        (unspec_volatile:SI [
13260 
          (match_dup 0)
13261 
          (match_dup 1)
13262 
        ] 1594))
13263 
   (set (reg:SI 96)
13264 
        (unspec_volatile:SI [
13265 
          (match_dup 0)
13266 
          (match_dup 1)
13267 
        ] 1596))]
13268 
  "CGEN_ENABLE_INSN_P (482)"
13269 
  "cpfacla0s0.h\\t%0,%1"
13270 
  [(set_attr "may_trap" "no")
13271 
   (set_attr "latency" "0")
13272 
   (set_attr "length" "4")
13273 
   (set_attr "slot" "cop")
13274 
   (set_attr "slots" "p0s")
13275 
   (set_attr "stall" "none")])
13276 
 
13277 
 
13278 
(define_insn "cgen_intrinsic_cpfacua0s0_h_P0S"
13279 
  [(set (reg:SI 86)
13280 
        (unspec_volatile:SI [
13281 
          (match_operand:DI 0 "general_operand" "x")
13282 
          (match_operand:DI 1 "general_operand" "x")
13283 
        ] 1598))
13284 
   (set (reg:SI 103)
13285 
        (unspec_volatile:SI [
13286 
          (match_dup 0)
13287 
          (match_dup 1)
13288 
        ] 1600))
13289 
   (set (reg:SI 102)
13290 
        (unspec_volatile:SI [
13291 
          (match_dup 0)
13292 
          (match_dup 1)
13293 
        ] 1602))
13294 
   (set (reg:SI 101)
13295 
        (unspec_volatile:SI [
13296 
          (match_dup 0)
13297 
          (match_dup 1)
13298 
        ] 1604))
13299 
   (set (reg:SI 100)
13300 
        (unspec_volatile:SI [
13301 
          (match_dup 0)
13302 
          (match_dup 1)
13303 
        ] 1606))]
13304 
  "CGEN_ENABLE_INSN_P (483)"
13305 
  "cpfacua0s0.h\\t%0,%1"
13306 
  [(set_attr "may_trap" "no")
13307 
   (set_attr "latency" "0")
13308 
   (set_attr "length" "4")
13309 
   (set_attr "slot" "cop")
13310 
   (set_attr "slots" "p0s")
13311 
   (set_attr "stall" "none")])
13312 
 
13313 
 
13314 
(define_insn "cgen_intrinsic_cpfaca0s0_b_P0S"
13315 
  [(set (reg:SI 86)
13316 
        (unspec_volatile:SI [
13317 
          (match_operand:DI 0 "general_operand" "x")
13318 
          (match_operand:DI 1 "general_operand" "x")
13319 
        ] 1608))
13320 
   (set (reg:SI 103)
13321 
        (unspec_volatile:SI [
13322 
          (match_dup 0)
13323 
          (match_dup 1)
13324 
        ] 1610))
13325 
   (set (reg:SI 102)
13326 
        (unspec_volatile:SI [
13327 
          (match_dup 0)
13328 
          (match_dup 1)
13329 
        ] 1612))
13330 
   (set (reg:SI 101)
13331 
        (unspec_volatile:SI [
13332 
          (match_dup 0)
13333 
          (match_dup 1)
13334 
        ] 1614))
13335 
   (set (reg:SI 100)
13336 
        (unspec_volatile:SI [
13337 
          (match_dup 0)
13338 
          (match_dup 1)
13339 
        ] 1616))
13340 
   (set (reg:SI 99)
13341 
        (unspec_volatile:SI [
13342 
          (match_dup 0)
13343 
          (match_dup 1)
13344 
        ] 1618))
13345 
   (set (reg:SI 98)
13346 
        (unspec_volatile:SI [
13347 
          (match_dup 0)
13348 
          (match_dup 1)
13349 
        ] 1620))
13350 
   (set (reg:SI 97)
13351 
        (unspec_volatile:SI [
13352 
          (match_dup 0)
13353 
          (match_dup 1)
13354 
        ] 1622))
13355 
   (set (reg:SI 96)
13356 
        (unspec_volatile:SI [
13357 
          (match_dup 0)
13358 
          (match_dup 1)
13359 
        ] 1624))]
13360 
  "CGEN_ENABLE_INSN_P (484)"
13361 
  "cpfaca0s0.b\\t%0,%1"
13362 
  [(set_attr "may_trap" "no")
13363 
   (set_attr "latency" "0")
13364 
   (set_attr "length" "4")
13365 
   (set_attr "slot" "cop")
13366 
   (set_attr "slots" "p0s")
13367 
   (set_attr "stall" "none")])
13368 
 
13369 
 
13370 
(define_insn "cgen_intrinsic_cpfaca0s0u_b_P0S"
13371 
  [(set (reg:SI 86)
13372 
        (unspec_volatile:SI [
13373 
          (match_operand:DI 0 "general_operand" "x")
13374 
          (match_operand:DI 1 "general_operand" "x")
13375 
        ] 1626))
13376 
   (set (reg:SI 103)
13377 
        (unspec_volatile:SI [
13378 
          (match_dup 0)
13379 
          (match_dup 1)
13380 
        ] 1628))
13381 
   (set (reg:SI 102)
13382 
        (unspec_volatile:SI [
13383 
          (match_dup 0)
13384 
          (match_dup 1)
13385 
        ] 1630))
13386 
   (set (reg:SI 101)
13387 
        (unspec_volatile:SI [
13388 
          (match_dup 0)
13389 
          (match_dup 1)
13390 
        ] 1632))
13391 
   (set (reg:SI 100)
13392 
        (unspec_volatile:SI [
13393 
          (match_dup 0)
13394 
          (match_dup 1)
13395 
        ] 1634))
13396 
   (set (reg:SI 99)
13397 
        (unspec_volatile:SI [
13398 
          (match_dup 0)
13399 
          (match_dup 1)
13400 
        ] 1636))
13401 
   (set (reg:SI 98)
13402 
        (unspec_volatile:SI [
13403 
          (match_dup 0)
13404 
          (match_dup 1)
13405 
        ] 1638))
13406 
   (set (reg:SI 97)
13407 
        (unspec_volatile:SI [
13408 
          (match_dup 0)
13409 
          (match_dup 1)
13410 
        ] 1640))
13411 
   (set (reg:SI 96)
13412 
        (unspec_volatile:SI [
13413 
          (match_dup 0)
13414 
          (match_dup 1)
13415 
        ] 1642))]
13416 
  "CGEN_ENABLE_INSN_P (485)"
13417 
  "cpfaca0s0u.b\\t%0,%1"
13418 
  [(set_attr "may_trap" "no")
13419 
   (set_attr "latency" "0")
13420 
   (set_attr "length" "4")
13421 
   (set_attr "slot" "cop")
13422 
   (set_attr "slots" "p0s")
13423 
   (set_attr "stall" "none")])
13424 
 
13425 
 
13426 
(define_insn "cgen_intrinsic_cpfsftbla0s0_h_P0S"
13427 
  [(set (reg:SI 99)
13428 
        (unspec_volatile:SI [
13429 
          (match_operand:DI 0 "general_operand" "x")
13430 
          (match_operand:DI 1 "general_operand" "x")
13431 
        ] 1644))
13432 
   (set (reg:SI 98)
13433 
        (unspec_volatile:SI [
13434 
          (match_dup 0)
13435 
          (match_dup 1)
13436 
        ] 1646))
13437 
   (set (reg:SI 97)
13438 
        (unspec_volatile:SI [
13439 
          (match_dup 0)
13440 
          (match_dup 1)
13441 
        ] 1648))
13442 
   (set (reg:SI 96)
13443 
        (unspec_volatile:SI [
13444 
          (match_dup 0)
13445 
          (match_dup 1)
13446 
        ] 1650))]
13447 
  "CGEN_ENABLE_INSN_P (486)"
13448 
  "cpfsftbla0s0.h\\t%0,%1"
13449 
  [(set_attr "may_trap" "no")
13450 
   (set_attr "latency" "0")
13451 
   (set_attr "length" "4")
13452 
   (set_attr "slot" "cop")
13453 
   (set_attr "slots" "p0s")
13454 
   (set_attr "stall" "none")])
13455 
 
13456 
 
13457 
(define_insn "cgen_intrinsic_cpfsftbua0s0_h_P0S"
13458 
  [(set (reg:SI 103)
13459 
        (unspec_volatile:SI [
13460 
          (match_operand:DI 0 "general_operand" "x")
13461 
          (match_operand:DI 1 "general_operand" "x")
13462 
        ] 1652))
13463 
   (set (reg:SI 102)
13464 
        (unspec_volatile:SI [
13465 
          (match_dup 0)
13466 
          (match_dup 1)
13467 
        ] 1654))
13468 
   (set (reg:SI 101)
13469 
        (unspec_volatile:SI [
13470 
          (match_dup 0)
13471 
          (match_dup 1)
13472 
        ] 1656))
13473 
   (set (reg:SI 100)
13474 
        (unspec_volatile:SI [
13475 
          (match_dup 0)
13476 
          (match_dup 1)
13477 
        ] 1658))]
13478 
  "CGEN_ENABLE_INSN_P (487)"
13479 
  "cpfsftbua0s0.h\\t%0,%1"
13480 
  [(set_attr "may_trap" "no")
13481 
   (set_attr "latency" "0")
13482 
   (set_attr "length" "4")
13483 
   (set_attr "slot" "cop")
13484 
   (set_attr "slots" "p0s")
13485 
   (set_attr "stall" "none")])
13486 
 
13487 
 
13488 
(define_insn "cgen_intrinsic_cpfsftba0s0_b_P0S"
13489 
  [(set (reg:SI 103)
13490 
        (unspec_volatile:SI [
13491 
          (match_operand:DI 0 "general_operand" "x")
13492 
          (match_operand:DI 1 "general_operand" "x")
13493 
        ] 1660))
13494 
   (set (reg:SI 102)
13495 
        (unspec_volatile:SI [
13496 
          (match_dup 0)
13497 
          (match_dup 1)
13498 
        ] 1662))
13499 
   (set (reg:SI 101)
13500 
        (unspec_volatile:SI [
13501 
          (match_dup 0)
13502 
          (match_dup 1)
13503 
        ] 1664))
13504 
   (set (reg:SI 100)
13505 
        (unspec_volatile:SI [
13506 
          (match_dup 0)
13507 
          (match_dup 1)
13508 
        ] 1666))
13509 
   (set (reg:SI 99)
13510 
        (unspec_volatile:SI [
13511 
          (match_dup 0)
13512 
          (match_dup 1)
13513 
        ] 1668))
13514 
   (set (reg:SI 98)
13515 
        (unspec_volatile:SI [
13516 
          (match_dup 0)
13517 
          (match_dup 1)
13518 
        ] 1670))
13519 
   (set (reg:SI 97)
13520 
        (unspec_volatile:SI [
13521 
          (match_dup 0)
13522 
          (match_dup 1)
13523 
        ] 1672))
13524 
   (set (reg:SI 96)
13525 
        (unspec_volatile:SI [
13526 
          (match_dup 0)
13527 
          (match_dup 1)
13528 
        ] 1674))]
13529 
  "CGEN_ENABLE_INSN_P (488)"
13530 
  "cpfsftba0s0.b\\t%0,%1"
13531 
  [(set_attr "may_trap" "no")
13532 
   (set_attr "latency" "0")
13533 
   (set_attr "length" "4")
13534 
   (set_attr "slot" "cop")
13535 
   (set_attr "slots" "p0s")
13536 
   (set_attr "stall" "none")])
13537 
 
13538 
 
13539 
(define_insn "cgen_intrinsic_cpfsftba0s0u_b_P0S"
13540 
  [(set (reg:SI 103)
13541 
        (unspec_volatile:SI [
13542 
          (match_operand:DI 0 "general_operand" "x")
13543 
          (match_operand:DI 1 "general_operand" "x")
13544 
        ] 1676))
13545 
   (set (reg:SI 102)
13546 
        (unspec_volatile:SI [
13547 
          (match_dup 0)
13548 
          (match_dup 1)
13549 
        ] 1678))
13550 
   (set (reg:SI 101)
13551 
        (unspec_volatile:SI [
13552 
          (match_dup 0)
13553 
          (match_dup 1)
13554 
        ] 1680))
13555 
   (set (reg:SI 100)
13556 
        (unspec_volatile:SI [
13557 
          (match_dup 0)
13558 
          (match_dup 1)
13559 
        ] 1682))
13560 
   (set (reg:SI 99)
13561 
        (unspec_volatile:SI [
13562 
          (match_dup 0)
13563 
          (match_dup 1)
13564 
        ] 1684))
13565 
   (set (reg:SI 98)
13566 
        (unspec_volatile:SI [
13567 
          (match_dup 0)
13568 
          (match_dup 1)
13569 
        ] 1686))
13570 
   (set (reg:SI 97)
13571 
        (unspec_volatile:SI [
13572 
          (match_dup 0)
13573 
          (match_dup 1)
13574 
        ] 1688))
13575 
   (set (reg:SI 96)
13576 
        (unspec_volatile:SI [
13577 
          (match_dup 0)
13578 
          (match_dup 1)
13579 
        ] 1690))]
13580 
  "CGEN_ENABLE_INSN_P (489)"
13581 
  "cpfsftba0s0u.b\\t%0,%1"
13582 
  [(set_attr "may_trap" "no")
13583 
   (set_attr "latency" "0")
13584 
   (set_attr "length" "4")
13585 
   (set_attr "slot" "cop")
13586 
   (set_attr "slots" "p0s")
13587 
   (set_attr "stall" "none")])
13588 
 
13589 
 
13590 
(define_insn "cgen_intrinsic_cpsllia0_P0S"
13591 
  [(set (reg:SI 103)
13592 
        (unspec_volatile:SI [
13593 
          (match_operand:SI 0 "cgen_h_uint_5a1_immediate" "")
13594 
        ] 1692))
13595 
   (set (reg:SI 102)
13596 
        (unspec_volatile:SI [
13597 
          (match_dup 0)
13598 
        ] 1694))
13599 
   (set (reg:SI 101)
13600 
        (unspec_volatile:SI [
13601 
          (match_dup 0)
13602 
        ] 1696))
13603 
   (set (reg:SI 100)
13604 
        (unspec_volatile:SI [
13605 
          (match_dup 0)
13606 
        ] 1698))
13607 
   (set (reg:SI 99)
13608 
        (unspec_volatile:SI [
13609 
          (match_dup 0)
13610 
        ] 1700))
13611 
   (set (reg:SI 98)
13612 
        (unspec_volatile:SI [
13613 
          (match_dup 0)
13614 
        ] 1702))
13615 
   (set (reg:SI 97)
13616 
        (unspec_volatile:SI [
13617 
          (match_dup 0)
13618 
        ] 1704))
13619 
   (set (reg:SI 96)
13620 
        (unspec_volatile:SI [
13621 
          (match_dup 0)
13622 
        ] 1706))]
13623 
  "CGEN_ENABLE_INSN_P (490)"
13624 
  "cpsllia0\\t%0"
13625 
  [(set_attr "may_trap" "no")
13626 
   (set_attr "latency" "0")
13627 
   (set_attr "length" "4")
13628 
   (set_attr "slot" "cop")
13629 
   (set_attr "slots" "p0s")
13630 
   (set_attr "stall" "none")])
13631 
 
13632 
 
13633 
(define_insn "cgen_intrinsic_cpsraia0_P0S"
13634 
  [(set (reg:SI 103)
13635 
        (unspec_volatile:SI [
13636 
          (match_operand:SI 0 "cgen_h_uint_5a1_immediate" "")
13637 
        ] 1708))
13638 
   (set (reg:SI 102)
13639 
        (unspec_volatile:SI [
13640 
          (match_dup 0)
13641 
        ] 1710))
13642 
   (set (reg:SI 101)
13643 
        (unspec_volatile:SI [
13644 
          (match_dup 0)
13645 
        ] 1712))
13646 
   (set (reg:SI 100)
13647 
        (unspec_volatile:SI [
13648 
          (match_dup 0)
13649 
        ] 1714))
13650 
   (set (reg:SI 99)
13651 
        (unspec_volatile:SI [
13652 
          (match_dup 0)
13653 
        ] 1716))
13654 
   (set (reg:SI 98)
13655 
        (unspec_volatile:SI [
13656 
          (match_dup 0)
13657 
        ] 1718))
13658 
   (set (reg:SI 97)
13659 
        (unspec_volatile:SI [
13660 
          (match_dup 0)
13661 
        ] 1720))
13662 
   (set (reg:SI 96)
13663 
        (unspec_volatile:SI [
13664 
          (match_dup 0)
13665 
        ] 1722))]
13666 
  "CGEN_ENABLE_INSN_P (491)"
13667 
  "cpsraia0\\t%0"
13668 
  [(set_attr "may_trap" "no")
13669 
   (set_attr "latency" "0")
13670 
   (set_attr "length" "4")
13671 
   (set_attr "slot" "cop")
13672 
   (set_attr "slots" "p0s")
13673 
   (set_attr "stall" "none")])
13674 
 
13675 
 
13676 
(define_insn "cgen_intrinsic_cpsrlia0_P0S"
13677 
  [(set (reg:SI 103)
13678 
        (unspec_volatile:SI [
13679 
          (match_operand:SI 0 "cgen_h_uint_5a1_immediate" "")
13680 
        ] 1724))
13681 
   (set (reg:SI 102)
13682 
        (unspec_volatile:SI [
13683 
          (match_dup 0)
13684 
        ] 1726))
13685 
   (set (reg:SI 101)
13686 
        (unspec_volatile:SI [
13687 
          (match_dup 0)
13688 
        ] 1728))
13689 
   (set (reg:SI 100)
13690 
        (unspec_volatile:SI [
13691 
          (match_dup 0)
13692 
        ] 1730))
13693 
   (set (reg:SI 99)
13694 
        (unspec_volatile:SI [
13695 
          (match_dup 0)
13696 
        ] 1732))
13697 
   (set (reg:SI 98)
13698 
        (unspec_volatile:SI [
13699 
          (match_dup 0)
13700 
        ] 1734))
13701 
   (set (reg:SI 97)
13702 
        (unspec_volatile:SI [
13703 
          (match_dup 0)
13704 
        ] 1736))
13705 
   (set (reg:SI 96)
13706 
        (unspec_volatile:SI [
13707 
          (match_dup 0)
13708 
        ] 1738))]
13709 
  "CGEN_ENABLE_INSN_P (492)"
13710 
  "cpsrlia0\\t%0"
13711 
  [(set_attr "may_trap" "no")
13712 
   (set_attr "latency" "0")
13713 
   (set_attr "length" "4")
13714 
   (set_attr "slot" "cop")
13715 
   (set_attr "slots" "p0s")
13716 
   (set_attr "stall" "none")])
13717 
 
13718 
 
13719 
(define_insn "cgen_intrinsic_cpslla0_P0S"
13720 
  [(set (reg:SI 103)
13721 
        (unspec_volatile:SI [
13722 
          (match_operand:DI 0 "general_operand" "x")
13723 
        ] 1740))
13724 
   (set (reg:SI 102)
13725 
        (unspec_volatile:SI [
13726 
          (match_dup 0)
13727 
        ] 1742))
13728 
   (set (reg:SI 101)
13729 
        (unspec_volatile:SI [
13730 
          (match_dup 0)
13731 
        ] 1744))
13732 
   (set (reg:SI 100)
13733 
        (unspec_volatile:SI [
13734 
          (match_dup 0)
13735 
        ] 1746))
13736 
   (set (reg:SI 99)
13737 
        (unspec_volatile:SI [
13738 
          (match_dup 0)
13739 
        ] 1748))
13740 
   (set (reg:SI 98)
13741 
        (unspec_volatile:SI [
13742 
          (match_dup 0)
13743 
        ] 1750))
13744 
   (set (reg:SI 97)
13745 
        (unspec_volatile:SI [
13746 
          (match_dup 0)
13747 
        ] 1752))
13748 
   (set (reg:SI 96)
13749 
        (unspec_volatile:SI [
13750 
          (match_dup 0)
13751 
        ] 1754))]
13752 
  "CGEN_ENABLE_INSN_P (493)"
13753 
  "cpslla0\\t%0"
13754 
  [(set_attr "may_trap" "no")
13755 
   (set_attr "latency" "0")
13756 
   (set_attr "length" "4")
13757 
   (set_attr "slot" "cop")
13758 
   (set_attr "slots" "p0s")
13759 
   (set_attr "stall" "none")])
13760 
 
13761 
 
13762 
(define_insn "cgen_intrinsic_cpsraa0_P0S"
13763 
  [(set (reg:SI 103)
13764 
        (unspec_volatile:SI [
13765 
          (match_operand:DI 0 "general_operand" "x")
13766 
        ] 1756))
13767 
   (set (reg:SI 102)
13768 
        (unspec_volatile:SI [
13769 
          (match_dup 0)
13770 
        ] 1758))
13771 
   (set (reg:SI 101)
13772 
        (unspec_volatile:SI [
13773 
          (match_dup 0)
13774 
        ] 1760))
13775 
   (set (reg:SI 100)
13776 
        (unspec_volatile:SI [
13777 
          (match_dup 0)
13778 
        ] 1762))
13779 
   (set (reg:SI 99)
13780 
        (unspec_volatile:SI [
13781 
          (match_dup 0)
13782 
        ] 1764))
13783 
   (set (reg:SI 98)
13784 
        (unspec_volatile:SI [
13785 
          (match_dup 0)
13786 
        ] 1766))
13787 
   (set (reg:SI 97)
13788 
        (unspec_volatile:SI [
13789 
          (match_dup 0)
13790 
        ] 1768))
13791 
   (set (reg:SI 96)
13792 
        (unspec_volatile:SI [
13793 
          (match_dup 0)
13794 
        ] 1770))]
13795 
  "CGEN_ENABLE_INSN_P (494)"
13796 
  "cpsraa0\\t%0"
13797 
  [(set_attr "may_trap" "no")
13798 
   (set_attr "latency" "0")
13799 
   (set_attr "length" "4")
13800 
   (set_attr "slot" "cop")
13801 
   (set_attr "slots" "p0s")
13802 
   (set_attr "stall" "none")])
13803 
 
13804 
 
13805 
(define_insn "cgen_intrinsic_cpsrla0_P0S"
13806 
  [(set (reg:SI 103)
13807 
        (unspec_volatile:SI [
13808 
          (match_operand:DI 0 "general_operand" "x")
13809 
        ] 1772))
13810 
   (set (reg:SI 102)
13811 
        (unspec_volatile:SI [
13812 
          (match_dup 0)
13813 
        ] 1774))
13814 
   (set (reg:SI 101)
13815 
        (unspec_volatile:SI [
13816 
          (match_dup 0)
13817 
        ] 1776))
13818 
   (set (reg:SI 100)
13819 
        (unspec_volatile:SI [
13820 
          (match_dup 0)
13821 
        ] 1778))
13822 
   (set (reg:SI 99)
13823 
        (unspec_volatile:SI [
13824 
          (match_dup 0)
13825 
        ] 1780))
13826 
   (set (reg:SI 98)
13827 
        (unspec_volatile:SI [
13828 
          (match_dup 0)
13829 
        ] 1782))
13830 
   (set (reg:SI 97)
13831 
        (unspec_volatile:SI [
13832 
          (match_dup 0)
13833 
        ] 1784))
13834 
   (set (reg:SI 96)
13835 
        (unspec_volatile:SI [
13836 
          (match_dup 0)
13837 
        ] 1786))]
13838 
  "CGEN_ENABLE_INSN_P (495)"
13839 
  "cpsrla0\\t%0"
13840 
  [(set_attr "may_trap" "no")
13841 
   (set_attr "latency" "0")
13842 
   (set_attr "length" "4")
13843 
   (set_attr "slot" "cop")
13844 
   (set_attr "slots" "p0s")
13845 
   (set_attr "stall" "none")])
13846 
 
13847 
 
13848 
(define_insn "cgen_intrinsic_cpaccpa0_P0S"
13849 
  [(set (reg:SI 103)
13850 
        (unspec_volatile:SI [
13851 
          (const_int 0)
13852 
        ] 1788))
13853 
   (set (reg:SI 102)
13854 
        (unspec_volatile:SI [
13855 
          (const_int 0)
13856 
        ] 1790))
13857 
   (set (reg:SI 101)
13858 
        (unspec_volatile:SI [
13859 
          (const_int 0)
13860 
        ] 1792))
13861 
   (set (reg:SI 100)
13862 
        (unspec_volatile:SI [
13863 
          (const_int 0)
13864 
        ] 1794))
13865 
   (set (reg:SI 99)
13866 
        (unspec_volatile:SI [
13867 
          (const_int 0)
13868 
        ] 1796))
13869 
   (set (reg:SI 98)
13870 
        (unspec_volatile:SI [
13871 
          (const_int 0)
13872 
        ] 1798))
13873 
   (set (reg:SI 97)
13874 
        (unspec_volatile:SI [
13875 
          (const_int 0)
13876 
        ] 1800))
13877 
   (set (reg:SI 96)
13878 
        (unspec_volatile:SI [
13879 
          (const_int 0)
13880 
        ] 1802))]
13881 
  "CGEN_ENABLE_INSN_P (496)"
13882 
  "cpaccpa0"
13883 
  [(set_attr "may_trap" "no")
13884 
   (set_attr "latency" "0")
13885 
   (set_attr "length" "4")
13886 
   (set_attr "slot" "cop")
13887 
   (set_attr "slots" "p0s")
13888 
   (set_attr "stall" "none")])
13889 
 
13890 
 
13891 
(define_insn "cgen_intrinsic_cpacsuma0_P0S"
13892 
  [(set (reg:SI 86)
13893 
        (unspec_volatile:SI [
13894 
          (const_int 0)
13895 
        ] 1804))
13896 
   (set (reg:SI 103)
13897 
        (unspec_volatile:SI [
13898 
          (const_int 0)
13899 
        ] 1806))
13900 
   (set (reg:SI 102)
13901 
        (unspec_volatile:SI [
13902 
          (const_int 0)
13903 
        ] 1808))
13904 
   (set (reg:SI 101)
13905 
        (unspec_volatile:SI [
13906 
          (const_int 0)
13907 
        ] 1810))
13908 
   (set (reg:SI 100)
13909 
        (unspec_volatile:SI [
13910 
          (const_int 0)
13911 
        ] 1812))
13912 
   (set (reg:SI 99)
13913 
        (unspec_volatile:SI [
13914 
          (const_int 0)
13915 
        ] 1814))
13916 
   (set (reg:SI 98)
13917 
        (unspec_volatile:SI [
13918 
          (const_int 0)
13919 
        ] 1816))
13920 
   (set (reg:SI 97)
13921 
        (unspec_volatile:SI [
13922 
          (const_int 0)
13923 
        ] 1818))
13924 
   (set (reg:SI 96)
13925 
        (unspec_volatile:SI [
13926 
          (const_int 0)
13927 
        ] 1820))]
13928 
  "CGEN_ENABLE_INSN_P (497)"
13929 
  "cpacsuma0"
13930 
  [(set_attr "may_trap" "no")
13931 
   (set_attr "latency" "0")
13932 
   (set_attr "length" "4")
13933 
   (set_attr "slot" "cop")
13934 
   (set_attr "slots" "p0s")
13935 
   (set_attr "stall" "none")])
13936 
 
13937 
 
13938 
(define_insn "cgen_intrinsic_cpmovhla0_w_P0S"
13939 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
13940 
        (unspec_volatile:DI [
13941 
          (const_int 0)
13942 
        ] 1822))]
13943 
  "CGEN_ENABLE_INSN_P (498)"
13944 
  "cpmovhla0.w\\t%0"
13945 
  [(set_attr "may_trap" "no")
13946 
   (set_attr "latency" "0")
13947 
   (set_attr "length" "4")
13948 
   (set_attr "slot" "cop")
13949 
   (set_attr "slots" "p0s")
13950 
   (set_attr "stall" "none")])
13951 
 
13952 
 
13953 
(define_insn "cgen_intrinsic_cpmovhua0_w_P0S"
13954 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
13955 
        (unspec_volatile:DI [
13956 
          (const_int 0)
13957 
        ] 1824))]
13958 
  "CGEN_ENABLE_INSN_P (499)"
13959 
  "cpmovhua0.w\\t%0"
13960 
  [(set_attr "may_trap" "no")
13961 
   (set_attr "latency" "0")
13962 
   (set_attr "length" "4")
13963 
   (set_attr "slot" "cop")
13964 
   (set_attr "slots" "p0s")
13965 
   (set_attr "stall" "none")])
13966 
 
13967 
 
13968 
(define_insn "cgen_intrinsic_cppackla0_w_P0S"
13969 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
13970 
        (unspec_volatile:DI [
13971 
          (const_int 0)
13972 
        ] 1826))]
13973 
  "CGEN_ENABLE_INSN_P (500)"
13974 
  "cppackla0.w\\t%0"
13975 
  [(set_attr "may_trap" "no")
13976 
   (set_attr "latency" "0")
13977 
   (set_attr "length" "4")
13978 
   (set_attr "slot" "cop")
13979 
   (set_attr "slots" "p0s")
13980 
   (set_attr "stall" "none")])
13981 
 
13982 
 
13983 
(define_insn "cgen_intrinsic_cppackua0_w_P0S"
13984 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
13985 
        (unspec_volatile:DI [
13986 
          (const_int 0)
13987 
        ] 1828))]
13988 
  "CGEN_ENABLE_INSN_P (501)"
13989 
  "cppackua0.w\\t%0"
13990 
  [(set_attr "may_trap" "no")
13991 
   (set_attr "latency" "0")
13992 
   (set_attr "length" "4")
13993 
   (set_attr "slot" "cop")
13994 
   (set_attr "slots" "p0s")
13995 
   (set_attr "stall" "none")])
13996 
 
13997 
 
13998 
(define_insn "cgen_intrinsic_cppackla0_h_P0S"
13999 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
14000 
        (unspec_volatile:DI [
14001 
          (const_int 0)
14002 
        ] 1830))]
14003 
  "CGEN_ENABLE_INSN_P (502)"
14004 
  "cppackla0.h\\t%0"
14005 
  [(set_attr "may_trap" "no")
14006 
   (set_attr "latency" "0")
14007 
   (set_attr "length" "4")
14008 
   (set_attr "slot" "cop")
14009 
   (set_attr "slots" "p0s")
14010 
   (set_attr "stall" "none")])
14011 
 
14012 
 
14013 
(define_insn "cgen_intrinsic_cppackua0_h_P0S"
14014 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
14015 
        (unspec_volatile:DI [
14016 
          (const_int 0)
14017 
        ] 1832))]
14018 
  "CGEN_ENABLE_INSN_P (503)"
14019 
  "cppackua0.h\\t%0"
14020 
  [(set_attr "may_trap" "no")
14021 
   (set_attr "latency" "0")
14022 
   (set_attr "length" "4")
14023 
   (set_attr "slot" "cop")
14024 
   (set_attr "slots" "p0s")
14025 
   (set_attr "stall" "none")])
14026 
 
14027 
 
14028 
(define_insn "cgen_intrinsic_cppacka0_b_P0S"
14029 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
14030 
        (unspec_volatile:DI [
14031 
          (const_int 0)
14032 
        ] 1834))]
14033 
  "CGEN_ENABLE_INSN_P (504)"
14034 
  "cppacka0.b\\t%0"
14035 
  [(set_attr "may_trap" "no")
14036 
   (set_attr "latency" "0")
14037 
   (set_attr "length" "4")
14038 
   (set_attr "slot" "cop")
14039 
   (set_attr "slots" "p0s")
14040 
   (set_attr "stall" "none")])
14041 
 
14042 
 
14043 
(define_insn "cgen_intrinsic_cppacka0u_b_P0S"
14044 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
14045 
        (unspec_volatile:DI [
14046 
          (const_int 0)
14047 
        ] 1836))]
14048 
  "CGEN_ENABLE_INSN_P (505)"
14049 
  "cppacka0u.b\\t%0"
14050 
  [(set_attr "may_trap" "no")
14051 
   (set_attr "latency" "0")
14052 
   (set_attr "length" "4")
14053 
   (set_attr "slot" "cop")
14054 
   (set_attr "slots" "p0s")
14055 
   (set_attr "stall" "none")])
14056 
 
14057 
 
14058 
(define_insn "cgen_intrinsic_cpmovlla0_w_P0S"
14059 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
14060 
        (unspec_volatile:DI [
14061 
          (const_int 0)
14062 
        ] 1838))]
14063 
  "CGEN_ENABLE_INSN_P (506)"
14064 
  "cpmovlla0.w\\t%0"
14065 
  [(set_attr "may_trap" "no")
14066 
   (set_attr "latency" "0")
14067 
   (set_attr "length" "4")
14068 
   (set_attr "slot" "cop")
14069 
   (set_attr "slots" "p0s")
14070 
   (set_attr "stall" "none")])
14071 
 
14072 
 
14073 
(define_insn "cgen_intrinsic_cpmovlua0_w_P0S"
14074 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
14075 
        (unspec_volatile:DI [
14076 
          (const_int 0)
14077 
        ] 1840))]
14078 
  "CGEN_ENABLE_INSN_P (507)"
14079 
  "cpmovlua0.w\\t%0"
14080 
  [(set_attr "may_trap" "no")
14081 
   (set_attr "latency" "0")
14082 
   (set_attr "length" "4")
14083 
   (set_attr "slot" "cop")
14084 
   (set_attr "slots" "p0s")
14085 
   (set_attr "stall" "none")])
14086 
 
14087 
 
14088 
(define_insn "cgen_intrinsic_cpmovula0_w_P0S"
14089 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
14090 
        (unspec_volatile:DI [
14091 
          (const_int 0)
14092 
        ] 1842))]
14093 
  "CGEN_ENABLE_INSN_P (508)"
14094 
  "cpmovula0.w\\t%0"
14095 
  [(set_attr "may_trap" "no")
14096 
   (set_attr "latency" "0")
14097 
   (set_attr "length" "4")
14098 
   (set_attr "slot" "cop")
14099 
   (set_attr "slots" "p0s")
14100 
   (set_attr "stall" "none")])
14101 
 
14102 
 
14103 
(define_insn "cgen_intrinsic_cpmovuua0_w_P0S"
14104 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
14105 
        (unspec_volatile:DI [
14106 
          (const_int 0)
14107 
        ] 1844))]
14108 
  "CGEN_ENABLE_INSN_P (509)"
14109 
  "cpmovuua0.w\\t%0"
14110 
  [(set_attr "may_trap" "no")
14111 
   (set_attr "latency" "0")
14112 
   (set_attr "length" "4")
14113 
   (set_attr "slot" "cop")
14114 
   (set_attr "slots" "p0s")
14115 
   (set_attr "stall" "none")])
14116 
 
14117 
 
14118 
(define_insn "cgen_intrinsic_cpmovla0_h_P0S"
14119 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
14120 
        (unspec_volatile:DI [
14121 
          (const_int 0)
14122 
        ] 1846))]
14123 
  "CGEN_ENABLE_INSN_P (510)"
14124 
  "cpmovla0.h\\t%0"
14125 
  [(set_attr "may_trap" "no")
14126 
   (set_attr "latency" "0")
14127 
   (set_attr "length" "4")
14128 
   (set_attr "slot" "cop")
14129 
   (set_attr "slots" "p0s")
14130 
   (set_attr "stall" "none")])
14131 
 
14132 
 
14133 
(define_insn "cgen_intrinsic_cpmovua0_h_P0S"
14134 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
14135 
        (unspec_volatile:DI [
14136 
          (const_int 0)
14137 
        ] 1848))]
14138 
  "CGEN_ENABLE_INSN_P (511)"
14139 
  "cpmovua0.h\\t%0"
14140 
  [(set_attr "may_trap" "no")
14141 
   (set_attr "latency" "0")
14142 
   (set_attr "length" "4")
14143 
   (set_attr "slot" "cop")
14144 
   (set_attr "slots" "p0s")
14145 
   (set_attr "stall" "none")])
14146 
 
14147 
 
14148 
(define_insn "cgen_intrinsic_cpmova0_b_P0S"
14149 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
14150 
        (unspec_volatile:DI [
14151 
          (const_int 0)
14152 
        ] 1850))]
14153 
  "CGEN_ENABLE_INSN_P (512)"
14154 
  "cpmova0.b\\t%0"
14155 
  [(set_attr "may_trap" "no")
14156 
   (set_attr "latency" "0")
14157 
   (set_attr "length" "4")
14158 
   (set_attr "slot" "cop")
14159 
   (set_attr "slots" "p0s")
14160 
   (set_attr "stall" "none")])
14161 
 
14162 
 
14163 
(define_insn "cgen_intrinsic_cpsetla0_w_P0S"
14164 
  [(set (reg:SI 99)
14165 
        (unspec_volatile:SI [
14166 
          (match_operand:DI 0 "general_operand" "x")
14167 
          (match_operand:DI 1 "general_operand" "x")
14168 
        ] 1852))
14169 
   (set (reg:SI 98)
14170 
        (unspec_volatile:SI [
14171 
          (match_dup 0)
14172 
          (match_dup 1)
14173 
        ] 1854))
14174 
   (set (reg:SI 97)
14175 
        (unspec_volatile:SI [
14176 
          (match_dup 0)
14177 
          (match_dup 1)
14178 
        ] 1856))
14179 
   (set (reg:SI 96)
14180 
        (unspec_volatile:SI [
14181 
          (match_dup 0)
14182 
          (match_dup 1)
14183 
        ] 1858))]
14184 
  "CGEN_ENABLE_INSN_P (513)"
14185 
  "cpsetla0.w\\t%0,%1"
14186 
  [(set_attr "may_trap" "no")
14187 
   (set_attr "latency" "0")
14188 
   (set_attr "length" "4")
14189 
   (set_attr "slot" "cop")
14190 
   (set_attr "slots" "p0s")
14191 
   (set_attr "stall" "none")])
14192 
 
14193 
 
14194 
(define_insn "cgen_intrinsic_cpsetua0_w_P0S"
14195 
  [(set (reg:SI 103)
14196 
        (unspec_volatile:SI [
14197 
          (match_operand:DI 0 "general_operand" "x")
14198 
          (match_operand:DI 1 "general_operand" "x")
14199 
        ] 1860))
14200 
   (set (reg:SI 102)
14201 
        (unspec_volatile:SI [
14202 
          (match_dup 0)
14203 
          (match_dup 1)
14204 
        ] 1862))
14205 
   (set (reg:SI 101)
14206 
        (unspec_volatile:SI [
14207 
          (match_dup 0)
14208 
          (match_dup 1)
14209 
        ] 1864))
14210 
   (set (reg:SI 100)
14211 
        (unspec_volatile:SI [
14212 
          (match_dup 0)
14213 
          (match_dup 1)
14214 
        ] 1866))]
14215 
  "CGEN_ENABLE_INSN_P (514)"
14216 
  "cpsetua0.w\\t%0,%1"
14217 
  [(set_attr "may_trap" "no")
14218 
   (set_attr "latency" "0")
14219 
   (set_attr "length" "4")
14220 
   (set_attr "slot" "cop")
14221 
   (set_attr "slots" "p0s")
14222 
   (set_attr "stall" "none")])
14223 
 
14224 
 
14225 
(define_insn "cgen_intrinsic_cpseta0_h_P0S"
14226 
  [(set (reg:SI 103)
14227 
        (unspec_volatile:SI [
14228 
          (match_operand:DI 0 "general_operand" "x")
14229 
          (match_operand:DI 1 "general_operand" "x")
14230 
        ] 1868))
14231 
   (set (reg:SI 102)
14232 
        (unspec_volatile:SI [
14233 
          (match_dup 0)
14234 
          (match_dup 1)
14235 
        ] 1870))
14236 
   (set (reg:SI 101)
14237 
        (unspec_volatile:SI [
14238 
          (match_dup 0)
14239 
          (match_dup 1)
14240 
        ] 1872))
14241 
   (set (reg:SI 100)
14242 
        (unspec_volatile:SI [
14243 
          (match_dup 0)
14244 
          (match_dup 1)
14245 
        ] 1874))
14246 
   (set (reg:SI 99)
14247 
        (unspec_volatile:SI [
14248 
          (match_dup 0)
14249 
          (match_dup 1)
14250 
        ] 1876))
14251 
   (set (reg:SI 98)
14252 
        (unspec_volatile:SI [
14253 
          (match_dup 0)
14254 
          (match_dup 1)
14255 
        ] 1878))
14256 
   (set (reg:SI 97)
14257 
        (unspec_volatile:SI [
14258 
          (match_dup 0)
14259 
          (match_dup 1)
14260 
        ] 1880))
14261 
   (set (reg:SI 96)
14262 
        (unspec_volatile:SI [
14263 
          (match_dup 0)
14264 
          (match_dup 1)
14265 
        ] 1882))]
14266 
  "CGEN_ENABLE_INSN_P (515)"
14267 
  "cpseta0.h\\t%0,%1"
14268 
  [(set_attr "may_trap" "no")
14269 
   (set_attr "latency" "0")
14270 
   (set_attr "length" "4")
14271 
   (set_attr "slot" "cop")
14272 
   (set_attr "slots" "p0s")
14273 
   (set_attr "stall" "none")])
14274 
 
14275 
 
14276 
(define_insn "cgen_intrinsic_cpsadla0_h_P0S"
14277 
  [(set (reg:SI 86)
14278 
        (unspec_volatile:SI [
14279 
          (match_operand:DI 0 "general_operand" "x")
14280 
          (match_operand:DI 1 "general_operand" "x")
14281 
        ] 1884))
14282 
   (set (reg:SI 99)
14283 
        (unspec_volatile:SI [
14284 
          (match_dup 0)
14285 
          (match_dup 1)
14286 
        ] 1886))
14287 
   (set (reg:SI 98)
14288 
        (unspec_volatile:SI [
14289 
          (match_dup 0)
14290 
          (match_dup 1)
14291 
        ] 1888))
14292 
   (set (reg:SI 97)
14293 
        (unspec_volatile:SI [
14294 
          (match_dup 0)
14295 
          (match_dup 1)
14296 
        ] 1890))
14297 
   (set (reg:SI 96)
14298 
        (unspec_volatile:SI [
14299 
          (match_dup 0)
14300 
          (match_dup 1)
14301 
        ] 1892))]
14302 
  "CGEN_ENABLE_INSN_P (516)"
14303 
  "cpsadla0.h\\t%0,%1"
14304 
  [(set_attr "may_trap" "no")
14305 
   (set_attr "latency" "0")
14306 
   (set_attr "length" "4")
14307 
   (set_attr "slot" "cop")
14308 
   (set_attr "slots" "p0s")
14309 
   (set_attr "stall" "none")])
14310 
 
14311 
 
14312 
(define_insn "cgen_intrinsic_cpsadua0_h_P0S"
14313 
  [(set (reg:SI 86)
14314 
        (unspec_volatile:SI [
14315 
          (match_operand:DI 0 "general_operand" "x")
14316 
          (match_operand:DI 1 "general_operand" "x")
14317 
        ] 1894))
14318 
   (set (reg:SI 103)
14319 
        (unspec_volatile:SI [
14320 
          (match_dup 0)
14321 
          (match_dup 1)
14322 
        ] 1896))
14323 
   (set (reg:SI 102)
14324 
        (unspec_volatile:SI [
14325 
          (match_dup 0)
14326 
          (match_dup 1)
14327 
        ] 1898))
14328 
   (set (reg:SI 101)
14329 
        (unspec_volatile:SI [
14330 
          (match_dup 0)
14331 
          (match_dup 1)
14332 
        ] 1900))
14333 
   (set (reg:SI 100)
14334 
        (unspec_volatile:SI [
14335 
          (match_dup 0)
14336 
          (match_dup 1)
14337 
        ] 1902))]
14338 
  "CGEN_ENABLE_INSN_P (517)"
14339 
  "cpsadua0.h\\t%0,%1"
14340 
  [(set_attr "may_trap" "no")
14341 
   (set_attr "latency" "0")
14342 
   (set_attr "length" "4")
14343 
   (set_attr "slot" "cop")
14344 
   (set_attr "slots" "p0s")
14345 
   (set_attr "stall" "none")])
14346 
 
14347 
 
14348 
(define_insn "cgen_intrinsic_cpsada0_b_P0S"
14349 
  [(set (reg:SI 86)
14350 
        (unspec_volatile:SI [
14351 
          (match_operand:DI 0 "general_operand" "x")
14352 
          (match_operand:DI 1 "general_operand" "x")
14353 
        ] 1904))
14354 
   (set (reg:SI 103)
14355 
        (unspec_volatile:SI [
14356 
          (match_dup 0)
14357 
          (match_dup 1)
14358 
        ] 1906))
14359 
   (set (reg:SI 102)
14360 
        (unspec_volatile:SI [
14361 
          (match_dup 0)
14362 
          (match_dup 1)
14363 
        ] 1908))
14364 
   (set (reg:SI 101)
14365 
        (unspec_volatile:SI [
14366 
          (match_dup 0)
14367 
          (match_dup 1)
14368 
        ] 1910))
14369 
   (set (reg:SI 100)
14370 
        (unspec_volatile:SI [
14371 
          (match_dup 0)
14372 
          (match_dup 1)
14373 
        ] 1912))
14374 
   (set (reg:SI 99)
14375 
        (unspec_volatile:SI [
14376 
          (match_dup 0)
14377 
          (match_dup 1)
14378 
        ] 1914))
14379 
   (set (reg:SI 98)
14380 
        (unspec_volatile:SI [
14381 
          (match_dup 0)
14382 
          (match_dup 1)
14383 
        ] 1916))
14384 
   (set (reg:SI 97)
14385 
        (unspec_volatile:SI [
14386 
          (match_dup 0)
14387 
          (match_dup 1)
14388 
        ] 1918))
14389 
   (set (reg:SI 96)
14390 
        (unspec_volatile:SI [
14391 
          (match_dup 0)
14392 
          (match_dup 1)
14393 
        ] 1920))]
14394 
  "CGEN_ENABLE_INSN_P (518)"
14395 
  "cpsada0.b\\t%0,%1"
14396 
  [(set_attr "may_trap" "no")
14397 
   (set_attr "latency" "0")
14398 
   (set_attr "length" "4")
14399 
   (set_attr "slot" "cop")
14400 
   (set_attr "slots" "p0s")
14401 
   (set_attr "stall" "none")])
14402 
 
14403 
 
14404 
(define_insn "cgen_intrinsic_cpsada0u_b_P0S"
14405 
  [(set (reg:SI 86)
14406 
        (unspec_volatile:SI [
14407 
          (match_operand:DI 0 "general_operand" "x")
14408 
          (match_operand:DI 1 "general_operand" "x")
14409 
        ] 1922))
14410 
   (set (reg:SI 103)
14411 
        (unspec_volatile:SI [
14412 
          (match_dup 0)
14413 
          (match_dup 1)
14414 
        ] 1924))
14415 
   (set (reg:SI 102)
14416 
        (unspec_volatile:SI [
14417 
          (match_dup 0)
14418 
          (match_dup 1)
14419 
        ] 1926))
14420 
   (set (reg:SI 101)
14421 
        (unspec_volatile:SI [
14422 
          (match_dup 0)
14423 
          (match_dup 1)
14424 
        ] 1928))
14425 
   (set (reg:SI 100)
14426 
        (unspec_volatile:SI [
14427 
          (match_dup 0)
14428 
          (match_dup 1)
14429 
        ] 1930))
14430 
   (set (reg:SI 99)
14431 
        (unspec_volatile:SI [
14432 
          (match_dup 0)
14433 
          (match_dup 1)
14434 
        ] 1932))
14435 
   (set (reg:SI 98)
14436 
        (unspec_volatile:SI [
14437 
          (match_dup 0)
14438 
          (match_dup 1)
14439 
        ] 1934))
14440 
   (set (reg:SI 97)
14441 
        (unspec_volatile:SI [
14442 
          (match_dup 0)
14443 
          (match_dup 1)
14444 
        ] 1936))
14445 
   (set (reg:SI 96)
14446 
        (unspec_volatile:SI [
14447 
          (match_dup 0)
14448 
          (match_dup 1)
14449 
        ] 1938))]
14450 
  "CGEN_ENABLE_INSN_P (519)"
14451 
  "cpsada0u.b\\t%0,%1"
14452 
  [(set_attr "may_trap" "no")
14453 
   (set_attr "latency" "0")
14454 
   (set_attr "length" "4")
14455 
   (set_attr "slot" "cop")
14456 
   (set_attr "slots" "p0s")
14457 
   (set_attr "stall" "none")])
14458 
 
14459 
 
14460 
(define_insn "cgen_intrinsic_cpabsla0_h_P0S"
14461 
  [(set (reg:SI 99)
14462 
        (unspec_volatile:SI [
14463 
          (match_operand:DI 0 "general_operand" "x")
14464 
          (match_operand:DI 1 "general_operand" "x")
14465 
        ] 1940))
14466 
   (set (reg:SI 98)
14467 
        (unspec_volatile:SI [
14468 
          (match_dup 0)
14469 
          (match_dup 1)
14470 
        ] 1942))
14471 
   (set (reg:SI 97)
14472 
        (unspec_volatile:SI [
14473 
          (match_dup 0)
14474 
          (match_dup 1)
14475 
        ] 1944))
14476 
   (set (reg:SI 96)
14477 
        (unspec_volatile:SI [
14478 
          (match_dup 0)
14479 
          (match_dup 1)
14480 
        ] 1946))]
14481 
  "CGEN_ENABLE_INSN_P (520)"
14482 
  "cpabsla0.h\\t%0,%1"
14483 
  [(set_attr "may_trap" "no")
14484 
   (set_attr "latency" "0")
14485 
   (set_attr "length" "4")
14486 
   (set_attr "slot" "cop")
14487 
   (set_attr "slots" "p0s")
14488 
   (set_attr "stall" "none")])
14489 
 
14490 
 
14491 
(define_insn "cgen_intrinsic_cpabsua0_h_P0S"
14492 
  [(set (reg:SI 103)
14493 
        (unspec_volatile:SI [
14494 
          (match_operand:DI 0 "general_operand" "x")
14495 
          (match_operand:DI 1 "general_operand" "x")
14496 
        ] 1948))
14497 
   (set (reg:SI 102)
14498 
        (unspec_volatile:SI [
14499 
          (match_dup 0)
14500 
          (match_dup 1)
14501 
        ] 1950))
14502 
   (set (reg:SI 101)
14503 
        (unspec_volatile:SI [
14504 
          (match_dup 0)
14505 
          (match_dup 1)
14506 
        ] 1952))
14507 
   (set (reg:SI 100)
14508 
        (unspec_volatile:SI [
14509 
          (match_dup 0)
14510 
          (match_dup 1)
14511 
        ] 1954))]
14512 
  "CGEN_ENABLE_INSN_P (521)"
14513 
  "cpabsua0.h\\t%0,%1"
14514 
  [(set_attr "may_trap" "no")
14515 
   (set_attr "latency" "0")
14516 
   (set_attr "length" "4")
14517 
   (set_attr "slot" "cop")
14518 
   (set_attr "slots" "p0s")
14519 
   (set_attr "stall" "none")])
14520 
 
14521 
 
14522 
(define_insn "cgen_intrinsic_cpabsa0_b_P0S"
14523 
  [(set (reg:SI 103)
14524 
        (unspec_volatile:SI [
14525 
          (match_operand:DI 0 "general_operand" "x")
14526 
          (match_operand:DI 1 "general_operand" "x")
14527 
        ] 1956))
14528 
   (set (reg:SI 102)
14529 
        (unspec_volatile:SI [
14530 
          (match_dup 0)
14531 
          (match_dup 1)
14532 
        ] 1958))
14533 
   (set (reg:SI 101)
14534 
        (unspec_volatile:SI [
14535 
          (match_dup 0)
14536 
          (match_dup 1)
14537 
        ] 1960))
14538 
   (set (reg:SI 100)
14539 
        (unspec_volatile:SI [
14540 
          (match_dup 0)
14541 
          (match_dup 1)
14542 
        ] 1962))
14543 
   (set (reg:SI 99)
14544 
        (unspec_volatile:SI [
14545 
          (match_dup 0)
14546 
          (match_dup 1)
14547 
        ] 1964))
14548 
   (set (reg:SI 98)
14549 
        (unspec_volatile:SI [
14550 
          (match_dup 0)
14551 
          (match_dup 1)
14552 
        ] 1966))
14553 
   (set (reg:SI 97)
14554 
        (unspec_volatile:SI [
14555 
          (match_dup 0)
14556 
          (match_dup 1)
14557 
        ] 1968))
14558 
   (set (reg:SI 96)
14559 
        (unspec_volatile:SI [
14560 
          (match_dup 0)
14561 
          (match_dup 1)
14562 
        ] 1970))]
14563 
  "CGEN_ENABLE_INSN_P (522)"
14564 
  "cpabsa0.b\\t%0,%1"
14565 
  [(set_attr "may_trap" "no")
14566 
   (set_attr "latency" "0")
14567 
   (set_attr "length" "4")
14568 
   (set_attr "slot" "cop")
14569 
   (set_attr "slots" "p0s")
14570 
   (set_attr "stall" "none")])
14571 
 
14572 
 
14573 
(define_insn "cgen_intrinsic_cpabsa0u_b_P0S"
14574 
  [(set (reg:SI 103)
14575 
        (unspec_volatile:SI [
14576 
          (match_operand:DI 0 "general_operand" "x")
14577 
          (match_operand:DI 1 "general_operand" "x")
14578 
        ] 1972))
14579 
   (set (reg:SI 102)
14580 
        (unspec_volatile:SI [
14581 
          (match_dup 0)
14582 
          (match_dup 1)
14583 
        ] 1974))
14584 
   (set (reg:SI 101)
14585 
        (unspec_volatile:SI [
14586 
          (match_dup 0)
14587 
          (match_dup 1)
14588 
        ] 1976))
14589 
   (set (reg:SI 100)
14590 
        (unspec_volatile:SI [
14591 
          (match_dup 0)
14592 
          (match_dup 1)
14593 
        ] 1978))
14594 
   (set (reg:SI 99)
14595 
        (unspec_volatile:SI [
14596 
          (match_dup 0)
14597 
          (match_dup 1)
14598 
        ] 1980))
14599 
   (set (reg:SI 98)
14600 
        (unspec_volatile:SI [
14601 
          (match_dup 0)
14602 
          (match_dup 1)
14603 
        ] 1982))
14604 
   (set (reg:SI 97)
14605 
        (unspec_volatile:SI [
14606 
          (match_dup 0)
14607 
          (match_dup 1)
14608 
        ] 1984))
14609 
   (set (reg:SI 96)
14610 
        (unspec_volatile:SI [
14611 
          (match_dup 0)
14612 
          (match_dup 1)
14613 
        ] 1986))]
14614 
  "CGEN_ENABLE_INSN_P (523)"
14615 
  "cpabsa0u.b\\t%0,%1"
14616 
  [(set_attr "may_trap" "no")
14617 
   (set_attr "latency" "0")
14618 
   (set_attr "length" "4")
14619 
   (set_attr "slot" "cop")
14620 
   (set_attr "slots" "p0s")
14621 
   (set_attr "stall" "none")])
14622 
 
14623 
 
14624 
(define_insn "cgen_intrinsic_cpsubacla0_h_P0S"
14625 
  [(set (reg:SI 86)
14626 
        (unspec_volatile:SI [
14627 
          (match_operand:DI 0 "general_operand" "x")
14628 
          (match_operand:DI 1 "general_operand" "x")
14629 
        ] 1988))
14630 
   (set (reg:SI 99)
14631 
        (unspec_volatile:SI [
14632 
          (match_dup 0)
14633 
          (match_dup 1)
14634 
        ] 1990))
14635 
   (set (reg:SI 98)
14636 
        (unspec_volatile:SI [
14637 
          (match_dup 0)
14638 
          (match_dup 1)
14639 
        ] 1992))
14640 
   (set (reg:SI 97)
14641 
        (unspec_volatile:SI [
14642 
          (match_dup 0)
14643 
          (match_dup 1)
14644 
        ] 1994))
14645 
   (set (reg:SI 96)
14646 
        (unspec_volatile:SI [
14647 
          (match_dup 0)
14648 
          (match_dup 1)
14649 
        ] 1996))]
14650 
  "CGEN_ENABLE_INSN_P (524)"
14651 
  "cpsubacla0.h\\t%0,%1"
14652 
  [(set_attr "may_trap" "no")
14653 
   (set_attr "latency" "0")
14654 
   (set_attr "length" "4")
14655 
   (set_attr "slot" "cop")
14656 
   (set_attr "slots" "p0s")
14657 
   (set_attr "stall" "none")])
14658 
 
14659 
 
14660 
(define_insn "cgen_intrinsic_cpsubacua0_h_P0S"
14661 
  [(set (reg:SI 86)
14662 
        (unspec_volatile:SI [
14663 
          (match_operand:DI 0 "general_operand" "x")
14664 
          (match_operand:DI 1 "general_operand" "x")
14665 
        ] 1998))
14666 
   (set (reg:SI 103)
14667 
        (unspec_volatile:SI [
14668 
          (match_dup 0)
14669 
          (match_dup 1)
14670 
        ] 2000))
14671 
   (set (reg:SI 102)
14672 
        (unspec_volatile:SI [
14673 
          (match_dup 0)
14674 
          (match_dup 1)
14675 
        ] 2002))
14676 
   (set (reg:SI 101)
14677 
        (unspec_volatile:SI [
14678 
          (match_dup 0)
14679 
          (match_dup 1)
14680 
        ] 2004))
14681 
   (set (reg:SI 100)
14682 
        (unspec_volatile:SI [
14683 
          (match_dup 0)
14684 
          (match_dup 1)
14685 
        ] 2006))]
14686 
  "CGEN_ENABLE_INSN_P (525)"
14687 
  "cpsubacua0.h\\t%0,%1"
14688 
  [(set_attr "may_trap" "no")
14689 
   (set_attr "latency" "0")
14690 
   (set_attr "length" "4")
14691 
   (set_attr "slot" "cop")
14692 
   (set_attr "slots" "p0s")
14693 
   (set_attr "stall" "none")])
14694 
 
14695 
 
14696 
(define_insn "cgen_intrinsic_cpsubaca0_b_P0S"
14697 
  [(set (reg:SI 86)
14698 
        (unspec_volatile:SI [
14699 
          (match_operand:DI 0 "general_operand" "x")
14700 
          (match_operand:DI 1 "general_operand" "x")
14701 
        ] 2008))
14702 
   (set (reg:SI 103)
14703 
        (unspec_volatile:SI [
14704 
          (match_dup 0)
14705 
          (match_dup 1)
14706 
        ] 2010))
14707 
   (set (reg:SI 102)
14708 
        (unspec_volatile:SI [
14709 
          (match_dup 0)
14710 
          (match_dup 1)
14711 
        ] 2012))
14712 
   (set (reg:SI 101)
14713 
        (unspec_volatile:SI [
14714 
          (match_dup 0)
14715 
          (match_dup 1)
14716 
        ] 2014))
14717 
   (set (reg:SI 100)
14718 
        (unspec_volatile:SI [
14719 
          (match_dup 0)
14720 
          (match_dup 1)
14721 
        ] 2016))
14722 
   (set (reg:SI 99)
14723 
        (unspec_volatile:SI [
14724 
          (match_dup 0)
14725 
          (match_dup 1)
14726 
        ] 2018))
14727 
   (set (reg:SI 98)
14728 
        (unspec_volatile:SI [
14729 
          (match_dup 0)
14730 
          (match_dup 1)
14731 
        ] 2020))
14732 
   (set (reg:SI 97)
14733 
        (unspec_volatile:SI [
14734 
          (match_dup 0)
14735 
          (match_dup 1)
14736 
        ] 2022))
14737 
   (set (reg:SI 96)
14738 
        (unspec_volatile:SI [
14739 
          (match_dup 0)
14740 
          (match_dup 1)
14741 
        ] 2024))]
14742 
  "CGEN_ENABLE_INSN_P (526)"
14743 
  "cpsubaca0.b\\t%0,%1"
14744 
  [(set_attr "may_trap" "no")
14745 
   (set_attr "latency" "0")
14746 
   (set_attr "length" "4")
14747 
   (set_attr "slot" "cop")
14748 
   (set_attr "slots" "p0s")
14749 
   (set_attr "stall" "none")])
14750 
 
14751 
 
14752 
(define_insn "cgen_intrinsic_cpsubaca0u_b_P0S"
14753 
  [(set (reg:SI 86)
14754 
        (unspec_volatile:SI [
14755 
          (match_operand:DI 0 "general_operand" "x")
14756 
          (match_operand:DI 1 "general_operand" "x")
14757 
        ] 2026))
14758 
   (set (reg:SI 103)
14759 
        (unspec_volatile:SI [
14760 
          (match_dup 0)
14761 
          (match_dup 1)
14762 
        ] 2028))
14763 
   (set (reg:SI 102)
14764 
        (unspec_volatile:SI [
14765 
          (match_dup 0)
14766 
          (match_dup 1)
14767 
        ] 2030))
14768 
   (set (reg:SI 101)
14769 
        (unspec_volatile:SI [
14770 
          (match_dup 0)
14771 
          (match_dup 1)
14772 
        ] 2032))
14773 
   (set (reg:SI 100)
14774 
        (unspec_volatile:SI [
14775 
          (match_dup 0)
14776 
          (match_dup 1)
14777 
        ] 2034))
14778 
   (set (reg:SI 99)
14779 
        (unspec_volatile:SI [
14780 
          (match_dup 0)
14781 
          (match_dup 1)
14782 
        ] 2036))
14783 
   (set (reg:SI 98)
14784 
        (unspec_volatile:SI [
14785 
          (match_dup 0)
14786 
          (match_dup 1)
14787 
        ] 2038))
14788 
   (set (reg:SI 97)
14789 
        (unspec_volatile:SI [
14790 
          (match_dup 0)
14791 
          (match_dup 1)
14792 
        ] 2040))
14793 
   (set (reg:SI 96)
14794 
        (unspec_volatile:SI [
14795 
          (match_dup 0)
14796 
          (match_dup 1)
14797 
        ] 2042))]
14798 
  "CGEN_ENABLE_INSN_P (527)"
14799 
  "cpsubaca0u.b\\t%0,%1"
14800 
  [(set_attr "may_trap" "no")
14801 
   (set_attr "latency" "0")
14802 
   (set_attr "length" "4")
14803 
   (set_attr "slot" "cop")
14804 
   (set_attr "slots" "p0s")
14805 
   (set_attr "stall" "none")])
14806 
 
14807 
 
14808 
(define_insn "cgen_intrinsic_cpsubla0_h_P0S"
14809 
  [(set (reg:SI 99)
14810 
        (unspec_volatile:SI [
14811 
          (match_operand:DI 0 "general_operand" "x")
14812 
          (match_operand:DI 1 "general_operand" "x")
14813 
        ] 2044))
14814 
   (set (reg:SI 98)
14815 
        (unspec_volatile:SI [
14816 
          (match_dup 0)
14817 
          (match_dup 1)
14818 
        ] 2046))
14819 
   (set (reg:SI 97)
14820 
        (unspec_volatile:SI [
14821 
          (match_dup 0)
14822 
          (match_dup 1)
14823 
        ] 2048))
14824 
   (set (reg:SI 96)
14825 
        (unspec_volatile:SI [
14826 
          (match_dup 0)
14827 
          (match_dup 1)
14828 
        ] 2050))]
14829 
  "CGEN_ENABLE_INSN_P (528)"
14830 
  "cpsubla0.h\\t%0,%1"
14831 
  [(set_attr "may_trap" "no")
14832 
   (set_attr "latency" "0")
14833 
   (set_attr "length" "4")
14834 
   (set_attr "slot" "cop")
14835 
   (set_attr "slots" "p0s")
14836 
   (set_attr "stall" "none")])
14837 
 
14838 
 
14839 
(define_insn "cgen_intrinsic_cpsubua0_h_P0S"
14840 
  [(set (reg:SI 103)
14841 
        (unspec_volatile:SI [
14842 
          (match_operand:DI 0 "general_operand" "x")
14843 
          (match_operand:DI 1 "general_operand" "x")
14844 
        ] 2052))
14845 
   (set (reg:SI 102)
14846 
        (unspec_volatile:SI [
14847 
          (match_dup 0)
14848 
          (match_dup 1)
14849 
        ] 2054))
14850 
   (set (reg:SI 101)
14851 
        (unspec_volatile:SI [
14852 
          (match_dup 0)
14853 
          (match_dup 1)
14854 
        ] 2056))
14855 
   (set (reg:SI 100)
14856 
        (unspec_volatile:SI [
14857 
          (match_dup 0)
14858 
          (match_dup 1)
14859 
        ] 2058))]
14860 
  "CGEN_ENABLE_INSN_P (529)"
14861 
  "cpsubua0.h\\t%0,%1"
14862 
  [(set_attr "may_trap" "no")
14863 
   (set_attr "latency" "0")
14864 
   (set_attr "length" "4")
14865 
   (set_attr "slot" "cop")
14866 
   (set_attr "slots" "p0s")
14867 
   (set_attr "stall" "none")])
14868 
 
14869 
 
14870 
(define_insn "cgen_intrinsic_cpsuba0_b_P0S"
14871 
  [(set (reg:SI 103)
14872 
        (unspec_volatile:SI [
14873 
          (match_operand:DI 0 "general_operand" "x")
14874 
          (match_operand:DI 1 "general_operand" "x")
14875 
        ] 2060))
14876 
   (set (reg:SI 102)
14877 
        (unspec_volatile:SI [
14878 
          (match_dup 0)
14879 
          (match_dup 1)
14880 
        ] 2062))
14881 
   (set (reg:SI 101)
14882 
        (unspec_volatile:SI [
14883 
          (match_dup 0)
14884 
          (match_dup 1)
14885 
        ] 2064))
14886 
   (set (reg:SI 100)
14887 
        (unspec_volatile:SI [
14888 
          (match_dup 0)
14889 
          (match_dup 1)
14890 
        ] 2066))
14891 
   (set (reg:SI 99)
14892 
        (unspec_volatile:SI [
14893 
          (match_dup 0)
14894 
          (match_dup 1)
14895 
        ] 2068))
14896 
   (set (reg:SI 98)
14897 
        (unspec_volatile:SI [
14898 
          (match_dup 0)
14899 
          (match_dup 1)
14900 
        ] 2070))
14901 
   (set (reg:SI 97)
14902 
        (unspec_volatile:SI [
14903 
          (match_dup 0)
14904 
          (match_dup 1)
14905 
        ] 2072))
14906 
   (set (reg:SI 96)
14907 
        (unspec_volatile:SI [
14908 
          (match_dup 0)
14909 
          (match_dup 1)
14910 
        ] 2074))]
14911 
  "CGEN_ENABLE_INSN_P (530)"
14912 
  "cpsuba0.b\\t%0,%1"
14913 
  [(set_attr "may_trap" "no")
14914 
   (set_attr "latency" "0")
14915 
   (set_attr "length" "4")
14916 
   (set_attr "slot" "cop")
14917 
   (set_attr "slots" "p0s")
14918 
   (set_attr "stall" "none")])
14919 
 
14920 
 
14921 
(define_insn "cgen_intrinsic_cpsuba0u_b_P0S"
14922 
  [(set (reg:SI 103)
14923 
        (unspec_volatile:SI [
14924 
          (match_operand:DI 0 "general_operand" "x")
14925 
          (match_operand:DI 1 "general_operand" "x")
14926 
        ] 2076))
14927 
   (set (reg:SI 102)
14928 
        (unspec_volatile:SI [
14929 
          (match_dup 0)
14930 
          (match_dup 1)
14931 
        ] 2078))
14932 
   (set (reg:SI 101)
14933 
        (unspec_volatile:SI [
14934 
          (match_dup 0)
14935 
          (match_dup 1)
14936 
        ] 2080))
14937 
   (set (reg:SI 100)
14938 
        (unspec_volatile:SI [
14939 
          (match_dup 0)
14940 
          (match_dup 1)
14941 
        ] 2082))
14942 
   (set (reg:SI 99)
14943 
        (unspec_volatile:SI [
14944 
          (match_dup 0)
14945 
          (match_dup 1)
14946 
        ] 2084))
14947 
   (set (reg:SI 98)
14948 
        (unspec_volatile:SI [
14949 
          (match_dup 0)
14950 
          (match_dup 1)
14951 
        ] 2086))
14952 
   (set (reg:SI 97)
14953 
        (unspec_volatile:SI [
14954 
          (match_dup 0)
14955 
          (match_dup 1)
14956 
        ] 2088))
14957 
   (set (reg:SI 96)
14958 
        (unspec_volatile:SI [
14959 
          (match_dup 0)
14960 
          (match_dup 1)
14961 
        ] 2090))]
14962 
  "CGEN_ENABLE_INSN_P (531)"
14963 
  "cpsuba0u.b\\t%0,%1"
14964 
  [(set_attr "may_trap" "no")
14965 
   (set_attr "latency" "0")
14966 
   (set_attr "length" "4")
14967 
   (set_attr "slot" "cop")
14968 
   (set_attr "slots" "p0s")
14969 
   (set_attr "stall" "none")])
14970 
 
14971 
 
14972 
(define_insn "cgen_intrinsic_cpaddacla0_h_P0S"
14973 
  [(set (reg:SI 86)
14974 
        (unspec_volatile:SI [
14975 
          (match_operand:DI 0 "general_operand" "x")
14976 
          (match_operand:DI 1 "general_operand" "x")
14977 
        ] 2092))
14978 
   (set (reg:SI 99)
14979 
        (unspec_volatile:SI [
14980 
          (match_dup 0)
14981 
          (match_dup 1)
14982 
        ] 2094))
14983 
   (set (reg:SI 98)
14984 
        (unspec_volatile:SI [
14985 
          (match_dup 0)
14986 
          (match_dup 1)
14987 
        ] 2096))
14988 
   (set (reg:SI 97)
14989 
        (unspec_volatile:SI [
14990 
          (match_dup 0)
14991 
          (match_dup 1)
14992 
        ] 2098))
14993 
   (set (reg:SI 96)
14994 
        (unspec_volatile:SI [
14995 
          (match_dup 0)
14996 
          (match_dup 1)
14997 
        ] 2100))]
14998 
  "CGEN_ENABLE_INSN_P (532)"
14999 
  "cpaddacla0.h\\t%0,%1"
15000 
  [(set_attr "may_trap" "no")
15001 
   (set_attr "latency" "0")
15002 
   (set_attr "length" "4")
15003 
   (set_attr "slot" "cop")
15004 
   (set_attr "slots" "p0s")
15005 
   (set_attr "stall" "none")])
15006 
 
15007 
 
15008 
(define_insn "cgen_intrinsic_cpaddacua0_h_P0S"
15009 
  [(set (reg:SI 86)
15010 
        (unspec_volatile:SI [
15011 
          (match_operand:DI 0 "general_operand" "x")
15012 
          (match_operand:DI 1 "general_operand" "x")
15013 
        ] 2102))
15014 
   (set (reg:SI 103)
15015 
        (unspec_volatile:SI [
15016 
          (match_dup 0)
15017 
          (match_dup 1)
15018 
        ] 2104))
15019 
   (set (reg:SI 102)
15020 
        (unspec_volatile:SI [
15021 
          (match_dup 0)
15022 
          (match_dup 1)
15023 
        ] 2106))
15024 
   (set (reg:SI 101)
15025 
        (unspec_volatile:SI [
15026 
          (match_dup 0)
15027 
          (match_dup 1)
15028 
        ] 2108))
15029 
   (set (reg:SI 100)
15030 
        (unspec_volatile:SI [
15031 
          (match_dup 0)
15032 
          (match_dup 1)
15033 
        ] 2110))]
15034 
  "CGEN_ENABLE_INSN_P (533)"
15035 
  "cpaddacua0.h\\t%0,%1"
15036 
  [(set_attr "may_trap" "no")
15037 
   (set_attr "latency" "0")
15038 
   (set_attr "length" "4")
15039 
   (set_attr "slot" "cop")
15040 
   (set_attr "slots" "p0s")
15041 
   (set_attr "stall" "none")])
15042 
 
15043 
 
15044 
(define_insn "cgen_intrinsic_cpaddaca0_b_P0S"
15045 
  [(set (reg:SI 86)
15046 
        (unspec_volatile:SI [
15047 
          (match_operand:DI 0 "general_operand" "x")
15048 
          (match_operand:DI 1 "general_operand" "x")
15049 
        ] 2112))
15050 
   (set (reg:SI 103)
15051 
        (unspec_volatile:SI [
15052 
          (match_dup 0)
15053 
          (match_dup 1)
15054 
        ] 2114))
15055 
   (set (reg:SI 102)
15056 
        (unspec_volatile:SI [
15057 
          (match_dup 0)
15058 
          (match_dup 1)
15059 
        ] 2116))
15060 
   (set (reg:SI 101)
15061 
        (unspec_volatile:SI [
15062 
          (match_dup 0)
15063 
          (match_dup 1)
15064 
        ] 2118))
15065 
   (set (reg:SI 100)
15066 
        (unspec_volatile:SI [
15067 
          (match_dup 0)
15068 
          (match_dup 1)
15069 
        ] 2120))
15070 
   (set (reg:SI 99)
15071 
        (unspec_volatile:SI [
15072 
          (match_dup 0)
15073 
          (match_dup 1)
15074 
        ] 2122))
15075 
   (set (reg:SI 98)
15076 
        (unspec_volatile:SI [
15077 
          (match_dup 0)
15078 
          (match_dup 1)
15079 
        ] 2124))
15080 
   (set (reg:SI 97)
15081 
        (unspec_volatile:SI [
15082 
          (match_dup 0)
15083 
          (match_dup 1)
15084 
        ] 2126))
15085 
   (set (reg:SI 96)
15086 
        (unspec_volatile:SI [
15087 
          (match_dup 0)
15088 
          (match_dup 1)
15089 
        ] 2128))]
15090 
  "CGEN_ENABLE_INSN_P (534)"
15091 
  "cpaddaca0.b\\t%0,%1"
15092 
  [(set_attr "may_trap" "no")
15093 
   (set_attr "latency" "0")
15094 
   (set_attr "length" "4")
15095 
   (set_attr "slot" "cop")
15096 
   (set_attr "slots" "p0s")
15097 
   (set_attr "stall" "none")])
15098 
 
15099 
 
15100 
(define_insn "cgen_intrinsic_cpaddaca0u_b_P0S"
15101 
  [(set (reg:SI 86)
15102 
        (unspec_volatile:SI [
15103 
          (match_operand:DI 0 "general_operand" "x")
15104 
          (match_operand:DI 1 "general_operand" "x")
15105 
        ] 2130))
15106 
   (set (reg:SI 103)
15107 
        (unspec_volatile:SI [
15108 
          (match_dup 0)
15109 
          (match_dup 1)
15110 
        ] 2132))
15111 
   (set (reg:SI 102)
15112 
        (unspec_volatile:SI [
15113 
          (match_dup 0)
15114 
          (match_dup 1)
15115 
        ] 2134))
15116 
   (set (reg:SI 101)
15117 
        (unspec_volatile:SI [
15118 
          (match_dup 0)
15119 
          (match_dup 1)
15120 
        ] 2136))
15121 
   (set (reg:SI 100)
15122 
        (unspec_volatile:SI [
15123 
          (match_dup 0)
15124 
          (match_dup 1)
15125 
        ] 2138))
15126 
   (set (reg:SI 99)
15127 
        (unspec_volatile:SI [
15128 
          (match_dup 0)
15129 
          (match_dup 1)
15130 
        ] 2140))
15131 
   (set (reg:SI 98)
15132 
        (unspec_volatile:SI [
15133 
          (match_dup 0)
15134 
          (match_dup 1)
15135 
        ] 2142))
15136 
   (set (reg:SI 97)
15137 
        (unspec_volatile:SI [
15138 
          (match_dup 0)
15139 
          (match_dup 1)
15140 
        ] 2144))
15141 
   (set (reg:SI 96)
15142 
        (unspec_volatile:SI [
15143 
          (match_dup 0)
15144 
          (match_dup 1)
15145 
        ] 2146))]
15146 
  "CGEN_ENABLE_INSN_P (535)"
15147 
  "cpaddaca0u.b\\t%0,%1"
15148 
  [(set_attr "may_trap" "no")
15149 
   (set_attr "latency" "0")
15150 
   (set_attr "length" "4")
15151 
   (set_attr "slot" "cop")
15152 
   (set_attr "slots" "p0s")
15153 
   (set_attr "stall" "none")])
15154 
 
15155 
 
15156 
(define_insn "cgen_intrinsic_cpaddla0_h_P0S"
15157 
  [(set (reg:SI 99)
15158 
        (unspec_volatile:SI [
15159 
          (match_operand:DI 0 "general_operand" "x")
15160 
          (match_operand:DI 1 "general_operand" "x")
15161 
        ] 2148))
15162 
   (set (reg:SI 98)
15163 
        (unspec_volatile:SI [
15164 
          (match_dup 0)
15165 
          (match_dup 1)
15166 
        ] 2150))
15167 
   (set (reg:SI 97)
15168 
        (unspec_volatile:SI [
15169 
          (match_dup 0)
15170 
          (match_dup 1)
15171 
        ] 2152))
15172 
   (set (reg:SI 96)
15173 
        (unspec_volatile:SI [
15174 
          (match_dup 0)
15175 
          (match_dup 1)
15176 
        ] 2154))]
15177 
  "CGEN_ENABLE_INSN_P (536)"
15178 
  "cpaddla0.h\\t%0,%1"
15179 
  [(set_attr "may_trap" "no")
15180 
   (set_attr "latency" "0")
15181 
   (set_attr "length" "4")
15182 
   (set_attr "slot" "cop")
15183 
   (set_attr "slots" "p0s")
15184 
   (set_attr "stall" "none")])
15185 
 
15186 
 
15187 
(define_insn "cgen_intrinsic_cpaddua0_h_P0S"
15188 
  [(set (reg:SI 103)
15189 
        (unspec_volatile:SI [
15190 
          (match_operand:DI 0 "general_operand" "x")
15191 
          (match_operand:DI 1 "general_operand" "x")
15192 
        ] 2156))
15193 
   (set (reg:SI 102)
15194 
        (unspec_volatile:SI [
15195 
          (match_dup 0)
15196 
          (match_dup 1)
15197 
        ] 2158))
15198 
   (set (reg:SI 101)
15199 
        (unspec_volatile:SI [
15200 
          (match_dup 0)
15201 
          (match_dup 1)
15202 
        ] 2160))
15203 
   (set (reg:SI 100)
15204 
        (unspec_volatile:SI [
15205 
          (match_dup 0)
15206 
          (match_dup 1)
15207 
        ] 2162))]
15208 
  "CGEN_ENABLE_INSN_P (537)"
15209 
  "cpaddua0.h\\t%0,%1"
15210 
  [(set_attr "may_trap" "no")
15211 
   (set_attr "latency" "0")
15212 
   (set_attr "length" "4")
15213 
   (set_attr "slot" "cop")
15214 
   (set_attr "slots" "p0s")
15215 
   (set_attr "stall" "none")])
15216 
 
15217 
 
15218 
(define_insn "cgen_intrinsic_cpadda0_b_P0S"
15219 
  [(set (reg:SI 103)
15220 
        (unspec_volatile:SI [
15221 
          (match_operand:DI 0 "general_operand" "x")
15222 
          (match_operand:DI 1 "general_operand" "x")
15223 
        ] 2164))
15224 
   (set (reg:SI 102)
15225 
        (unspec_volatile:SI [
15226 
          (match_dup 0)
15227 
          (match_dup 1)
15228 
        ] 2166))
15229 
   (set (reg:SI 101)
15230 
        (unspec_volatile:SI [
15231 
          (match_dup 0)
15232 
          (match_dup 1)
15233 
        ] 2168))
15234 
   (set (reg:SI 100)
15235 
        (unspec_volatile:SI [
15236 
          (match_dup 0)
15237 
          (match_dup 1)
15238 
        ] 2170))
15239 
   (set (reg:SI 99)
15240 
        (unspec_volatile:SI [
15241 
          (match_dup 0)
15242 
          (match_dup 1)
15243 
        ] 2172))
15244 
   (set (reg:SI 98)
15245 
        (unspec_volatile:SI [
15246 
          (match_dup 0)
15247 
          (match_dup 1)
15248 
        ] 2174))
15249 
   (set (reg:SI 97)
15250 
        (unspec_volatile:SI [
15251 
          (match_dup 0)
15252 
          (match_dup 1)
15253 
        ] 2176))
15254 
   (set (reg:SI 96)
15255 
        (unspec_volatile:SI [
15256 
          (match_dup 0)
15257 
          (match_dup 1)
15258 
        ] 2178))]
15259 
  "CGEN_ENABLE_INSN_P (538)"
15260 
  "cpadda0.b\\t%0,%1"
15261 
  [(set_attr "may_trap" "no")
15262 
   (set_attr "latency" "0")
15263 
   (set_attr "length" "4")
15264 
   (set_attr "slot" "cop")
15265 
   (set_attr "slots" "p0s")
15266 
   (set_attr "stall" "none")])
15267 
 
15268 
 
15269 
(define_insn "cgen_intrinsic_cpadda0u_b_P0S"
15270 
  [(set (reg:SI 103)
15271 
        (unspec_volatile:SI [
15272 
          (match_operand:DI 0 "general_operand" "x")
15273 
          (match_operand:DI 1 "general_operand" "x")
15274 
        ] 2180))
15275 
   (set (reg:SI 102)
15276 
        (unspec_volatile:SI [
15277 
          (match_dup 0)
15278 
          (match_dup 1)
15279 
        ] 2182))
15280 
   (set (reg:SI 101)
15281 
        (unspec_volatile:SI [
15282 
          (match_dup 0)
15283 
          (match_dup 1)
15284 
        ] 2184))
15285 
   (set (reg:SI 100)
15286 
        (unspec_volatile:SI [
15287 
          (match_dup 0)
15288 
          (match_dup 1)
15289 
        ] 2186))
15290 
   (set (reg:SI 99)
15291 
        (unspec_volatile:SI [
15292 
          (match_dup 0)
15293 
          (match_dup 1)
15294 
        ] 2188))
15295 
   (set (reg:SI 98)
15296 
        (unspec_volatile:SI [
15297 
          (match_dup 0)
15298 
          (match_dup 1)
15299 
        ] 2190))
15300 
   (set (reg:SI 97)
15301 
        (unspec_volatile:SI [
15302 
          (match_dup 0)
15303 
          (match_dup 1)
15304 
        ] 2192))
15305 
   (set (reg:SI 96)
15306 
        (unspec_volatile:SI [
15307 
          (match_dup 0)
15308 
          (match_dup 1)
15309 
        ] 2194))]
15310 
  "CGEN_ENABLE_INSN_P (539)"
15311 
  "cpadda0u.b\\t%0,%1"
15312 
  [(set_attr "may_trap" "no")
15313 
   (set_attr "latency" "0")
15314 
   (set_attr "length" "4")
15315 
   (set_attr "slot" "cop")
15316 
   (set_attr "slots" "p0s")
15317 
   (set_attr "stall" "none")])
15318 
 
15319 
 
15320 
(define_insn "cgen_intrinsic_cpcmpge_w_C3"
15321 
  [(set (reg:SI 81)
15322 
        (unspec_volatile:SI [
15323 
          (match_operand:DI 0 "general_operand" "x")
15324 
          (match_operand:DI 1 "general_operand" "x")
15325 
        ] 3282))]
15326 
  "CGEN_ENABLE_INSN_P (540)"
15327 
  "cpcmpge.w\\t%0,%1"
15328 
  [(set_attr "may_trap" "no")
15329 
   (set_attr "latency" "0")
15330 
   (set_attr "length" "4")
15331 
   (set_attr "slot" "cop")
15332 
   (set_attr "slots" "c3")
15333 
   (set_attr "stall" "none")])
15334 
 
15335 
 
15336 
(define_insn "cgen_intrinsic_cpcmpge_w_P0S_P1"
15337 
  [(set (reg:SI 81)
15338 
        (unspec_volatile:SI [
15339 
          (match_operand:DI 0 "general_operand" "x")
15340 
          (match_operand:DI 1 "general_operand" "x")
15341 
        ] 3282))]
15342 
  "CGEN_ENABLE_INSN_P (541)"
15343 
  "cpcmpge.w\\t%0,%1"
15344 
  [(set_attr "may_trap" "no")
15345 
   (set_attr "latency" "0")
15346 
   (set_attr "length" "4")
15347 
   (set_attr "slot" "cop")
15348 
   (set_attr "slots" "p0s_p1")
15349 
   (set_attr "stall" "none")])
15350 
 
15351 
 
15352 
(define_insn "cgen_intrinsic_cpcmpgeu_w_C3"
15353 
  [(set (reg:SI 81)
15354 
        (unspec_volatile:SI [
15355 
          (match_operand:DI 0 "general_operand" "x")
15356 
          (match_operand:DI 1 "general_operand" "x")
15357 
        ] 3284))]
15358 
  "CGEN_ENABLE_INSN_P (542)"
15359 
  "cpcmpgeu.w\\t%0,%1"
15360 
  [(set_attr "may_trap" "no")
15361 
   (set_attr "latency" "0")
15362 
   (set_attr "length" "4")
15363 
   (set_attr "slot" "cop")
15364 
   (set_attr "slots" "c3")
15365 
   (set_attr "stall" "none")])
15366 
 
15367 
 
15368 
(define_insn "cgen_intrinsic_cpcmpgeu_w_P0S_P1"
15369 
  [(set (reg:SI 81)
15370 
        (unspec_volatile:SI [
15371 
          (match_operand:DI 0 "general_operand" "x")
15372 
          (match_operand:DI 1 "general_operand" "x")
15373 
        ] 3284))]
15374 
  "CGEN_ENABLE_INSN_P (543)"
15375 
  "cpcmpgeu.w\\t%0,%1"
15376 
  [(set_attr "may_trap" "no")
15377 
   (set_attr "latency" "0")
15378 
   (set_attr "length" "4")
15379 
   (set_attr "slot" "cop")
15380 
   (set_attr "slots" "p0s_p1")
15381 
   (set_attr "stall" "none")])
15382 
 
15383 
 
15384 
(define_insn "cgen_intrinsic_cpcmpge_h_C3"
15385 
  [(set (reg:SI 81)
15386 
        (unspec_volatile:SI [
15387 
          (match_operand:DI 0 "general_operand" "x")
15388 
          (match_operand:DI 1 "general_operand" "x")
15389 
        ] 3286))]
15390 
  "CGEN_ENABLE_INSN_P (544)"
15391 
  "cpcmpge.h\\t%0,%1"
15392 
  [(set_attr "may_trap" "no")
15393 
   (set_attr "latency" "0")
15394 
   (set_attr "length" "4")
15395 
   (set_attr "slot" "cop")
15396 
   (set_attr "slots" "c3")
15397 
   (set_attr "stall" "none")])
15398 
 
15399 
 
15400 
(define_insn "cgen_intrinsic_cpcmpge_h_P0S_P1"
15401 
  [(set (reg:SI 81)
15402 
        (unspec_volatile:SI [
15403 
          (match_operand:DI 0 "general_operand" "x")
15404 
          (match_operand:DI 1 "general_operand" "x")
15405 
        ] 3286))]
15406 
  "CGEN_ENABLE_INSN_P (545)"
15407 
  "cpcmpge.h\\t%0,%1"
15408 
  [(set_attr "may_trap" "no")
15409 
   (set_attr "latency" "0")
15410 
   (set_attr "length" "4")
15411 
   (set_attr "slot" "cop")
15412 
   (set_attr "slots" "p0s_p1")
15413 
   (set_attr "stall" "none")])
15414 
 
15415 
 
15416 
(define_insn "cgen_intrinsic_cpcmpge_b_C3"
15417 
  [(set (reg:SI 81)
15418 
        (unspec_volatile:SI [
15419 
          (match_operand:DI 0 "general_operand" "x")
15420 
          (match_operand:DI 1 "general_operand" "x")
15421 
        ] 3288))]
15422 
  "CGEN_ENABLE_INSN_P (546)"
15423 
  "cpcmpge.b\\t%0,%1"
15424 
  [(set_attr "may_trap" "no")
15425 
   (set_attr "latency" "0")
15426 
   (set_attr "length" "4")
15427 
   (set_attr "slot" "cop")
15428 
   (set_attr "slots" "c3")
15429 
   (set_attr "stall" "none")])
15430 
 
15431 
 
15432 
(define_insn "cgen_intrinsic_cpcmpge_b_P0S_P1"
15433 
  [(set (reg:SI 81)
15434 
        (unspec_volatile:SI [
15435 
          (match_operand:DI 0 "general_operand" "x")
15436 
          (match_operand:DI 1 "general_operand" "x")
15437 
        ] 3288))]
15438 
  "CGEN_ENABLE_INSN_P (547)"
15439 
  "cpcmpge.b\\t%0,%1"
15440 
  [(set_attr "may_trap" "no")
15441 
   (set_attr "latency" "0")
15442 
   (set_attr "length" "4")
15443 
   (set_attr "slot" "cop")
15444 
   (set_attr "slots" "p0s_p1")
15445 
   (set_attr "stall" "none")])
15446 
 
15447 
 
15448 
(define_insn "cgen_intrinsic_cpcmpgeu_b_C3"
15449 
  [(set (reg:SI 81)
15450 
        (unspec_volatile:SI [
15451 
          (match_operand:DI 0 "general_operand" "x")
15452 
          (match_operand:DI 1 "general_operand" "x")
15453 
        ] 3290))]
15454 
  "CGEN_ENABLE_INSN_P (548)"
15455 
  "cpcmpgeu.b\\t%0,%1"
15456 
  [(set_attr "may_trap" "no")
15457 
   (set_attr "latency" "0")
15458 
   (set_attr "length" "4")
15459 
   (set_attr "slot" "cop")
15460 
   (set_attr "slots" "c3")
15461 
   (set_attr "stall" "none")])
15462 
 
15463 
 
15464 
(define_insn "cgen_intrinsic_cpcmpgeu_b_P0S_P1"
15465 
  [(set (reg:SI 81)
15466 
        (unspec_volatile:SI [
15467 
          (match_operand:DI 0 "general_operand" "x")
15468 
          (match_operand:DI 1 "general_operand" "x")
15469 
        ] 3290))]
15470 
  "CGEN_ENABLE_INSN_P (549)"
15471 
  "cpcmpgeu.b\\t%0,%1"
15472 
  [(set_attr "may_trap" "no")
15473 
   (set_attr "latency" "0")
15474 
   (set_attr "length" "4")
15475 
   (set_attr "slot" "cop")
15476 
   (set_attr "slots" "p0s_p1")
15477 
   (set_attr "stall" "none")])
15478 
 
15479 
 
15480 
(define_insn "cgen_intrinsic_cpcmpgt_w_C3"
15481 
  [(set (reg:SI 81)
15482 
        (unspec_volatile:SI [
15483 
          (match_operand:DI 0 "general_operand" "x")
15484 
          (match_operand:DI 1 "general_operand" "x")
15485 
        ] 3292))]
15486 
  "CGEN_ENABLE_INSN_P (550)"
15487 
  "cpcmpgt.w\\t%0,%1"
15488 
  [(set_attr "may_trap" "no")
15489 
   (set_attr "latency" "0")
15490 
   (set_attr "length" "4")
15491 
   (set_attr "slot" "cop")
15492 
   (set_attr "slots" "c3")
15493 
   (set_attr "stall" "none")])
15494 
 
15495 
 
15496 
(define_insn "cgen_intrinsic_cpcmpgt_w_P0S_P1"
15497 
  [(set (reg:SI 81)
15498 
        (unspec_volatile:SI [
15499 
          (match_operand:DI 0 "general_operand" "x")
15500 
          (match_operand:DI 1 "general_operand" "x")
15501 
        ] 3292))]
15502 
  "CGEN_ENABLE_INSN_P (551)"
15503 
  "cpcmpgt.w\\t%0,%1"
15504 
  [(set_attr "may_trap" "no")
15505 
   (set_attr "latency" "0")
15506 
   (set_attr "length" "4")
15507 
   (set_attr "slot" "cop")
15508 
   (set_attr "slots" "p0s_p1")
15509 
   (set_attr "stall" "none")])
15510 
 
15511 
 
15512 
(define_insn "cgen_intrinsic_cpcmpgtu_w_C3"
15513 
  [(set (reg:SI 81)
15514 
        (unspec_volatile:SI [
15515 
          (match_operand:DI 0 "general_operand" "x")
15516 
          (match_operand:DI 1 "general_operand" "x")
15517 
        ] 3294))]
15518 
  "CGEN_ENABLE_INSN_P (552)"
15519 
  "cpcmpgtu.w\\t%0,%1"
15520 
  [(set_attr "may_trap" "no")
15521 
   (set_attr "latency" "0")
15522 
   (set_attr "length" "4")
15523 
   (set_attr "slot" "cop")
15524 
   (set_attr "slots" "c3")
15525 
   (set_attr "stall" "none")])
15526 
 
15527 
 
15528 
(define_insn "cgen_intrinsic_cpcmpgtu_w_P0S_P1"
15529 
  [(set (reg:SI 81)
15530 
        (unspec_volatile:SI [
15531 
          (match_operand:DI 0 "general_operand" "x")
15532 
          (match_operand:DI 1 "general_operand" "x")
15533 
        ] 3294))]
15534 
  "CGEN_ENABLE_INSN_P (553)"
15535 
  "cpcmpgtu.w\\t%0,%1"
15536 
  [(set_attr "may_trap" "no")
15537 
   (set_attr "latency" "0")
15538 
   (set_attr "length" "4")
15539 
   (set_attr "slot" "cop")
15540 
   (set_attr "slots" "p0s_p1")
15541 
   (set_attr "stall" "none")])
15542 
 
15543 
 
15544 
(define_insn "cgen_intrinsic_cpcmpgt_h_C3"
15545 
  [(set (reg:SI 81)
15546 
        (unspec_volatile:SI [
15547 
          (match_operand:DI 0 "general_operand" "x")
15548 
          (match_operand:DI 1 "general_operand" "x")
15549 
        ] 3296))]
15550 
  "CGEN_ENABLE_INSN_P (554)"
15551 
  "cpcmpgt.h\\t%0,%1"
15552 
  [(set_attr "may_trap" "no")
15553 
   (set_attr "latency" "0")
15554 
   (set_attr "length" "4")
15555 
   (set_attr "slot" "cop")
15556 
   (set_attr "slots" "c3")
15557 
   (set_attr "stall" "none")])
15558 
 
15559 
 
15560 
(define_insn "cgen_intrinsic_cpcmpgt_h_P0S_P1"
15561 
  [(set (reg:SI 81)
15562 
        (unspec_volatile:SI [
15563 
          (match_operand:DI 0 "general_operand" "x")
15564 
          (match_operand:DI 1 "general_operand" "x")
15565 
        ] 3296))]
15566 
  "CGEN_ENABLE_INSN_P (555)"
15567 
  "cpcmpgt.h\\t%0,%1"
15568 
  [(set_attr "may_trap" "no")
15569 
   (set_attr "latency" "0")
15570 
   (set_attr "length" "4")
15571 
   (set_attr "slot" "cop")
15572 
   (set_attr "slots" "p0s_p1")
15573 
   (set_attr "stall" "none")])
15574 
 
15575 
 
15576 
(define_insn "cgen_intrinsic_cpcmpgt_b_C3"
15577 
  [(set (reg:SI 81)
15578 
        (unspec_volatile:SI [
15579 
          (match_operand:DI 0 "general_operand" "x")
15580 
          (match_operand:DI 1 "general_operand" "x")
15581 
        ] 3298))]
15582 
  "CGEN_ENABLE_INSN_P (556)"
15583 
  "cpcmpgt.b\\t%0,%1"
15584 
  [(set_attr "may_trap" "no")
15585 
   (set_attr "latency" "0")
15586 
   (set_attr "length" "4")
15587 
   (set_attr "slot" "cop")
15588 
   (set_attr "slots" "c3")
15589 
   (set_attr "stall" "none")])
15590 
 
15591 
 
15592 
(define_insn "cgen_intrinsic_cpcmpgt_b_P0S_P1"
15593 
  [(set (reg:SI 81)
15594 
        (unspec_volatile:SI [
15595 
          (match_operand:DI 0 "general_operand" "x")
15596 
          (match_operand:DI 1 "general_operand" "x")
15597 
        ] 3298))]
15598 
  "CGEN_ENABLE_INSN_P (557)"
15599 
  "cpcmpgt.b\\t%0,%1"
15600 
  [(set_attr "may_trap" "no")
15601 
   (set_attr "latency" "0")
15602 
   (set_attr "length" "4")
15603 
   (set_attr "slot" "cop")
15604 
   (set_attr "slots" "p0s_p1")
15605 
   (set_attr "stall" "none")])
15606 
 
15607 
 
15608 
(define_insn "cgen_intrinsic_cpcmpgtu_b_C3"
15609 
  [(set (reg:SI 81)
15610 
        (unspec_volatile:SI [
15611 
          (match_operand:DI 0 "general_operand" "x")
15612 
          (match_operand:DI 1 "general_operand" "x")
15613 
        ] 3300))]
15614 
  "CGEN_ENABLE_INSN_P (558)"
15615 
  "cpcmpgtu.b\\t%0,%1"
15616 
  [(set_attr "may_trap" "no")
15617 
   (set_attr "latency" "0")
15618 
   (set_attr "length" "4")
15619 
   (set_attr "slot" "cop")
15620 
   (set_attr "slots" "c3")
15621 
   (set_attr "stall" "none")])
15622 
 
15623 
 
15624 
(define_insn "cgen_intrinsic_cpcmpgtu_b_P0S_P1"
15625 
  [(set (reg:SI 81)
15626 
        (unspec_volatile:SI [
15627 
          (match_operand:DI 0 "general_operand" "x")
15628 
          (match_operand:DI 1 "general_operand" "x")
15629 
        ] 3300))]
15630 
  "CGEN_ENABLE_INSN_P (559)"
15631 
  "cpcmpgtu.b\\t%0,%1"
15632 
  [(set_attr "may_trap" "no")
15633 
   (set_attr "latency" "0")
15634 
   (set_attr "length" "4")
15635 
   (set_attr "slot" "cop")
15636 
   (set_attr "slots" "p0s_p1")
15637 
   (set_attr "stall" "none")])
15638 
 
15639 
 
15640 
(define_insn "cgen_intrinsic_cpcmpne_w_C3"
15641 
  [(set (reg:SI 81)
15642 
        (unspec_volatile:SI [
15643 
          (match_operand:DI 0 "general_operand" "x")
15644 
          (match_operand:DI 1 "general_operand" "x")
15645 
        ] 3302))]
15646 
  "CGEN_ENABLE_INSN_P (560)"
15647 
  "cpcmpne.w\\t%0,%1"
15648 
  [(set_attr "may_trap" "no")
15649 
   (set_attr "latency" "0")
15650 
   (set_attr "length" "4")
15651 
   (set_attr "slot" "cop")
15652 
   (set_attr "slots" "c3")
15653 
   (set_attr "stall" "none")])
15654 
 
15655 
 
15656 
(define_insn "cgen_intrinsic_cpcmpne_w_P0S_P1"
15657 
  [(set (reg:SI 81)
15658 
        (unspec_volatile:SI [
15659 
          (match_operand:DI 0 "general_operand" "x")
15660 
          (match_operand:DI 1 "general_operand" "x")
15661 
        ] 3302))]
15662 
  "CGEN_ENABLE_INSN_P (561)"
15663 
  "cpcmpne.w\\t%0,%1"
15664 
  [(set_attr "may_trap" "no")
15665 
   (set_attr "latency" "0")
15666 
   (set_attr "length" "4")
15667 
   (set_attr "slot" "cop")
15668 
   (set_attr "slots" "p0s_p1")
15669 
   (set_attr "stall" "none")])
15670 
 
15671 
 
15672 
(define_insn "cgen_intrinsic_cpcmpne_h_C3"
15673 
  [(set (reg:SI 81)
15674 
        (unspec_volatile:SI [
15675 
          (match_operand:DI 0 "general_operand" "x")
15676 
          (match_operand:DI 1 "general_operand" "x")
15677 
        ] 3304))]
15678 
  "CGEN_ENABLE_INSN_P (562)"
15679 
  "cpcmpne.h\\t%0,%1"
15680 
  [(set_attr "may_trap" "no")
15681 
   (set_attr "latency" "0")
15682 
   (set_attr "length" "4")
15683 
   (set_attr "slot" "cop")
15684 
   (set_attr "slots" "c3")
15685 
   (set_attr "stall" "none")])
15686 
 
15687 
 
15688 
(define_insn "cgen_intrinsic_cpcmpne_h_P0S_P1"
15689 
  [(set (reg:SI 81)
15690 
        (unspec_volatile:SI [
15691 
          (match_operand:DI 0 "general_operand" "x")
15692 
          (match_operand:DI 1 "general_operand" "x")
15693 
        ] 3304))]
15694 
  "CGEN_ENABLE_INSN_P (563)"
15695 
  "cpcmpne.h\\t%0,%1"
15696 
  [(set_attr "may_trap" "no")
15697 
   (set_attr "latency" "0")
15698 
   (set_attr "length" "4")
15699 
   (set_attr "slot" "cop")
15700 
   (set_attr "slots" "p0s_p1")
15701 
   (set_attr "stall" "none")])
15702 
 
15703 
 
15704 
(define_insn "cgen_intrinsic_cpcmpne_b_C3"
15705 
  [(set (reg:SI 81)
15706 
        (unspec_volatile:SI [
15707 
          (match_operand:DI 0 "general_operand" "x")
15708 
          (match_operand:DI 1 "general_operand" "x")
15709 
        ] 3306))]
15710 
  "CGEN_ENABLE_INSN_P (564)"
15711 
  "cpcmpne.b\\t%0,%1"
15712 
  [(set_attr "may_trap" "no")
15713 
   (set_attr "latency" "0")
15714 
   (set_attr "length" "4")
15715 
   (set_attr "slot" "cop")
15716 
   (set_attr "slots" "c3")
15717 
   (set_attr "stall" "none")])
15718 
 
15719 
 
15720 
(define_insn "cgen_intrinsic_cpcmpne_b_P0S_P1"
15721 
  [(set (reg:SI 81)
15722 
        (unspec_volatile:SI [
15723 
          (match_operand:DI 0 "general_operand" "x")
15724 
          (match_operand:DI 1 "general_operand" "x")
15725 
        ] 3306))]
15726 
  "CGEN_ENABLE_INSN_P (565)"
15727 
  "cpcmpne.b\\t%0,%1"
15728 
  [(set_attr "may_trap" "no")
15729 
   (set_attr "latency" "0")
15730 
   (set_attr "length" "4")
15731 
   (set_attr "slot" "cop")
15732 
   (set_attr "slots" "p0s_p1")
15733 
   (set_attr "stall" "none")])
15734 
 
15735 
 
15736 
(define_insn "cgen_intrinsic_cpcmpeq_w_C3"
15737 
  [(set (reg:SI 81)
15738 
        (unspec_volatile:SI [
15739 
          (match_operand:DI 0 "general_operand" "x")
15740 
          (match_operand:DI 1 "general_operand" "x")
15741 
        ] 3308))]
15742 
  "CGEN_ENABLE_INSN_P (566)"
15743 
  "cpcmpeq.w\\t%0,%1"
15744 
  [(set_attr "may_trap" "no")
15745 
   (set_attr "latency" "0")
15746 
   (set_attr "length" "4")
15747 
   (set_attr "slot" "cop")
15748 
   (set_attr "slots" "c3")
15749 
   (set_attr "stall" "none")])
15750 
 
15751 
 
15752 
(define_insn "cgen_intrinsic_cpcmpeq_w_P0S_P1"
15753 
  [(set (reg:SI 81)
15754 
        (unspec_volatile:SI [
15755 
          (match_operand:DI 0 "general_operand" "x")
15756 
          (match_operand:DI 1 "general_operand" "x")
15757 
        ] 3308))]
15758 
  "CGEN_ENABLE_INSN_P (567)"
15759 
  "cpcmpeq.w\\t%0,%1"
15760 
  [(set_attr "may_trap" "no")
15761 
   (set_attr "latency" "0")
15762 
   (set_attr "length" "4")
15763 
   (set_attr "slot" "cop")
15764 
   (set_attr "slots" "p0s_p1")
15765 
   (set_attr "stall" "none")])
15766 
 
15767 
 
15768 
(define_insn "cgen_intrinsic_cpcmpeq_h_C3"
15769 
  [(set (reg:SI 81)
15770 
        (unspec_volatile:SI [
15771 
          (match_operand:DI 0 "general_operand" "x")
15772 
          (match_operand:DI 1 "general_operand" "x")
15773 
        ] 3310))]
15774 
  "CGEN_ENABLE_INSN_P (568)"
15775 
  "cpcmpeq.h\\t%0,%1"
15776 
  [(set_attr "may_trap" "no")
15777 
   (set_attr "latency" "0")
15778 
   (set_attr "length" "4")
15779 
   (set_attr "slot" "cop")
15780 
   (set_attr "slots" "c3")
15781 
   (set_attr "stall" "none")])
15782 
 
15783 
 
15784 
(define_insn "cgen_intrinsic_cpcmpeq_h_P0S_P1"
15785 
  [(set (reg:SI 81)
15786 
        (unspec_volatile:SI [
15787 
          (match_operand:DI 0 "general_operand" "x")
15788 
          (match_operand:DI 1 "general_operand" "x")
15789 
        ] 3310))]
15790 
  "CGEN_ENABLE_INSN_P (569)"
15791 
  "cpcmpeq.h\\t%0,%1"
15792 
  [(set_attr "may_trap" "no")
15793 
   (set_attr "latency" "0")
15794 
   (set_attr "length" "4")
15795 
   (set_attr "slot" "cop")
15796 
   (set_attr "slots" "p0s_p1")
15797 
   (set_attr "stall" "none")])
15798 
 
15799 
 
15800 
(define_insn "cgen_intrinsic_cpcmpeq_b_C3"
15801 
  [(set (reg:SI 81)
15802 
        (unspec_volatile:SI [
15803 
          (match_operand:DI 0 "general_operand" "x")
15804 
          (match_operand:DI 1 "general_operand" "x")
15805 
        ] 3312))]
15806 
  "CGEN_ENABLE_INSN_P (570)"
15807 
  "cpcmpeq.b\\t%0,%1"
15808 
  [(set_attr "may_trap" "no")
15809 
   (set_attr "latency" "0")
15810 
   (set_attr "length" "4")
15811 
   (set_attr "slot" "cop")
15812 
   (set_attr "slots" "c3")
15813 
   (set_attr "stall" "none")])
15814 
 
15815 
 
15816 
(define_insn "cgen_intrinsic_cpcmpeq_b_P0S_P1"
15817 
  [(set (reg:SI 81)
15818 
        (unspec_volatile:SI [
15819 
          (match_operand:DI 0 "general_operand" "x")
15820 
          (match_operand:DI 1 "general_operand" "x")
15821 
        ] 3312))]
15822 
  "CGEN_ENABLE_INSN_P (571)"
15823 
  "cpcmpeq.b\\t%0,%1"
15824 
  [(set_attr "may_trap" "no")
15825 
   (set_attr "latency" "0")
15826 
   (set_attr "length" "4")
15827 
   (set_attr "slot" "cop")
15828 
   (set_attr "slots" "p0s_p1")
15829 
   (set_attr "stall" "none")])
15830 
 
15831 
 
15832 
(define_insn "cgen_intrinsic_cpcmpeqz_b_C3"
15833 
  [(set (reg:SI 81)
15834 
        (unspec_volatile:SI [
15835 
          (match_operand:DI 0 "general_operand" "x")
15836 
          (match_operand:DI 1 "general_operand" "x")
15837 
        ] 3314))]
15838 
  "CGEN_ENABLE_INSN_P (572)"
15839 
  "cpcmpeqz.b\\t%0,%1"
15840 
  [(set_attr "may_trap" "no")
15841 
   (set_attr "latency" "0")
15842 
   (set_attr "length" "4")
15843 
   (set_attr "slot" "cop")
15844 
   (set_attr "slots" "c3")
15845 
   (set_attr "stall" "none")])
15846 
 
15847 
 
15848 
(define_insn "cgen_intrinsic_cpcmpeqz_b_P0S_P1"
15849 
  [(set (reg:SI 81)
15850 
        (unspec_volatile:SI [
15851 
          (match_operand:DI 0 "general_operand" "x")
15852 
          (match_operand:DI 1 "general_operand" "x")
15853 
        ] 3314))]
15854 
  "CGEN_ENABLE_INSN_P (573)"
15855 
  "cpcmpeqz.b\\t%0,%1"
15856 
  [(set_attr "may_trap" "no")
15857 
   (set_attr "latency" "0")
15858 
   (set_attr "length" "4")
15859 
   (set_attr "slot" "cop")
15860 
   (set_attr "slots" "p0s_p1")
15861 
   (set_attr "stall" "none")])
15862 
 
15863 
 
15864 
(define_insn "cgen_intrinsic_cpmovtocc_C3"
15865 
  [(set (reg:SI 81)
15866 
        (unspec_volatile:SI [
15867 
          (match_operand:DI 0 "general_operand" "x")
15868 
        ] 3378))]
15869 
  "CGEN_ENABLE_INSN_P (574)"
15870 
  "cpmovtocc\\t%0"
15871 
  [(set_attr "may_trap" "no")
15872 
   (set_attr "latency" "0")
15873 
   (set_attr "length" "4")
15874 
   (set_attr "slot" "cop")
15875 
   (set_attr "slots" "c3")
15876 
   (set_attr "stall" "none")])
15877 
 
15878 
 
15879 
(define_insn "cgen_intrinsic_cpmovtocc_P0S_P1"
15880 
  [(set (reg:SI 81)
15881 
        (unspec_volatile:SI [
15882 
          (match_operand:DI 0 "general_operand" "x")
15883 
        ] 3378))]
15884 
  "CGEN_ENABLE_INSN_P (575)"
15885 
  "cpmovtocc\\t%0"
15886 
  [(set_attr "may_trap" "no")
15887 
   (set_attr "latency" "0")
15888 
   (set_attr "length" "4")
15889 
   (set_attr "slot" "cop")
15890 
   (set_attr "slots" "p0s_p1")
15891 
   (set_attr "stall" "none")])
15892 
 
15893 
 
15894 
(define_insn "cgen_intrinsic_cpmovtocsar1_C3"
15895 
  [(set (reg:SI 95)
15896 
        (unspec_volatile:SI [
15897 
          (match_operand:DI 0 "general_operand" "x")
15898 
        ] 3380))]
15899 
  "CGEN_ENABLE_INSN_P (576)"
15900 
  "cpmovtocsar1\\t%0"
15901 
  [(set_attr "may_trap" "no")
15902 
   (set_attr "latency" "0")
15903 
   (set_attr "length" "4")
15904 
   (set_attr "slot" "cop")
15905 
   (set_attr "slots" "c3")
15906 
   (set_attr "stall" "none")])
15907 
 
15908 
 
15909 
(define_insn "cgen_intrinsic_cpmovtocsar1_P0S_P1"
15910 
  [(set (reg:SI 95)
15911 
        (unspec_volatile:SI [
15912 
          (match_operand:DI 0 "general_operand" "x")
15913 
        ] 3380))]
15914 
  "CGEN_ENABLE_INSN_P (577)"
15915 
  "cpmovtocsar1\\t%0"
15916 
  [(set_attr "may_trap" "no")
15917 
   (set_attr "latency" "0")
15918 
   (set_attr "length" "4")
15919 
   (set_attr "slot" "cop")
15920 
   (set_attr "slots" "p0s_p1")
15921 
   (set_attr "stall" "none")])
15922 
 
15923 
 
15924 
(define_insn "cgen_intrinsic_cpmovtocsar0_C3"
15925 
  [(set (reg:SI 80)
15926 
        (unspec_volatile:SI [
15927 
          (match_operand:DI 0 "general_operand" "x")
15928 
        ] 3382))]
15929 
  "CGEN_ENABLE_INSN_P (578)"
15930 
  "cpmovtocsar0\\t%0"
15931 
  [(set_attr "may_trap" "no")
15932 
   (set_attr "latency" "0")
15933 
   (set_attr "length" "4")
15934 
   (set_attr "slot" "cop")
15935 
   (set_attr "slots" "c3")
15936 
   (set_attr "stall" "none")])
15937 
 
15938 
 
15939 
(define_insn "cgen_intrinsic_cpmovtocsar0_P0S_P1"
15940 
  [(set (reg:SI 80)
15941 
        (unspec_volatile:SI [
15942 
          (match_operand:DI 0 "general_operand" "x")
15943 
        ] 3382))]
15944 
  "CGEN_ENABLE_INSN_P (579)"
15945 
  "cpmovtocsar0\\t%0"
15946 
  [(set_attr "may_trap" "no")
15947 
   (set_attr "latency" "0")
15948 
   (set_attr "length" "4")
15949 
   (set_attr "slot" "cop")
15950 
   (set_attr "slots" "p0s_p1")
15951 
   (set_attr "stall" "none")])
15952 
 
15953 
 
15954 
(define_insn "cgen_intrinsic_cpmovfrcc_C3"
15955 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
15956 
        (unspec_volatile:DI [
15957 
          (const_int 0)
15958 
        ] 3384))]
15959 
  "CGEN_ENABLE_INSN_P (580)"
15960 
  "cpmovfrcc\\t%0"
15961 
  [(set_attr "may_trap" "no")
15962 
   (set_attr "latency" "0")
15963 
   (set_attr "length" "4")
15964 
   (set_attr "slot" "cop")
15965 
   (set_attr "slots" "c3")
15966 
   (set_attr "stall" "none")])
15967 
 
15968 
 
15969 
(define_insn "cgen_intrinsic_cpmovfrcc_P0S_P1"
15970 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
15971 
        (unspec_volatile:DI [
15972 
          (const_int 0)
15973 
        ] 3384))]
15974 
  "CGEN_ENABLE_INSN_P (581)"
15975 
  "cpmovfrcc\\t%0"
15976 
  [(set_attr "may_trap" "no")
15977 
   (set_attr "latency" "0")
15978 
   (set_attr "length" "4")
15979 
   (set_attr "slot" "cop")
15980 
   (set_attr "slots" "p0s_p1")
15981 
   (set_attr "stall" "none")])
15982 
 
15983 
 
15984 
(define_insn "cgen_intrinsic_cpmovfrcsar1_C3"
15985 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
15986 
        (unspec_volatile:DI [
15987 
          (const_int 0)
15988 
        ] 3386))]
15989 
  "CGEN_ENABLE_INSN_P (582)"
15990 
  "cpmovfrcsar1\\t%0"
15991 
  [(set_attr "may_trap" "no")
15992 
   (set_attr "latency" "0")
15993 
   (set_attr "length" "4")
15994 
   (set_attr "slot" "cop")
15995 
   (set_attr "slots" "c3")
15996 
   (set_attr "stall" "none")])
15997 
 
15998 
 
15999 
(define_insn "cgen_intrinsic_cpmovfrcsar1_P0S_P1"
16000 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16001 
        (unspec_volatile:DI [
16002 
          (const_int 0)
16003 
        ] 3386))]
16004 
  "CGEN_ENABLE_INSN_P (583)"
16005 
  "cpmovfrcsar1\\t%0"
16006 
  [(set_attr "may_trap" "no")
16007 
   (set_attr "latency" "0")
16008 
   (set_attr "length" "4")
16009 
   (set_attr "slot" "cop")
16010 
   (set_attr "slots" "p0s_p1")
16011 
   (set_attr "stall" "none")])
16012 
 
16013 
 
16014 
(define_insn "cgen_intrinsic_cpmovfrcsar0_C3"
16015 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16016 
        (unspec_volatile:DI [
16017 
          (const_int 0)
16018 
        ] 3388))]
16019 
  "CGEN_ENABLE_INSN_P (584)"
16020 
  "cpmovfrcsar0\\t%0"
16021 
  [(set_attr "may_trap" "no")
16022 
   (set_attr "latency" "0")
16023 
   (set_attr "length" "4")
16024 
   (set_attr "slot" "cop")
16025 
   (set_attr "slots" "c3")
16026 
   (set_attr "stall" "none")])
16027 
 
16028 
 
16029 
(define_insn "cgen_intrinsic_cpmovfrcsar0_P0S_P1"
16030 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16031 
        (unspec_volatile:DI [
16032 
          (const_int 0)
16033 
        ] 3388))]
16034 
  "CGEN_ENABLE_INSN_P (585)"
16035 
  "cpmovfrcsar0\\t%0"
16036 
  [(set_attr "may_trap" "no")
16037 
   (set_attr "latency" "0")
16038 
   (set_attr "length" "4")
16039 
   (set_attr "slot" "cop")
16040 
   (set_attr "slots" "p0s_p1")
16041 
   (set_attr "stall" "none")])
16042 
 
16043 
 
16044 
(define_insn "cgen_intrinsic_cdcastw_C3"
16045 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16046 
        (unspec:DI [
16047 
          (match_operand:DI 1 "general_operand" "x")
16048 
        ] 3316))]
16049 
  "CGEN_ENABLE_INSN_P (586)"
16050 
  "cdcastw\\t%0,%1"
16051 
  [(set_attr "may_trap" "no")
16052 
   (set_attr "latency" "0")
16053 
   (set_attr "length" "4")
16054 
   (set_attr "slot" "cop")
16055 
   (set_attr "slots" "c3")
16056 
   (set_attr "stall" "none")])
16057 
 
16058 
 
16059 
(define_insn "cgen_intrinsic_cdcastw_P0S_P1"
16060 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16061 
        (unspec:DI [
16062 
          (match_operand:DI 1 "general_operand" "x")
16063 
        ] 3316))]
16064 
  "CGEN_ENABLE_INSN_P (587)"
16065 
  "cdcastw\\t%0,%1"
16066 
  [(set_attr "may_trap" "no")
16067 
   (set_attr "latency" "0")
16068 
   (set_attr "length" "4")
16069 
   (set_attr "slot" "cop")
16070 
   (set_attr "slots" "p0s_p1")
16071 
   (set_attr "stall" "none")])
16072 
 
16073 
 
16074 
(define_insn "cgen_intrinsic_cdcastuw_C3"
16075 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16076 
        (unspec:DI [
16077 
          (match_operand:DI 1 "general_operand" "x")
16078 
        ] 3318))]
16079 
  "CGEN_ENABLE_INSN_P (588)"
16080 
  "cdcastuw\\t%0,%1"
16081 
  [(set_attr "may_trap" "no")
16082 
   (set_attr "latency" "0")
16083 
   (set_attr "length" "4")
16084 
   (set_attr "slot" "cop")
16085 
   (set_attr "slots" "c3")
16086 
   (set_attr "stall" "none")])
16087 
 
16088 
 
16089 
(define_insn "cgen_intrinsic_cdcastuw_P0S_P1"
16090 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16091 
        (unspec:DI [
16092 
          (match_operand:DI 1 "general_operand" "x")
16093 
        ] 3318))]
16094 
  "CGEN_ENABLE_INSN_P (589)"
16095 
  "cdcastuw\\t%0,%1"
16096 
  [(set_attr "may_trap" "no")
16097 
   (set_attr "latency" "0")
16098 
   (set_attr "length" "4")
16099 
   (set_attr "slot" "cop")
16100 
   (set_attr "slots" "p0s_p1")
16101 
   (set_attr "stall" "none")])
16102 
 
16103 
 
16104 
(define_insn "cgen_intrinsic_cpcasth_w_C3"
16105 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16106 
        (unspec:DI [
16107 
          (match_operand:DI 1 "general_operand" "x")
16108 
        ] 3320))]
16109 
  "CGEN_ENABLE_INSN_P (590)"
16110 
  "cpcasth.w\\t%0,%1"
16111 
  [(set_attr "may_trap" "no")
16112 
   (set_attr "latency" "0")
16113 
   (set_attr "length" "4")
16114 
   (set_attr "slot" "cop")
16115 
   (set_attr "slots" "c3")
16116 
   (set_attr "stall" "none")])
16117 
 
16118 
 
16119 
(define_insn "cgen_intrinsic_cpcasth_w_P0S_P1"
16120 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16121 
        (unspec:DI [
16122 
          (match_operand:DI 1 "general_operand" "x")
16123 
        ] 3320))]
16124 
  "CGEN_ENABLE_INSN_P (591)"
16125 
  "cpcasth.w\\t%0,%1"
16126 
  [(set_attr "may_trap" "no")
16127 
   (set_attr "latency" "0")
16128 
   (set_attr "length" "4")
16129 
   (set_attr "slot" "cop")
16130 
   (set_attr "slots" "p0s_p1")
16131 
   (set_attr "stall" "none")])
16132 
 
16133 
 
16134 
(define_insn "cgen_intrinsic_cpcastuh_w_C3"
16135 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16136 
        (unspec:DI [
16137 
          (match_operand:DI 1 "general_operand" "x")
16138 
        ] 3322))]
16139 
  "CGEN_ENABLE_INSN_P (592)"
16140 
  "cpcastuh.w\\t%0,%1"
16141 
  [(set_attr "may_trap" "no")
16142 
   (set_attr "latency" "0")
16143 
   (set_attr "length" "4")
16144 
   (set_attr "slot" "cop")
16145 
   (set_attr "slots" "c3")
16146 
   (set_attr "stall" "none")])
16147 
 
16148 
 
16149 
(define_insn "cgen_intrinsic_cpcastuh_w_P0S_P1"
16150 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16151 
        (unspec:DI [
16152 
          (match_operand:DI 1 "general_operand" "x")
16153 
        ] 3322))]
16154 
  "CGEN_ENABLE_INSN_P (593)"
16155 
  "cpcastuh.w\\t%0,%1"
16156 
  [(set_attr "may_trap" "no")
16157 
   (set_attr "latency" "0")
16158 
   (set_attr "length" "4")
16159 
   (set_attr "slot" "cop")
16160 
   (set_attr "slots" "p0s_p1")
16161 
   (set_attr "stall" "none")])
16162 
 
16163 
 
16164 
(define_insn "cgen_intrinsic_cpcastb_w_C3"
16165 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16166 
        (unspec:DI [
16167 
          (match_operand:DI 1 "general_operand" "x")
16168 
        ] 3324))]
16169 
  "CGEN_ENABLE_INSN_P (594)"
16170 
  "cpcastb.w\\t%0,%1"
16171 
  [(set_attr "may_trap" "no")
16172 
   (set_attr "latency" "0")
16173 
   (set_attr "length" "4")
16174 
   (set_attr "slot" "cop")
16175 
   (set_attr "slots" "c3")
16176 
   (set_attr "stall" "none")])
16177 
 
16178 
 
16179 
(define_insn "cgen_intrinsic_cpcastb_w_P0S_P1"
16180 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16181 
        (unspec:DI [
16182 
          (match_operand:DI 1 "general_operand" "x")
16183 
        ] 3324))]
16184 
  "CGEN_ENABLE_INSN_P (595)"
16185 
  "cpcastb.w\\t%0,%1"
16186 
  [(set_attr "may_trap" "no")
16187 
   (set_attr "latency" "0")
16188 
   (set_attr "length" "4")
16189 
   (set_attr "slot" "cop")
16190 
   (set_attr "slots" "p0s_p1")
16191 
   (set_attr "stall" "none")])
16192 
 
16193 
 
16194 
(define_insn "cgen_intrinsic_cpcastub_w_C3"
16195 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16196 
        (unspec:DI [
16197 
          (match_operand:DI 1 "general_operand" "x")
16198 
        ] 3326))]
16199 
  "CGEN_ENABLE_INSN_P (596)"
16200 
  "cpcastub.w\\t%0,%1"
16201 
  [(set_attr "may_trap" "no")
16202 
   (set_attr "latency" "0")
16203 
   (set_attr "length" "4")
16204 
   (set_attr "slot" "cop")
16205 
   (set_attr "slots" "c3")
16206 
   (set_attr "stall" "none")])
16207 
 
16208 
 
16209 
(define_insn "cgen_intrinsic_cpcastub_w_P0S_P1"
16210 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16211 
        (unspec:DI [
16212 
          (match_operand:DI 1 "general_operand" "x")
16213 
        ] 3326))]
16214 
  "CGEN_ENABLE_INSN_P (597)"
16215 
  "cpcastub.w\\t%0,%1"
16216 
  [(set_attr "may_trap" "no")
16217 
   (set_attr "latency" "0")
16218 
   (set_attr "length" "4")
16219 
   (set_attr "slot" "cop")
16220 
   (set_attr "slots" "p0s_p1")
16221 
   (set_attr "stall" "none")])
16222 
 
16223 
 
16224 
(define_insn "cgen_intrinsic_cpcastb_h_C3"
16225 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16226 
        (unspec:DI [
16227 
          (match_operand:DI 1 "general_operand" "x")
16228 
        ] 3328))]
16229 
  "CGEN_ENABLE_INSN_P (598)"
16230 
  "cpcastb.h\\t%0,%1"
16231 
  [(set_attr "may_trap" "no")
16232 
   (set_attr "latency" "0")
16233 
   (set_attr "length" "4")
16234 
   (set_attr "slot" "cop")
16235 
   (set_attr "slots" "c3")
16236 
   (set_attr "stall" "none")])
16237 
 
16238 
 
16239 
(define_insn "cgen_intrinsic_cpcastb_h_P0S_P1"
16240 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16241 
        (unspec:DI [
16242 
          (match_operand:DI 1 "general_operand" "x")
16243 
        ] 3328))]
16244 
  "CGEN_ENABLE_INSN_P (599)"
16245 
  "cpcastb.h\\t%0,%1"
16246 
  [(set_attr "may_trap" "no")
16247 
   (set_attr "latency" "0")
16248 
   (set_attr "length" "4")
16249 
   (set_attr "slot" "cop")
16250 
   (set_attr "slots" "p0s_p1")
16251 
   (set_attr "stall" "none")])
16252 
 
16253 
 
16254 
(define_insn "cgen_intrinsic_cpcastub_h_C3"
16255 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16256 
        (unspec:DI [
16257 
          (match_operand:DI 1 "general_operand" "x")
16258 
        ] 3330))]
16259 
  "CGEN_ENABLE_INSN_P (600)"
16260 
  "cpcastub.h\\t%0,%1"
16261 
  [(set_attr "may_trap" "no")
16262 
   (set_attr "latency" "0")
16263 
   (set_attr "length" "4")
16264 
   (set_attr "slot" "cop")
16265 
   (set_attr "slots" "c3")
16266 
   (set_attr "stall" "none")])
16267 
 
16268 
 
16269 
(define_insn "cgen_intrinsic_cpcastub_h_P0S_P1"
16270 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16271 
        (unspec:DI [
16272 
          (match_operand:DI 1 "general_operand" "x")
16273 
        ] 3330))]
16274 
  "CGEN_ENABLE_INSN_P (601)"
16275 
  "cpcastub.h\\t%0,%1"
16276 
  [(set_attr "may_trap" "no")
16277 
   (set_attr "latency" "0")
16278 
   (set_attr "length" "4")
16279 
   (set_attr "slot" "cop")
16280 
   (set_attr "slots" "p0s_p1")
16281 
   (set_attr "stall" "none")])
16282 
 
16283 
 
16284 
(define_insn "cgen_intrinsic_cpextl_h_C3"
16285 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16286 
        (unspec:DI [
16287 
          (match_operand:DI 1 "general_operand" "x")
16288 
        ] 3332))]
16289 
  "CGEN_ENABLE_INSN_P (602)"
16290 
  "cpextl.h\\t%0,%1"
16291 
  [(set_attr "may_trap" "no")
16292 
   (set_attr "latency" "0")
16293 
   (set_attr "length" "4")
16294 
   (set_attr "slot" "cop")
16295 
   (set_attr "slots" "c3")
16296 
   (set_attr "stall" "none")])
16297 
 
16298 
 
16299 
(define_insn "cgen_intrinsic_cpextl_h_P0S_P1"
16300 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16301 
        (unspec:DI [
16302 
          (match_operand:DI 1 "general_operand" "x")
16303 
        ] 3332))]
16304 
  "CGEN_ENABLE_INSN_P (603)"
16305 
  "cpextl.h\\t%0,%1"
16306 
  [(set_attr "may_trap" "no")
16307 
   (set_attr "latency" "0")
16308 
   (set_attr "length" "4")
16309 
   (set_attr "slot" "cop")
16310 
   (set_attr "slots" "p0s_p1")
16311 
   (set_attr "stall" "none")])
16312 
 
16313 
 
16314 
(define_insn "cgen_intrinsic_cpextlu_h_C3"
16315 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16316 
        (unspec:DI [
16317 
          (match_operand:DI 1 "general_operand" "x")
16318 
        ] 3334))]
16319 
  "CGEN_ENABLE_INSN_P (604)"
16320 
  "cpextlu.h\\t%0,%1"
16321 
  [(set_attr "may_trap" "no")
16322 
   (set_attr "latency" "0")
16323 
   (set_attr "length" "4")
16324 
   (set_attr "slot" "cop")
16325 
   (set_attr "slots" "c3")
16326 
   (set_attr "stall" "none")])
16327 
 
16328 
 
16329 
(define_insn "cgen_intrinsic_cpextlu_h_P0S_P1"
16330 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16331 
        (unspec:DI [
16332 
          (match_operand:DI 1 "general_operand" "x")
16333 
        ] 3334))]
16334 
  "CGEN_ENABLE_INSN_P (605)"
16335 
  "cpextlu.h\\t%0,%1"
16336 
  [(set_attr "may_trap" "no")
16337 
   (set_attr "latency" "0")
16338 
   (set_attr "length" "4")
16339 
   (set_attr "slot" "cop")
16340 
   (set_attr "slots" "p0s_p1")
16341 
   (set_attr "stall" "none")])
16342 
 
16343 
 
16344 
(define_insn "cgen_intrinsic_cpextl_b_C3"
16345 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16346 
        (unspec:DI [
16347 
          (match_operand:DI 1 "general_operand" "x")
16348 
        ] 3336))]
16349 
  "CGEN_ENABLE_INSN_P (606)"
16350 
  "cpextl.b\\t%0,%1"
16351 
  [(set_attr "may_trap" "no")
16352 
   (set_attr "latency" "0")
16353 
   (set_attr "length" "4")
16354 
   (set_attr "slot" "cop")
16355 
   (set_attr "slots" "c3")
16356 
   (set_attr "stall" "none")])
16357 
 
16358 
 
16359 
(define_insn "cgen_intrinsic_cpextl_b_P0S_P1"
16360 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16361 
        (unspec:DI [
16362 
          (match_operand:DI 1 "general_operand" "x")
16363 
        ] 3336))]
16364 
  "CGEN_ENABLE_INSN_P (607)"
16365 
  "cpextl.b\\t%0,%1"
16366 
  [(set_attr "may_trap" "no")
16367 
   (set_attr "latency" "0")
16368 
   (set_attr "length" "4")
16369 
   (set_attr "slot" "cop")
16370 
   (set_attr "slots" "p0s_p1")
16371 
   (set_attr "stall" "none")])
16372 
 
16373 
 
16374 
(define_insn "cgen_intrinsic_cpextlu_b_C3"
16375 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16376 
        (unspec:DI [
16377 
          (match_operand:DI 1 "general_operand" "x")
16378 
        ] 3338))]
16379 
  "CGEN_ENABLE_INSN_P (608)"
16380 
  "cpextlu.b\\t%0,%1"
16381 
  [(set_attr "may_trap" "no")
16382 
   (set_attr "latency" "0")
16383 
   (set_attr "length" "4")
16384 
   (set_attr "slot" "cop")
16385 
   (set_attr "slots" "c3")
16386 
   (set_attr "stall" "none")])
16387 
 
16388 
 
16389 
(define_insn "cgen_intrinsic_cpextlu_b_P0S_P1"
16390 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16391 
        (unspec:DI [
16392 
          (match_operand:DI 1 "general_operand" "x")
16393 
        ] 3338))]
16394 
  "CGEN_ENABLE_INSN_P (609)"
16395 
  "cpextlu.b\\t%0,%1"
16396 
  [(set_attr "may_trap" "no")
16397 
   (set_attr "latency" "0")
16398 
   (set_attr "length" "4")
16399 
   (set_attr "slot" "cop")
16400 
   (set_attr "slots" "p0s_p1")
16401 
   (set_attr "stall" "none")])
16402 
 
16403 
 
16404 
(define_insn "cgen_intrinsic_cpextu_h_C3"
16405 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16406 
        (unspec:DI [
16407 
          (match_operand:DI 1 "general_operand" "x")
16408 
        ] 3340))]
16409 
  "CGEN_ENABLE_INSN_P (610)"
16410 
  "cpextu.h\\t%0,%1"
16411 
  [(set_attr "may_trap" "no")
16412 
   (set_attr "latency" "0")
16413 
   (set_attr "length" "4")
16414 
   (set_attr "slot" "cop")
16415 
   (set_attr "slots" "c3")
16416 
   (set_attr "stall" "none")])
16417 
 
16418 
 
16419 
(define_insn "cgen_intrinsic_cpextu_h_P0S_P1"
16420 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16421 
        (unspec:DI [
16422 
          (match_operand:DI 1 "general_operand" "x")
16423 
        ] 3340))]
16424 
  "CGEN_ENABLE_INSN_P (611)"
16425 
  "cpextu.h\\t%0,%1"
16426 
  [(set_attr "may_trap" "no")
16427 
   (set_attr "latency" "0")
16428 
   (set_attr "length" "4")
16429 
   (set_attr "slot" "cop")
16430 
   (set_attr "slots" "p0s_p1")
16431 
   (set_attr "stall" "none")])
16432 
 
16433 
 
16434 
(define_insn "cgen_intrinsic_cpextuu_h_C3"
16435 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16436 
        (unspec:DI [
16437 
          (match_operand:DI 1 "general_operand" "x")
16438 
        ] 3342))]
16439 
  "CGEN_ENABLE_INSN_P (612)"
16440 
  "cpextuu.h\\t%0,%1"
16441 
  [(set_attr "may_trap" "no")
16442 
   (set_attr "latency" "0")
16443 
   (set_attr "length" "4")
16444 
   (set_attr "slot" "cop")
16445 
   (set_attr "slots" "c3")
16446 
   (set_attr "stall" "none")])
16447 
 
16448 
 
16449 
(define_insn "cgen_intrinsic_cpextuu_h_P0S_P1"
16450 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16451 
        (unspec:DI [
16452 
          (match_operand:DI 1 "general_operand" "x")
16453 
        ] 3342))]
16454 
  "CGEN_ENABLE_INSN_P (613)"
16455 
  "cpextuu.h\\t%0,%1"
16456 
  [(set_attr "may_trap" "no")
16457 
   (set_attr "latency" "0")
16458 
   (set_attr "length" "4")
16459 
   (set_attr "slot" "cop")
16460 
   (set_attr "slots" "p0s_p1")
16461 
   (set_attr "stall" "none")])
16462 
 
16463 
 
16464 
(define_insn "cgen_intrinsic_cpextu_b_C3"
16465 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16466 
        (unspec:DI [
16467 
          (match_operand:DI 1 "general_operand" "x")
16468 
        ] 3344))]
16469 
  "CGEN_ENABLE_INSN_P (614)"
16470 
  "cpextu.b\\t%0,%1"
16471 
  [(set_attr "may_trap" "no")
16472 
   (set_attr "latency" "0")
16473 
   (set_attr "length" "4")
16474 
   (set_attr "slot" "cop")
16475 
   (set_attr "slots" "c3")
16476 
   (set_attr "stall" "none")])
16477 
 
16478 
 
16479 
(define_insn "cgen_intrinsic_cpextu_b_P0S_P1"
16480 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16481 
        (unspec:DI [
16482 
          (match_operand:DI 1 "general_operand" "x")
16483 
        ] 3344))]
16484 
  "CGEN_ENABLE_INSN_P (615)"
16485 
  "cpextu.b\\t%0,%1"
16486 
  [(set_attr "may_trap" "no")
16487 
   (set_attr "latency" "0")
16488 
   (set_attr "length" "4")
16489 
   (set_attr "slot" "cop")
16490 
   (set_attr "slots" "p0s_p1")
16491 
   (set_attr "stall" "none")])
16492 
 
16493 
 
16494 
(define_insn "cgen_intrinsic_cpextuu_b_C3"
16495 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16496 
        (unspec:DI [
16497 
          (match_operand:DI 1 "general_operand" "x")
16498 
        ] 3346))]
16499 
  "CGEN_ENABLE_INSN_P (616)"
16500 
  "cpextuu.b\\t%0,%1"
16501 
  [(set_attr "may_trap" "no")
16502 
   (set_attr "latency" "0")
16503 
   (set_attr "length" "4")
16504 
   (set_attr "slot" "cop")
16505 
   (set_attr "slots" "c3")
16506 
   (set_attr "stall" "none")])
16507 
 
16508 
 
16509 
(define_insn "cgen_intrinsic_cpextuu_b_P0S_P1"
16510 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16511 
        (unspec:DI [
16512 
          (match_operand:DI 1 "general_operand" "x")
16513 
        ] 3346))]
16514 
  "CGEN_ENABLE_INSN_P (617)"
16515 
  "cpextuu.b\\t%0,%1"
16516 
  [(set_attr "may_trap" "no")
16517 
   (set_attr "latency" "0")
16518 
   (set_attr "length" "4")
16519 
   (set_attr "slot" "cop")
16520 
   (set_attr "slots" "p0s_p1")
16521 
   (set_attr "stall" "none")])
16522 
 
16523 
 
16524 
(define_insn "cgen_intrinsic_cpbcast_w_C3"
16525 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16526 
        (unspec:DI [
16527 
          (match_operand:DI 1 "general_operand" "x")
16528 
        ] 3348))]
16529 
  "CGEN_ENABLE_INSN_P (618)"
16530 
  "cpbcast.w\\t%0,%1"
16531 
  [(set_attr "may_trap" "no")
16532 
   (set_attr "latency" "0")
16533 
   (set_attr "length" "4")
16534 
   (set_attr "slot" "cop")
16535 
   (set_attr "slots" "c3")
16536 
   (set_attr "stall" "none")])
16537 
 
16538 
 
16539 
(define_insn "cgen_intrinsic_cpbcast_w_P0S_P1"
16540 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16541 
        (unspec:DI [
16542 
          (match_operand:DI 1 "general_operand" "x")
16543 
        ] 3348))]
16544 
  "CGEN_ENABLE_INSN_P (619)"
16545 
  "cpbcast.w\\t%0,%1"
16546 
  [(set_attr "may_trap" "no")
16547 
   (set_attr "latency" "0")
16548 
   (set_attr "length" "4")
16549 
   (set_attr "slot" "cop")
16550 
   (set_attr "slots" "p0s_p1")
16551 
   (set_attr "stall" "none")])
16552 
 
16553 
 
16554 
(define_insn "cgen_intrinsic_cpbcast_h_C3"
16555 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16556 
        (unspec:DI [
16557 
          (match_operand:DI 1 "general_operand" "x")
16558 
        ] 3350))]
16559 
  "CGEN_ENABLE_INSN_P (620)"
16560 
  "cpbcast.h\\t%0,%1"
16561 
  [(set_attr "may_trap" "no")
16562 
   (set_attr "latency" "0")
16563 
   (set_attr "length" "4")
16564 
   (set_attr "slot" "cop")
16565 
   (set_attr "slots" "c3")
16566 
   (set_attr "stall" "none")])
16567 
 
16568 
 
16569 
(define_insn "cgen_intrinsic_cpbcast_h_P0S_P1"
16570 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16571 
        (unspec:DI [
16572 
          (match_operand:DI 1 "general_operand" "x")
16573 
        ] 3350))]
16574 
  "CGEN_ENABLE_INSN_P (621)"
16575 
  "cpbcast.h\\t%0,%1"
16576 
  [(set_attr "may_trap" "no")
16577 
   (set_attr "latency" "0")
16578 
   (set_attr "length" "4")
16579 
   (set_attr "slot" "cop")
16580 
   (set_attr "slots" "p0s_p1")
16581 
   (set_attr "stall" "none")])
16582 
 
16583 
 
16584 
(define_insn "cgen_intrinsic_cpbcast_b_C3"
16585 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16586 
        (unspec:DI [
16587 
          (match_operand:DI 1 "general_operand" "x")
16588 
        ] 3352))]
16589 
  "CGEN_ENABLE_INSN_P (622)"
16590 
  "cpbcast.b\\t%0,%1"
16591 
  [(set_attr "may_trap" "no")
16592 
   (set_attr "latency" "0")
16593 
   (set_attr "length" "4")
16594 
   (set_attr "slot" "cop")
16595 
   (set_attr "slots" "c3")
16596 
   (set_attr "stall" "none")])
16597 
 
16598 
 
16599 
(define_insn "cgen_intrinsic_cpbcast_b_P0S_P1"
16600 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16601 
        (unspec:DI [
16602 
          (match_operand:DI 1 "general_operand" "x")
16603 
        ] 3352))]
16604 
  "CGEN_ENABLE_INSN_P (623)"
16605 
  "cpbcast.b\\t%0,%1"
16606 
  [(set_attr "may_trap" "no")
16607 
   (set_attr "latency" "0")
16608 
   (set_attr "length" "4")
16609 
   (set_attr "slot" "cop")
16610 
   (set_attr "slots" "p0s_p1")
16611 
   (set_attr "stall" "none")])
16612 
 
16613 
 
16614 
(define_insn "cgen_intrinsic_cpccadd_b_C3"
16615 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16616 
        (unspec_volatile:DI [
16617 
          (match_operand:DI 1 "general_operand" "0")
16618 
        ] 3354))]
16619 
  "CGEN_ENABLE_INSN_P (624)"
16620 
  "cpccadd.b\\t%1"
16621 
  [(set_attr "may_trap" "no")
16622 
   (set_attr "latency" "0")
16623 
   (set_attr "length" "4")
16624 
   (set_attr "slot" "cop")
16625 
   (set_attr "slots" "c3")
16626 
   (set_attr "stall" "none")])
16627 
 
16628 
 
16629 
(define_insn "cgen_intrinsic_cpccadd_b_P0S_P1"
16630 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16631 
        (unspec_volatile:DI [
16632 
          (match_operand:DI 1 "general_operand" "0")
16633 
        ] 3354))]
16634 
  "CGEN_ENABLE_INSN_P (625)"
16635 
  "cpccadd.b\\t%1"
16636 
  [(set_attr "may_trap" "no")
16637 
   (set_attr "latency" "0")
16638 
   (set_attr "length" "4")
16639 
   (set_attr "slot" "cop")
16640 
   (set_attr "slots" "p0s_p1")
16641 
   (set_attr "stall" "none")])
16642 
 
16643 
 
16644 
(define_insn "cgen_intrinsic_cphadd_w_C3"
16645 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16646 
        (unspec:DI [
16647 
          (match_operand:DI 1 "general_operand" "x")
16648 
        ] 3356))]
16649 
  "CGEN_ENABLE_INSN_P (626)"
16650 
  "cphadd.w\\t%0,%1"
16651 
  [(set_attr "may_trap" "no")
16652 
   (set_attr "latency" "0")
16653 
   (set_attr "length" "4")
16654 
   (set_attr "slot" "cop")
16655 
   (set_attr "slots" "c3")
16656 
   (set_attr "stall" "none")])
16657 
 
16658 
 
16659 
(define_insn "cgen_intrinsic_cphadd_w_P0S_P1"
16660 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16661 
        (unspec:DI [
16662 
          (match_operand:DI 1 "general_operand" "x")
16663 
        ] 3356))]
16664 
  "CGEN_ENABLE_INSN_P (627)"
16665 
  "cphadd.w\\t%0,%1"
16666 
  [(set_attr "may_trap" "no")
16667 
   (set_attr "latency" "0")
16668 
   (set_attr "length" "4")
16669 
   (set_attr "slot" "cop")
16670 
   (set_attr "slots" "p0s_p1")
16671 
   (set_attr "stall" "none")])
16672 
 
16673 
 
16674 
(define_insn "cgen_intrinsic_cphadd_h_C3"
16675 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16676 
        (unspec:DI [
16677 
          (match_operand:DI 1 "general_operand" "x")
16678 
        ] 3358))]
16679 
  "CGEN_ENABLE_INSN_P (628)"
16680 
  "cphadd.h\\t%0,%1"
16681 
  [(set_attr "may_trap" "no")
16682 
   (set_attr "latency" "0")
16683 
   (set_attr "length" "4")
16684 
   (set_attr "slot" "cop")
16685 
   (set_attr "slots" "c3")
16686 
   (set_attr "stall" "none")])
16687 
 
16688 
 
16689 
(define_insn "cgen_intrinsic_cphadd_h_P0S_P1"
16690 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16691 
        (unspec:DI [
16692 
          (match_operand:DI 1 "general_operand" "x")
16693 
        ] 3358))]
16694 
  "CGEN_ENABLE_INSN_P (629)"
16695 
  "cphadd.h\\t%0,%1"
16696 
  [(set_attr "may_trap" "no")
16697 
   (set_attr "latency" "0")
16698 
   (set_attr "length" "4")
16699 
   (set_attr "slot" "cop")
16700 
   (set_attr "slots" "p0s_p1")
16701 
   (set_attr "stall" "none")])
16702 
 
16703 
 
16704 
(define_insn "cgen_intrinsic_cphadd_b_C3"
16705 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16706 
        (unspec:DI [
16707 
          (match_operand:DI 1 "general_operand" "x")
16708 
        ] 3360))]
16709 
  "CGEN_ENABLE_INSN_P (630)"
16710 
  "cphadd.b\\t%0,%1"
16711 
  [(set_attr "may_trap" "no")
16712 
   (set_attr "latency" "0")
16713 
   (set_attr "length" "4")
16714 
   (set_attr "slot" "cop")
16715 
   (set_attr "slots" "c3")
16716 
   (set_attr "stall" "none")])
16717 
 
16718 
 
16719 
(define_insn "cgen_intrinsic_cphadd_b_P0S_P1"
16720 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16721 
        (unspec:DI [
16722 
          (match_operand:DI 1 "general_operand" "x")
16723 
        ] 3360))]
16724 
  "CGEN_ENABLE_INSN_P (631)"
16725 
  "cphadd.b\\t%0,%1"
16726 
  [(set_attr "may_trap" "no")
16727 
   (set_attr "latency" "0")
16728 
   (set_attr "length" "4")
16729 
   (set_attr "slot" "cop")
16730 
   (set_attr "slots" "p0s_p1")
16731 
   (set_attr "stall" "none")])
16732 
 
16733 
 
16734 
(define_insn "cgen_intrinsic_cphaddu_b_C3"
16735 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16736 
        (unspec:DI [
16737 
          (match_operand:DI 1 "general_operand" "x")
16738 
        ] 3362))]
16739 
  "CGEN_ENABLE_INSN_P (632)"
16740 
  "cphaddu.b\\t%0,%1"
16741 
  [(set_attr "may_trap" "no")
16742 
   (set_attr "latency" "0")
16743 
   (set_attr "length" "4")
16744 
   (set_attr "slot" "cop")
16745 
   (set_attr "slots" "c3")
16746 
   (set_attr "stall" "none")])
16747 
 
16748 
 
16749 
(define_insn "cgen_intrinsic_cphaddu_b_P0S_P1"
16750 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16751 
        (unspec:DI [
16752 
          (match_operand:DI 1 "general_operand" "x")
16753 
        ] 3362))]
16754 
  "CGEN_ENABLE_INSN_P (633)"
16755 
  "cphaddu.b\\t%0,%1"
16756 
  [(set_attr "may_trap" "no")
16757 
   (set_attr "latency" "0")
16758 
   (set_attr "length" "4")
16759 
   (set_attr "slot" "cop")
16760 
   (set_attr "slots" "p0s_p1")
16761 
   (set_attr "stall" "none")])
16762 
 
16763 
 
16764 
(define_insn "cgen_intrinsic_cpnorm_w_C3"
16765 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16766 
        (unspec:DI [
16767 
          (match_operand:DI 1 "general_operand" "x")
16768 
        ] 3364))]
16769 
  "CGEN_ENABLE_INSN_P (634)"
16770 
  "cpnorm.w\\t%0,%1"
16771 
  [(set_attr "may_trap" "no")
16772 
   (set_attr "latency" "0")
16773 
   (set_attr "length" "4")
16774 
   (set_attr "slot" "cop")
16775 
   (set_attr "slots" "c3")
16776 
   (set_attr "stall" "none")])
16777 
 
16778 
 
16779 
(define_insn "cgen_intrinsic_cpnorm_w_P0S_P1"
16780 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16781 
        (unspec:DI [
16782 
          (match_operand:DI 1 "general_operand" "x")
16783 
        ] 3364))]
16784 
  "CGEN_ENABLE_INSN_P (635)"
16785 
  "cpnorm.w\\t%0,%1"
16786 
  [(set_attr "may_trap" "no")
16787 
   (set_attr "latency" "0")
16788 
   (set_attr "length" "4")
16789 
   (set_attr "slot" "cop")
16790 
   (set_attr "slots" "p0s_p1")
16791 
   (set_attr "stall" "none")])
16792 
 
16793 
 
16794 
(define_insn "cgen_intrinsic_cpnorm_h_C3"
16795 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16796 
        (unspec:DI [
16797 
          (match_operand:DI 1 "general_operand" "x")
16798 
        ] 3366))]
16799 
  "CGEN_ENABLE_INSN_P (636)"
16800 
  "cpnorm.h\\t%0,%1"
16801 
  [(set_attr "may_trap" "no")
16802 
   (set_attr "latency" "0")
16803 
   (set_attr "length" "4")
16804 
   (set_attr "slot" "cop")
16805 
   (set_attr "slots" "c3")
16806 
   (set_attr "stall" "none")])
16807 
 
16808 
 
16809 
(define_insn "cgen_intrinsic_cpnorm_h_P0S_P1"
16810 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16811 
        (unspec:DI [
16812 
          (match_operand:DI 1 "general_operand" "x")
16813 
        ] 3366))]
16814 
  "CGEN_ENABLE_INSN_P (637)"
16815 
  "cpnorm.h\\t%0,%1"
16816 
  [(set_attr "may_trap" "no")
16817 
   (set_attr "latency" "0")
16818 
   (set_attr "length" "4")
16819 
   (set_attr "slot" "cop")
16820 
   (set_attr "slots" "p0s_p1")
16821 
   (set_attr "stall" "none")])
16822 
 
16823 
 
16824 
(define_insn "cgen_intrinsic_cpldz_w_C3"
16825 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16826 
        (unspec:DI [
16827 
          (match_operand:DI 1 "general_operand" "x")
16828 
        ] 3368))]
16829 
  "CGEN_ENABLE_INSN_P (638)"
16830 
  "cpldz.w\\t%0,%1"
16831 
  [(set_attr "may_trap" "no")
16832 
   (set_attr "latency" "0")
16833 
   (set_attr "length" "4")
16834 
   (set_attr "slot" "cop")
16835 
   (set_attr "slots" "c3")
16836 
   (set_attr "stall" "none")])
16837 
 
16838 
 
16839 
(define_insn "cgen_intrinsic_cpldz_w_P0S_P1"
16840 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16841 
        (unspec:DI [
16842 
          (match_operand:DI 1 "general_operand" "x")
16843 
        ] 3368))]
16844 
  "CGEN_ENABLE_INSN_P (639)"
16845 
  "cpldz.w\\t%0,%1"
16846 
  [(set_attr "may_trap" "no")
16847 
   (set_attr "latency" "0")
16848 
   (set_attr "length" "4")
16849 
   (set_attr "slot" "cop")
16850 
   (set_attr "slots" "p0s_p1")
16851 
   (set_attr "stall" "none")])
16852 
 
16853 
 
16854 
(define_insn "cgen_intrinsic_cpldz_h_C3"
16855 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16856 
        (unspec:DI [
16857 
          (match_operand:DI 1 "general_operand" "x")
16858 
        ] 3370))]
16859 
  "CGEN_ENABLE_INSN_P (640)"
16860 
  "cpldz.h\\t%0,%1"
16861 
  [(set_attr "may_trap" "no")
16862 
   (set_attr "latency" "0")
16863 
   (set_attr "length" "4")
16864 
   (set_attr "slot" "cop")
16865 
   (set_attr "slots" "c3")
16866 
   (set_attr "stall" "none")])
16867 
 
16868 
 
16869 
(define_insn "cgen_intrinsic_cpldz_h_P0S_P1"
16870 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16871 
        (unspec:DI [
16872 
          (match_operand:DI 1 "general_operand" "x")
16873 
        ] 3370))]
16874 
  "CGEN_ENABLE_INSN_P (641)"
16875 
  "cpldz.h\\t%0,%1"
16876 
  [(set_attr "may_trap" "no")
16877 
   (set_attr "latency" "0")
16878 
   (set_attr "length" "4")
16879 
   (set_attr "slot" "cop")
16880 
   (set_attr "slots" "p0s_p1")
16881 
   (set_attr "stall" "none")])
16882 
 
16883 
 
16884 
(define_insn "cgen_intrinsic_cpabsz_w_C3"
16885 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16886 
        (unspec:DI [
16887 
          (match_operand:DI 1 "general_operand" "x")
16888 
        ] 3372))]
16889 
  "CGEN_ENABLE_INSN_P (642)"
16890 
  "cpabsz.w\\t%0,%1"
16891 
  [(set_attr "may_trap" "no")
16892 
   (set_attr "latency" "0")
16893 
   (set_attr "length" "4")
16894 
   (set_attr "slot" "cop")
16895 
   (set_attr "slots" "c3")
16896 
   (set_attr "stall" "none")])
16897 
 
16898 
 
16899 
(define_insn "cgen_intrinsic_cpabsz_w_P0S_P1"
16900 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16901 
        (unspec:DI [
16902 
          (match_operand:DI 1 "general_operand" "x")
16903 
        ] 3372))]
16904 
  "CGEN_ENABLE_INSN_P (643)"
16905 
  "cpabsz.w\\t%0,%1"
16906 
  [(set_attr "may_trap" "no")
16907 
   (set_attr "latency" "0")
16908 
   (set_attr "length" "4")
16909 
   (set_attr "slot" "cop")
16910 
   (set_attr "slots" "p0s_p1")
16911 
   (set_attr "stall" "none")])
16912 
 
16913 
 
16914 
(define_insn "cgen_intrinsic_cpabsz_h_C3"
16915 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16916 
        (unspec:DI [
16917 
          (match_operand:DI 1 "general_operand" "x")
16918 
        ] 3374))]
16919 
  "CGEN_ENABLE_INSN_P (644)"
16920 
  "cpabsz.h\\t%0,%1"
16921 
  [(set_attr "may_trap" "no")
16922 
   (set_attr "latency" "0")
16923 
   (set_attr "length" "4")
16924 
   (set_attr "slot" "cop")
16925 
   (set_attr "slots" "c3")
16926 
   (set_attr "stall" "none")])
16927 
 
16928 
 
16929 
(define_insn "cgen_intrinsic_cpabsz_h_P0S_P1"
16930 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16931 
        (unspec:DI [
16932 
          (match_operand:DI 1 "general_operand" "x")
16933 
        ] 3374))]
16934 
  "CGEN_ENABLE_INSN_P (645)"
16935 
  "cpabsz.h\\t%0,%1"
16936 
  [(set_attr "may_trap" "no")
16937 
   (set_attr "latency" "0")
16938 
   (set_attr "length" "4")
16939 
   (set_attr "slot" "cop")
16940 
   (set_attr "slots" "p0s_p1")
16941 
   (set_attr "stall" "none")])
16942 
 
16943 
 
16944 
(define_insn "cgen_intrinsic_cpabsz_b_C3"
16945 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16946 
        (unspec:DI [
16947 
          (match_operand:DI 1 "general_operand" "x")
16948 
        ] 3376))]
16949 
  "CGEN_ENABLE_INSN_P (646)"
16950 
  "cpabsz.b\\t%0,%1"
16951 
  [(set_attr "may_trap" "no")
16952 
   (set_attr "latency" "0")
16953 
   (set_attr "length" "4")
16954 
   (set_attr "slot" "cop")
16955 
   (set_attr "slots" "c3")
16956 
   (set_attr "stall" "none")])
16957 
 
16958 
 
16959 
(define_insn "cgen_intrinsic_cpabsz_b_P0S_P1"
16960 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16961 
        (unspec:DI [
16962 
          (match_operand:DI 1 "general_operand" "x")
16963 
        ] 3376))]
16964 
  "CGEN_ENABLE_INSN_P (647)"
16965 
  "cpabsz.b\\t%0,%1"
16966 
  [(set_attr "may_trap" "no")
16967 
   (set_attr "latency" "0")
16968 
   (set_attr "length" "4")
16969 
   (set_attr "slot" "cop")
16970 
   (set_attr "slots" "p0s_p1")
16971 
   (set_attr "stall" "none")])
16972 
 
16973 
 
16974 
(define_insn "cgen_intrinsic_cpmov_C3"
16975 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16976 
        (unspec:DI [
16977 
          (match_operand:DI 1 "general_operand" "x")
16978 
        ] 4172))]
16979 
  "CGEN_ENABLE_INSN_P (648)"
16980 
  "cpmov\\t%0,%1"
16981 
  [(set_attr "may_trap" "no")
16982 
   (set_attr "latency" "0")
16983 
   (set_attr "length" "4")
16984 
   (set_attr "slot" "cop")
16985 
   (set_attr "slots" "c3")
16986 
   (set_attr "stall" "none")])
16987 
 
16988 
 
16989 
(define_insn "cgen_intrinsic_cpmov_P0S_P1"
16990 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16991 
        (unspec:DI [
16992 
          (match_operand:DI 1 "general_operand" "x")
16993 
        ] 4172))]
16994 
  "CGEN_ENABLE_INSN_P (649)"
16995 
  "cpmov\\t%0,%1"
16996 
  [(set_attr "may_trap" "no")
16997 
   (set_attr "latency" "0")
16998 
   (set_attr "length" "4")
16999 
   (set_attr "slot" "cop")
17000 
   (set_attr "slots" "p0s_p1")
17001 
   (set_attr "stall" "none")])
17002 
 
17003 
 
17004 
(define_insn "cgen_intrinsic_cpfsftbs1_C3"
17005 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17006 
        (unspec_volatile:DI [
17007 
          (match_operand:DI 1 "general_operand" "x")
17008 
          (match_operand:DI 2 "general_operand" "x")
17009 
        ] 3524))]
17010 
  "CGEN_ENABLE_INSN_P (650)"
17011 
  "cpfsftbs1\\t%0,%1,%2"
17012 
  [(set_attr "may_trap" "no")
17013 
   (set_attr "latency" "0")
17014 
   (set_attr "length" "4")
17015 
   (set_attr "slot" "cop")
17016 
   (set_attr "slots" "c3")
17017 
   (set_attr "stall" "none")])
17018 
 
17019 
 
17020 
(define_insn "cgen_intrinsic_cpfsftbs1_P0S_P1"
17021 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17022 
        (unspec_volatile:DI [
17023 
          (match_operand:DI 1 "general_operand" "x")
17024 
          (match_operand:DI 2 "general_operand" "x")
17025 
        ] 3524))]
17026 
  "CGEN_ENABLE_INSN_P (651)"
17027 
  "cpfsftbs1\\t%0,%1,%2"
17028 
  [(set_attr "may_trap" "no")
17029 
   (set_attr "latency" "0")
17030 
   (set_attr "length" "4")
17031 
   (set_attr "slot" "cop")
17032 
   (set_attr "slots" "p0s_p1")
17033 
   (set_attr "stall" "none")])
17034 
 
17035 
 
17036 
(define_insn "cgen_intrinsic_cpfsftbs0_C3"
17037 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17038 
        (unspec_volatile:DI [
17039 
          (match_operand:DI 1 "general_operand" "x")
17040 
          (match_operand:DI 2 "general_operand" "x")
17041 
        ] 3526))]
17042 
  "CGEN_ENABLE_INSN_P (652)"
17043 
  "cpfsftbs0\\t%0,%1,%2"
17044 
  [(set_attr "may_trap" "no")
17045 
   (set_attr "latency" "0")
17046 
   (set_attr "length" "4")
17047 
   (set_attr "slot" "cop")
17048 
   (set_attr "slots" "c3")
17049 
   (set_attr "stall" "none")])
17050 
 
17051 
 
17052 
(define_insn "cgen_intrinsic_cpfsftbs0_P0S_P1"
17053 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17054 
        (unspec_volatile:DI [
17055 
          (match_operand:DI 1 "general_operand" "x")
17056 
          (match_operand:DI 2 "general_operand" "x")
17057 
        ] 3526))]
17058 
  "CGEN_ENABLE_INSN_P (653)"
17059 
  "cpfsftbs0\\t%0,%1,%2"
17060 
  [(set_attr "may_trap" "no")
17061 
   (set_attr "latency" "0")
17062 
   (set_attr "length" "4")
17063 
   (set_attr "slot" "cop")
17064 
   (set_attr "slots" "p0s_p1")
17065 
   (set_attr "stall" "none")])
17066 
 
17067 
 
17068 
(define_insn "cgen_intrinsic_cpsel_C3"
17069 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17070 
        (unspec_volatile:DI [
17071 
          (match_operand:DI 1 "general_operand" "x")
17072 
          (match_operand:DI 2 "general_operand" "x")
17073 
        ] 3530))]
17074 
  "CGEN_ENABLE_INSN_P (654)"
17075 
  "cpsel\\t%0,%1,%2"
17076 
  [(set_attr "may_trap" "no")
17077 
   (set_attr "latency" "0")
17078 
   (set_attr "length" "4")
17079 
   (set_attr "slot" "cop")
17080 
   (set_attr "slots" "c3")
17081 
   (set_attr "stall" "none")])
17082 
 
17083 
 
17084 
(define_insn "cgen_intrinsic_cpsel_P0S_P1"
17085 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17086 
        (unspec_volatile:DI [
17087 
          (match_operand:DI 1 "general_operand" "x")
17088 
          (match_operand:DI 2 "general_operand" "x")
17089 
        ] 3530))]
17090 
  "CGEN_ENABLE_INSN_P (655)"
17091 
  "cpsel\\t%0,%1,%2"
17092 
  [(set_attr "may_trap" "no")
17093 
   (set_attr "latency" "0")
17094 
   (set_attr "length" "4")
17095 
   (set_attr "slot" "cop")
17096 
   (set_attr "slots" "p0s_p1")
17097 
   (set_attr "stall" "none")])
17098 
 
17099 
 
17100 
(define_insn "cgen_intrinsic_cpunpackl_w_C3"
17101 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17102 
        (unspec:DI [
17103 
          (match_operand:DI 1 "general_operand" "x")
17104 
          (match_operand:DI 2 "general_operand" "x")
17105 
        ] 3512))]
17106 
  "CGEN_ENABLE_INSN_P (656)"
17107 
  "cpunpackl.w\\t%0,%1,%2"
17108 
  [(set_attr "may_trap" "no")
17109 
   (set_attr "latency" "0")
17110 
   (set_attr "length" "4")
17111 
   (set_attr "slot" "cop")
17112 
   (set_attr "slots" "c3")
17113 
   (set_attr "stall" "none")])
17114 
 
17115 
 
17116 
(define_insn "cgen_intrinsic_cpunpackl_w_P0S_P1"
17117 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17118 
        (unspec:DI [
17119 
          (match_operand:DI 1 "general_operand" "x")
17120 
          (match_operand:DI 2 "general_operand" "x")
17121 
        ] 3512))]
17122 
  "CGEN_ENABLE_INSN_P (657)"
17123 
  "cpunpackl.w\\t%0,%1,%2"
17124 
  [(set_attr "may_trap" "no")
17125 
   (set_attr "latency" "0")
17126 
   (set_attr "length" "4")
17127 
   (set_attr "slot" "cop")
17128 
   (set_attr "slots" "p0s_p1")
17129 
   (set_attr "stall" "none")])
17130 
 
17131 
 
17132 
(define_insn "cgen_intrinsic_cpunpackl_h_C3"
17133 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17134 
        (unspec:DI [
17135 
          (match_operand:DI 1 "general_operand" "x")
17136 
          (match_operand:DI 2 "general_operand" "x")
17137 
        ] 3514))]
17138 
  "CGEN_ENABLE_INSN_P (658)"
17139 
  "cpunpackl.h\\t%0,%1,%2"
17140 
  [(set_attr "may_trap" "no")
17141 
   (set_attr "latency" "0")
17142 
   (set_attr "length" "4")
17143 
   (set_attr "slot" "cop")
17144 
   (set_attr "slots" "c3")
17145 
   (set_attr "stall" "none")])
17146 
 
17147 
 
17148 
(define_insn "cgen_intrinsic_cpunpackl_h_P0S_P1"
17149 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17150 
        (unspec:DI [
17151 
          (match_operand:DI 1 "general_operand" "x")
17152 
          (match_operand:DI 2 "general_operand" "x")
17153 
        ] 3514))]
17154 
  "CGEN_ENABLE_INSN_P (659)"
17155 
  "cpunpackl.h\\t%0,%1,%2"
17156 
  [(set_attr "may_trap" "no")
17157 
   (set_attr "latency" "0")
17158 
   (set_attr "length" "4")
17159 
   (set_attr "slot" "cop")
17160 
   (set_attr "slots" "p0s_p1")
17161 
   (set_attr "stall" "none")])
17162 
 
17163 
 
17164 
(define_insn "cgen_intrinsic_cpunpackl_b_C3"
17165 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17166 
        (unspec:DI [
17167 
          (match_operand:DI 1 "general_operand" "x")
17168 
          (match_operand:DI 2 "general_operand" "x")
17169 
        ] 3516))]
17170 
  "CGEN_ENABLE_INSN_P (660)"
17171 
  "cpunpackl.b\\t%0,%1,%2"
17172 
  [(set_attr "may_trap" "no")
17173 
   (set_attr "latency" "0")
17174 
   (set_attr "length" "4")
17175 
   (set_attr "slot" "cop")
17176 
   (set_attr "slots" "c3")
17177 
   (set_attr "stall" "none")])
17178 
 
17179 
 
17180 
(define_insn "cgen_intrinsic_cpunpackl_b_P0S_P1"
17181 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17182 
        (unspec:DI [
17183 
          (match_operand:DI 1 "general_operand" "x")
17184 
          (match_operand:DI 2 "general_operand" "x")
17185 
        ] 3516))]
17186 
  "CGEN_ENABLE_INSN_P (661)"
17187 
  "cpunpackl.b\\t%0,%1,%2"
17188 
  [(set_attr "may_trap" "no")
17189 
   (set_attr "latency" "0")
17190 
   (set_attr "length" "4")
17191 
   (set_attr "slot" "cop")
17192 
   (set_attr "slots" "p0s_p1")
17193 
   (set_attr "stall" "none")])
17194 
 
17195 
 
17196 
(define_insn "cgen_intrinsic_cpunpacku_w_C3"
17197 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17198 
        (unspec:DI [
17199 
          (match_operand:DI 1 "general_operand" "x")
17200 
          (match_operand:DI 2 "general_operand" "x")
17201 
        ] 3518))]
17202 
  "CGEN_ENABLE_INSN_P (662)"
17203 
  "cpunpacku.w\\t%0,%1,%2"
17204 
  [(set_attr "may_trap" "no")
17205 
   (set_attr "latency" "0")
17206 
   (set_attr "length" "4")
17207 
   (set_attr "slot" "cop")
17208 
   (set_attr "slots" "c3")
17209 
   (set_attr "stall" "none")])
17210 
 
17211 
 
17212 
(define_insn "cgen_intrinsic_cpunpacku_w_P0S_P1"
17213 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17214 
        (unspec:DI [
17215 
          (match_operand:DI 1 "general_operand" "x")
17216 
          (match_operand:DI 2 "general_operand" "x")
17217 
        ] 3518))]
17218 
  "CGEN_ENABLE_INSN_P (663)"
17219 
  "cpunpacku.w\\t%0,%1,%2"
17220 
  [(set_attr "may_trap" "no")
17221 
   (set_attr "latency" "0")
17222 
   (set_attr "length" "4")
17223 
   (set_attr "slot" "cop")
17224 
   (set_attr "slots" "p0s_p1")
17225 
   (set_attr "stall" "none")])
17226 
 
17227 
 
17228 
(define_insn "cgen_intrinsic_cpunpacku_h_C3"
17229 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17230 
        (unspec:DI [
17231 
          (match_operand:DI 1 "general_operand" "x")
17232 
          (match_operand:DI 2 "general_operand" "x")
17233 
        ] 3520))]
17234 
  "CGEN_ENABLE_INSN_P (664)"
17235 
  "cpunpacku.h\\t%0,%1,%2"
17236 
  [(set_attr "may_trap" "no")
17237 
   (set_attr "latency" "0")
17238 
   (set_attr "length" "4")
17239 
   (set_attr "slot" "cop")
17240 
   (set_attr "slots" "c3")
17241 
   (set_attr "stall" "none")])
17242 
 
17243 
 
17244 
(define_insn "cgen_intrinsic_cpunpacku_h_P0S_P1"
17245 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17246 
        (unspec:DI [
17247 
          (match_operand:DI 1 "general_operand" "x")
17248 
          (match_operand:DI 2 "general_operand" "x")
17249 
        ] 3520))]
17250 
  "CGEN_ENABLE_INSN_P (665)"
17251 
  "cpunpacku.h\\t%0,%1,%2"
17252 
  [(set_attr "may_trap" "no")
17253 
   (set_attr "latency" "0")
17254 
   (set_attr "length" "4")
17255 
   (set_attr "slot" "cop")
17256 
   (set_attr "slots" "p0s_p1")
17257 
   (set_attr "stall" "none")])
17258 
 
17259 
 
17260 
(define_insn "cgen_intrinsic_cpunpacku_b_C3"
17261 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17262 
        (unspec:DI [
17263 
          (match_operand:DI 1 "general_operand" "x")
17264 
          (match_operand:DI 2 "general_operand" "x")
17265 
        ] 3522))]
17266 
  "CGEN_ENABLE_INSN_P (666)"
17267 
  "cpunpacku.b\\t%0,%1,%2"
17268 
  [(set_attr "may_trap" "no")
17269 
   (set_attr "latency" "0")
17270 
   (set_attr "length" "4")
17271 
   (set_attr "slot" "cop")
17272 
   (set_attr "slots" "c3")
17273 
   (set_attr "stall" "none")])
17274 
 
17275 
 
17276 
(define_insn "cgen_intrinsic_cpunpacku_b_P0S_P1"
17277 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17278 
        (unspec:DI [
17279 
          (match_operand:DI 1 "general_operand" "x")
17280 
          (match_operand:DI 2 "general_operand" "x")
17281 
        ] 3522))]
17282 
  "CGEN_ENABLE_INSN_P (667)"
17283 
  "cpunpacku.b\\t%0,%1,%2"
17284 
  [(set_attr "may_trap" "no")
17285 
   (set_attr "latency" "0")
17286 
   (set_attr "length" "4")
17287 
   (set_attr "slot" "cop")
17288 
   (set_attr "slots" "p0s_p1")
17289 
   (set_attr "stall" "none")])
17290 
 
17291 
 
17292 
(define_insn "cgen_intrinsic_cpadd3_w_C3"
17293 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17294 
        (unspec:DI [
17295 
          (match_operand:DI 1 "general_operand" "x")
17296 
          (match_operand:DI 2 "general_operand" "x")
17297 
        ] 3550))]
17298 
  "CGEN_ENABLE_INSN_P (668)"
17299 
  "cpadd3.w\\t%0,%1,%2"
17300 
  [(set_attr "may_trap" "no")
17301 
   (set_attr "latency" "0")
17302 
   (set_attr "length" "4")
17303 
   (set_attr "slot" "cop")
17304 
   (set_attr "slots" "c3")
17305 
   (set_attr "stall" "none")])
17306 
 
17307 
 
17308 
(define_insn "cgen_intrinsic_cpadd3_w_P0S_P1"
17309 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17310 
        (unspec:DI [
17311 
          (match_operand:DI 1 "general_operand" "x")
17312 
          (match_operand:DI 2 "general_operand" "x")
17313 
        ] 3550))]
17314 
  "CGEN_ENABLE_INSN_P (669)"
17315 
  "cpadd3.w\\t%0,%1,%2"
17316 
  [(set_attr "may_trap" "no")
17317 
   (set_attr "latency" "0")
17318 
   (set_attr "length" "4")
17319 
   (set_attr "slot" "cop")
17320 
   (set_attr "slots" "p0s_p1")
17321 
   (set_attr "stall" "none")])
17322 
 
17323 
 
17324 
(define_insn "cgen_intrinsic_cpadd3_h_C3"
17325 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17326 
        (unspec:DI [
17327 
          (match_operand:DI 1 "general_operand" "x")
17328 
          (match_operand:DI 2 "general_operand" "x")
17329 
        ] 3552))]
17330 
  "CGEN_ENABLE_INSN_P (670)"
17331 
  "cpadd3.h\\t%0,%1,%2"
17332 
  [(set_attr "may_trap" "no")
17333 
   (set_attr "latency" "0")
17334 
   (set_attr "length" "4")
17335 
   (set_attr "slot" "cop")
17336 
   (set_attr "slots" "c3")
17337 
   (set_attr "stall" "none")])
17338 
 
17339 
 
17340 
(define_insn "cgen_intrinsic_cpadd3_h_P0S_P1"
17341 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17342 
        (unspec:DI [
17343 
          (match_operand:DI 1 "general_operand" "x")
17344 
          (match_operand:DI 2 "general_operand" "x")
17345 
        ] 3552))]
17346 
  "CGEN_ENABLE_INSN_P (671)"
17347 
  "cpadd3.h\\t%0,%1,%2"
17348 
  [(set_attr "may_trap" "no")
17349 
   (set_attr "latency" "0")
17350 
   (set_attr "length" "4")
17351 
   (set_attr "slot" "cop")
17352 
   (set_attr "slots" "p0s_p1")
17353 
   (set_attr "stall" "none")])
17354 
 
17355 
 
17356 
(define_insn "cgen_intrinsic_cpadd3_b_C3"
17357 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17358 
        (unspec:DI [
17359 
          (match_operand:DI 1 "general_operand" "x")
17360 
          (match_operand:DI 2 "general_operand" "x")
17361 
        ] 3554))]
17362 
  "CGEN_ENABLE_INSN_P (672)"
17363 
  "cpadd3.b\\t%0,%1,%2"
17364 
  [(set_attr "may_trap" "no")
17365 
   (set_attr "latency" "0")
17366 
   (set_attr "length" "4")
17367 
   (set_attr "slot" "cop")
17368 
   (set_attr "slots" "c3")
17369 
   (set_attr "stall" "none")])
17370 
 
17371 
 
17372 
(define_insn "cgen_intrinsic_cpadd3_b_P0S_P1"
17373 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17374 
        (unspec:DI [
17375 
          (match_operand:DI 1 "general_operand" "x")
17376 
          (match_operand:DI 2 "general_operand" "x")
17377 
        ] 3554))]
17378 
  "CGEN_ENABLE_INSN_P (673)"
17379 
  "cpadd3.b\\t%0,%1,%2"
17380 
  [(set_attr "may_trap" "no")
17381 
   (set_attr "latency" "0")
17382 
   (set_attr "length" "4")
17383 
   (set_attr "slot" "cop")
17384 
   (set_attr "slots" "p0s_p1")
17385 
   (set_attr "stall" "none")])
17386 
 
17387 
 
17388 
(define_insn "cgen_intrinsic_c0nop_P0_P0S"
17389 
  [(unspec_volatile [
17390 
     (const_int 0)
17391 
   ] 2196)]
17392 
  "CGEN_ENABLE_INSN_P (674)"
17393 
  "c0nop"
17394 
  [(set_attr "may_trap" "no")
17395 
   (set_attr "latency" "0")
17396 
   (set_attr "length" "4")
17397 
   (set_attr "slot" "cop")
17398 
   (set_attr "slots" "p0_p0s")
17399 
   (set_attr "stall" "none")])
17400 
 
17401 
 
17402 
(define_insn "cgen_intrinsic_cpmoviu_h_C3"
17403 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17404 
        (unspec:DI [
17405 
          (match_operand:DI 1 "cgen_h_uint_8a1_immediate" "")
17406 
        ] 3178))]
17407 
  "CGEN_ENABLE_INSN_P (675)"
17408 
  "cpmoviu.h\\t%0,%1"
17409 
  [(set_attr "may_trap" "no")
17410 
   (set_attr "latency" "0")
17411 
   (set_attr "length" "4")
17412 
   (set_attr "slot" "cop")
17413 
   (set_attr "slots" "c3")
17414 
   (set_attr "stall" "none")])
17415 
 
17416 
 
17417 
(define_insn "cgen_intrinsic_cmovh_rn_crm"
17418 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
17419 
        (unspec:SI [
17420 
          (match_operand:DI 1 "general_operand" "x")
17421 
        ] 4156))]
17422 
  "CGEN_ENABLE_INSN_P (676)"
17423 
  "cmovh\\t%0,%1"
17424 
  [(set_attr "may_trap" "no")
17425 
   (set_attr "latency" "0")
17426 
   (set_attr "length" "4")
17427 
   (set_attr "slot" "cop")
17428 
   (set_attr "slots" "c3")
17429 
   (set_attr "stall" "none")])
17430 
 
17431 
 
17432 
(define_insn "cgen_intrinsic_cmovh_rn_crm_p0"
17433 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
17434 
        (unspec:SI [
17435 
          (match_operand:DI 1 "general_operand" "x")
17436 
        ] 4156))]
17437 
  "CGEN_ENABLE_INSN_P (677)"
17438 
  "cmovh\\t%0,%1"
17439 
  [(set_attr "may_trap" "no")
17440 
   (set_attr "latency" "0")
17441 
   (set_attr "length" "4")
17442 
   (set_attr "slot" "cop")
17443 
   (set_attr "slots" "p0")
17444 
   (set_attr "stall" "none")])
17445 
 
17446 
 
17447 
(define_insn "cgen_intrinsic_cmovh_crn_rm"
17448 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17449 
        (unspec:DI [
17450 
          (match_operand:DI 1 "general_operand" "0")
17451 
          (match_operand:SI 2 "general_operand" "r")
17452 
        ] 4158))]
17453 
  "CGEN_ENABLE_INSN_P (678)"
17454 
  "cmovh\\t%1,%2"
17455 
  [(set_attr "may_trap" "no")
17456 
   (set_attr "latency" "0")
17457 
   (set_attr "length" "4")
17458 
   (set_attr "slot" "cop")
17459 
   (set_attr "slots" "c3")
17460 
   (set_attr "stall" "none")])
17461 
 
17462 
 
17463 
(define_insn "cgen_intrinsic_cmovh_crn_rm_p0"
17464 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17465 
        (unspec:DI [
17466 
          (match_operand:DI 1 "general_operand" "0")
17467 
          (match_operand:SI 2 "general_operand" "r")
17468 
        ] 4158))]
17469 
  "CGEN_ENABLE_INSN_P (679)"
17470 
  "cmovh\\t%1,%2"
17471 
  [(set_attr "may_trap" "no")
17472 
   (set_attr "latency" "0")
17473 
   (set_attr "length" "4")
17474 
   (set_attr "slot" "cop")
17475 
   (set_attr "slots" "p0")
17476 
   (set_attr "stall" "none")])
17477 
 
17478 
 
17479 
(define_insn "cgen_intrinsic_cmovc_rn_ccrm"
17480 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
17481 
        (unspec_volatile:SI [
17482 
          (match_operand:SI 1 "general_operand" "y")
17483 
        ] 4160))]
17484 
  "CGEN_ENABLE_INSN_P (680)"
17485 
  "cmovc\\t%0,%1"
17486 
  [(set_attr "may_trap" "no")
17487 
   (set_attr "latency" "0")
17488 
   (set_attr "length" "4")
17489 
   (set_attr "slot" "cop")
17490 
   (set_attr "slots" "c3")
17491 
   (set_attr "stall" "none")])
17492 
 
17493 
 
17494 
(define_insn "cgen_intrinsic_cmovc_rn_ccrm_p0"
17495 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
17496 
        (unspec_volatile:SI [
17497 
          (match_operand:SI 1 "general_operand" "y")
17498 
        ] 4160))]
17499 
  "CGEN_ENABLE_INSN_P (681)"
17500 
  "cmovc\\t%0,%1"
17501 
  [(set_attr "may_trap" "no")
17502 
   (set_attr "latency" "0")
17503 
   (set_attr "length" "4")
17504 
   (set_attr "slot" "cop")
17505 
   (set_attr "slots" "p0")
17506 
   (set_attr "stall" "none")])
17507 
 
17508 
 
17509 
(define_insn "cgen_intrinsic_cmovc_ccrn_rm"
17510 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=y")
17511 
        (unspec_volatile:SI [
17512 
          (match_operand:SI 1 "general_operand" "r")
17513 
        ] 4162))]
17514 
  "CGEN_ENABLE_INSN_P (682)"
17515 
  "cmovc\\t%0,%1"
17516 
  [(set_attr "may_trap" "no")
17517 
   (set_attr "latency" "0")
17518 
   (set_attr "length" "4")
17519 
   (set_attr "slot" "cop")
17520 
   (set_attr "slots" "c3")
17521 
   (set_attr "stall" "none")])
17522 
 
17523 
 
17524 
(define_insn "cgen_intrinsic_cmovc_ccrn_rm_p0"
17525 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=y")
17526 
        (unspec_volatile:SI [
17527 
          (match_operand:SI 1 "general_operand" "r")
17528 
        ] 4162))]
17529 
  "CGEN_ENABLE_INSN_P (683)"
17530 
  "cmovc\\t%0,%1"
17531 
  [(set_attr "may_trap" "no")
17532 
   (set_attr "latency" "0")
17533 
   (set_attr "length" "4")
17534 
   (set_attr "slot" "cop")
17535 
   (set_attr "slots" "p0")
17536 
   (set_attr "stall" "none")])
17537 
 
17538 
 
17539 
(define_insn "cgen_intrinsic_cmov_rn_crm"
17540 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
17541 
        (unspec:SI [
17542 
          (match_operand:DI 1 "general_operand" "x")
17543 
        ] 4164))]
17544 
  "CGEN_ENABLE_INSN_P (684)"
17545 
  "cmov\\t%0,%1"
17546 
  [(set_attr "may_trap" "no")
17547 
   (set_attr "latency" "0")
17548 
   (set_attr "length" "4")
17549 
   (set_attr "slot" "cop")
17550 
   (set_attr "slots" "c3")
17551 
   (set_attr "stall" "none")])
17552 
 
17553 
 
17554 
(define_insn "cgen_intrinsic_cmov_rn_crm_p0"
17555 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
17556 
        (unspec:SI [
17557 
          (match_operand:DI 1 "general_operand" "x")
17558 
        ] 4164))]
17559 
  "CGEN_ENABLE_INSN_P (685)"
17560 
  "cmov\\t%0,%1"
17561 
  [(set_attr "may_trap" "no")
17562 
   (set_attr "latency" "0")
17563 
   (set_attr "length" "4")
17564 
   (set_attr "slot" "cop")
17565 
   (set_attr "slots" "p0")
17566 
   (set_attr "stall" "none")])
17567 
 
17568 
 
17569 
(define_insn "cgen_intrinsic_cmov_crn_rm"
17570 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17571 
        (unspec:DI [
17572 
          (match_operand:DI 1 "general_operand" "0")
17573 
          (match_operand:SI 2 "general_operand" "r")
17574 
        ] 4166))]
17575 
  "CGEN_ENABLE_INSN_P (686)"
17576 
  "cmov\\t%1,%2"
17577 
  [(set_attr "may_trap" "no")
17578 
   (set_attr "latency" "0")
17579 
   (set_attr "length" "4")
17580 
   (set_attr "slot" "cop")
17581 
   (set_attr "slots" "c3")
17582 
   (set_attr "stall" "none")])
17583 
 
17584 
 
17585 
(define_insn "cgen_intrinsic_cmov_crn_rm_p0"
17586 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17587 
        (unspec:DI [
17588 
          (match_operand:SI 1 "general_operand" "r")
17589 
        ] 4166))]
17590 
  "CGEN_ENABLE_INSN_P (687)"
17591 
  "cmov\\t%0,%1"
17592 
  [(set_attr "may_trap" "no")
17593 
   (set_attr "latency" "0")
17594 
   (set_attr "length" "4")
17595 
   (set_attr "slot" "cop")
17596 
   (set_attr "slots" "p0")
17597 
   (set_attr "stall" "none")])
17598 
 
17599 
 
17600 
(define_insn "cgen_intrinsic_bsrv"
17601 
  [(set (pc)
17602 
        (if_then_else (eq (unspec [
17603 
                            (match_operand:SI 0 "immediate_operand" "")
17604 
                            (reg:SI 32)
17605 
                            (reg:SI 42)
17606 
                          ] 3556)
17607 
                          (const_int 0))
17608 
                      (match_dup 0)
17609 
                      (pc)))
17610 
   (set (reg:SI 17)
17611 
        (unspec:SI [
17612 
          (match_dup 0)
17613 
          (reg:SI 32)
17614 
          (reg:SI 42)
17615 
        ] 3558))
17616 
   (set (reg:SI 114)
17617 
        (unspec:SI [
17618 
          (match_dup 0)
17619 
          (reg:SI 32)
17620 
          (reg:SI 42)
17621 
        ] 3559))]
17622 
  "CGEN_ENABLE_INSN_P (688)"
17623 
  "bsrv\\t%l0"
17624 
  [(set_attr "may_trap" "no")
17625 
   (set_attr "latency" "0")
17626 
   (set_attr "length" "4")
17627 
   (set_attr "slot" "core")
17628 
   (set_attr "slots" "core")
17629 
   (set_attr "stall" "none")])
17630 
 
17631 
 
17632 
(define_insn "cgen_intrinsic_jsrv"
17633 
  [(set (pc)
17634 
        (unspec:SI [
17635 
          (match_operand:SI 0 "general_operand" "r")
17636 
          (reg:SI 32)
17637 
          (reg:SI 42)
17638 
        ] 3560))
17639 
   (set (reg:SI 17)
17640 
        (unspec:SI [
17641 
          (match_dup 0)
17642 
          (reg:SI 32)
17643 
          (reg:SI 42)
17644 
        ] 3562))
17645 
   (set (reg:SI 114)
17646 
        (unspec:SI [
17647 
          (match_dup 0)
17648 
          (reg:SI 32)
17649 
          (reg:SI 42)
17650 
        ] 3563))]
17651 
  "CGEN_ENABLE_INSN_P (689)"
17652 
  "jsrv\\t%0"
17653 
  [(set_attr "may_trap" "no")
17654 
   (set_attr "latency" "0")
17655 
   (set_attr "length" "2")
17656 
   (set_attr "slot" "core")
17657 
   (set_attr "slots" "core")
17658 
   (set_attr "stall" "none")])
17659 
 
17660 
 
17661 
(define_insn "cgen_intrinsic_synccp"
17662 
  [(unspec_volatile [
17663 
     (const_int 0)
17664 
   ] 3564)]
17665 
  "CGEN_ENABLE_INSN_P (690)"
17666 
  "synccp"
17667 
  [(set_attr "may_trap" "no")
17668 
   (set_attr "latency" "0")
17669 
   (set_attr "length" "2")
17670 
   (set_attr "slot" "core")
17671 
   (set_attr "slots" "core")
17672 
   (set_attr "stall" "none")])
17673 
 
17674 
 
17675 
(define_insn "cgen_intrinsic_bcpaf"
17676 
  [(set (pc)
17677 
        (if_then_else (eq (unspec [
17678 
                            (match_operand:SI 0 "cgen_h_uint_4a1_immediate" "")
17679 
                            (match_operand:SI 1 "immediate_operand" "")
17680 
                            (reg:SI 32)
17681 
                            (reg:SI 42)
17682 
                            (reg:SI 81)
17683 
                          ] 3566)
17684 
                          (const_int 0))
17685 
                      (match_dup 1)
17686 
                      (pc)))]
17687 
  "CGEN_ENABLE_INSN_P (691)"
17688 
  "bcpaf\\t%0,%l1"
17689 
  [(set_attr "may_trap" "no")
17690 
   (set_attr "latency" "0")
17691 
   (set_attr "length" "4")
17692 
   (set_attr "slot" "core")
17693 
   (set_attr "slots" "core")
17694 
   (set_attr "stall" "none")])
17695 
 
17696 
 
17697 
(define_insn "cgen_intrinsic_bcpat"
17698 
  [(set (pc)
17699 
        (if_then_else (eq (unspec [
17700 
                            (match_operand:SI 0 "cgen_h_uint_4a1_immediate" "")
17701 
                            (match_operand:SI 1 "immediate_operand" "")
17702 
                            (reg:SI 32)
17703 
                            (reg:SI 42)
17704 
                            (reg:SI 81)
17705 
                          ] 3568)
17706 
                          (const_int 0))
17707 
                      (match_dup 1)
17708 
                      (pc)))]
17709 
  "CGEN_ENABLE_INSN_P (692)"
17710 
  "bcpat\\t%0,%l1"
17711 
  [(set_attr "may_trap" "no")
17712 
   (set_attr "latency" "0")
17713 
   (set_attr "length" "4")
17714 
   (set_attr "slot" "core")
17715 
   (set_attr "slots" "core")
17716 
   (set_attr "stall" "none")])
17717 
 
17718 
 
17719 
(define_insn "cgen_intrinsic_bcpne"
17720 
  [(set (pc)
17721 
        (if_then_else (eq (unspec [
17722 
                            (match_operand:SI 0 "cgen_h_uint_4a1_immediate" "")
17723 
                            (match_operand:SI 1 "immediate_operand" "")
17724 
                            (reg:SI 32)
17725 
                            (reg:SI 42)
17726 
                            (reg:SI 81)
17727 
                          ] 3570)
17728 
                          (const_int 0))
17729 
                      (match_dup 1)
17730 
                      (pc)))]
17731 
  "CGEN_ENABLE_INSN_P (693)"
17732 
  "bcpne\\t%0,%l1"
17733 
  [(set_attr "may_trap" "no")
17734 
   (set_attr "latency" "0")
17735 
   (set_attr "length" "4")
17736 
   (set_attr "slot" "core")
17737 
   (set_attr "slots" "core")
17738 
   (set_attr "stall" "none")])
17739 
 
17740 
 
17741 
(define_insn "cgen_intrinsic_bcpeq"
17742 
  [(set (pc)
17743 
        (if_then_else (eq (unspec [
17744 
                            (match_operand:SI 0 "cgen_h_uint_4a1_immediate" "")
17745 
                            (match_operand:SI 1 "immediate_operand" "")
17746 
                            (reg:SI 32)
17747 
                            (reg:SI 42)
17748 
                            (reg:SI 81)
17749 
                          ] 3572)
17750 
                          (const_int 0))
17751 
                      (match_dup 1)
17752 
                      (pc)))]
17753 
  "CGEN_ENABLE_INSN_P (694)"
17754 
  "bcpeq\\t%0,%l1"
17755 
  [(set_attr "may_trap" "no")
17756 
   (set_attr "latency" "0")
17757 
   (set_attr "length" "4")
17758 
   (set_attr "slot" "core")
17759 
   (set_attr "slots" "core")
17760 
   (set_attr "stall" "none")])
17761 
 
17762 
 
17763 
(define_insn "cgen_intrinsic_lmcpm1"
17764 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=em")
17765 
        (unspec:DI [
17766 
          (match_operand:SI 2 "general_operand" "1")
17767 
          (match_operand:DI 3 "cgen_h_sint_10a1_immediate" "")
17768 
          (reg:SI 31)
17769 
          (reg:SI 30)
17770 
        ] 3574))
17771 
   (set (match_operand:SI 1 "nonimmediate_operand" "=r")
17772 
        (unspec:SI [
17773 
          (match_dup 2)
17774 
          (match_dup 3)
17775 
          (reg:SI 31)
17776 
          (reg:SI 30)
17777 
        ] 3576))]
17778 
  "CGEN_ENABLE_INSN_P (695)"
17779 
  "lmcpm1\\t%0,(%2+),%3"
17780 
  [(set_attr "may_trap" "no")
17781 
   (set_attr "latency" "0")
17782 
   (set_attr "length" "4")
17783 
   (set_attr "slot" "core")
17784 
   (set_attr "slots" "core")
17785 
   (set_attr "stall" "none")])
17786 
 
17787 
 
17788 
(define_insn "cgen_intrinsic_smcpm1"
17789 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
17790 
        (unspec:SI [
17791 
          (match_operand:DI 1 "general_operand" "em")
17792 
          (match_operand:SI 2 "general_operand" "0")
17793 
          (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
17794 
          (reg:SI 31)
17795 
          (reg:SI 30)
17796 
        ] 3578))]
17797 
  "CGEN_ENABLE_INSN_P (696)"
17798 
  "smcpm1\\t%1,(%2+),%3"
17799 
  [(set_attr "may_trap" "no")
17800 
   (set_attr "latency" "0")
17801 
   (set_attr "length" "4")
17802 
   (set_attr "slot" "core")
17803 
   (set_attr "slots" "core")
17804 
   (set_attr "stall" "none")])
17805 
 
17806 
 
17807 
(define_insn "cgen_intrinsic_lwcpm1"
17808 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
17809 
        (unspec:SI [
17810 
          (match_operand:SI 2 "general_operand" "1")
17811 
          (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
17812 
          (reg:SI 31)
17813 
          (reg:SI 30)
17814 
          (mem:SI (scratch:SI))
17815 
        ] 3580))
17816 
   (set (match_operand:SI 1 "nonimmediate_operand" "=r")
17817 
        (unspec:SI [
17818 
          (match_dup 2)
17819 
          (match_dup 3)
17820 
          (reg:SI 31)
17821 
          (reg:SI 30)
17822 
          (mem:SI (scratch:SI))
17823 
        ] 3582))]
17824 
  "CGEN_ENABLE_INSN_P (697)"
17825 
  "lwcpm1\\t%0,(%2+),%3"
17826 
  [(set_attr "may_trap" "no")
17827 
   (set_attr "latency" "0")
17828 
   (set_attr "length" "4")
17829 
   (set_attr "slot" "core")
17830 
   (set_attr "slots" "core")
17831 
   (set_attr "stall" "none")])
17832 
 
17833 
 
17834 
(define_insn "cgen_intrinsic_swcpm1"
17835 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
17836 
        (unspec:SI [
17837 
          (match_operand:SI 1 "general_operand" "em")
17838 
          (match_operand:SI 2 "general_operand" "0")
17839 
          (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
17840 
          (reg:SI 31)
17841 
          (reg:SI 30)
17842 
        ] 3584))
17843 
   (set (mem:SI (scratch:SI))
17844 
        (unspec:SI [
17845 
          (match_dup 1)
17846 
          (match_dup 2)
17847 
          (match_dup 3)
17848 
          (reg:SI 31)
17849 
          (reg:SI 30)
17850 
        ] 3586))]
17851 
  "CGEN_ENABLE_INSN_P (698)"
17852 
  "swcpm1\\t%1,(%2+),%3"
17853 
  [(set_attr "may_trap" "no")
17854 
   (set_attr "latency" "0")
17855 
   (set_attr "length" "4")
17856 
   (set_attr "slot" "core")
17857 
   (set_attr "slots" "core")
17858 
   (set_attr "stall" "none")])
17859 
 
17860 
 
17861 
(define_insn "cgen_intrinsic_lhcpm1"
17862 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
17863 
        (unspec:SI [
17864 
          (match_operand:SI 2 "general_operand" "1")
17865 
          (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
17866 
          (reg:SI 31)
17867 
          (reg:SI 30)
17868 
          (mem:SI (scratch:SI))
17869 
        ] 3588))
17870 
   (set (match_operand:SI 1 "nonimmediate_operand" "=r")
17871 
        (unspec:SI [
17872 
          (match_dup 2)
17873 
          (match_dup 3)
17874 
          (reg:SI 31)
17875 
          (reg:SI 30)
17876 
          (mem:SI (scratch:SI))
17877 
        ] 3590))]
17878 
  "CGEN_ENABLE_INSN_P (699)"
17879 
  "lhcpm1\\t%0,(%2+),%3"
17880 
  [(set_attr "may_trap" "no")
17881 
   (set_attr "latency" "0")
17882 
   (set_attr "length" "4")
17883 
   (set_attr "slot" "core")
17884 
   (set_attr "slots" "core")
17885 
   (set_attr "stall" "none")])
17886 
 
17887 
 
17888 
(define_insn "cgen_intrinsic_shcpm1"
17889 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
17890 
        (unspec:SI [
17891 
          (match_operand:SI 1 "general_operand" "em")
17892 
          (match_operand:SI 2 "general_operand" "0")
17893 
          (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
17894 
          (reg:SI 31)
17895 
          (reg:SI 30)
17896 
        ] 3592))
17897 
   (set (mem:SI (scratch:SI))
17898 
        (unspec:SI [
17899 
          (match_dup 1)
17900 
          (match_dup 2)
17901 
          (match_dup 3)
17902 
          (reg:SI 31)
17903 
          (reg:SI 30)
17904 
        ] 3594))]
17905 
  "CGEN_ENABLE_INSN_P (700)"
17906 
  "shcpm1\\t%1,(%2+),%3"
17907 
  [(set_attr "may_trap" "no")
17908 
   (set_attr "latency" "0")
17909 
   (set_attr "length" "4")
17910 
   (set_attr "slot" "core")
17911 
   (set_attr "slots" "core")
17912 
   (set_attr "stall" "none")])
17913 
 
17914 
 
17915 
(define_insn "cgen_intrinsic_lbcpm1"
17916 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
17917 
        (unspec:SI [
17918 
          (match_operand:SI 2 "general_operand" "1")
17919 
          (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
17920 
          (reg:SI 31)
17921 
          (reg:SI 30)
17922 
          (mem:SI (scratch:SI))
17923 
        ] 3596))
17924 
   (set (match_operand:SI 1 "nonimmediate_operand" "=r")
17925 
        (unspec:SI [
17926 
          (match_dup 2)
17927 
          (match_dup 3)
17928 
          (reg:SI 31)
17929 
          (reg:SI 30)
17930 
          (mem:SI (scratch:SI))
17931 
        ] 3598))]
17932 
  "CGEN_ENABLE_INSN_P (701)"
17933 
  "lbcpm1\\t%0,(%2+),%3"
17934 
  [(set_attr "may_trap" "no")
17935 
   (set_attr "latency" "0")
17936 
   (set_attr "length" "4")
17937 
   (set_attr "slot" "core")
17938 
   (set_attr "slots" "core")
17939 
   (set_attr "stall" "none")])
17940 
 
17941 
 
17942 
(define_insn "cgen_intrinsic_sbcpm1"
17943 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
17944 
        (unspec:SI [
17945 
          (match_operand:SI 1 "general_operand" "em")
17946 
          (match_operand:SI 2 "general_operand" "0")
17947 
          (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
17948 
          (reg:SI 31)
17949 
          (reg:SI 30)
17950 
        ] 3600))
17951 
   (set (mem:SI (scratch:SI))
17952 
        (unspec:SI [
17953 
          (match_dup 1)
17954 
          (match_dup 2)
17955 
          (match_dup 3)
17956 
          (reg:SI 31)
17957 
          (reg:SI 30)
17958 
        ] 3602))]
17959 
  "CGEN_ENABLE_INSN_P (702)"
17960 
  "sbcpm1\\t%1,(%2+),%3"
17961 
  [(set_attr "may_trap" "no")
17962 
   (set_attr "latency" "0")
17963 
   (set_attr "length" "4")
17964 
   (set_attr "slot" "core")
17965 
   (set_attr "slots" "core")
17966 
   (set_attr "stall" "none")])
17967 
 
17968 
 
17969 
(define_insn "cgen_intrinsic_lmcpm0"
17970 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=em")
17971 
        (unspec:DI [
17972 
          (match_operand:SI 2 "general_operand" "1")
17973 
          (match_operand:DI 3 "cgen_h_sint_10a1_immediate" "")
17974 
          (reg:SI 29)
17975 
          (reg:SI 28)
17976 
        ] 3604))
17977 
   (set (match_operand:SI 1 "nonimmediate_operand" "=r")
17978 
        (unspec:SI [
17979 
          (match_dup 2)
17980 
          (match_dup 3)
17981 
          (reg:SI 29)
17982 
          (reg:SI 28)
17983 
        ] 3606))]
17984 
  "CGEN_ENABLE_INSN_P (703)"
17985 
  "lmcpm0\\t%0,(%2+),%3"
17986 
  [(set_attr "may_trap" "no")
17987 
   (set_attr "latency" "0")
17988 
   (set_attr "length" "4")
17989 
   (set_attr "slot" "core")
17990 
   (set_attr "slots" "core")
17991 
   (set_attr "stall" "none")])
17992 
 
17993 
 
17994 
(define_insn "cgen_intrinsic_smcpm0"
17995 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
17996 
        (unspec:SI [
17997 
          (match_operand:DI 1 "general_operand" "em")
17998 
          (match_operand:SI 2 "general_operand" "0")
17999 
          (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
18000 
          (reg:SI 29)
18001 
          (reg:SI 28)
18002 
        ] 3608))]
18003 
  "CGEN_ENABLE_INSN_P (704)"
18004 
  "smcpm0\\t%1,(%2+),%3"
18005 
  [(set_attr "may_trap" "no")
18006 
   (set_attr "latency" "0")
18007 
   (set_attr "length" "4")
18008 
   (set_attr "slot" "core")
18009 
   (set_attr "slots" "core")
18010 
   (set_attr "stall" "none")])
18011 
 
18012 
 
18013 
(define_insn "cgen_intrinsic_lwcpm0"
18014 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
18015 
        (unspec:SI [
18016 
          (match_operand:SI 2 "general_operand" "1")
18017 
          (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
18018 
          (reg:SI 29)
18019 
          (reg:SI 28)
18020 
          (mem:SI (scratch:SI))
18021 
        ] 3610))
18022 
   (set (match_operand:SI 1 "nonimmediate_operand" "=r")
18023 
        (unspec:SI [
18024 
          (match_dup 2)
18025 
          (match_dup 3)
18026 
          (reg:SI 29)
18027 
          (reg:SI 28)
18028 
          (mem:SI (scratch:SI))
18029 
        ] 3612))]
18030 
  "CGEN_ENABLE_INSN_P (705)"
18031 
  "lwcpm0\\t%0,(%2+),%3"
18032 
  [(set_attr "may_trap" "no")
18033 
   (set_attr "latency" "0")
18034 
   (set_attr "length" "4")
18035 
   (set_attr "slot" "core")
18036 
   (set_attr "slots" "core")
18037 
   (set_attr "stall" "none")])
18038 
 
18039 
 
18040 
(define_insn "cgen_intrinsic_swcpm0"
18041 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
18042 
        (unspec:SI [
18043 
          (match_operand:SI 1 "general_operand" "em")
18044 
          (match_operand:SI 2 "general_operand" "0")
18045 
          (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
18046 
          (reg:SI 29)
18047 
          (reg:SI 28)
18048 
        ] 3614))
18049 
   (set (mem:SI (scratch:SI))
18050 
        (unspec:SI [
18051 
          (match_dup 1)
18052 
          (match_dup 2)
18053 
          (match_dup 3)
18054 
          (reg:SI 29)
18055 
          (reg:SI 28)
18056 
        ] 3616))]
18057 
  "CGEN_ENABLE_INSN_P (706)"
18058 
  "swcpm0\\t%1,(%2+),%3"
18059 
  [(set_attr "may_trap" "no")
18060 
   (set_attr "latency" "0")
18061 
   (set_attr "length" "4")
18062 
   (set_attr "slot" "core")
18063 
   (set_attr "slots" "core")
18064 
   (set_attr "stall" "none")])
18065 
 
18066 
 
18067 
(define_insn "cgen_intrinsic_lhcpm0"
18068 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
18069 
        (unspec:SI [
18070 
          (match_operand:SI 2 "general_operand" "1")
18071 
          (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
18072 
          (reg:SI 29)
18073 
          (reg:SI 28)
18074 
          (mem:SI (scratch:SI))
18075 
        ] 3618))
18076 
   (set (match_operand:SI 1 "nonimmediate_operand" "=r")
18077 
        (unspec:SI [
18078 
          (match_dup 2)
18079 
          (match_dup 3)
18080 
          (reg:SI 29)
18081 
          (reg:SI 28)
18082 
          (mem:SI (scratch:SI))
18083 
        ] 3620))]
18084 
  "CGEN_ENABLE_INSN_P (707)"
18085 
  "lhcpm0\\t%0,(%2+),%3"
18086 
  [(set_attr "may_trap" "no")
18087 
   (set_attr "latency" "0")
18088 
   (set_attr "length" "4")
18089 
   (set_attr "slot" "core")
18090 
   (set_attr "slots" "core")
18091 
   (set_attr "stall" "none")])
18092 
 
18093 
 
18094 
(define_insn "cgen_intrinsic_shcpm0"
18095 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
18096 
        (unspec:SI [
18097 
          (match_operand:SI 1 "general_operand" "em")
18098 
          (match_operand:SI 2 "general_operand" "0")
18099 
          (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
18100 
          (reg:SI 29)
18101 
          (reg:SI 28)
18102 
        ] 3622))
18103 
   (set (mem:SI (scratch:SI))
18104 
        (unspec:SI [
18105 
          (match_dup 1)
18106 
          (match_dup 2)
18107 
          (match_dup 3)
18108 
          (reg:SI 29)
18109 
          (reg:SI 28)
18110 
        ] 3624))]
18111 
  "CGEN_ENABLE_INSN_P (708)"
18112 
  "shcpm0\\t%1,(%2+),%3"
18113 
  [(set_attr "may_trap" "no")
18114 
   (set_attr "latency" "0")
18115 
   (set_attr "length" "4")
18116 
   (set_attr "slot" "core")
18117 
   (set_attr "slots" "core")
18118 
   (set_attr "stall" "none")])
18119 
 
18120 
 
18121 
(define_insn "cgen_intrinsic_lbcpm0"
18122 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
18123 
        (unspec:SI [
18124 
          (match_operand:SI 2 "general_operand" "1")
18125 
          (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
18126 
          (reg:SI 29)
18127 
          (reg:SI 28)
18128 
          (mem:SI (scratch:SI))
18129 
        ] 3626))
18130 
   (set (match_operand:SI 1 "nonimmediate_operand" "=r")
18131 
        (unspec:SI [
18132 
          (match_dup 2)
18133 
          (match_dup 3)
18134 
          (reg:SI 29)
18135 
          (reg:SI 28)
18136 
          (mem:SI (scratch:SI))
18137 
        ] 3628))]
18138 
  "CGEN_ENABLE_INSN_P (709)"
18139 
  "lbcpm0\\t%0,(%2+),%3"
18140 
  [(set_attr "may_trap" "no")
18141 
   (set_attr "latency" "0")
18142 
   (set_attr "length" "4")
18143 
   (set_attr "slot" "core")
18144 
   (set_attr "slots" "core")
18145 
   (set_attr "stall" "none")])
18146 
 
18147 
 
18148 
(define_insn "cgen_intrinsic_sbcpm0"
18149 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
18150 
        (unspec:SI [
18151 
          (match_operand:SI 1 "general_operand" "em")
18152 
          (match_operand:SI 2 "general_operand" "0")
18153 
          (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
18154 
          (reg:SI 29)
18155 
          (reg:SI 28)
18156 
        ] 3630))
18157 
   (set (mem:SI (scratch:SI))
18158 
        (unspec:SI [
18159 
          (match_dup 1)
18160 
          (match_dup 2)
18161 
          (match_dup 3)
18162 
          (reg:SI 29)
18163 
          (reg:SI 28)
18164 
        ] 3632))]
18165 
  "CGEN_ENABLE_INSN_P (710)"
18166 
  "sbcpm0\\t%1,(%2+),%3"
18167 
  [(set_attr "may_trap" "no")
18168 
   (set_attr "latency" "0")
18169 
   (set_attr "length" "4")
18170 
   (set_attr "slot" "core")
18171 
   (set_attr "slots" "core")
18172 
   (set_attr "stall" "none")])
18173 
 
18174 
 
18175 
(define_insn "cgen_intrinsic_lmcpa"
18176 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=em")
18177 
        (unspec:DI [
18178 
          (match_operand:SI 2 "general_operand" "1")
18179 
          (match_operand:DI 3 "cgen_h_sint_10a1_immediate" "")
18180 
        ] 3634))
18181 
   (set (match_operand:SI 1 "nonimmediate_operand" "=r")
18182 
        (unspec:SI [
18183 
          (match_dup 2)
18184 
          (match_dup 3)
18185 
        ] 3636))]
18186 
  "CGEN_ENABLE_INSN_P (711)"
18187 
  "lmcpa\\t%0,(%2+),%3"
18188 
  [(set_attr "may_trap" "no")
18189 
   (set_attr "latency" "0")
18190 
   (set_attr "length" "4")
18191 
   (set_attr "slot" "core")
18192 
   (set_attr "slots" "core")
18193 
   (set_attr "stall" "load")])
18194 
 
18195 
 
18196 
(define_insn "cgen_intrinsic_smcpa"
18197 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
18198 
        (unspec:SI [
18199 
          (match_operand:DI 1 "general_operand" "em")
18200 
          (match_operand:SI 2 "general_operand" "0")
18201 
          (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
18202 
        ] 3638))]
18203 
  "CGEN_ENABLE_INSN_P (712)"
18204 
  "smcpa\\t%1,(%2+),%3"
18205 
  [(set_attr "may_trap" "no")
18206 
   (set_attr "latency" "0")
18207 
   (set_attr "length" "4")
18208 
   (set_attr "slot" "core")
18209 
   (set_attr "slots" "core")
18210 
   (set_attr "stall" "store")])
18211 
 
18212 
 
18213 
(define_insn "cgen_intrinsic_lwcpa"
18214 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
18215 
        (unspec:SI [
18216 
          (match_operand:SI 2 "general_operand" "1")
18217 
          (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
18218 
          (mem:SI (scratch:SI))
18219 
        ] 3640))
18220 
   (set (match_operand:SI 1 "nonimmediate_operand" "=r")
18221 
        (unspec:SI [
18222 
          (match_dup 2)
18223 
          (match_dup 3)
18224 
          (mem:SI (scratch:SI))
18225 
        ] 3642))]
18226 
  "CGEN_ENABLE_INSN_P (713)"
18227 
  "lwcpa\\t%0,(%2+),%3"
18228 
  [(set_attr "may_trap" "no")
18229 
   (set_attr "latency" "0")
18230 
   (set_attr "length" "4")
18231 
   (set_attr "slot" "core")
18232 
   (set_attr "slots" "core")
18233 
   (set_attr "stall" "load")])
18234 
 
18235 
 
18236 
(define_insn "cgen_intrinsic_swcpa"
18237 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
18238 
        (unspec:SI [
18239 
          (match_operand:SI 1 "general_operand" "em")
18240 
          (match_operand:SI 2 "general_operand" "0")
18241 
          (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
18242 
        ] 3644))
18243 
   (set (mem:SI (scratch:SI))
18244 
        (unspec:SI [
18245 
          (match_dup 1)
18246 
          (match_dup 2)
18247 
          (match_dup 3)
18248 
        ] 3646))]
18249 
  "CGEN_ENABLE_INSN_P (714)"
18250 
  "swcpa\\t%1,(%2+),%3"
18251 
  [(set_attr "may_trap" "no")
18252 
   (set_attr "latency" "0")
18253 
   (set_attr "length" "4")
18254 
   (set_attr "slot" "core")
18255 
   (set_attr "slots" "core")
18256 
   (set_attr "stall" "store")])
18257 
 
18258 
 
18259 
(define_insn "cgen_intrinsic_lhcpa"
18260 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
18261 
        (unspec:SI [
18262 
          (match_operand:SI 2 "general_operand" "1")
18263 
          (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
18264 
          (mem:SI (scratch:SI))
18265 
        ] 3648))
18266 
   (set (match_operand:SI 1 "nonimmediate_operand" "=r")
18267 
        (unspec:SI [
18268 
          (match_dup 2)
18269 
          (match_dup 3)
18270 
          (mem:SI (scratch:SI))
18271 
        ] 3650))]
18272 
  "CGEN_ENABLE_INSN_P (715)"
18273 
  "lhcpa\\t%0,(%2+),%3"
18274 
  [(set_attr "may_trap" "no")
18275 
   (set_attr "latency" "0")
18276 
   (set_attr "length" "4")
18277 
   (set_attr "slot" "core")
18278 
   (set_attr "slots" "core")
18279 
   (set_attr "stall" "load")])
18280 
 
18281 
 
18282 
(define_insn "cgen_intrinsic_shcpa"
18283 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
18284 
        (unspec:SI [
18285 
          (match_operand:SI 1 "general_operand" "em")
18286 
          (match_operand:SI 2 "general_operand" "0")
18287 
          (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
18288 
        ] 3652))
18289 
   (set (mem:SI (scratch:SI))
18290 
        (unspec:SI [
18291 
          (match_dup 1)
18292 
          (match_dup 2)
18293 
          (match_dup 3)
18294 
        ] 3654))]
18295 
  "CGEN_ENABLE_INSN_P (716)"
18296 
  "shcpa\\t%1,(%2+),%3"
18297 
  [(set_attr "may_trap" "no")
18298 
   (set_attr "latency" "0")
18299 
   (set_attr "length" "4")
18300 
   (set_attr "slot" "core")
18301 
   (set_attr "slots" "core")
18302 
   (set_attr "stall" "store")])
18303 
 
18304 
 
18305 
(define_insn "cgen_intrinsic_lbcpa"
18306 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
18307 
        (unspec:SI [
18308 
          (match_operand:SI 2 "general_operand" "1")
18309 
          (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
18310 
          (mem:SI (scratch:SI))
18311 
        ] 3656))
18312 
   (set (match_operand:SI 1 "nonimmediate_operand" "=r")
18313 
        (unspec:SI [
18314 
          (match_dup 2)
18315 
          (match_dup 3)
18316 
          (mem:SI (scratch:SI))
18317 
        ] 3658))]
18318 
  "CGEN_ENABLE_INSN_P (717)"
18319 
  "lbcpa\\t%0,(%2+),%3"
18320 
  [(set_attr "may_trap" "no")
18321 
   (set_attr "latency" "0")
18322 
   (set_attr "length" "4")
18323 
   (set_attr "slot" "core")
18324 
   (set_attr "slots" "core")
18325 
   (set_attr "stall" "load")])
18326 
 
18327 
 
18328 
(define_insn "cgen_intrinsic_sbcpa"
18329 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
18330 
        (unspec:SI [
18331 
          (match_operand:SI 1 "general_operand" "em")
18332 
          (match_operand:SI 2 "general_operand" "0")
18333 
          (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
18334 
        ] 3660))
18335 
   (set (mem:SI (scratch:SI))
18336 
        (unspec:SI [
18337 
          (match_dup 1)
18338 
          (match_dup 2)
18339 
          (match_dup 3)
18340 
        ] 3662))]
18341 
  "CGEN_ENABLE_INSN_P (718)"
18342 
  "sbcpa\\t%1,(%2+),%3"
18343 
  [(set_attr "may_trap" "no")
18344 
   (set_attr "latency" "0")
18345 
   (set_attr "length" "4")
18346 
   (set_attr "slot" "core")
18347 
   (set_attr "slots" "core")
18348 
   (set_attr "stall" "store")])
18349 
 
18350 
 
18351 
(define_insn "cgen_intrinsic_lmcp16"
18352 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=em")
18353 
        (unspec:DI [
18354 
          (match_operand:DI 1 "cgen_h_sint_16a1_immediate" "")
18355 
          (match_operand:SI 2 "general_operand" "r")
18356 
        ] 3664))]
18357 
  "CGEN_ENABLE_INSN_P (719)"
18358 
  "lmcp\\t%0,%1(%2)"
18359 
  [(set_attr "may_trap" "no")
18360 
   (set_attr "latency" "0")
18361 
   (set_attr "length" "4")
18362 
   (set_attr "slot" "core")
18363 
   (set_attr "slots" "core")
18364 
   (set_attr "stall" "load")])
18365 
 
18366 
 
18367 
(define_insn "cgen_intrinsic_smcp16"
18368 
  [(unspec_volatile [
18369 
     (match_operand:DI 0 "general_operand" "em")
18370 
     (match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
18371 
     (match_operand:SI 2 "general_operand" "r")
18372 
   ] 3666)]
18373 
  "CGEN_ENABLE_INSN_P (720)"
18374 
  "smcp\\t%0,%1(%2)"
18375 
  [(set_attr "may_trap" "no")
18376 
   (set_attr "latency" "0")
18377 
   (set_attr "length" "4")
18378 
   (set_attr "slot" "core")
18379 
   (set_attr "slots" "core")
18380 
   (set_attr "stall" "store")])
18381 
 
18382 
 
18383 
(define_insn "cgen_intrinsic_lwcp16"
18384 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
18385 
        (unspec:SI [
18386 
          (match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
18387 
          (match_operand:SI 2 "general_operand" "r")
18388 
          (mem:SI (scratch:SI))
18389 
        ] 3668))]
18390 
  "CGEN_ENABLE_INSN_P (721)"
18391 
  "lwcp\\t%0,%1(%2)"
18392 
  [(set_attr "may_trap" "no")
18393 
   (set_attr "latency" "0")
18394 
   (set_attr "length" "4")
18395 
   (set_attr "slot" "core")
18396 
   (set_attr "slots" "core")
18397 
   (set_attr "stall" "load")])
18398 
 
18399 
 
18400 
(define_insn "cgen_intrinsic_swcp16"
18401 
  [(set (mem:SI (scratch:SI))
18402 
        (unspec:SI [
18403 
          (match_operand:SI 0 "general_operand" "em")
18404 
          (match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
18405 
          (match_operand:SI 2 "general_operand" "r")
18406 
        ] 3670))]
18407 
  "CGEN_ENABLE_INSN_P (722)"
18408 
  "swcp\\t%0,%1(%2)"
18409 
  [(set_attr "may_trap" "no")
18410 
   (set_attr "latency" "0")
18411 
   (set_attr "length" "4")
18412 
   (set_attr "slot" "core")
18413 
   (set_attr "slots" "core")
18414 
   (set_attr "stall" "store")])
18415 
 
18416 
 
18417 
(define_insn "cgen_intrinsic_lmcpi"
18418 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=em")
18419 
        (unspec:DI [
18420 
          (match_operand:SI 2 "general_operand" "1")
18421 
        ] 3672))
18422 
   (set (match_operand:SI 1 "nonimmediate_operand" "=r")
18423 
        (unspec:SI [
18424 
          (match_dup 2)
18425 
        ] 3674))]
18426 
  "CGEN_ENABLE_INSN_P (723)"
18427 
  "lmcpi\\t%0,(%2+)"
18428 
  [(set_attr "may_trap" "no")
18429 
   (set_attr "latency" "0")
18430 
   (set_attr "length" "2")
18431 
   (set_attr "slot" "core")
18432 
   (set_attr "slots" "core")
18433 
   (set_attr "stall" "load")])
18434 
 
18435 
 
18436 
(define_insn "cgen_intrinsic_smcpi"
18437 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
18438 
        (unspec:SI [
18439 
          (match_operand:DI 1 "general_operand" "em")
18440 
          (match_operand:SI 2 "general_operand" "0")
18441 
        ] 3676))]
18442 
  "CGEN_ENABLE_INSN_P (724)"
18443 
  "smcpi\\t%1,(%2+)"
18444 
  [(set_attr "may_trap" "no")
18445 
   (set_attr "latency" "0")
18446 
   (set_attr "length" "2")
18447 
   (set_attr "slot" "core")
18448 
   (set_attr "slots" "core")
18449 
   (set_attr "stall" "store")])
18450 
 
18451 
 
18452 
(define_insn "cgen_intrinsic_lwcpi"
18453 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
18454 
        (unspec:SI [
18455 
          (match_operand:SI 2 "general_operand" "1")
18456 
          (mem:SI (scratch:SI))
18457 
        ] 3678))
18458 
   (set (match_operand:SI 1 "nonimmediate_operand" "=r")
18459 
        (unspec:SI [
18460 
          (match_dup 2)
18461 
          (mem:SI (scratch:SI))
18462 
        ] 3680))]
18463 
  "CGEN_ENABLE_INSN_P (725)"
18464 
  "lwcpi\\t%0,(%2+)"
18465 
  [(set_attr "may_trap" "no")
18466 
   (set_attr "latency" "0")
18467 
   (set_attr "length" "2")
18468 
   (set_attr "slot" "core")
18469 
   (set_attr "slots" "core")
18470 
   (set_attr "stall" "load")])
18471 
 
18472 
 
18473 
(define_insn "cgen_intrinsic_swcpi"
18474 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
18475 
        (unspec:SI [
18476 
          (match_operand:SI 1 "general_operand" "em")
18477 
          (match_operand:SI 2 "general_operand" "0")
18478 
        ] 3682))
18479 
   (set (mem:SI (scratch:SI))
18480 
        (unspec:SI [
18481 
          (match_dup 1)
18482 
          (match_dup 2)
18483 
        ] 3684))]
18484 
  "CGEN_ENABLE_INSN_P (726)"
18485 
  "swcpi\\t%1,(%2+)"
18486 
  [(set_attr "may_trap" "no")
18487 
   (set_attr "latency" "0")
18488 
   (set_attr "length" "2")
18489 
   (set_attr "slot" "core")
18490 
   (set_attr "slots" "core")
18491 
   (set_attr "stall" "store")])
18492 
 
18493 
 
18494 
(define_insn "cgen_intrinsic_lmcp"
18495 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=em")
18496 
        (unspec:DI [
18497 
          (match_operand:SI 1 "general_operand" "r")
18498 
        ] 3686))]
18499 
  "CGEN_ENABLE_INSN_P (727)"
18500 
  "lmcp\\t%0,(%1)"
18501 
  [(set_attr "may_trap" "no")
18502 
   (set_attr "latency" "0")
18503 
   (set_attr "length" "2")
18504 
   (set_attr "slot" "core")
18505 
   (set_attr "slots" "core")
18506 
   (set_attr "stall" "load")])
18507 
 
18508 
 
18509 
(define_insn "cgen_intrinsic_smcp"
18510 
  [(unspec_volatile [
18511 
     (match_operand:DI 0 "general_operand" "em")
18512 
     (match_operand:SI 1 "general_operand" "r")
18513 
   ] 3688)]
18514 
  "CGEN_ENABLE_INSN_P (728)"
18515 
  "smcp\\t%0,(%1)"
18516 
  [(set_attr "may_trap" "no")
18517 
   (set_attr "latency" "0")
18518 
   (set_attr "length" "2")
18519 
   (set_attr "slot" "core")
18520 
   (set_attr "slots" "core")
18521 
   (set_attr "stall" "store")])
18522 
 
18523 
 
18524 
(define_insn "cgen_intrinsic_lwcp"
18525 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
18526 
        (unspec:SI [
18527 
          (match_operand:SI 1 "general_operand" "r")
18528 
          (mem:SI (scratch:SI))
18529 
        ] 3690))]
18530 
  "CGEN_ENABLE_INSN_P (729)"
18531 
  "lwcp\\t%0,(%1)"
18532 
  [(set_attr "may_trap" "no")
18533 
   (set_attr "latency" "0")
18534 
   (set_attr "length" "2")
18535 
   (set_attr "slot" "core")
18536 
   (set_attr "slots" "core")
18537 
   (set_attr "stall" "load")])
18538 
 
18539 
 
18540 
(define_insn "cgen_intrinsic_swcp"
18541 
  [(set (mem:SI (scratch:SI))
18542 
        (unspec:SI [
18543 
          (match_operand:SI 0 "general_operand" "em")
18544 
          (match_operand:SI 1 "general_operand" "r")
18545 
        ] 3692))]
18546 
  "CGEN_ENABLE_INSN_P (730)"
18547 
  "swcp\\t%0,(%1)"
18548 
  [(set_attr "may_trap" "no")
18549 
   (set_attr "latency" "0")
18550 
   (set_attr "length" "2")
18551 
   (set_attr "slot" "core")
18552 
   (set_attr "slots" "core")
18553 
   (set_attr "stall" "store")])
18554 
 
18555 
 
18556 
(define_insn "cgen_intrinsic_ssubu"
18557 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
18558 
        (unspec:SI [
18559 
          (match_operand:SI 1 "general_operand" "0")
18560 
          (match_operand:SI 2 "general_operand" "r")
18561 
        ] 3694))]
18562 
  "CGEN_ENABLE_INSN_P (731)"
18563 
  "ssubu\\t%1,%2"
18564 
  [(set_attr "may_trap" "no")
18565 
   (set_attr "latency" "0")
18566 
   (set_attr "length" "4")
18567 
   (set_attr "slot" "core")
18568 
   (set_attr "slots" "core")
18569 
   (set_attr "stall" "int2")])
18570 
 
18571 
 
18572 
(define_insn "cgen_intrinsic_saddu"
18573 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
18574 
        (unspec:SI [
18575 
          (match_operand:SI 1 "general_operand" "0")
18576 
          (match_operand:SI 2 "general_operand" "r")
18577 
        ] 3696))]
18578 
  "CGEN_ENABLE_INSN_P (732)"
18579 
  "saddu\\t%1,%2"
18580 
  [(set_attr "may_trap" "no")
18581 
   (set_attr "latency" "0")
18582 
   (set_attr "length" "4")
18583 
   (set_attr "slot" "core")
18584 
   (set_attr "slots" "core")
18585 
   (set_attr "stall" "int2")])
18586 
 
18587 
 
18588 
(define_insn "cgen_intrinsic_ssub"
18589 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
18590 
        (unspec:SI [
18591 
          (match_operand:SI 1 "general_operand" "0")
18592 
          (match_operand:SI 2 "general_operand" "r")
18593 
        ] 3698))]
18594 
  "CGEN_ENABLE_INSN_P (733)"
18595 
  "ssub\\t%1,%2"
18596 
  [(set_attr "may_trap" "no")
18597 
   (set_attr "latency" "0")
18598 
   (set_attr "length" "4")
18599 
   (set_attr "slot" "core")
18600 
   (set_attr "slots" "core")
18601 
   (set_attr "stall" "int2")])
18602 
 
18603 
 
18604 
(define_insn "cgen_intrinsic_sadd"
18605 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
18606 
        (unspec:SI [
18607 
          (match_operand:SI 1 "general_operand" "0")
18608 
          (match_operand:SI 2 "general_operand" "r")
18609 
        ] 3700))]
18610 
  "CGEN_ENABLE_INSN_P (734)"
18611 
  "sadd\\t%1,%2"
18612 
  [(set_attr "may_trap" "no")
18613 
   (set_attr "latency" "0")
18614 
   (set_attr "length" "4")
18615 
   (set_attr "slot" "core")
18616 
   (set_attr "slots" "core")
18617 
   (set_attr "stall" "int2")])
18618 
 
18619 
 
18620 
(define_insn "cgen_intrinsic_clipu"
18621 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
18622 
        (unspec:SI [
18623 
          (match_operand:SI 1 "general_operand" "0")
18624 
          (match_operand:SI 2 "cgen_h_uint_5a1_immediate" "")
18625 
        ] 3702))]
18626 
  "CGEN_ENABLE_INSN_P (735)"
18627 
  "clipu\\t%1,%2"
18628 
  [(set_attr "may_trap" "no")
18629 
   (set_attr "latency" "0")
18630 
   (set_attr "length" "4")
18631 
   (set_attr "slot" "core")
18632 
   (set_attr "slots" "core")
18633 
   (set_attr "stall" "int2")])
18634 
 
18635 
 
18636 
(define_insn "cgen_intrinsic_clip"
18637 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
18638 
        (unspec:SI [
18639 
          (match_operand:SI 1 "general_operand" "0")
18640 
          (match_operand:SI 2 "cgen_h_uint_5a1_immediate" "")
18641 
        ] 3704))]
18642 
  "CGEN_ENABLE_INSN_P (736)"
18643 
  "clip\\t%1,%2"
18644 
  [(set_attr "may_trap" "no")
18645 
   (set_attr "latency" "0")
18646 
   (set_attr "length" "4")
18647 
   (set_attr "slot" "core")
18648 
   (set_attr "slots" "core")
18649 
   (set_attr "stall" "int2")])
18650 
 
18651 
 
18652 
(define_insn "cgen_intrinsic_maxu"
18653 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
18654 
        (unspec:SI [
18655 
          (match_operand:SI 1 "general_operand" "0")
18656 
          (match_operand:SI 2 "general_operand" "r")
18657 
        ] 3706))]
18658 
  "CGEN_ENABLE_INSN_P (737)"
18659 
  "maxu\\t%1,%2"
18660 
  [(set_attr "may_trap" "no")
18661 
   (set_attr "latency" "0")
18662 
   (set_attr "length" "4")
18663 
   (set_attr "slot" "core")
18664 
   (set_attr "slots" "core")
18665 
   (set_attr "stall" "int2")])
18666 
 
18667 
 
18668 
(define_insn "cgen_intrinsic_minu"
18669 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
18670 
        (unspec:SI [
18671 
          (match_operand:SI 1 "general_operand" "0")
18672 
          (match_operand:SI 2 "general_operand" "r")
18673 
        ] 3708))]
18674 
  "CGEN_ENABLE_INSN_P (738)"
18675 
  "minu\\t%1,%2"
18676 
  [(set_attr "may_trap" "no")
18677 
   (set_attr "latency" "0")
18678 
   (set_attr "length" "4")
18679 
   (set_attr "slot" "core")
18680 
   (set_attr "slots" "core")
18681 
   (set_attr "stall" "int2")])
18682 
 
18683 
 
18684 
(define_insn "cgen_intrinsic_max"
18685 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
18686 
        (unspec:SI [
18687 
          (match_operand:SI 1 "general_operand" "0")
18688 
          (match_operand:SI 2 "general_operand" "r")
18689 
        ] 3710))]
18690 
  "CGEN_ENABLE_INSN_P (739)"
18691 
  "max\\t%1,%2"
18692 
  [(set_attr "may_trap" "no")
18693 
   (set_attr "latency" "0")
18694 
   (set_attr "length" "4")
18695 
   (set_attr "slot" "core")
18696 
   (set_attr "slots" "core")
18697 
   (set_attr "stall" "int2")])
18698 
 
18699 
 
18700 
(define_insn "cgen_intrinsic_min"
18701 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
18702 
        (unspec:SI [
18703 
          (match_operand:SI 1 "general_operand" "0")
18704 
          (match_operand:SI 2 "general_operand" "r")
18705 
        ] 3712))]
18706 
  "CGEN_ENABLE_INSN_P (740)"
18707 
  "min\\t%1,%2"
18708 
  [(set_attr "may_trap" "no")
18709 
   (set_attr "latency" "0")
18710 
   (set_attr "length" "4")
18711 
   (set_attr "slot" "core")
18712 
   (set_attr "slots" "core")
18713 
   (set_attr "stall" "int2")])
18714 
 
18715 
 
18716 
(define_insn "cgen_intrinsic_ave"
18717 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
18718 
        (unspec:SI [
18719 
          (match_operand:SI 1 "general_operand" "0")
18720 
          (match_operand:SI 2 "general_operand" "r")
18721 
        ] 3714))]
18722 
  "CGEN_ENABLE_INSN_P (741)"
18723 
  "ave\\t%1,%2"
18724 
  [(set_attr "may_trap" "no")
18725 
   (set_attr "latency" "0")
18726 
   (set_attr "length" "4")
18727 
   (set_attr "slot" "core")
18728 
   (set_attr "slots" "core")
18729 
   (set_attr "stall" "int2")])
18730 
 
18731 
 
18732 
(define_insn "cgen_intrinsic_abs"
18733 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
18734 
        (unspec:SI [
18735 
          (match_operand:SI 1 "general_operand" "0")
18736 
          (match_operand:SI 2 "general_operand" "r")
18737 
        ] 3716))]
18738 
  "CGEN_ENABLE_INSN_P (742)"
18739 
  "abs\\t%1,%2"
18740 
  [(set_attr "may_trap" "no")
18741 
   (set_attr "latency" "0")
18742 
   (set_attr "length" "4")
18743 
   (set_attr "slot" "core")
18744 
   (set_attr "slots" "core")
18745 
   (set_attr "stall" "int2")])
18746 
 
18747 
 
18748 
(define_insn "cgen_intrinsic_ldz"
18749 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
18750 
        (unspec:SI [
18751 
          (match_operand:SI 1 "general_operand" "r")
18752 
        ] 3718))]
18753 
  "CGEN_ENABLE_INSN_P (743)"
18754 
  "ldz\\t%0,%1"
18755 
  [(set_attr "may_trap" "no")
18756 
   (set_attr "latency" "0")
18757 
   (set_attr "length" "4")
18758 
   (set_attr "slot" "core")
18759 
   (set_attr "slots" "core")
18760 
   (set_attr "stall" "int2")])
18761 
 
18762 
 
18763 
(define_insn "cgen_intrinsic_dbreak"
18764 
  [(set (reg:SI 40)
18765 
        (unspec_volatile:SI [
18766 
          (reg:SI 40)
18767 
        ] 3720))]
18768 
  "CGEN_ENABLE_INSN_P (744)"
18769 
  "dbreak"
18770 
  [(set_attr "may_trap" "yes")
18771 
   (set_attr "latency" "0")
18772 
   (set_attr "length" "2")
18773 
   (set_attr "slot" "core")
18774 
   (set_attr "slots" "core")
18775 
   (set_attr "stall" "none")])
18776 
 
18777 
 
18778 
(define_insn "cgen_intrinsic_dret"
18779 
  [(set (pc)
18780 
        (unspec:SI [
18781 
          (reg:SI 41)
18782 
          (reg:SI 40)
18783 
        ] 3722))
18784 
   (set (reg:SI 40)
18785 
        (unspec:SI [
18786 
          (reg:SI 41)
18787 
          (reg:SI 40)
18788 
        ] 3724))
18789 
   (set (reg:SI 115)
18790 
        (unspec:SI [
18791 
          (reg:SI 41)
18792 
          (reg:SI 40)
18793 
        ] 3725))]
18794 
  "CGEN_ENABLE_INSN_P (745)"
18795 
  "dret"
18796 
  [(set_attr "may_trap" "no")
18797 
   (set_attr "latency" "0")
18798 
   (set_attr "length" "2")
18799 
   (set_attr "slot" "core")
18800 
   (set_attr "slots" "core")
18801 
   (set_attr "stall" "none")])
18802 
 
18803 
 
18804 
(define_insn "cgen_intrinsic_divu"
18805 
  [(set (pc)
18806 
        (unspec:SI [
18807 
          (match_operand:SI 0 "general_operand" "r")
18808 
          (match_operand:SI 1 "general_operand" "r")
18809 
        ] 3726))
18810 
   (set (reg:SI 24)
18811 
        (unspec:SI [
18812 
          (match_dup 0)
18813 
          (match_dup 1)
18814 
        ] 3728))
18815 
   (set (reg:SI 116)
18816 
        (unspec:SI [
18817 
          (match_dup 0)
18818 
          (match_dup 1)
18819 
        ] 3729))
18820 
   (set (reg:SI 23)
18821 
        (unspec:SI [
18822 
          (match_dup 0)
18823 
          (match_dup 1)
18824 
        ] 3730))
18825 
   (set (reg:SI 117)
18826 
        (unspec:SI [
18827 
          (match_dup 0)
18828 
          (match_dup 1)
18829 
        ] 3731))]
18830 
  "CGEN_ENABLE_INSN_P (746)"
18831 
  "divu\\t%0,%1"
18832 
  [(set_attr "may_trap" "yes")
18833 
   (set_attr "latency" "34")
18834 
   (set_attr "length" "2")
18835 
   (set_attr "slot" "core")
18836 
   (set_attr "slots" "core")
18837 
   (set_attr "stall" "div")])
18838 
 
18839 
 
18840 
(define_insn "cgen_intrinsic_div"
18841 
  [(set (pc)
18842 
        (unspec:SI [
18843 
          (match_operand:SI 0 "general_operand" "r")
18844 
          (match_operand:SI 1 "general_operand" "r")
18845 
        ] 3732))
18846 
   (set (reg:SI 24)
18847 
        (unspec:SI [
18848 
          (match_dup 0)
18849 
          (match_dup 1)
18850 
        ] 3734))
18851 
   (set (reg:SI 116)
18852 
        (unspec:SI [
18853 
          (match_dup 0)
18854 
          (match_dup 1)
18855 
        ] 3735))
18856 
   (set (reg:SI 23)
18857 
        (unspec:SI [
18858 
          (match_dup 0)
18859 
          (match_dup 1)
18860 
        ] 3736))
18861 
   (set (reg:SI 117)
18862 
        (unspec:SI [
18863 
          (match_dup 0)
18864 
          (match_dup 1)
18865 
        ] 3737))]
18866 
  "CGEN_ENABLE_INSN_P (747)"
18867 
  "div\\t%0,%1"
18868 
  [(set_attr "may_trap" "yes")
18869 
   (set_attr "latency" "34")
18870 
   (set_attr "length" "2")
18871 
   (set_attr "slot" "core")
18872 
   (set_attr "slots" "core")
18873 
   (set_attr "stall" "div")])
18874 
 
18875 
 
18876 
(define_insn "cgen_intrinsic_maddru"
18877 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
18878 
        (unspec:SI [
18879 
          (match_operand:SI 1 "general_operand" "0")
18880 
          (match_operand:SI 2 "general_operand" "r")
18881 
          (reg:SI 24)
18882 
          (reg:SI 23)
18883 
        ] 3738))
18884 
   (set (reg:SI 24)
18885 
        (unspec:SI [
18886 
          (match_dup 1)
18887 
          (match_dup 2)
18888 
          (reg:SI 24)
18889 
          (reg:SI 23)
18890 
        ] 3740))
18891 
   (set (reg:SI 116)
18892 
        (unspec:SI [
18893 
          (match_dup 1)
18894 
          (match_dup 2)
18895 
          (reg:SI 24)
18896 
          (reg:SI 23)
18897 
        ] 3741))
18898 
   (set (reg:SI 23)
18899 
        (unspec:SI [
18900 
          (match_dup 1)
18901 
          (match_dup 2)
18902 
          (reg:SI 24)
18903 
          (reg:SI 23)
18904 
        ] 3742))
18905 
   (set (reg:SI 117)
18906 
        (unspec:SI [
18907 
          (match_dup 1)
18908 
          (match_dup 2)
18909 
          (reg:SI 24)
18910 
          (reg:SI 23)
18911 
        ] 3743))]
18912 
  "CGEN_ENABLE_INSN_P (748)"
18913 
  "maddru\\t%1,%2"
18914 
  [(set_attr "may_trap" "no")
18915 
   (set_attr "latency" "3")
18916 
   (set_attr "length" "4")
18917 
   (set_attr "slot" "core")
18918 
   (set_attr "slots" "core")
18919 
   (set_attr "stall" "mulr")])
18920 
 
18921 
 
18922 
(define_insn "cgen_intrinsic_maddr"
18923 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
18924 
        (unspec:SI [
18925 
          (match_operand:SI 1 "general_operand" "0")
18926 
          (match_operand:SI 2 "general_operand" "r")
18927 
          (reg:SI 24)
18928 
          (reg:SI 23)
18929 
        ] 3744))
18930 
   (set (reg:SI 24)
18931 
        (unspec:SI [
18932 
          (match_dup 1)
18933 
          (match_dup 2)
18934 
          (reg:SI 24)
18935 
          (reg:SI 23)
18936 
        ] 3746))
18937 
   (set (reg:SI 116)
18938 
        (unspec:SI [
18939 
          (match_dup 1)
18940 
          (match_dup 2)
18941 
          (reg:SI 24)
18942 
          (reg:SI 23)
18943 
        ] 3747))
18944 
   (set (reg:SI 23)
18945 
        (unspec:SI [
18946 
          (match_dup 1)
18947 
          (match_dup 2)
18948 
          (reg:SI 24)
18949 
          (reg:SI 23)
18950 
        ] 3748))
18951 
   (set (reg:SI 117)
18952 
        (unspec:SI [
18953 
          (match_dup 1)
18954 
          (match_dup 2)
18955 
          (reg:SI 24)
18956 
          (reg:SI 23)
18957 
        ] 3749))]
18958 
  "CGEN_ENABLE_INSN_P (749)"
18959 
  "maddr\\t%1,%2"
18960 
  [(set_attr "may_trap" "no")
18961 
   (set_attr "latency" "3")
18962 
   (set_attr "length" "4")
18963 
   (set_attr "slot" "core")
18964 
   (set_attr "slots" "core")
18965 
   (set_attr "stall" "mulr")])
18966 
 
18967 
 
18968 
(define_insn "cgen_intrinsic_maddu"
18969 
  [(set (reg:SI 24)
18970 
        (unspec:SI [
18971 
          (match_operand:SI 0 "general_operand" "r")
18972 
          (match_operand:SI 1 "general_operand" "r")
18973 
          (reg:SI 24)
18974 
          (reg:SI 23)
18975 
        ] 3750))
18976 
   (set (reg:SI 116)
18977 
        (unspec:SI [
18978 
          (match_dup 0)
18979 
          (match_dup 1)
18980 
          (reg:SI 24)
18981 
          (reg:SI 23)
18982 
        ] 3751))
18983 
   (set (reg:SI 23)
18984 
        (unspec:SI [
18985 
          (match_dup 0)
18986 
          (match_dup 1)
18987 
          (reg:SI 24)
18988 
          (reg:SI 23)
18989 
        ] 3752))
18990 
   (set (reg:SI 117)
18991 
        (unspec:SI [
18992 
          (match_dup 0)
18993 
          (match_dup 1)
18994 
          (reg:SI 24)
18995 
          (reg:SI 23)
18996 
        ] 3753))]
18997 
  "CGEN_ENABLE_INSN_P (750)"
18998 
  "maddu\\t%0,%1"
18999 
  [(set_attr "may_trap" "no")
19000 
   (set_attr "latency" "0")
19001 
   (set_attr "length" "4")
19002 
   (set_attr "slot" "core")
19003 
   (set_attr "slots" "core")
19004 
   (set_attr "stall" "mul")])
19005 
 
19006 
 
19007 
(define_insn "cgen_intrinsic_madd"
19008 
  [(set (reg:SI 24)
19009 
        (unspec:SI [
19010 
          (match_operand:SI 0 "general_operand" "r")
19011 
          (match_operand:SI 1 "general_operand" "r")
19012 
          (reg:SI 24)
19013 
          (reg:SI 23)
19014 
        ] 3754))
19015 
   (set (reg:SI 116)
19016 
        (unspec:SI [
19017 
          (match_dup 0)
19018 
          (match_dup 1)
19019 
          (reg:SI 24)
19020 
          (reg:SI 23)
19021 
        ] 3755))
19022 
   (set (reg:SI 23)
19023 
        (unspec:SI [
19024 
          (match_dup 0)
19025 
          (match_dup 1)
19026 
          (reg:SI 24)
19027 
          (reg:SI 23)
19028 
        ] 3756))
19029 
   (set (reg:SI 117)
19030 
        (unspec:SI [
19031 
          (match_dup 0)
19032 
          (match_dup 1)
19033 
          (reg:SI 24)
19034 
          (reg:SI 23)
19035 
        ] 3757))]
19036 
  "CGEN_ENABLE_INSN_P (751)"
19037 
  "madd\\t%0,%1"
19038 
  [(set_attr "may_trap" "no")
19039 
   (set_attr "latency" "0")
19040 
   (set_attr "length" "4")
19041 
   (set_attr "slot" "core")
19042 
   (set_attr "slots" "core")
19043 
   (set_attr "stall" "mul")])
19044 
 
19045 
 
19046 
(define_insn "cgen_intrinsic_mulru"
19047 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
19048 
        (unspec:SI [
19049 
          (match_operand:SI 1 "general_operand" "0")
19050 
          (match_operand:SI 2 "general_operand" "r")
19051 
        ] 3758))
19052 
   (set (reg:SI 24)
19053 
        (unspec:SI [
19054 
          (match_dup 1)
19055 
          (match_dup 2)
19056 
        ] 3760))
19057 
   (set (reg:SI 116)
19058 
        (unspec:SI [
19059 
          (match_dup 1)
19060 
          (match_dup 2)
19061 
        ] 3761))
19062 
   (set (reg:SI 23)
19063 
        (unspec:SI [
19064 
          (match_dup 1)
19065 
          (match_dup 2)
19066 
        ] 3762))
19067 
   (set (reg:SI 117)
19068 
        (unspec:SI [
19069 
          (match_dup 1)
19070 
          (match_dup 2)
19071 
        ] 3763))]
19072 
  "CGEN_ENABLE_INSN_P (752)"
19073 
  "mulru\\t%1,%2"
19074 
  [(set_attr "may_trap" "no")
19075 
   (set_attr "latency" "3")
19076 
   (set_attr "length" "2")
19077 
   (set_attr "slot" "core")
19078 
   (set_attr "slots" "core")
19079 
   (set_attr "stall" "mulr")])
19080 
 
19081 
 
19082 
(define_insn "cgen_intrinsic_mulr"
19083 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
19084 
        (unspec:SI [
19085 
          (match_operand:SI 1 "general_operand" "0")
19086 
          (match_operand:SI 2 "general_operand" "r")
19087 
        ] 3764))
19088 
   (set (reg:SI 24)
19089 
        (unspec:SI [
19090 
          (match_dup 1)
19091 
          (match_dup 2)
19092 
        ] 3766))
19093 
   (set (reg:SI 116)
19094 
        (unspec:SI [
19095 
          (match_dup 1)
19096 
          (match_dup 2)
19097 
        ] 3767))
19098 
   (set (reg:SI 23)
19099 
        (unspec:SI [
19100 
          (match_dup 1)
19101 
          (match_dup 2)
19102 
        ] 3768))
19103 
   (set (reg:SI 117)
19104 
        (unspec:SI [
19105 
          (match_dup 1)
19106 
          (match_dup 2)
19107 
        ] 3769))]
19108 
  "CGEN_ENABLE_INSN_P (753)"
19109 
  "mulr\\t%1,%2"
19110 
  [(set_attr "may_trap" "no")
19111 
   (set_attr "latency" "3")
19112 
   (set_attr "length" "2")
19113 
   (set_attr "slot" "core")
19114 
   (set_attr "slots" "core")
19115 
   (set_attr "stall" "mulr")])
19116 
 
19117 
 
19118 
(define_insn "cgen_intrinsic_mulu"
19119 
  [(set (reg:SI 24)
19120 
        (unspec:SI [
19121 
          (match_operand:SI 0 "general_operand" "r")
19122 
          (match_operand:SI 1 "general_operand" "r")
19123 
        ] 3770))
19124 
   (set (reg:SI 116)
19125 
        (unspec:SI [
19126 
          (match_dup 0)
19127 
          (match_dup 1)
19128 
        ] 3771))
19129 
   (set (reg:SI 23)
19130 
        (unspec:SI [
19131 
          (match_dup 0)
19132 
          (match_dup 1)
19133 
        ] 3772))
19134 
   (set (reg:SI 117)
19135 
        (unspec:SI [
19136 
          (match_dup 0)
19137 
          (match_dup 1)
19138 
        ] 3773))]
19139 
  "CGEN_ENABLE_INSN_P (754)"
19140 
  "mulu\\t%0,%1"
19141 
  [(set_attr "may_trap" "no")
19142 
   (set_attr "latency" "0")
19143 
   (set_attr "length" "2")
19144 
   (set_attr "slot" "core")
19145 
   (set_attr "slots" "core")
19146 
   (set_attr "stall" "mul")])
19147 
 
19148 
 
19149 
(define_insn "cgen_intrinsic_mul"
19150 
  [(set (reg:SI 24)
19151 
        (unspec:SI [
19152 
          (match_operand:SI 0 "general_operand" "r")
19153 
          (match_operand:SI 1 "general_operand" "r")
19154 
        ] 3774))
19155 
   (set (reg:SI 116)
19156 
        (unspec:SI [
19157 
          (match_dup 0)
19158 
          (match_dup 1)
19159 
        ] 3775))
19160 
   (set (reg:SI 23)
19161 
        (unspec:SI [
19162 
          (match_dup 0)
19163 
          (match_dup 1)
19164 
        ] 3776))
19165 
   (set (reg:SI 117)
19166 
        (unspec:SI [
19167 
          (match_dup 0)
19168 
          (match_dup 1)
19169 
        ] 3777))]
19170 
  "CGEN_ENABLE_INSN_P (755)"
19171 
  "mul\\t%0,%1"
19172 
  [(set_attr "may_trap" "no")
19173 
   (set_attr "latency" "0")
19174 
   (set_attr "length" "2")
19175 
   (set_attr "slot" "core")
19176 
   (set_attr "slots" "core")
19177 
   (set_attr "stall" "mul")])
19178 
 
19179 
 
19180 
(define_insn "cgen_intrinsic_cache"
19181 
  [(unspec_volatile [
19182 
     (match_operand:SI 0 "cgen_h_uint_4a1_immediate" "")
19183 
     (match_operand:SI 1 "general_operand" "r")
19184 
   ] 3778)]
19185 
  "CGEN_ENABLE_INSN_P (756)"
19186 
  "cache\\t%0,(%1)"
19187 
  [(set_attr "may_trap" "no")
19188 
   (set_attr "latency" "0")
19189 
   (set_attr "length" "2")
19190 
   (set_attr "slot" "core")
19191 
   (set_attr "slots" "core")
19192 
   (set_attr "stall" "none")])
19193 
 
19194 
 
19195 
(define_insn "cgen_intrinsic_tas"
19196 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
19197 
        (unspec:SI [
19198 
          (match_operand:SI 1 "general_operand" "r")
19199 
          (mem:SI (scratch:SI))
19200 
        ] 3780))
19201 
   (set (mem:SI (scratch:SI))
19202 
        (unspec:SI [
19203 
          (match_dup 1)
19204 
          (mem:SI (scratch:SI))
19205 
        ] 3782))]
19206 
  "CGEN_ENABLE_INSN_P (757)"
19207 
  "tas\\t%0,(%1)"
19208 
  [(set_attr "may_trap" "no")
19209 
   (set_attr "latency" "0")
19210 
   (set_attr "length" "2")
19211 
   (set_attr "slot" "core")
19212 
   (set_attr "slots" "core")
19213 
   (set_attr "stall" "none")])
19214 
 
19215 
 
19216 
(define_insn "cgen_intrinsic_btstm"
19217 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=z")
19218 
        (unspec:SI [
19219 
          (match_operand:SI 1 "general_operand" "r")
19220 
          (match_operand:SI 2 "cgen_h_uint_3a1_immediate" "")
19221 
          (mem:SI (scratch:SI))
19222 
        ] 3784))]
19223 
  "CGEN_ENABLE_INSN_P (758)"
19224 
  "btstm\\t$0,(%1),%2"
19225 
  [(set_attr "may_trap" "no")
19226 
   (set_attr "latency" "0")
19227 
   (set_attr "length" "2")
19228 
   (set_attr "slot" "core")
19229 
   (set_attr "slots" "core")
19230 
   (set_attr "stall" "none")])
19231 
 
19232 
 
19233 
(define_insn "cgen_intrinsic_bnotm"
19234 
  [(set (mem:SI (scratch:SI))
19235 
        (unspec:SI [
19236 
          (match_operand:SI 0 "general_operand" "r")
19237 
          (match_operand:SI 1 "cgen_h_uint_3a1_immediate" "")
19238 
          (mem:SI (scratch:SI))
19239 
        ] 3786))]
19240 
  "CGEN_ENABLE_INSN_P (759)"
19241 
  "bnotm\\t(%0),%1"
19242 
  [(set_attr "may_trap" "no")
19243 
   (set_attr "latency" "0")
19244 
   (set_attr "length" "2")
19245 
   (set_attr "slot" "core")
19246 
   (set_attr "slots" "core")
19247 
   (set_attr "stall" "none")])
19248 
 
19249 
 
19250 
(define_insn "cgen_intrinsic_bclrm"
19251 
  [(set (mem:SI (scratch:SI))
19252 
        (unspec:SI [
19253 
          (match_operand:SI 0 "general_operand" "r")
19254 
          (match_operand:SI 1 "cgen_h_uint_3a1_immediate" "")
19255 
          (mem:SI (scratch:SI))
19256 
        ] 3788))]
19257 
  "CGEN_ENABLE_INSN_P (760)"
19258 
  "bclrm\\t(%0),%1"
19259 
  [(set_attr "may_trap" "no")
19260 
   (set_attr "latency" "0")
19261 
   (set_attr "length" "2")
19262 
   (set_attr "slot" "core")
19263 
   (set_attr "slots" "core")
19264 
   (set_attr "stall" "none")])
19265 
 
19266 
 
19267 
(define_insn "cgen_intrinsic_bsetm"
19268 
  [(set (mem:SI (scratch:SI))
19269 
        (unspec:SI [
19270 
          (match_operand:SI 0 "general_operand" "r")
19271 
          (match_operand:SI 1 "cgen_h_uint_3a1_immediate" "")
19272 
          (mem:SI (scratch:SI))
19273 
        ] 3790))]
19274 
  "CGEN_ENABLE_INSN_P (761)"
19275 
  "bsetm\\t(%0),%1"
19276 
  [(set_attr "may_trap" "no")
19277 
   (set_attr "latency" "0")
19278 
   (set_attr "length" "2")
19279 
   (set_attr "slot" "core")
19280 
   (set_attr "slots" "core")
19281 
   (set_attr "stall" "none")])
19282 
 
19283 
 
19284 
(define_insn "cgen_intrinsic_ldcb"
19285 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
19286 
        (unspec_volatile:SI [
19287 
          (match_operand:SI 1 "cgen_h_uint_16a1_immediate" "")
19288 
        ] 3792))]
19289 
  "CGEN_ENABLE_INSN_P (762)"
19290 
  "ldcb\\t%0,%1"
19291 
  [(set_attr "may_trap" "no")
19292 
   (set_attr "latency" "3")
19293 
   (set_attr "length" "4")
19294 
   (set_attr "slot" "core")
19295 
   (set_attr "slots" "core")
19296 
   (set_attr "stall" "ldcb")])
19297 
 
19298 
 
19299 
(define_insn "cgen_intrinsic_stcb"
19300 
  [(unspec_volatile [
19301 
     (match_operand:SI 0 "general_operand" "r")
19302 
     (match_operand:SI 1 "cgen_h_uint_16a1_immediate" "")
19303 
   ] 3794)]
19304 
  "CGEN_ENABLE_INSN_P (763)"
19305 
  "stcb\\t%0,%1"
19306 
  [(set_attr "may_trap" "no")
19307 
   (set_attr "latency" "0")
19308 
   (set_attr "length" "4")
19309 
   (set_attr "slot" "core")
19310 
   (set_attr "slots" "core")
19311 
   (set_attr "stall" "stcb")])
19312 
 
19313 
 
19314 
(define_insn "cgen_intrinsic_syncm"
19315 
  [(unspec_volatile [
19316 
     (const_int 0)
19317 
   ] 3796)]
19318 
  "CGEN_ENABLE_INSN_P (764)"
19319 
  "syncm"
19320 
  [(set_attr "may_trap" "no")
19321 
   (set_attr "latency" "0")
19322 
   (set_attr "length" "2")
19323 
   (set_attr "slot" "core")
19324 
   (set_attr "slots" "core")
19325 
   (set_attr "stall" "none")])
19326 
 
19327 
 
19328 
(define_insn "cgen_intrinsic_break"
19329 
  [(set (pc)
19330 
        (unspec_volatile:SI [
19331 
          (const_int 0)
19332 
        ] 3798))]
19333 
  "CGEN_ENABLE_INSN_P (765)"
19334 
  "break"
19335 
  [(set_attr "may_trap" "yes")
19336 
   (set_attr "latency" "0")
19337 
   (set_attr "length" "2")
19338 
   (set_attr "slot" "core")
19339 
   (set_attr "slots" "core")
19340 
   (set_attr "stall" "none")])
19341 
 
19342 
 
19343 
(define_insn "cgen_intrinsic_swi"
19344 
  [(set (reg:SI 36)
19345 
        (unspec_volatile:SI [
19346 
          (match_operand:SI 0 "cgen_h_uint_2a1_immediate" "")
19347 
          (reg:SI 36)
19348 
        ] 3800))]
19349 
  "CGEN_ENABLE_INSN_P (766)"
19350 
  "swi\\t%0"
19351 
  [(set_attr "may_trap" "yes")
19352 
   (set_attr "latency" "0")
19353 
   (set_attr "length" "2")
19354 
   (set_attr "slot" "core")
19355 
   (set_attr "slots" "core")
19356 
   (set_attr "stall" "none")])
19357 
 
19358 
 
19359 
(define_insn "cgen_intrinsic_sleep"
19360 
  [(unspec_volatile [
19361 
     (const_int 0)
19362 
   ] 3802)]
19363 
  "CGEN_ENABLE_INSN_P (767)"
19364 
  "sleep"
19365 
  [(set_attr "may_trap" "no")
19366 
   (set_attr "latency" "0")
19367 
   (set_attr "length" "2")
19368 
   (set_attr "slot" "core")
19369 
   (set_attr "slots" "core")
19370 
   (set_attr "stall" "none")])
19371 
 
19372 
 
19373 
(define_insn "cgen_intrinsic_halt"
19374 
  [(unspec_volatile [
19375 
     (reg:SI 32)
19376 
   ] 3804)]
19377 
  "CGEN_ENABLE_INSN_P (768)"
19378 
  "halt"
19379 
  [(set_attr "may_trap" "no")
19380 
   (set_attr "latency" "0")
19381 
   (set_attr "length" "2")
19382 
   (set_attr "slot" "core")
19383 
   (set_attr "slots" "core")
19384 
   (set_attr "stall" "none")])
19385 
 
19386 
 
19387 
(define_insn "cgen_intrinsic_reti"
19388 
  [(set (pc)
19389 
        (unspec:SI [
19390 
          (reg:SI 32)
19391 
          (reg:SI 42)
19392 
          (reg:SI 39)
19393 
          (reg:SI 35)
19394 
        ] 3806))]
19395 
  "CGEN_ENABLE_INSN_P (769)"
19396 
  "reti"
19397 
  [(set_attr "may_trap" "no")
19398 
   (set_attr "latency" "0")
19399 
   (set_attr "length" "2")
19400 
   (set_attr "slot" "core")
19401 
   (set_attr "slots" "core")
19402 
   (set_attr "stall" "ret")])
19403 
 
19404 
 
19405 
(define_insn "cgen_intrinsic_ei"
19406 
  [(set (reg:SI 32)
19407 
        (unspec_volatile:SI [
19408 
          (reg:SI 32)
19409 
        ] 3808))]
19410 
  "CGEN_ENABLE_INSN_P (770)"
19411 
  "ei"
19412 
  [(set_attr "may_trap" "no")
19413 
   (set_attr "latency" "0")
19414 
   (set_attr "length" "2")
19415 
   (set_attr "slot" "core")
19416 
   (set_attr "slots" "core")
19417 
   (set_attr "stall" "none")])
19418 
 
19419 
 
19420 
(define_insn "cgen_intrinsic_di"
19421 
  [(set (reg:SI 32)
19422 
        (unspec_volatile:SI [
19423 
          (reg:SI 32)
19424 
        ] 3810))]
19425 
  "CGEN_ENABLE_INSN_P (771)"
19426 
  "di"
19427 
  [(set_attr "may_trap" "no")
19428 
   (set_attr "latency" "0")
19429 
   (set_attr "length" "2")
19430 
   (set_attr "slot" "core")
19431 
   (set_attr "slots" "core")
19432 
   (set_attr "stall" "none")])
19433 
 
19434 
 
19435 
(define_insn "cgen_intrinsic_ldc"
19436 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
19437 
        (unspec_volatile:SI [
19438 
          (match_operand:SI 1 "general_operand" "c")
19439 
          (reg:SI 32)
19440 
          (reg:SI 42)
19441 
        ] 3812))]
19442 
  "CGEN_ENABLE_INSN_P (772)"
19443 
  "ldc\\t%0,%1"
19444 
  [(set_attr "may_trap" "no")
19445 
   (set_attr "latency" "2")
19446 
   (set_attr "length" "2")
19447 
   (set_attr "slot" "core")
19448 
   (set_attr "slots" "core")
19449 
   (set_attr "stall" "ldc")])
19450 
 
19451 
 
19452 
(define_insn "cgen_intrinsic_ldc_lo"
19453 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
19454 
        (unspec:SI [
19455 
          (reg:SI 24)
19456 
        ] 3814))]
19457 
  "CGEN_ENABLE_INSN_P (773)"
19458 
  "ldc\\t%0,$lo"
19459 
  [(set_attr "may_trap" "no")
19460 
   (set_attr "latency" "0")
19461 
   (set_attr "length" "2")
19462 
   (set_attr "slot" "core")
19463 
   (set_attr "slots" "core")
19464 
   (set_attr "stall" "ldc")])
19465 
 
19466 
 
19467 
(define_insn "cgen_intrinsic_ldc_hi"
19468 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
19469 
        (unspec:SI [
19470 
          (reg:SI 23)
19471 
        ] 3816))]
19472 
  "CGEN_ENABLE_INSN_P (774)"
19473 
  "ldc\\t%0,$hi"
19474 
  [(set_attr "may_trap" "no")
19475 
   (set_attr "latency" "0")
19476 
   (set_attr "length" "2")
19477 
   (set_attr "slot" "core")
19478 
   (set_attr "slots" "core")
19479 
   (set_attr "stall" "ldc")])
19480 
 
19481 
 
19482 
(define_insn "cgen_intrinsic_ldc_lp"
19483 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
19484 
        (unspec:SI [
19485 
          (reg:SI 17)
19486 
        ] 3818))]
19487 
  "CGEN_ENABLE_INSN_P (775)"
19488 
  "ldc\\t%0,$lp"
19489 
  [(set_attr "may_trap" "no")
19490 
   (set_attr "latency" "0")
19491 
   (set_attr "length" "2")
19492 
   (set_attr "slot" "core")
19493 
   (set_attr "slots" "core")
19494 
   (set_attr "stall" "ldc")])
19495 
 
19496 
 
19497 
(define_insn "cgen_intrinsic_stc"
19498 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=c")
19499 
        (unspec_volatile:SI [
19500 
          (match_operand:SI 1 "general_operand" "r")
19501 
        ] 3820))]
19502 
  "CGEN_ENABLE_INSN_P (776)"
19503 
  "stc\\t%1,%0"
19504 
  [(set_attr "may_trap" "no")
19505 
   (set_attr "latency" "0")
19506 
   (set_attr "length" "2")
19507 
   (set_attr "slot" "core")
19508 
   (set_attr "slots" "core")
19509 
   (set_attr "stall" "stc")])
19510 
 
19511 
 
19512 
(define_insn "cgen_intrinsic_stc_lo"
19513 
  [(set (reg:SI 24)
19514 
        (unspec:SI [
19515 
          (match_operand:SI 0 "general_operand" "r")
19516 
        ] 3822))
19517 
   (set (reg:SI 116)
19518 
        (unspec:SI [
19519 
          (match_dup 0)
19520 
        ] 3823))]
19521 
  "CGEN_ENABLE_INSN_P (777)"
19522 
  "stc\\t%0,$lo"
19523 
  [(set_attr "may_trap" "no")
19524 
   (set_attr "latency" "0")
19525 
   (set_attr "length" "2")
19526 
   (set_attr "slot" "core")
19527 
   (set_attr "slots" "core")
19528 
   (set_attr "stall" "stc")])
19529 
 
19530 
 
19531 
(define_insn "cgen_intrinsic_stc_hi"
19532 
  [(set (reg:SI 23)
19533 
        (unspec:SI [
19534 
          (match_operand:SI 0 "general_operand" "r")
19535 
        ] 3824))
19536 
   (set (reg:SI 117)
19537 
        (unspec:SI [
19538 
          (match_dup 0)
19539 
        ] 3825))]
19540 
  "CGEN_ENABLE_INSN_P (778)"
19541 
  "stc\\t%0,$hi"
19542 
  [(set_attr "may_trap" "no")
19543 
   (set_attr "latency" "0")
19544 
   (set_attr "length" "2")
19545 
   (set_attr "slot" "core")
19546 
   (set_attr "slots" "core")
19547 
   (set_attr "stall" "stc")])
19548 
 
19549 
 
19550 
(define_insn "cgen_intrinsic_stc_lp"
19551 
  [(set (reg:SI 17)
19552 
        (unspec:SI [
19553 
          (match_operand:SI 0 "general_operand" "r")
19554 
        ] 3826))
19555 
   (set (reg:SI 114)
19556 
        (unspec:SI [
19557 
          (match_dup 0)
19558 
        ] 3827))]
19559 
  "CGEN_ENABLE_INSN_P (779)"
19560 
  "stc\\t%0,$lp"
19561 
  [(set_attr "may_trap" "no")
19562 
   (set_attr "latency" "0")
19563 
   (set_attr "length" "2")
19564 
   (set_attr "slot" "core")
19565 
   (set_attr "slots" "core")
19566 
   (set_attr "stall" "stc")])
19567 
 
19568 
 
19569 
(define_insn "cgen_intrinsic_erepeat"
19570 
  [(set (reg:SI 22)
19571 
        (unspec:SI [
19572 
          (match_operand:SI 0 "immediate_operand" "")
19573 
          (reg:SI 32)
19574 
          (reg:SI 42)
19575 
        ] 3828))
19576 
   (set (reg:SI 118)
19577 
        (unspec:SI [
19578 
          (match_dup 0)
19579 
          (reg:SI 32)
19580 
          (reg:SI 42)
19581 
        ] 3829))
19582 
   (set (reg:SI 21)
19583 
        (unspec:SI [
19584 
          (match_dup 0)
19585 
          (reg:SI 32)
19586 
          (reg:SI 42)
19587 
        ] 3830))
19588 
   (set (reg:SI 119)
19589 
        (unspec:SI [
19590 
          (match_dup 0)
19591 
          (reg:SI 32)
19592 
          (reg:SI 42)
19593 
        ] 3831))
19594 
   (set (reg:SI 20)
19595 
        (unspec:SI [
19596 
          (match_dup 0)
19597 
          (reg:SI 32)
19598 
          (reg:SI 42)
19599 
        ] 3832))
19600 
   (set (reg:SI 120)
19601 
        (unspec:SI [
19602 
          (match_dup 0)
19603 
          (reg:SI 32)
19604 
          (reg:SI 42)
19605 
        ] 3833))]
19606 
  "CGEN_ENABLE_INSN_P (780)"
19607 
  "erepeat\\t%l0"
19608 
  [(set_attr "may_trap" "no")
19609 
   (set_attr "latency" "0")
19610 
   (set_attr "length" "4")
19611 
   (set_attr "slot" "core")
19612 
   (set_attr "slots" "core")
19613 
   (set_attr "stall" "none")])
19614 
 
19615 
 
19616 
(define_insn "cgen_intrinsic_repeat"
19617 
  [(set (reg:SI 22)
19618 
        (unspec:SI [
19619 
          (match_operand:SI 0 "general_operand" "r")
19620 
          (match_operand:SI 1 "immediate_operand" "")
19621 
          (reg:SI 32)
19622 
          (reg:SI 42)
19623 
        ] 3834))
19624 
   (set (reg:SI 118)
19625 
        (unspec:SI [
19626 
          (match_dup 0)
19627 
          (match_dup 1)
19628 
          (reg:SI 32)
19629 
          (reg:SI 42)
19630 
        ] 3835))
19631 
   (set (reg:SI 21)
19632 
        (unspec:SI [
19633 
          (match_dup 0)
19634 
          (match_dup 1)
19635 
          (reg:SI 32)
19636 
          (reg:SI 42)
19637 
        ] 3836))
19638 
   (set (reg:SI 119)
19639 
        (unspec:SI [
19640 
          (match_dup 0)
19641 
          (match_dup 1)
19642 
          (reg:SI 32)
19643 
          (reg:SI 42)
19644 
        ] 3837))
19645 
   (set (reg:SI 20)
19646 
        (unspec:SI [
19647 
          (match_dup 0)
19648 
          (match_dup 1)
19649 
          (reg:SI 32)
19650 
          (reg:SI 42)
19651 
        ] 3838))
19652 
   (set (reg:SI 120)
19653 
        (unspec:SI [
19654 
          (match_dup 0)
19655 
          (match_dup 1)
19656 
          (reg:SI 32)
19657 
          (reg:SI 42)
19658 
        ] 3839))]
19659 
  "CGEN_ENABLE_INSN_P (781)"
19660 
  "repeat\\t%0,%l1"
19661 
  [(set_attr "may_trap" "no")
19662 
   (set_attr "latency" "0")
19663 
   (set_attr "length" "4")
19664 
   (set_attr "slot" "core")
19665 
   (set_attr "slots" "core")
19666 
   (set_attr "stall" "none")])
19667 
 
19668 
 
19669 
(define_insn "cgen_intrinsic_ret"
19670 
  [(set (pc)
19671 
        (unspec:SI [
19672 
          (reg:SI 32)
19673 
          (reg:SI 42)
19674 
          (reg:SI 17)
19675 
        ] 3840))]
19676 
  "CGEN_ENABLE_INSN_P (782)"
19677 
  "ret"
19678 
  [(set_attr "may_trap" "no")
19679 
   (set_attr "latency" "0")
19680 
   (set_attr "length" "2")
19681 
   (set_attr "slot" "core")
19682 
   (set_attr "slots" "core")
19683 
   (set_attr "stall" "ret")])
19684 
 
19685 
 
19686 
(define_insn "cgen_intrinsic_jsr"
19687 
  [(set (pc)
19688 
        (unspec:SI [
19689 
          (match_operand:SI 0 "general_operand" "r")
19690 
          (reg:SI 32)
19691 
          (reg:SI 42)
19692 
        ] 3842))
19693 
   (set (reg:SI 17)
19694 
        (unspec:SI [
19695 
          (match_dup 0)
19696 
          (reg:SI 32)
19697 
          (reg:SI 42)
19698 
        ] 3844))
19699 
   (set (reg:SI 114)
19700 
        (unspec:SI [
19701 
          (match_dup 0)
19702 
          (reg:SI 32)
19703 
          (reg:SI 42)
19704 
        ] 3845))]
19705 
  "CGEN_ENABLE_INSN_P (783)"
19706 
  "jsr\\t%0"
19707 
  [(set_attr "may_trap" "no")
19708 
   (set_attr "latency" "0")
19709 
   (set_attr "length" "2")
19710 
   (set_attr "slot" "core")
19711 
   (set_attr "slots" "core")
19712 
   (set_attr "stall" "none")])
19713 
 
19714 
 
19715 
(define_insn "cgen_intrinsic_jmp24"
19716 
  [(set (pc)
19717 
        (if_then_else (eq (unspec [
19718 
                            (match_operand:SI 0 "immediate_operand" "")
19719 
                            (reg:SI 32)
19720 
                            (reg:SI 42)
19721 
                          ] 3846)
19722 
                          (const_int 0))
19723 
                      (match_dup 0)
19724 
                      (pc)))]
19725 
  "CGEN_ENABLE_INSN_P (784)"
19726 
  "jmp\\t%l0"
19727 
  [(set_attr "may_trap" "no")
19728 
   (set_attr "latency" "0")
19729 
   (set_attr "length" "4")
19730 
   (set_attr "slot" "core")
19731 
   (set_attr "slots" "core")
19732 
   (set_attr "stall" "none")])
19733 
 
19734 
 
19735 
(define_insn "cgen_intrinsic_jmp"
19736 
  [(set (pc)
19737 
        (unspec:SI [
19738 
          (match_operand:SI 0 "general_operand" "r")
19739 
          (reg:SI 32)
19740 
          (reg:SI 42)
19741 
        ] 3848))]
19742 
  "CGEN_ENABLE_INSN_P (785)"
19743 
  "jmp\\t%0"
19744 
  [(set_attr "may_trap" "no")
19745 
   (set_attr "latency" "0")
19746 
   (set_attr "length" "2")
19747 
   (set_attr "slot" "core")
19748 
   (set_attr "slots" "core")
19749 
   (set_attr "stall" "none")])
19750 
 
19751 
 
19752 
(define_insn "cgen_intrinsic_bsr12"
19753 
  [(set (pc)
19754 
        (if_then_else (eq (unspec [
19755 
                            (match_operand:SI 0 "immediate_operand" "")
19756 
                            (reg:SI 32)
19757 
                            (reg:SI 42)
19758 
                          ] 3854)
19759 
                          (const_int 0))
19760 
                      (match_dup 0)
19761 
                      (pc)))
19762 
   (set (reg:SI 17)
19763 
        (unspec:SI [
19764 
          (match_dup 0)
19765 
          (reg:SI 32)
19766 
          (reg:SI 42)
19767 
        ] 3856))
19768 
   (set (reg:SI 114)
19769 
        (unspec:SI [
19770 
          (match_dup 0)
19771 
          (reg:SI 32)
19772 
          (reg:SI 42)
19773 
        ] 3857))]
19774 
  "CGEN_ENABLE_INSN_P (786)"
19775 
  "bsr\\t%l0"
19776 
  [(set_attr "may_trap" "no")
19777 
   (set_attr "latency" "0")
19778 
   (set_attr "length" "2")
19779 
   (set_attr "slot" "core")
19780 
   (set_attr "slots" "core")
19781 
   (set_attr "stall" "none")])
19782 
 
19783 
 
19784 
(define_insn "cgen_intrinsic_bsr24"
19785 
  [(set (pc)
19786 
        (if_then_else (eq (unspec [
19787 
                            (match_operand:SI 0 "immediate_operand" "")
19788 
                            (reg:SI 32)
19789 
                            (reg:SI 42)
19790 
                          ] 3850)
19791 
                          (const_int 0))
19792 
                      (match_dup 0)
19793 
                      (pc)))
19794 
   (set (reg:SI 17)
19795 
        (unspec:SI [
19796 
          (match_dup 0)
19797 
          (reg:SI 32)
19798 
          (reg:SI 42)
19799 
        ] 3852))
19800 
   (set (reg:SI 114)
19801 
        (unspec:SI [
19802 
          (match_dup 0)
19803 
          (reg:SI 32)
19804 
          (reg:SI 42)
19805 
        ] 3853))]
19806 
  "CGEN_ENABLE_INSN_P (787)"
19807 
  "bsr\\t%l0"
19808 
  [(set_attr "may_trap" "no")
19809 
   (set_attr "latency" "0")
19810 
   (set_attr "length" "4")
19811 
   (set_attr "slot" "core")
19812 
   (set_attr "slots" "core")
19813 
   (set_attr "stall" "none")])
19814 
 
19815 
 
19816 
(define_insn "cgen_intrinsic_bne"
19817 
  [(set (pc)
19818 
        (if_then_else (eq (unspec [
19819 
                            (match_operand:SI 0 "general_operand" "r")
19820 
                            (match_operand:SI 1 "general_operand" "r")
19821 
                            (match_operand:SI 2 "immediate_operand" "")
19822 
                            (reg:SI 32)
19823 
                            (reg:SI 42)
19824 
                          ] 3858)
19825 
                          (const_int 0))
19826 
                      (match_dup 2)
19827 
                      (pc)))]
19828 
  "CGEN_ENABLE_INSN_P (788)"
19829 
  "bne\\t%0,%1,%l2"
19830 
  [(set_attr "may_trap" "no")
19831 
   (set_attr "latency" "0")
19832 
   (set_attr "length" "4")
19833 
   (set_attr "slot" "core")
19834 
   (set_attr "slots" "core")
19835 
   (set_attr "stall" "none")])
19836 
 
19837 
 
19838 
(define_insn "cgen_intrinsic_beq"
19839 
  [(set (pc)
19840 
        (if_then_else (eq (unspec [
19841 
                            (match_operand:SI 0 "general_operand" "r")
19842 
                            (match_operand:SI 1 "general_operand" "r")
19843 
                            (match_operand:SI 2 "immediate_operand" "")
19844 
                            (reg:SI 32)
19845 
                            (reg:SI 42)
19846 
                          ] 3860)
19847 
                          (const_int 0))
19848 
                      (match_dup 2)
19849 
                      (pc)))]
19850 
  "CGEN_ENABLE_INSN_P (789)"
19851 
  "beq\\t%0,%1,%l2"
19852 
  [(set_attr "may_trap" "no")
19853 
   (set_attr "latency" "0")
19854 
   (set_attr "length" "4")
19855 
   (set_attr "slot" "core")
19856 
   (set_attr "slots" "core")
19857 
   (set_attr "stall" "none")])
19858 
 
19859 
 
19860 
(define_insn "cgen_intrinsic_bgei"
19861 
  [(set (pc)
19862 
        (if_then_else (eq (unspec [
19863 
                            (match_operand:SI 0 "general_operand" "r")
19864 
                            (match_operand:SI 1 "cgen_h_uint_4a1_immediate" "")
19865 
                            (match_operand:SI 2 "immediate_operand" "")
19866 
                            (reg:SI 32)
19867 
                            (reg:SI 42)
19868 
                          ] 3862)
19869 
                          (const_int 0))
19870 
                      (match_dup 2)
19871 
                      (pc)))]
19872 
  "CGEN_ENABLE_INSN_P (790)"
19873 
  "bgei\\t%0,%1,%l2"
19874 
  [(set_attr "may_trap" "no")
19875 
   (set_attr "latency" "0")
19876 
   (set_attr "length" "4")
19877 
   (set_attr "slot" "core")
19878 
   (set_attr "slots" "core")
19879 
   (set_attr "stall" "none")])
19880 
 
19881 
 
19882 
(define_insn "cgen_intrinsic_blti"
19883 
  [(set (pc)
19884 
        (if_then_else (eq (unspec [
19885 
                            (match_operand:SI 0 "general_operand" "r")
19886 
                            (match_operand:SI 1 "cgen_h_uint_4a1_immediate" "")
19887 
                            (match_operand:SI 2 "immediate_operand" "")
19888 
                            (reg:SI 32)
19889 
                            (reg:SI 42)
19890 
                          ] 3864)
19891 
                          (const_int 0))
19892 
                      (match_dup 2)
19893 
                      (pc)))]
19894 
  "CGEN_ENABLE_INSN_P (791)"
19895 
  "blti\\t%0,%1,%l2"
19896 
  [(set_attr "may_trap" "no")
19897 
   (set_attr "latency" "0")
19898 
   (set_attr "length" "4")
19899 
   (set_attr "slot" "core")
19900 
   (set_attr "slots" "core")
19901 
   (set_attr "stall" "none")])
19902 
 
19903 
 
19904 
(define_insn "cgen_intrinsic_bnei"
19905 
  [(set (pc)
19906 
        (if_then_else (eq (unspec [
19907 
                            (match_operand:SI 0 "general_operand" "r")
19908 
                            (match_operand:SI 1 "cgen_h_uint_4a1_immediate" "")
19909 
                            (match_operand:SI 2 "immediate_operand" "")
19910 
                            (reg:SI 32)
19911 
                            (reg:SI 42)
19912 
                          ] 3866)
19913 
                          (const_int 0))
19914 
                      (match_dup 2)
19915 
                      (pc)))]
19916 
  "CGEN_ENABLE_INSN_P (792)"
19917 
  "bnei\\t%0,%1,%l2"
19918 
  [(set_attr "may_trap" "no")
19919 
   (set_attr "latency" "0")
19920 
   (set_attr "length" "4")
19921 
   (set_attr "slot" "core")
19922 
   (set_attr "slots" "core")
19923 
   (set_attr "stall" "none")])
19924 
 
19925 
 
19926 
(define_insn "cgen_intrinsic_beqi"
19927 
  [(set (pc)
19928 
        (if_then_else (eq (unspec [
19929 
                            (match_operand:SI 0 "general_operand" "r")
19930 
                            (match_operand:SI 1 "cgen_h_uint_4a1_immediate" "")
19931 
                            (match_operand:SI 2 "immediate_operand" "")
19932 
                            (reg:SI 32)
19933 
                            (reg:SI 42)
19934 
                          ] 3868)
19935 
                          (const_int 0))
19936 
                      (match_dup 2)
19937 
                      (pc)))]
19938 
  "CGEN_ENABLE_INSN_P (793)"
19939 
  "beqi\\t%0,%1,%l2"
19940 
  [(set_attr "may_trap" "no")
19941 
   (set_attr "latency" "0")
19942 
   (set_attr "length" "4")
19943 
   (set_attr "slot" "core")
19944 
   (set_attr "slots" "core")
19945 
   (set_attr "stall" "none")])
19946 
 
19947 
 
19948 
(define_insn "cgen_intrinsic_bnez"
19949 
  [(set (pc)
19950 
        (if_then_else (eq (unspec [
19951 
                            (match_operand:SI 0 "general_operand" "r")
19952 
                            (match_operand:SI 1 "immediate_operand" "")
19953 
                            (reg:SI 32)
19954 
                            (reg:SI 42)
19955 
                          ] 3870)
19956 
                          (const_int 0))
19957 
                      (match_dup 1)
19958 
                      (pc)))]
19959 
  "CGEN_ENABLE_INSN_P (794)"
19960 
  "bnez\\t%0,%l1"
19961 
  [(set_attr "may_trap" "no")
19962 
   (set_attr "latency" "0")
19963 
   (set_attr "length" "2")
19964 
   (set_attr "slot" "core")
19965 
   (set_attr "slots" "core")
19966 
   (set_attr "stall" "none")])
19967 
 
19968 
 
19969 
(define_insn "cgen_intrinsic_beqz"
19970 
  [(set (pc)
19971 
        (if_then_else (eq (unspec [
19972 
                            (match_operand:SI 0 "general_operand" "r")
19973 
                            (match_operand:SI 1 "immediate_operand" "")
19974 
                            (reg:SI 32)
19975 
                            (reg:SI 42)
19976 
                          ] 3872)
19977 
                          (const_int 0))
19978 
                      (match_dup 1)
19979 
                      (pc)))]
19980 
  "CGEN_ENABLE_INSN_P (795)"
19981 
  "beqz\\t%0,%l1"
19982 
  [(set_attr "may_trap" "no")
19983 
   (set_attr "latency" "0")
19984 
   (set_attr "length" "2")
19985 
   (set_attr "slot" "core")
19986 
   (set_attr "slots" "core")
19987 
   (set_attr "stall" "none")])
19988 
 
19989 
 
19990 
(define_insn "cgen_intrinsic_bra"
19991 
  [(set (pc)
19992 
        (if_then_else (eq (unspec [
19993 
                            (match_operand:SI 0 "immediate_operand" "")
19994 
                            (reg:SI 32)
19995 
                            (reg:SI 42)
19996 
                          ] 3874)
19997 
                          (const_int 0))
19998 
                      (match_dup 0)
19999 
                      (pc)))]
20000 
  "CGEN_ENABLE_INSN_P (796)"
20001 
  "bra\\t%l0"
20002 
  [(set_attr "may_trap" "no")
20003 
   (set_attr "latency" "0")
20004 
   (set_attr "length" "2")
20005 
   (set_attr "slot" "core")
20006 
   (set_attr "slots" "core")
20007 
   (set_attr "stall" "none")])
20008 
 
20009 
 
20010 
(define_insn "cgen_intrinsic_fsft"
20011 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20012 
        (unspec_volatile:SI [
20013 
          (match_operand:SI 1 "general_operand" "0")
20014 
          (match_operand:SI 2 "general_operand" "r")
20015 
          (reg:SI 18)
20016 
        ] 3876))]
20017 
  "CGEN_ENABLE_INSN_P (797)"
20018 
  "fsft\\t%1,%2"
20019 
  [(set_attr "may_trap" "no")
20020 
   (set_attr "latency" "0")
20021 
   (set_attr "length" "2")
20022 
   (set_attr "slot" "core")
20023 
   (set_attr "slots" "core")
20024 
   (set_attr "stall" "fsft")])
20025 
 
20026 
 
20027 
(define_insn "cgen_intrinsic_sll3"
20028 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=z")
20029 
        (unspec:SI [
20030 
          (match_operand:SI 1 "general_operand" "r")
20031 
          (match_operand:SI 2 "cgen_h_uint_5a1_immediate" "")
20032 
        ] 3878))]
20033 
  "CGEN_ENABLE_INSN_P (798)"
20034 
  "sll3\\t$0,%1,%2"
20035 
  [(set_attr "may_trap" "no")
20036 
   (set_attr "latency" "0")
20037 
   (set_attr "length" "2")
20038 
   (set_attr "slot" "core")
20039 
   (set_attr "slots" "core")
20040 
   (set_attr "stall" "int2")])
20041 
 
20042 
 
20043 
(define_insn "cgen_intrinsic_slli"
20044 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20045 
        (unspec:SI [
20046 
          (match_operand:SI 1 "general_operand" "0")
20047 
          (match_operand:SI 2 "cgen_h_uint_5a1_immediate" "")
20048 
        ] 3880))]
20049 
  "CGEN_ENABLE_INSN_P (799)"
20050 
  "sll\\t%1,%2"
20051 
  [(set_attr "may_trap" "no")
20052 
   (set_attr "latency" "0")
20053 
   (set_attr "length" "2")
20054 
   (set_attr "slot" "core")
20055 
   (set_attr "slots" "core")
20056 
   (set_attr "shiftop" "operand2")])
20057 
 
20058 
 
20059 
(define_insn "cgen_intrinsic_srli"
20060 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20061 
        (unspec:SI [
20062 
          (match_operand:SI 1 "general_operand" "0")
20063 
          (match_operand:SI 2 "cgen_h_uint_5a1_immediate" "")
20064 
        ] 3882))]
20065 
  "CGEN_ENABLE_INSN_P (800)"
20066 
  "srl\\t%1,%2"
20067 
  [(set_attr "may_trap" "no")
20068 
   (set_attr "latency" "0")
20069 
   (set_attr "length" "2")
20070 
   (set_attr "slot" "core")
20071 
   (set_attr "slots" "core")
20072 
   (set_attr "shiftop" "operand2")])
20073 
 
20074 
 
20075 
(define_insn "cgen_intrinsic_srai"
20076 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20077 
        (unspec:SI [
20078 
          (match_operand:SI 1 "general_operand" "0")
20079 
          (match_operand:SI 2 "cgen_h_uint_5a1_immediate" "")
20080 
        ] 3884))]
20081 
  "CGEN_ENABLE_INSN_P (801)"
20082 
  "sra\\t%1,%2"
20083 
  [(set_attr "may_trap" "no")
20084 
   (set_attr "latency" "0")
20085 
   (set_attr "length" "2")
20086 
   (set_attr "slot" "core")
20087 
   (set_attr "slots" "core")
20088 
   (set_attr "shiftop" "operand2")])
20089 
 
20090 
 
20091 
(define_insn "cgen_intrinsic_sll"
20092 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20093 
        (unspec:SI [
20094 
          (match_operand:SI 1 "general_operand" "0")
20095 
          (match_operand:SI 2 "general_operand" "r")
20096 
        ] 3886))]
20097 
  "CGEN_ENABLE_INSN_P (802)"
20098 
  "sll\\t%1,%2"
20099 
  [(set_attr "may_trap" "no")
20100 
   (set_attr "latency" "0")
20101 
   (set_attr "length" "2")
20102 
   (set_attr "slot" "core")
20103 
   (set_attr "slots" "core")
20104 
   (set_attr "stall" "int2")])
20105 
 
20106 
 
20107 
(define_insn "cgen_intrinsic_srl"
20108 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20109 
        (unspec:SI [
20110 
          (match_operand:SI 1 "general_operand" "0")
20111 
          (match_operand:SI 2 "general_operand" "r")
20112 
        ] 3888))]
20113 
  "CGEN_ENABLE_INSN_P (803)"
20114 
  "srl\\t%1,%2"
20115 
  [(set_attr "may_trap" "no")
20116 
   (set_attr "latency" "0")
20117 
   (set_attr "length" "2")
20118 
   (set_attr "slot" "core")
20119 
   (set_attr "slots" "core")
20120 
   (set_attr "stall" "int2")])
20121 
 
20122 
 
20123 
(define_insn "cgen_intrinsic_sra"
20124 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20125 
        (unspec:SI [
20126 
          (match_operand:SI 1 "general_operand" "0")
20127 
          (match_operand:SI 2 "general_operand" "r")
20128 
        ] 3890))]
20129 
  "CGEN_ENABLE_INSN_P (804)"
20130 
  "sra\\t%1,%2"
20131 
  [(set_attr "may_trap" "no")
20132 
   (set_attr "latency" "0")
20133 
   (set_attr "length" "2")
20134 
   (set_attr "slot" "core")
20135 
   (set_attr "slots" "core")
20136 
   (set_attr "stall" "int2")])
20137 
 
20138 
 
20139 
(define_insn "cgen_intrinsic_xor3"
20140 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20141 
        (unspec:SI [
20142 
          (match_operand:SI 1 "general_operand" "r")
20143 
          (match_operand:SI 2 "cgen_h_uint_16a1_immediate" "")
20144 
        ] 3892))]
20145 
  "CGEN_ENABLE_INSN_P (805)"
20146 
  "xor3\\t%0,%1,%2"
20147 
  [(set_attr "may_trap" "no")
20148 
   (set_attr "latency" "0")
20149 
   (set_attr "length" "4")
20150 
   (set_attr "slot" "core")
20151 
   (set_attr "slots" "core")
20152 
   (set_attr "stall" "none")])
20153 
 
20154 
 
20155 
(define_insn "cgen_intrinsic_and3"
20156 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20157 
        (unspec:SI [
20158 
          (match_operand:SI 1 "general_operand" "r")
20159 
          (match_operand:SI 2 "cgen_h_uint_16a1_immediate" "")
20160 
        ] 3894))]
20161 
  "CGEN_ENABLE_INSN_P (806)"
20162 
  "and3\\t%0,%1,%2"
20163 
  [(set_attr "may_trap" "no")
20164 
   (set_attr "latency" "0")
20165 
   (set_attr "length" "4")
20166 
   (set_attr "slot" "core")
20167 
   (set_attr "slots" "core")
20168 
   (set_attr "stall" "none")])
20169 
 
20170 
 
20171 
(define_insn "cgen_intrinsic_or3"
20172 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20173 
        (unspec:SI [
20174 
          (match_operand:SI 1 "general_operand" "r")
20175 
          (match_operand:SI 2 "cgen_h_uint_16a1_immediate" "")
20176 
        ] 3896))]
20177 
  "CGEN_ENABLE_INSN_P (807)"
20178 
  "or3\\t%0,%1,%2"
20179 
  [(set_attr "may_trap" "no")
20180 
   (set_attr "latency" "0")
20181 
   (set_attr "length" "4")
20182 
   (set_attr "slot" "core")
20183 
   (set_attr "slots" "core")
20184 
   (set_attr "stall" "none")])
20185 
 
20186 
 
20187 
(define_insn "cgen_intrinsic_nor"
20188 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20189 
        (unspec:SI [
20190 
          (match_operand:SI 1 "general_operand" "0")
20191 
          (match_operand:SI 2 "general_operand" "r")
20192 
        ] 3898))]
20193 
  "CGEN_ENABLE_INSN_P (808)"
20194 
  "nor\\t%1,%2"
20195 
  [(set_attr "may_trap" "no")
20196 
   (set_attr "latency" "0")
20197 
   (set_attr "length" "2")
20198 
   (set_attr "slot" "core")
20199 
   (set_attr "slots" "core")
20200 
   (set_attr "stall" "none")])
20201 
 
20202 
 
20203 
(define_insn "cgen_intrinsic_xor"
20204 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20205 
        (unspec:SI [
20206 
          (match_operand:SI 1 "general_operand" "0")
20207 
          (match_operand:SI 2 "general_operand" "r")
20208 
        ] 3900))]
20209 
  "CGEN_ENABLE_INSN_P (809)"
20210 
  "xor\\t%1,%2"
20211 
  [(set_attr "may_trap" "no")
20212 
   (set_attr "latency" "0")
20213 
   (set_attr "length" "2")
20214 
   (set_attr "slot" "core")
20215 
   (set_attr "slots" "core")
20216 
   (set_attr "stall" "none")])
20217 
 
20218 
 
20219 
(define_insn "cgen_intrinsic_and"
20220 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20221 
        (unspec:SI [
20222 
          (match_operand:SI 1 "general_operand" "0")
20223 
          (match_operand:SI 2 "general_operand" "r")
20224 
        ] 3902))]
20225 
  "CGEN_ENABLE_INSN_P (810)"
20226 
  "and\\t%1,%2"
20227 
  [(set_attr "may_trap" "no")
20228 
   (set_attr "latency" "0")
20229 
   (set_attr "length" "2")
20230 
   (set_attr "slot" "core")
20231 
   (set_attr "slots" "core")
20232 
   (set_attr "stall" "none")])
20233 
 
20234 
 
20235 
(define_insn "cgen_intrinsic_or"
20236 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20237 
        (unspec:SI [
20238 
          (match_operand:SI 1 "general_operand" "0")
20239 
          (match_operand:SI 2 "general_operand" "r")
20240 
        ] 3904))]
20241 
  "CGEN_ENABLE_INSN_P (811)"
20242 
  "or\\t%1,%2"
20243 
  [(set_attr "may_trap" "no")
20244 
   (set_attr "latency" "0")
20245 
   (set_attr "length" "2")
20246 
   (set_attr "slot" "core")
20247 
   (set_attr "slots" "core")
20248 
   (set_attr "stall" "none")])
20249 
 
20250 
 
20251 
(define_insn "cgen_intrinsic_sltu3x"
20252 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20253 
        (unspec:SI [
20254 
          (match_operand:SI 1 "general_operand" "r")
20255 
          (match_operand:SI 2 "cgen_h_uint_16a1_immediate" "")
20256 
        ] 3906))]
20257 
  "CGEN_ENABLE_INSN_P (812)"
20258 
  "sltu3\\t%0,%1,%2"
20259 
  [(set_attr "may_trap" "no")
20260 
   (set_attr "latency" "0")
20261 
   (set_attr "length" "4")
20262 
   (set_attr "slot" "core")
20263 
   (set_attr "slots" "core")
20264 
   (set_attr "stall" "none")])
20265 
 
20266 
 
20267 
(define_insn "cgen_intrinsic_slt3x"
20268 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20269 
        (unspec:SI [
20270 
          (match_operand:SI 1 "general_operand" "r")
20271 
          (match_operand:SI 2 "cgen_h_sint_16a1_immediate" "")
20272 
        ] 3908))]
20273 
  "CGEN_ENABLE_INSN_P (813)"
20274 
  "slt3\\t%0,%1,%2"
20275 
  [(set_attr "may_trap" "no")
20276 
   (set_attr "latency" "0")
20277 
   (set_attr "length" "4")
20278 
   (set_attr "slot" "core")
20279 
   (set_attr "slots" "core")
20280 
   (set_attr "stall" "none")])
20281 
 
20282 
 
20283 
(define_insn "cgen_intrinsic_add3x"
20284 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20285 
        (unspec:SI [
20286 
          (match_operand:SI 1 "general_operand" "r")
20287 
          (match_operand:SI 2 "cgen_h_sint_16a1_immediate" "")
20288 
        ] 3910))]
20289 
  "CGEN_ENABLE_INSN_P (814)"
20290 
  "add3\\t%0,%1,%2"
20291 
  [(set_attr "may_trap" "no")
20292 
   (set_attr "latency" "0")
20293 
   (set_attr "length" "4")
20294 
   (set_attr "slot" "core")
20295 
   (set_attr "slots" "core")
20296 
   (set_attr "stall" "none")])
20297 
 
20298 
 
20299 
(define_insn "cgen_intrinsic_sl2ad3"
20300 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=z")
20301 
        (unspec:SI [
20302 
          (match_operand:SI 1 "general_operand" "r")
20303 
          (match_operand:SI 2 "general_operand" "r")
20304 
        ] 3912))]
20305 
  "CGEN_ENABLE_INSN_P (815)"
20306 
  "sl2ad3\\t$0,%1,%2"
20307 
  [(set_attr "may_trap" "no")
20308 
   (set_attr "latency" "0")
20309 
   (set_attr "length" "2")
20310 
   (set_attr "slot" "core")
20311 
   (set_attr "slots" "core")
20312 
   (set_attr "stall" "int2")])
20313 
 
20314 
 
20315 
(define_insn "cgen_intrinsic_sl1ad3"
20316 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=z")
20317 
        (unspec:SI [
20318 
          (match_operand:SI 1 "general_operand" "r")
20319 
          (match_operand:SI 2 "general_operand" "r")
20320 
        ] 3914))]
20321 
  "CGEN_ENABLE_INSN_P (816)"
20322 
  "sl1ad3\\t$0,%1,%2"
20323 
  [(set_attr "may_trap" "no")
20324 
   (set_attr "latency" "0")
20325 
   (set_attr "length" "2")
20326 
   (set_attr "slot" "core")
20327 
   (set_attr "slots" "core")
20328 
   (set_attr "stall" "int2")])
20329 
 
20330 
 
20331 
(define_insn "cgen_intrinsic_sltu3i"
20332 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=z")
20333 
        (unspec:SI [
20334 
          (match_operand:SI 1 "general_operand" "r")
20335 
          (match_operand:SI 2 "cgen_h_uint_5a1_immediate" "")
20336 
        ] 3916))]
20337 
  "CGEN_ENABLE_INSN_P (817)"
20338 
  "sltu3\\t$0,%1,%2"
20339 
  [(set_attr "may_trap" "no")
20340 
   (set_attr "latency" "0")
20341 
   (set_attr "length" "2")
20342 
   (set_attr "slot" "core")
20343 
   (set_attr "slots" "core")
20344 
   (set_attr "stall" "none")])
20345 
 
20346 
 
20347 
(define_insn "cgen_intrinsic_slt3i"
20348 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=z")
20349 
        (unspec:SI [
20350 
          (match_operand:SI 1 "general_operand" "r")
20351 
          (match_operand:SI 2 "cgen_h_uint_5a1_immediate" "")
20352 
        ] 3918))]
20353 
  "CGEN_ENABLE_INSN_P (818)"
20354 
  "slt3\\t$0,%1,%2"
20355 
  [(set_attr "may_trap" "no")
20356 
   (set_attr "latency" "0")
20357 
   (set_attr "length" "2")
20358 
   (set_attr "slot" "core")
20359 
   (set_attr "slots" "core")
20360 
   (set_attr "stall" "none")])
20361 
 
20362 
 
20363 
(define_insn "cgen_intrinsic_sltu3"
20364 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=z")
20365 
        (unspec:SI [
20366 
          (match_operand:SI 1 "general_operand" "r")
20367 
          (match_operand:SI 2 "general_operand" "r")
20368 
        ] 3920))]
20369 
  "CGEN_ENABLE_INSN_P (819)"
20370 
  "sltu3\\t$0,%1,%2"
20371 
  [(set_attr "may_trap" "no")
20372 
   (set_attr "latency" "0")
20373 
   (set_attr "length" "2")
20374 
   (set_attr "slot" "core")
20375 
   (set_attr "slots" "core")
20376 
   (set_attr "stall" "none")])
20377 
 
20378 
 
20379 
(define_insn "cgen_intrinsic_slt3"
20380 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=z")
20381 
        (unspec:SI [
20382 
          (match_operand:SI 1 "general_operand" "r")
20383 
          (match_operand:SI 2 "general_operand" "r")
20384 
        ] 3922))]
20385 
  "CGEN_ENABLE_INSN_P (820)"
20386 
  "slt3\\t$0,%1,%2"
20387 
  [(set_attr "may_trap" "no")
20388 
   (set_attr "latency" "0")
20389 
   (set_attr "length" "2")
20390 
   (set_attr "slot" "core")
20391 
   (set_attr "slots" "core")
20392 
   (set_attr "stall" "none")])
20393 
 
20394 
 
20395 
(define_insn "cgen_intrinsic_neg"
20396 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20397 
        (unspec:SI [
20398 
          (match_operand:SI 1 "general_operand" "r")
20399 
        ] 3924))]
20400 
  "CGEN_ENABLE_INSN_P (821)"
20401 
  "neg\\t%0,%1"
20402 
  [(set_attr "may_trap" "no")
20403 
   (set_attr "latency" "0")
20404 
   (set_attr "length" "2")
20405 
   (set_attr "slot" "core")
20406 
   (set_attr "slots" "core")
20407 
   (set_attr "stall" "none")])
20408 
 
20409 
 
20410 
(define_insn "cgen_intrinsic_sbvck3"
20411 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=z")
20412 
        (unspec:SI [
20413 
          (match_operand:SI 1 "general_operand" "r")
20414 
          (match_operand:SI 2 "general_operand" "r")
20415 
        ] 3926))]
20416 
  "CGEN_ENABLE_INSN_P (822)"
20417 
  "sbvck3\\t$0,%1,%2"
20418 
  [(set_attr "may_trap" "no")
20419 
   (set_attr "latency" "0")
20420 
   (set_attr "length" "2")
20421 
   (set_attr "slot" "core")
20422 
   (set_attr "slots" "core")
20423 
   (set_attr "stall" "advck")])
20424 
 
20425 
 
20426 
(define_insn "cgen_intrinsic_sub"
20427 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20428 
        (unspec:SI [
20429 
          (match_operand:SI 1 "general_operand" "0")
20430 
          (match_operand:SI 2 "general_operand" "r")
20431 
        ] 3928))]
20432 
  "CGEN_ENABLE_INSN_P (823)"
20433 
  "sub\\t%1,%2"
20434 
  [(set_attr "may_trap" "no")
20435 
   (set_attr "latency" "0")
20436 
   (set_attr "length" "2")
20437 
   (set_attr "slot" "core")
20438 
   (set_attr "slots" "core")
20439 
   (set_attr "stall" "none")])
20440 
 
20441 
 
20442 
(define_insn "cgen_intrinsic_advck3"
20443 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=z")
20444 
        (unspec:SI [
20445 
          (match_operand:SI 1 "general_operand" "r")
20446 
          (match_operand:SI 2 "general_operand" "r")
20447 
        ] 3930))]
20448 
  "CGEN_ENABLE_INSN_P (824)"
20449 
  "advck3\\t$0,%1,%2"
20450 
  [(set_attr "may_trap" "no")
20451 
   (set_attr "latency" "0")
20452 
   (set_attr "length" "2")
20453 
   (set_attr "slot" "core")
20454 
   (set_attr "slots" "core")
20455 
   (set_attr "stall" "advck")])
20456 
 
20457 
 
20458 
(define_insn "cgen_intrinsic_add3i"
20459 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20460 
        (unspec:SI [
20461 
          (match_operand:SI 1 "cgen_h_uint_5a4_immediate" "")
20462 
          (reg:SI 15)
20463 
        ] 3932))]
20464 
  "CGEN_ENABLE_INSN_P (825)"
20465 
  "add3\\t%0,$sp,%1"
20466 
  [(set_attr "may_trap" "no")
20467 
   (set_attr "latency" "0")
20468 
   (set_attr "length" "2")
20469 
   (set_attr "slot" "core")
20470 
   (set_attr "slots" "core")
20471 
   (set_attr "stall" "none")])
20472 
 
20473 
 
20474 
(define_insn "cgen_intrinsic_add"
20475 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20476 
        (unspec:SI [
20477 
          (match_operand:SI 1 "general_operand" "0")
20478 
          (match_operand:SI 2 "cgen_h_sint_6a1_immediate" "")
20479 
        ] 3934))]
20480 
  "CGEN_ENABLE_INSN_P (826)"
20481 
  "add\\t%1,%2"
20482 
  [(set_attr "may_trap" "no")
20483 
   (set_attr "latency" "0")
20484 
   (set_attr "length" "2")
20485 
   (set_attr "slot" "core")
20486 
   (set_attr "slots" "core")
20487 
   (set_attr "stall" "none")])
20488 
 
20489 
 
20490 
(define_insn "cgen_intrinsic_add3"
20491 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20492 
        (unspec:SI [
20493 
          (match_operand:SI 1 "general_operand" "r")
20494 
          (match_operand:SI 2 "general_operand" "r")
20495 
        ] 3936))]
20496 
  "CGEN_ENABLE_INSN_P (827)"
20497 
  "add3\\t%0,%1,%2"
20498 
  [(set_attr "may_trap" "no")
20499 
   (set_attr "latency" "0")
20500 
   (set_attr "length" "2")
20501 
   (set_attr "slot" "core")
20502 
   (set_attr "slots" "core")
20503 
   (set_attr "stall" "none")])
20504 
 
20505 
 
20506 
(define_insn "cgen_intrinsic_movh"
20507 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20508 
        (unspec:SI [
20509 
          (match_operand:SI 1 "cgen_h_uint_16a1_immediate" "")
20510 
        ] 3938))]
20511 
  "CGEN_ENABLE_INSN_P (828)"
20512 
  "movh\\t%0,%1"
20513 
  [(set_attr "may_trap" "no")
20514 
   (set_attr "latency" "0")
20515 
   (set_attr "length" "4")
20516 
   (set_attr "slot" "core")
20517 
   (set_attr "slots" "core")
20518 
   (set_attr "stall" "none")])
20519 
 
20520 
 
20521 
(define_insn "cgen_intrinsic_movu16"
20522 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20523 
        (unspec:SI [
20524 
          (match_operand:SI 1 "cgen_h_uint_16a1_immediate" "")
20525 
        ] 3940))]
20526 
  "CGEN_ENABLE_INSN_P (829)"
20527 
  "movu\\t%0,%1"
20528 
  [(set_attr "may_trap" "no")
20529 
   (set_attr "latency" "0")
20530 
   (set_attr "length" "4")
20531 
   (set_attr "slot" "core")
20532 
   (set_attr "slots" "core")
20533 
   (set_attr "stall" "none")])
20534 
 
20535 
 
20536 
(define_insn "cgen_intrinsic_movu24"
20537 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=t")
20538 
        (unspec:SI [
20539 
          (match_operand:SI 1 "cgen_h_uint_24a1_immediate" "")
20540 
        ] 3942))]
20541 
  "CGEN_ENABLE_INSN_P (830)"
20542 
  "movu\\t%0,%1"
20543 
  [(set_attr "may_trap" "no")
20544 
   (set_attr "latency" "0")
20545 
   (set_attr "length" "4")
20546 
   (set_attr "slot" "core")
20547 
   (set_attr "slots" "core")
20548 
   (set_attr "stall" "none")])
20549 
 
20550 
 
20551 
(define_insn "cgen_intrinsic_movi8"
20552 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20553 
        (unspec:SI [
20554 
          (match_operand:SI 1 "cgen_h_sint_8a1_immediate" "")
20555 
        ] 3946))]
20556 
  "CGEN_ENABLE_INSN_P (831)"
20557 
  "mov\\t%0,%1"
20558 
  [(set_attr "may_trap" "no")
20559 
   (set_attr "latency" "0")
20560 
   (set_attr "length" "2")
20561 
   (set_attr "slot" "core")
20562 
   (set_attr "slots" "core")
20563 
   (set_attr "stall" "none")])
20564 
 
20565 
 
20566 
(define_insn "cgen_intrinsic_movi16"
20567 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20568 
        (unspec:SI [
20569 
          (match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
20570 
        ] 3944))]
20571 
  "CGEN_ENABLE_INSN_P (832)"
20572 
  "mov\\t%0,%1"
20573 
  [(set_attr "may_trap" "no")
20574 
   (set_attr "latency" "0")
20575 
   (set_attr "length" "4")
20576 
   (set_attr "slot" "core")
20577 
   (set_attr "slots" "core")
20578 
   (set_attr "stall" "none")])
20579 
 
20580 
 
20581 
(define_insn "cgen_intrinsic_mov"
20582 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20583 
        (unspec:SI [
20584 
          (match_operand:SI 1 "general_operand" "r")
20585 
        ] 3948))]
20586 
  "CGEN_ENABLE_INSN_P (833)"
20587 
  "mov\\t%0,%1"
20588 
  [(set_attr "may_trap" "no")
20589 
   (set_attr "latency" "0")
20590 
   (set_attr "length" "2")
20591 
   (set_attr "slot" "core")
20592 
   (set_attr "slots" "core")
20593 
   (set_attr "stall" "none")])
20594 
 
20595 
 
20596 
(define_insn "cgen_intrinsic_ssarb"
20597 
  [(set (reg:SI 18)
20598 
        (unspec_volatile:SI [
20599 
          (match_operand:SI 0 "cgen_h_sint_2a1_immediate" "")
20600 
          (match_operand:SI 1 "general_operand" "r")
20601 
        ] 3950))]
20602 
  "CGEN_ENABLE_INSN_P (834)"
20603 
  "ssarb\\t%0(%1)"
20604 
  [(set_attr "may_trap" "no")
20605 
   (set_attr "latency" "0")
20606 
   (set_attr "length" "2")
20607 
   (set_attr "slot" "core")
20608 
   (set_attr "slots" "core")
20609 
   (set_attr "stall" "ssarb")])
20610 
 
20611 
 
20612 
(define_insn "cgen_intrinsic_extuh"
20613 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20614 
        (unspec:SI [
20615 
          (match_operand:SI 1 "general_operand" "0")
20616 
        ] 3952))]
20617 
  "CGEN_ENABLE_INSN_P (835)"
20618 
  "extuh\\t%1"
20619 
  [(set_attr "may_trap" "no")
20620 
   (set_attr "latency" "0")
20621 
   (set_attr "length" "2")
20622 
   (set_attr "slot" "core")
20623 
   (set_attr "slots" "core")
20624 
   (set_attr "stall" "none")])
20625 
 
20626 
 
20627 
(define_insn "cgen_intrinsic_extub"
20628 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20629 
        (unspec:SI [
20630 
          (match_operand:SI 1 "general_operand" "0")
20631 
        ] 3954))]
20632 
  "CGEN_ENABLE_INSN_P (836)"
20633 
  "extub\\t%1"
20634 
  [(set_attr "may_trap" "no")
20635 
   (set_attr "latency" "0")
20636 
   (set_attr "length" "2")
20637 
   (set_attr "slot" "core")
20638 
   (set_attr "slots" "core")
20639 
   (set_attr "stall" "none")])
20640 
 
20641 
 
20642 
(define_insn "cgen_intrinsic_exth"
20643 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20644 
        (unspec:SI [
20645 
          (match_operand:SI 1 "general_operand" "0")
20646 
        ] 3956))]
20647 
  "CGEN_ENABLE_INSN_P (837)"
20648 
  "exth\\t%1"
20649 
  [(set_attr "may_trap" "no")
20650 
   (set_attr "latency" "0")
20651 
   (set_attr "length" "2")
20652 
   (set_attr "slot" "core")
20653 
   (set_attr "slots" "core")
20654 
   (set_attr "stall" "none")])
20655 
 
20656 
 
20657 
(define_insn "cgen_intrinsic_extb"
20658 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20659 
        (unspec:SI [
20660 
          (match_operand:SI 1 "general_operand" "0")
20661 
        ] 3958))]
20662 
  "CGEN_ENABLE_INSN_P (838)"
20663 
  "extb\\t%1"
20664 
  [(set_attr "may_trap" "no")
20665 
   (set_attr "latency" "0")
20666 
   (set_attr "length" "2")
20667 
   (set_attr "slot" "core")
20668 
   (set_attr "slots" "core")
20669 
   (set_attr "stall" "none")])
20670 
 
20671 
 
20672 
(define_insn "cgen_intrinsic_lw24"
20673 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20674 
        (unspec:SI [
20675 
          (match_operand:SI 1 "cgen_h_uint_22a4_immediate" "")
20676 
          (mem:SI (scratch:SI))
20677 
        ] 3960))]
20678 
  "CGEN_ENABLE_INSN_P (839)"
20679 
  "lw\\t%0,(%1)"
20680 
  [(set_attr "may_trap" "no")
20681 
   (set_attr "latency" "2")
20682 
   (set_attr "length" "4")
20683 
   (set_attr "slot" "core")
20684 
   (set_attr "slots" "core")
20685 
   (set_attr "stall" "load")])
20686 
 
20687 
 
20688 
(define_insn "cgen_intrinsic_sw24"
20689 
  [(set (mem:SI (scratch:SI))
20690 
        (unspec:SI [
20691 
          (match_operand:SI 0 "general_operand" "r")
20692 
          (match_operand:SI 1 "cgen_h_uint_22a4_immediate" "")
20693 
        ] 3962))]
20694 
  "CGEN_ENABLE_INSN_P (840)"
20695 
  "sw\\t%0,(%1)"
20696 
  [(set_attr "may_trap" "no")
20697 
   (set_attr "latency" "0")
20698 
   (set_attr "length" "4")
20699 
   (set_attr "slot" "core")
20700 
   (set_attr "slots" "core")
20701 
   (set_attr "stall" "store")])
20702 
 
20703 
 
20704 
(define_insn "cgen_intrinsic_lhu16"
20705 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20706 
        (unspec:SI [
20707 
          (match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
20708 
          (match_operand:SI 2 "general_operand" "r")
20709 
          (mem:SI (scratch:SI))
20710 
        ] 3964))]
20711 
  "CGEN_ENABLE_INSN_P (841)"
20712 
  "lhu\\t%0,%1(%2)"
20713 
  [(set_attr "may_trap" "no")
20714 
   (set_attr "latency" "2")
20715 
   (set_attr "length" "4")
20716 
   (set_attr "slot" "core")
20717 
   (set_attr "slots" "core")
20718 
   (set_attr "stall" "load")])
20719 
 
20720 
 
20721 
(define_insn "cgen_intrinsic_lbu16"
20722 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20723 
        (unspec:SI [
20724 
          (match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
20725 
          (match_operand:SI 2 "general_operand" "r")
20726 
          (mem:SI (scratch:SI))
20727 
        ] 3966))]
20728 
  "CGEN_ENABLE_INSN_P (842)"
20729 
  "lbu\\t%0,%1(%2)"
20730 
  [(set_attr "may_trap" "no")
20731 
   (set_attr "latency" "2")
20732 
   (set_attr "length" "4")
20733 
   (set_attr "slot" "core")
20734 
   (set_attr "slots" "core")
20735 
   (set_attr "stall" "load")])
20736 
 
20737 
 
20738 
(define_insn "cgen_intrinsic_lw16"
20739 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20740 
        (unspec:SI [
20741 
          (match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
20742 
          (match_operand:SI 2 "general_operand" "r")
20743 
          (mem:SI (scratch:SI))
20744 
        ] 3968))]
20745 
  "CGEN_ENABLE_INSN_P (843)"
20746 
  "lw\\t%0,%1(%2)"
20747 
  [(set_attr "may_trap" "no")
20748 
   (set_attr "latency" "2")
20749 
   (set_attr "length" "4")
20750 
   (set_attr "slot" "core")
20751 
   (set_attr "slots" "core")
20752 
   (set_attr "stall" "load")])
20753 
 
20754 
 
20755 
(define_insn "cgen_intrinsic_lh16"
20756 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20757 
        (unspec:SI [
20758 
          (match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
20759 
          (match_operand:SI 2 "general_operand" "r")
20760 
          (mem:SI (scratch:SI))
20761 
        ] 3970))]
20762 
  "CGEN_ENABLE_INSN_P (844)"
20763 
  "lh\\t%0,%1(%2)"
20764 
  [(set_attr "may_trap" "no")
20765 
   (set_attr "latency" "2")
20766 
   (set_attr "length" "4")
20767 
   (set_attr "slot" "core")
20768 
   (set_attr "slots" "core")
20769 
   (set_attr "stall" "load")])
20770 
 
20771 
 
20772 
(define_insn "cgen_intrinsic_lb16"
20773 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20774 
        (unspec:SI [
20775 
          (match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
20776 
          (match_operand:SI 2 "general_operand" "r")
20777 
          (mem:SI (scratch:SI))
20778 
        ] 3972))]
20779 
  "CGEN_ENABLE_INSN_P (845)"
20780 
  "lb\\t%0,%1(%2)"
20781 
  [(set_attr "may_trap" "no")
20782 
   (set_attr "latency" "2")
20783 
   (set_attr "length" "4")
20784 
   (set_attr "slot" "core")
20785 
   (set_attr "slots" "core")
20786 
   (set_attr "stall" "load")])
20787 
 
20788 
 
20789 
(define_insn "cgen_intrinsic_sw16"
20790 
  [(set (mem:SI (scratch:SI))
20791 
        (unspec:SI [
20792 
          (match_operand:SI 0 "general_operand" "r")
20793 
          (match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
20794 
          (match_operand:SI 2 "general_operand" "r")
20795 
        ] 3974))]
20796 
  "CGEN_ENABLE_INSN_P (846)"
20797 
  "sw\\t%0,%1(%2)"
20798 
  [(set_attr "may_trap" "no")
20799 
   (set_attr "latency" "0")
20800 
   (set_attr "length" "4")
20801 
   (set_attr "slot" "core")
20802 
   (set_attr "slots" "core")
20803 
   (set_attr "stall" "store")])
20804 
 
20805 
 
20806 
(define_insn "cgen_intrinsic_sh16"
20807 
  [(set (mem:SI (scratch:SI))
20808 
        (unspec:SI [
20809 
          (match_operand:SI 0 "general_operand" "r")
20810 
          (match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
20811 
          (match_operand:SI 2 "general_operand" "r")
20812 
        ] 3976))]
20813 
  "CGEN_ENABLE_INSN_P (847)"
20814 
  "sh\\t%0,%1(%2)"
20815 
  [(set_attr "may_trap" "no")
20816 
   (set_attr "latency" "0")
20817 
   (set_attr "length" "4")
20818 
   (set_attr "slot" "core")
20819 
   (set_attr "slots" "core")
20820 
   (set_attr "stall" "store")])
20821 
 
20822 
 
20823 
(define_insn "cgen_intrinsic_sb16"
20824 
  [(set (mem:SI (scratch:SI))
20825 
        (unspec:SI [
20826 
          (match_operand:SI 0 "general_operand" "r")
20827 
          (match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
20828 
          (match_operand:SI 2 "general_operand" "r")
20829 
        ] 3978))]
20830 
  "CGEN_ENABLE_INSN_P (848)"
20831 
  "sb\\t%0,%1(%2)"
20832 
  [(set_attr "may_trap" "no")
20833 
   (set_attr "latency" "0")
20834 
   (set_attr "length" "4")
20835 
   (set_attr "slot" "core")
20836 
   (set_attr "slots" "core")
20837 
   (set_attr "stall" "store")])
20838 
 
20839 
 
20840 
(define_insn "cgen_intrinsic_lhu_tp"
20841 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=t")
20842 
        (unspec:SI [
20843 
          (match_operand:SI 1 "cgen_h_uint_6a2_immediate" "")
20844 
          (reg:SI 13)
20845 
          (mem:SI (scratch:SI))
20846 
        ] 3980))]
20847 
  "CGEN_ENABLE_INSN_P (849)"
20848 
  "lhu\\t%0,%1($tp)"
20849 
  [(set_attr "may_trap" "no")
20850 
   (set_attr "latency" "2")
20851 
   (set_attr "length" "2")
20852 
   (set_attr "slot" "core")
20853 
   (set_attr "slots" "core")
20854 
   (set_attr "stall" "load")])
20855 
 
20856 
 
20857 
(define_insn "cgen_intrinsic_lbu_tp"
20858 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=t")
20859 
        (unspec:SI [
20860 
          (match_operand:SI 1 "cgen_h_uint_7a1_immediate" "")
20861 
          (reg:SI 13)
20862 
          (mem:SI (scratch:SI))
20863 
        ] 3982))]
20864 
  "CGEN_ENABLE_INSN_P (850)"
20865 
  "lbu\\t%0,%1($tp)"
20866 
  [(set_attr "may_trap" "no")
20867 
   (set_attr "latency" "2")
20868 
   (set_attr "length" "2")
20869 
   (set_attr "slot" "core")
20870 
   (set_attr "slots" "core")
20871 
   (set_attr "stall" "load")])
20872 
 
20873 
 
20874 
(define_insn "cgen_intrinsic_lw_tp"
20875 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=t")
20876 
        (unspec:SI [
20877 
          (match_operand:SI 1 "cgen_h_uint_5a4_immediate" "")
20878 
          (reg:SI 13)
20879 
          (mem:SI (scratch:SI))
20880 
        ] 3984))]
20881 
  "CGEN_ENABLE_INSN_P (851)"
20882 
  "lw\\t%0,%1($tp)"
20883 
  [(set_attr "may_trap" "no")
20884 
   (set_attr "latency" "2")
20885 
   (set_attr "length" "2")
20886 
   (set_attr "slot" "core")
20887 
   (set_attr "slots" "core")
20888 
   (set_attr "stall" "load")])
20889 
 
20890 
 
20891 
(define_insn "cgen_intrinsic_lh_tp"
20892 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=t")
20893 
        (unspec:SI [
20894 
          (match_operand:SI 1 "cgen_h_uint_6a2_immediate" "")
20895 
          (reg:SI 13)
20896 
          (mem:SI (scratch:SI))
20897 
        ] 3986))]
20898 
  "CGEN_ENABLE_INSN_P (852)"
20899 
  "lh\\t%0,%1($tp)"
20900 
  [(set_attr "may_trap" "no")
20901 
   (set_attr "latency" "2")
20902 
   (set_attr "length" "2")
20903 
   (set_attr "slot" "core")
20904 
   (set_attr "slots" "core")
20905 
   (set_attr "stall" "load")])
20906 
 
20907 
 
20908 
(define_insn "cgen_intrinsic_lb_tp"
20909 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=t")
20910 
        (unspec:SI [
20911 
          (match_operand:SI 1 "cgen_h_uint_7a1_immediate" "")
20912 
          (reg:SI 13)
20913 
          (mem:SI (scratch:SI))
20914 
        ] 3988))]
20915 
  "CGEN_ENABLE_INSN_P (853)"
20916 
  "lb\\t%0,%1($tp)"
20917 
  [(set_attr "may_trap" "no")
20918 
   (set_attr "latency" "2")
20919 
   (set_attr "length" "2")
20920 
   (set_attr "slot" "core")
20921 
   (set_attr "slots" "core")
20922 
   (set_attr "stall" "load")])
20923 
 
20924 
 
20925 
(define_insn "cgen_intrinsic_sw_tp"
20926 
  [(set (mem:SI (scratch:SI))
20927 
        (unspec:SI [
20928 
          (match_operand:SI 0 "general_operand" "t")
20929 
          (match_operand:SI 1 "cgen_h_uint_5a4_immediate" "")
20930 
          (reg:SI 13)
20931 
        ] 3990))]
20932 
  "CGEN_ENABLE_INSN_P (854)"
20933 
  "sw\\t%0,%1($tp)"
20934 
  [(set_attr "may_trap" "no")
20935 
   (set_attr "latency" "0")
20936 
   (set_attr "length" "2")
20937 
   (set_attr "slot" "core")
20938 
   (set_attr "slots" "core")
20939 
   (set_attr "stall" "store")])
20940 
 
20941 
 
20942 
(define_insn "cgen_intrinsic_sh_tp"
20943 
  [(set (mem:SI (scratch:SI))
20944 
        (unspec:SI [
20945 
          (match_operand:SI 0 "general_operand" "t")
20946 
          (match_operand:SI 1 "cgen_h_uint_6a2_immediate" "")
20947 
          (reg:SI 13)
20948 
        ] 3992))]
20949 
  "CGEN_ENABLE_INSN_P (855)"
20950 
  "sh\\t%0,%1($tp)"
20951 
  [(set_attr "may_trap" "no")
20952 
   (set_attr "latency" "0")
20953 
   (set_attr "length" "2")
20954 
   (set_attr "slot" "core")
20955 
   (set_attr "slots" "core")
20956 
   (set_attr "stall" "store")])
20957 
 
20958 
 
20959 
(define_insn "cgen_intrinsic_sb_tp"
20960 
  [(set (mem:SI (scratch:SI))
20961 
        (unspec:SI [
20962 
          (match_operand:SI 0 "general_operand" "t")
20963 
          (match_operand:SI 1 "cgen_h_uint_7a1_immediate" "")
20964 
          (reg:SI 13)
20965 
        ] 3994))]
20966 
  "CGEN_ENABLE_INSN_P (856)"
20967 
  "sb\\t%0,%1($tp)"
20968 
  [(set_attr "may_trap" "no")
20969 
   (set_attr "latency" "0")
20970 
   (set_attr "length" "2")
20971 
   (set_attr "slot" "core")
20972 
   (set_attr "slots" "core")
20973 
   (set_attr "stall" "store")])
20974 
 
20975 
 
20976 
(define_insn "cgen_intrinsic_lw_sp"
20977 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20978 
        (unspec:SI [
20979 
          (match_operand:SI 1 "cgen_h_uint_5a4_immediate" "")
20980 
          (reg:SI 15)
20981 
          (mem:SI (scratch:SI))
20982 
        ] 3996))]
20983 
  "CGEN_ENABLE_INSN_P (857)"
20984 
  "lw\\t%0,%1($sp)"
20985 
  [(set_attr "may_trap" "no")
20986 
   (set_attr "latency" "2")
20987 
   (set_attr "length" "2")
20988 
   (set_attr "slot" "core")
20989 
   (set_attr "slots" "core")
20990 
   (set_attr "stall" "load")])
20991 
 
20992 
 
20993 
(define_insn "cgen_intrinsic_sw_sp"
20994 
  [(set (mem:SI (scratch:SI))
20995 
        (unspec:SI [
20996 
          (match_operand:SI 0 "general_operand" "r")
20997 
          (match_operand:SI 1 "cgen_h_uint_5a4_immediate" "")
20998 
          (reg:SI 15)
20999 
        ] 3998))]
21000 
  "CGEN_ENABLE_INSN_P (858)"
21001 
  "sw\\t%0,%1($sp)"
21002 
  [(set_attr "may_trap" "no")
21003 
   (set_attr "latency" "0")
21004 
   (set_attr "length" "2")
21005 
   (set_attr "slot" "core")
21006 
   (set_attr "slots" "core")
21007 
   (set_attr "stall" "store")])
21008 
 
21009 
 
21010 
(define_insn "cgen_intrinsic_lhu"
21011 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
21012 
        (unspec:SI [
21013 
          (match_operand:SI 1 "general_operand" "r")
21014 
          (mem:SI (scratch:SI))
21015 
        ] 4000))]
21016 
  "CGEN_ENABLE_INSN_P (859)"
21017 
  "lhu\\t%0,(%1)"
21018 
  [(set_attr "may_trap" "no")
21019 
   (set_attr "latency" "2")
21020 
   (set_attr "length" "2")
21021 
   (set_attr "slot" "core")
21022 
   (set_attr "slots" "core")
21023 
   (set_attr "stall" "load")])
21024 
 
21025 
 
21026 
(define_insn "cgen_intrinsic_lbu"
21027 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
21028 
        (unspec:SI [
21029 
          (match_operand:SI 1 "general_operand" "r")
21030 
          (mem:SI (scratch:SI))
21031 
        ] 4002))]
21032 
  "CGEN_ENABLE_INSN_P (860)"
21033 
  "lbu\\t%0,(%1)"
21034 
  [(set_attr "may_trap" "no")
21035 
   (set_attr "latency" "2")
21036 
   (set_attr "length" "2")
21037 
   (set_attr "slot" "core")
21038 
   (set_attr "slots" "core")
21039 
   (set_attr "stall" "load")])
21040 
 
21041 
 
21042 
(define_insn "cgen_intrinsic_lw"
21043 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
21044 
        (unspec:SI [
21045 
          (match_operand:SI 1 "general_operand" "r")
21046 
          (mem:SI (scratch:SI))
21047 
        ] 4004))]
21048 
  "CGEN_ENABLE_INSN_P (861)"
21049 
  "lw\\t%0,(%1)"
21050 
  [(set_attr "may_trap" "no")
21051 
   (set_attr "latency" "2")
21052 
   (set_attr "length" "2")
21053 
   (set_attr "slot" "core")
21054 
   (set_attr "slots" "core")
21055 
   (set_attr "stall" "load")])
21056 
 
21057 
 
21058 
(define_insn "cgen_intrinsic_lh"
21059 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
21060 
        (unspec:SI [
21061 
          (match_operand:SI 1 "general_operand" "r")
21062 
          (mem:SI (scratch:SI))
21063 
        ] 4006))]
21064 
  "CGEN_ENABLE_INSN_P (862)"
21065 
  "lh\\t%0,(%1)"
21066 
  [(set_attr "may_trap" "no")
21067 
   (set_attr "latency" "2")
21068 
   (set_attr "length" "2")
21069 
   (set_attr "slot" "core")
21070 
   (set_attr "slots" "core")
21071 
   (set_attr "stall" "load")])
21072 
 
21073 
 
21074 
(define_insn "cgen_intrinsic_lb"
21075 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
21076 
        (unspec:SI [
21077 
          (match_operand:SI 1 "general_operand" "r")
21078 
          (mem:SI (scratch:SI))
21079 
        ] 4008))]
21080 
  "CGEN_ENABLE_INSN_P (863)"
21081 
  "lb\\t%0,(%1)"
21082 
  [(set_attr "may_trap" "no")
21083 
   (set_attr "latency" "2")
21084 
   (set_attr "length" "2")
21085 
   (set_attr "slot" "core")
21086 
   (set_attr "slots" "core")
21087 
   (set_attr "stall" "load")])
21088 
 
21089 
 
21090 
(define_insn "cgen_intrinsic_sw"
21091 
  [(set (mem:SI (scratch:SI))
21092 
        (unspec:SI [
21093 
          (match_operand:SI 0 "general_operand" "r")
21094 
          (match_operand:SI 1 "general_operand" "r")
21095 
        ] 4010))]
21096 
  "CGEN_ENABLE_INSN_P (864)"
21097 
  "sw\\t%0,(%1)"
21098 
  [(set_attr "may_trap" "no")
21099 
   (set_attr "latency" "0")
21100 
   (set_attr "length" "2")
21101 
   (set_attr "slot" "core")
21102 
   (set_attr "slots" "core")
21103 
   (set_attr "stall" "store")])
21104 
 
21105 
 
21106 
(define_insn "cgen_intrinsic_sh"
21107 
  [(set (mem:SI (scratch:SI))
21108 
        (unspec:SI [
21109 
          (match_operand:SI 0 "general_operand" "r")
21110 
          (match_operand:SI 1 "general_operand" "r")
21111 
        ] 4012))]
21112 
  "CGEN_ENABLE_INSN_P (865)"
21113 
  "sh\\t%0,(%1)"
21114 
  [(set_attr "may_trap" "no")
21115 
   (set_attr "latency" "0")
21116 
   (set_attr "length" "2")
21117 
   (set_attr "slot" "core")
21118 
   (set_attr "slots" "core")
21119 
   (set_attr "stall" "store")])
21120 
 
21121 
 
21122 
(define_insn "cgen_intrinsic_sb"
21123 
  [(set (mem:SI (scratch:SI))
21124 
        (unspec:SI [
21125 
          (match_operand:SI 0 "general_operand" "r")
21126 
          (match_operand:SI 1 "general_operand" "r")
21127 
        ] 4014))]
21128 
  "CGEN_ENABLE_INSN_P (866)"
21129 
  "sb\\t%0,(%1)"
21130 
  [(set_attr "may_trap" "no")
21131 
   (set_attr "latency" "0")
21132 
   (set_attr "length" "2")
21133 
   (set_attr "slot" "core")
21134 
   (set_attr "slots" "core")
21135 
   (set_attr "stall" "store")])
21136 
 
21137 
 
21138 
(define_insn "cgen_intrinsic_dsp1"
21139 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
21140 
        (unspec_volatile:SI [
21141 
          (match_operand:SI 1 "general_operand" "0")
21142 
          (match_operand:SI 2 "cgen_h_uint_20a1_immediate" "")
21143 
        ] 4016))]
21144 
  "CGEN_ENABLE_INSN_P (867)"
21145 
  "dsp1\\t%1,%2"
21146 
  [(set_attr "may_trap" "no")
21147 
   (set_attr "latency" "0")
21148 
   (set_attr "length" "4")
21149 
   (set_attr "slot" "core")
21150 
   (set_attr "slots" "core")
21151 
   (set_attr "stall" "none")])
21152 
 
21153 
 
21154 
(define_insn "cgen_intrinsic_dsp0"
21155 
  [(unspec_volatile [
21156 
     (match_operand:SI 0 "cgen_h_uint_24a1_immediate" "")
21157 
   ] 4018)]
21158 
  "CGEN_ENABLE_INSN_P (868)"
21159 
  "dsp0\\t%0"
21160 
  [(set_attr "may_trap" "no")
21161 
   (set_attr "latency" "0")
21162 
   (set_attr "length" "4")
21163 
   (set_attr "slot" "core")
21164 
   (set_attr "slots" "core")
21165 
   (set_attr "stall" "none")])
21166 
 
21167 
 
21168 
(define_insn "cgen_intrinsic_dsp"
21169 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
21170 
        (unspec_volatile:SI [
21171 
          (match_operand:SI 1 "general_operand" "0")
21172 
          (match_operand:SI 2 "general_operand" "r")
21173 
          (match_operand:SI 3 "cgen_h_uint_16a1_immediate" "")
21174 
        ] 4020))]
21175 
  "CGEN_ENABLE_INSN_P (869)"
21176 
  "dsp\\t%1,%2,%3"
21177 
  [(set_attr "may_trap" "no")
21178 
   (set_attr "latency" "0")
21179 
   (set_attr "length" "4")
21180 
   (set_attr "slot" "core")
21181 
   (set_attr "slots" "core")
21182 
   (set_attr "stall" "none")])
21183 
 
21184 
 
21185 
(define_insn "cgen_intrinsic_uci"
21186 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
21187 
        (unspec_volatile:SI [
21188 
          (match_operand:SI 1 "general_operand" "0")
21189 
          (match_operand:SI 2 "general_operand" "r")
21190 
          (match_operand:SI 3 "cgen_h_uint_16a1_immediate" "")
21191 
        ] 4022))]
21192 
  "CGEN_ENABLE_INSN_P (870)"
21193 
  "uci\\t%1,%2,%3"
21194 
  [(set_attr "may_trap" "no")
21195 
   (set_attr "latency" "0")
21196 
   (set_attr "length" "4")
21197 
   (set_attr "slot" "core")
21198 
   (set_attr "slots" "core")
21199 
   (set_attr "stall" "none")])
21200 
 
21201 
 
21202 
(define_insn "cgen_intrinsic_lhucpm1"
21203 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
21204 
        (unspec:SI [
21205 
          (match_operand:SI 2 "general_operand" "1")
21206 
          (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
21207 
          (reg:SI 31)
21208 
          (reg:SI 30)
21209 
          (mem:SI (scratch:SI))
21210 
        ] 4024))
21211 
   (set (match_operand:SI 1 "nonimmediate_operand" "=r")
21212 
        (unspec:SI [
21213 
          (match_dup 2)
21214 
          (match_dup 3)
21215 
          (reg:SI 31)
21216 
          (reg:SI 30)
21217 
          (mem:SI (scratch:SI))
21218 
        ] 4026))]
21219 
  "CGEN_ENABLE_INSN_P (871)"
21220 
  "lhucpm1\\t%0,(%2+),%3"
21221 
  [(set_attr "may_trap" "no")
21222 
   (set_attr "latency" "0")
21223 
   (set_attr "length" "4")
21224 
   (set_attr "slot" "core")
21225 
   (set_attr "slots" "core")
21226 
   (set_attr "stall" "none")])
21227 
 
21228 
 
21229 
(define_insn "cgen_intrinsic_lbucpm1"
21230 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
21231 
        (unspec:SI [
21232 
          (match_operand:SI 2 "general_operand" "1")
21233 
          (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
21234 
          (reg:SI 31)
21235 
          (reg:SI 30)
21236 
          (mem:SI (scratch:SI))
21237 
        ] 4028))
21238 
   (set (match_operand:SI 1 "nonimmediate_operand" "=r")
21239 
        (unspec:SI [
21240 
          (match_dup 2)
21241 
          (match_dup 3)
21242 
          (reg:SI 31)
21243 
          (reg:SI 30)
21244 
          (mem:SI (scratch:SI))
21245 
        ] 4030))]
21246 
  "CGEN_ENABLE_INSN_P (872)"
21247 
  "lbucpm1\\t%0,(%2+),%3"
21248 
  [(set_attr "may_trap" "no")
21249 
   (set_attr "latency" "0")
21250 
   (set_attr "length" "4")
21251 
   (set_attr "slot" "core")
21252 
   (set_attr "slots" "core")
21253 
   (set_attr "stall" "none")])
21254 
 
21255 
 
21256 
(define_insn "cgen_intrinsic_lhucpm0"
21257 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
21258 
        (unspec:SI [
21259 
          (match_operand:SI 2 "general_operand" "1")
21260 
          (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
21261 
          (reg:SI 29)
21262 
          (reg:SI 28)
21263 
          (mem:SI (scratch:SI))
21264 
        ] 4032))
21265 
   (set (match_operand:SI 1 "nonimmediate_operand" "=r")
21266 
        (unspec:SI [
21267 
          (match_dup 2)
21268 
          (match_dup 3)
21269 
          (reg:SI 29)
21270 
          (reg:SI 28)
21271 
          (mem:SI (scratch:SI))
21272 
        ] 4034))]
21273 
  "CGEN_ENABLE_INSN_P (873)"
21274 
  "lhucpm0\\t%0,(%2+),%3"
21275 
  [(set_attr "may_trap" "no")
21276 
   (set_attr "latency" "0")
21277 
   (set_attr "length" "4")
21278 
   (set_attr "slot" "core")
21279 
   (set_attr "slots" "core")
21280 
   (set_attr "stall" "none")])
21281 
 
21282 
 
21283 
(define_insn "cgen_intrinsic_lbucpm0"
21284 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
21285 
        (unspec:SI [
21286 
          (match_operand:SI 2 "general_operand" "1")
21287 
          (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
21288 
          (reg:SI 29)
21289 
          (reg:SI 28)
21290 
          (mem:SI (scratch:SI))
21291 
        ] 4036))
21292 
   (set (match_operand:SI 1 "nonimmediate_operand" "=r")
21293 
        (unspec:SI [
21294 
          (match_dup 2)
21295 
          (match_dup 3)
21296 
          (reg:SI 29)
21297 
          (reg:SI 28)
21298 
          (mem:SI (scratch:SI))
21299 
        ] 4038))]
21300 
  "CGEN_ENABLE_INSN_P (874)"
21301 
  "lbucpm0\\t%0,(%2+),%3"
21302 
  [(set_attr "may_trap" "no")
21303 
   (set_attr "latency" "0")
21304 
   (set_attr "length" "4")
21305 
   (set_attr "slot" "core")
21306 
   (set_attr "slots" "core")
21307 
   (set_attr "stall" "none")])
21308 
 
21309 
 
21310 
(define_insn "cgen_intrinsic_lhucpa"
21311 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
21312 
        (unspec:SI [
21313 
          (match_operand:SI 2 "general_operand" "1")
21314 
          (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
21315 
          (mem:SI (scratch:SI))
21316 
        ] 4040))
21317 
   (set (match_operand:SI 1 "nonimmediate_operand" "=r")
21318 
        (unspec:SI [
21319 
          (match_dup 2)
21320 
          (match_dup 3)
21321 
          (mem:SI (scratch:SI))
21322 
        ] 4042))]
21323 
  "CGEN_ENABLE_INSN_P (875)"
21324 
  "lhucpa\\t%0,(%2+),%3"
21325 
  [(set_attr "may_trap" "no")
21326 
   (set_attr "latency" "0")
21327 
   (set_attr "length" "4")
21328 
   (set_attr "slot" "core")
21329 
   (set_attr "slots" "core")
21330 
   (set_attr "stall" "load")])
21331 
 
21332 
 
21333 
(define_insn "cgen_intrinsic_lbucpa"
21334 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
21335 
        (unspec:SI [
21336 
          (match_operand:SI 2 "general_operand" "1")
21337 
          (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
21338 
          (mem:SI (scratch:SI))
21339 
        ] 4044))
21340 
   (set (match_operand:SI 1 "nonimmediate_operand" "=r")
21341 
        (unspec:SI [
21342 
          (match_dup 2)
21343 
          (match_dup 3)
21344 
          (mem:SI (scratch:SI))
21345 
        ] 4046))]
21346 
  "CGEN_ENABLE_INSN_P (876)"
21347 
  "lbucpa\\t%0,(%2+),%3"
21348 
  [(set_attr "may_trap" "no")
21349 
   (set_attr "latency" "0")
21350 
   (set_attr "length" "4")
21351 
   (set_attr "slot" "core")
21352 
   (set_attr "slots" "core")
21353 
   (set_attr "stall" "load")])
21354 
 
21355 
 
21356 
(define_insn "cgen_intrinsic_lhucp"
21357 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
21358 
        (unspec:SI [
21359 
          (match_operand:SI 1 "cgen_h_sint_12a1_immediate" "")
21360 
          (match_operand:SI 2 "general_operand" "r")
21361 
          (mem:SI (scratch:SI))
21362 
        ] 4048))]
21363 
  "CGEN_ENABLE_INSN_P (877)"
21364 
  "lhucp\\t%0,%1(%2)"
21365 
  [(set_attr "may_trap" "no")
21366 
   (set_attr "latency" "0")
21367 
   (set_attr "length" "4")
21368 
   (set_attr "slot" "core")
21369 
   (set_attr "slots" "core")
21370 
   (set_attr "stall" "store")])
21371 
 
21372 
 
21373 
(define_insn "cgen_intrinsic_lhcp"
21374 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
21375 
        (unspec:SI [
21376 
          (match_operand:SI 1 "cgen_h_sint_12a1_immediate" "")
21377 
          (match_operand:SI 2 "general_operand" "r")
21378 
          (mem:SI (scratch:SI))
21379 
        ] 4050))]
21380 
  "CGEN_ENABLE_INSN_P (878)"
21381 
  "lhcp\\t%0,%1(%2)"
21382 
  [(set_attr "may_trap" "no")
21383 
   (set_attr "latency" "0")
21384 
   (set_attr "length" "4")
21385 
   (set_attr "slot" "core")
21386 
   (set_attr "slots" "core")
21387 
   (set_attr "stall" "store")])
21388 
 
21389 
 
21390 
(define_insn "cgen_intrinsic_shcp"
21391 
  [(set (mem:SI (scratch:SI))
21392 
        (unspec:SI [
21393 
          (match_operand:SI 0 "general_operand" "em")
21394 
          (match_operand:SI 1 "cgen_h_sint_12a1_immediate" "")
21395 
          (match_operand:SI 2 "general_operand" "r")
21396 
        ] 4052))]
21397 
  "CGEN_ENABLE_INSN_P (879)"
21398 
  "shcp\\t%0,%1(%2)"
21399 
  [(set_attr "may_trap" "no")
21400 
   (set_attr "latency" "0")
21401 
   (set_attr "length" "4")
21402 
   (set_attr "slot" "core")
21403 
   (set_attr "slots" "core")
21404 
   (set_attr "stall" "store")])
21405 
 
21406 
 
21407 
(define_insn "cgen_intrinsic_lbucp"
21408 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
21409 
        (unspec:SI [
21410 
          (match_operand:SI 1 "cgen_h_sint_12a1_immediate" "")
21411 
          (match_operand:SI 2 "general_operand" "r")
21412 
          (mem:SI (scratch:SI))
21413 
        ] 4054))]
21414 
  "CGEN_ENABLE_INSN_P (880)"
21415 
  "lbucp\\t%0,%1(%2)"
21416 
  [(set_attr "may_trap" "no")
21417 
   (set_attr "latency" "0")
21418 
   (set_attr "length" "4")
21419 
   (set_attr "slot" "core")
21420 
   (set_attr "slots" "core")
21421 
   (set_attr "stall" "store")])
21422 
 
21423 
 
21424 
(define_insn "cgen_intrinsic_lbcp"
21425 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
21426 
        (unspec:SI [
21427 
          (match_operand:SI 1 "cgen_h_sint_12a1_immediate" "")
21428 
          (match_operand:SI 2 "general_operand" "r")
21429 
          (mem:SI (scratch:SI))
21430 
        ] 4056))]
21431 
  "CGEN_ENABLE_INSN_P (881)"
21432 
  "lbcp\\t%0,%1(%2)"
21433 
  [(set_attr "may_trap" "no")
21434 
   (set_attr "latency" "0")
21435 
   (set_attr "length" "4")
21436 
   (set_attr "slot" "core")
21437 
   (set_attr "slots" "core")
21438 
   (set_attr "stall" "store")])
21439 
 
21440 
 
21441 
(define_insn "cgen_intrinsic_sbcp"
21442 
  [(set (mem:SI (scratch:SI))
21443 
        (unspec:SI [
21444 
          (match_operand:SI 0 "general_operand" "em")
21445 
          (match_operand:SI 1 "cgen_h_sint_12a1_immediate" "")
21446 
          (match_operand:SI 2 "general_operand" "r")
21447 
        ] 4058))]
21448 
  "CGEN_ENABLE_INSN_P (882)"
21449 
  "sbcp\\t%0,%1(%2)"
21450 
  [(set_attr "may_trap" "no")
21451 
   (set_attr "latency" "0")
21452 
   (set_attr "length" "4")
21453 
   (set_attr "slot" "core")
21454 
   (set_attr "slots" "core")
21455 
   (set_attr "stall" "store")])
21456 
 
21457 
 
21458 
(define_insn "cgen_intrinsic_casw3"
21459 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
21460 
        (unspec_volatile:SI [
21461 
          (match_operand:SI 1 "general_operand" "0")
21462 
          (match_operand:SI 2 "general_operand" "r")
21463 
          (match_operand:SI 3 "general_operand" "r")
21464 
        ] 4060))]
21465 
  "CGEN_ENABLE_INSN_P (883)"
21466 
  "casw3\\t%1,%2,(%3)"
21467 
  [(set_attr "may_trap" "no")
21468 
   (set_attr "latency" "0")
21469 
   (set_attr "length" "4")
21470 
   (set_attr "slot" "core")
21471 
   (set_attr "slots" "core")
21472 
   (set_attr "stall" "none")])
21473 
 
21474 
 
21475 
(define_insn "cgen_intrinsic_cash3"
21476 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
21477 
        (unspec_volatile:SI [
21478 
          (match_operand:SI 1 "general_operand" "0")
21479 
          (match_operand:SI 2 "general_operand" "r")
21480 
          (match_operand:SI 3 "general_operand" "r")
21481 
        ] 4062))]
21482 
  "CGEN_ENABLE_INSN_P (884)"
21483 
  "cash3\\t%1,%2,(%3)"
21484 
  [(set_attr "may_trap" "no")
21485 
   (set_attr "latency" "0")
21486 
   (set_attr "length" "4")
21487 
   (set_attr "slot" "core")
21488 
   (set_attr "slots" "core")
21489 
   (set_attr "stall" "none")])
21490 
 
21491 
 
21492 
(define_insn "cgen_intrinsic_casb3"
21493 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
21494 
        (unspec_volatile:SI [
21495 
          (match_operand:SI 1 "general_operand" "0")
21496 
          (match_operand:SI 2 "general_operand" "r")
21497 
          (match_operand:SI 3 "general_operand" "r")
21498 
        ] 4064))]
21499 
  "CGEN_ENABLE_INSN_P (885)"
21500 
  "casb3\\t%1,%2,(%3)"
21501 
  [(set_attr "may_trap" "no")
21502 
   (set_attr "latency" "0")
21503 
   (set_attr "length" "4")
21504 
   (set_attr "slot" "core")
21505 
   (set_attr "slots" "core")
21506 
   (set_attr "stall" "none")])
21507 
 
21508 
 
21509 
(define_insn "cgen_intrinsic_prefd"
21510 
  [(unspec_volatile [
21511 
     (match_operand:SI 0 "cgen_h_uint_4a1_immediate" "")
21512 
     (match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
21513 
     (match_operand:SI 2 "general_operand" "r")
21514 
   ] 4066)]
21515 
  "CGEN_ENABLE_INSN_P (886)"
21516 
  "pref\\t%0,%1(%2)"
21517 
  [(set_attr "may_trap" "no")
21518 
   (set_attr "latency" "0")
21519 
   (set_attr "length" "4")
21520 
   (set_attr "slot" "core")
21521 
   (set_attr "slots" "core")
21522 
   (set_attr "stall" "none")])
21523 
 
21524 
 
21525 
(define_insn "cgen_intrinsic_pref"
21526 
  [(unspec_volatile [
21527 
     (match_operand:SI 0 "cgen_h_uint_4a1_immediate" "")
21528 
     (match_operand:SI 1 "general_operand" "r")
21529 
   ] 4068)]
21530 
  "CGEN_ENABLE_INSN_P (887)"
21531 
  "pref\\t%0,(%1)"
21532 
  [(set_attr "may_trap" "no")
21533 
   (set_attr "latency" "0")
21534 
   (set_attr "length" "2")
21535 
   (set_attr "slot" "core")
21536 
   (set_attr "slots" "core")
21537 
   (set_attr "stall" "none")])
21538 
 
21539 
 
21540 
(define_insn "cgen_intrinsic_ldcb_r"
21541 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
21542 
        (unspec_volatile:SI [
21543 
          (match_operand:SI 1 "general_operand" "r")
21544 
        ] 4070))]
21545 
  "CGEN_ENABLE_INSN_P (888)"
21546 
  "ldcb\\t%0,(%1)"
21547 
  [(set_attr "may_trap" "no")
21548 
   (set_attr "latency" "3")
21549 
   (set_attr "length" "2")
21550 
   (set_attr "slot" "core")
21551 
   (set_attr "slots" "core")
21552 
   (set_attr "stall" "none")])
21553 
 
21554 
 
21555 
(define_insn "cgen_intrinsic_stcb_r"
21556 
  [(unspec_volatile [
21557 
     (match_operand:SI 0 "general_operand" "r")
21558 
     (match_operand:SI 1 "general_operand" "r")
21559 
   ] 4072)]
21560 
  "CGEN_ENABLE_INSN_P (889)"
21561 
  "stcb\\t%0,(%1)"
21562 
  [(set_attr "may_trap" "no")
21563 
   (set_attr "latency" "0")
21564 
   (set_attr "length" "2")
21565 
   (set_attr "slot" "core")
21566 
   (set_attr "slots" "core")
21567 
   (set_attr "stall" "none")])
21568 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.