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jeremybenn |
;; Copyright (C) 2007 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; . */
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;;
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;; .........................
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;;
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;; DFA-based pipeline description for MIPS64 model R20Kc.
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;; Contributed by Jason Eckhardt (jle@cygnus.com).
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;;
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;; The R20Kc is a dual-issue processor that can generally bundle
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;; instructions as follows:
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;; 1. integer with integer
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;; 2. integer with fp
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;; 3. fp with fpload/fpstore
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;;
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;; Of course, there are various restrictions.
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;; Reference:
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;; "Ruby (R20K) Technical Specification Rev. 1.2, December 28, 1999."
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;;
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;; .........................
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;; Use three automata to isolate long latency operations, reducing space.
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(define_automaton "r20kc_other, r20kc_fdiv, r20kc_idiv")
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;;
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;; Describe the resources.
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;;
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;; Global.
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(define_cpu_unit "r20kc_iss0, r20kc_iss1" "r20kc_other")
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;; Integer execution unit (pipeline A).
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(define_cpu_unit "r20kc_ixua_addsub_agen" "r20kc_other")
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(define_cpu_unit "r20kc_ixua_shift" "r20kc_other")
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(exclusion_set "r20kc_ixua_addsub_agen" "r20kc_ixua_shift")
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;; Integer execution unit (pipeline B).
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(define_cpu_unit "r20kc_ixub_addsub" "r20kc_other")
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(define_cpu_unit "r20kc_ixub_branch" "r20kc_other")
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(define_cpu_unit "r20kc_ixub_mpydiv" "r20kc_other")
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(define_cpu_unit "r20kc_ixub_mpydiv_iter" "r20kc_idiv")
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(exclusion_set "r20kc_ixub_addsub" "r20kc_ixub_branch, r20kc_ixub_mpydiv")
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(exclusion_set "r20kc_ixub_branch" "r20kc_ixub_mpydiv")
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;; Cache / memory interface.
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(define_cpu_unit "r20kc_cache" "r20kc_other")
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;; Floating-point unit.
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(define_cpu_unit "r20kc_fpu_add" "r20kc_other")
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(define_cpu_unit "r20kc_fpu_mpy" "r20kc_other")
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(define_cpu_unit "r20kc_fpu_mpy_iter" "r20kc_fdiv")
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(define_cpu_unit "r20kc_fpu_divsqrt" "r20kc_other")
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(define_cpu_unit "r20kc_fpu_divsqrt_iter" "r20kc_fdiv")
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(exclusion_set "r20kc_fpu_add" "r20kc_fpu_mpy, r20kc_fpu_divsqrt")
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(exclusion_set "r20kc_fpu_mpy" "r20kc_fpu_divsqrt")
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;; After branch any insn can not be issued.
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(absence_set "r20kc_iss0,r20kc_iss1" "r20kc_ixub_branch")
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;;
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;; Define reservations for unit name mnemonics or combinations.
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;;
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(define_reservation "r20kc_iss"
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"r20kc_iss0|r20kc_iss1")
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(define_reservation "r20kc_single_dispatch"
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"r20kc_iss0+r20kc_iss1")
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(define_reservation "r20kc_iaddsub"
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"r20kc_iss+(r20kc_ixua_addsub_agen|r20kc_ixub_addsub)")
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(define_reservation "r20kc_ishift"
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"r20kc_iss+r20kc_ixua_shift")
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(define_reservation "r20kc_fpmove"
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"r20kc_iss+r20kc_ixua_addsub_agen")
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(define_reservation "r20kc_imem"
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"r20kc_iss+r20kc_ixua_addsub_agen+r20kc_cache")
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(define_reservation "r20kc_icache"
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"r20kc_cache")
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(define_reservation "r20kc_impydiv"
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"r20kc_iss+r20kc_ixub_mpydiv")
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(define_reservation "r20kc_impydiv_iter"
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"r20kc_ixub_mpydiv_iter")
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(define_reservation "r20kc_ibranch"
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"r20kc_iss+r20kc_ixub_branch")
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(define_reservation "r20kc_fpadd"
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"r20kc_iss+r20kc_fpu_add")
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(define_reservation "r20kc_fpmpy"
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"r20kc_iss+r20kc_fpu_mpy")
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(define_reservation "r20kc_fpmpy_iter"
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"r20kc_fpu_mpy_iter")
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(define_reservation "r20kc_fpdivsqrt"
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"r20kc_iss+r20kc_fpu_divsqrt")
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(define_reservation "r20kc_fpdivsqrt_iter"
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"r20kc_fpu_divsqrt_iter")
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;;
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;; Describe instruction reservations for integer operations.
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;;
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;; Conditional moves always force single-dispatch.
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(define_insn_reservation "r20kc_cond_move_int" 1
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(and (eq_attr "cpu" "20kc")
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(and (eq_attr "type" "condmove")
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(eq_attr "mode" "!SF,DF")))
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"r20kc_single_dispatch")
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(define_insn_reservation "r20kc_cond_move_fp" 4
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(and (eq_attr "cpu" "20kc")
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(and (eq_attr "type" "condmove")
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(eq_attr "mode" "SF,DF")))
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"r20kc_single_dispatch")
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(define_insn_reservation "r20kc_int_other" 1
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(and (eq_attr "cpu" "20kc")
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(eq_attr "type" "move,arith,const,nop"))
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"r20kc_iaddsub")
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;; Shifts can only execute on ixu pipeline A.
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(define_insn_reservation "r20kc_int_shift" 1
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(and (eq_attr "cpu" "20kc")
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(eq_attr "type" "shift"))
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"r20kc_ishift")
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(define_insn_reservation "r20kc_ld" 2
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(and (eq_attr "cpu" "20kc")
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(eq_attr "type" "load,prefetch,prefetchx"))
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"r20kc_imem")
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;; A load immediately following a store will stall, so
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;; say that a store uses the cache for an extra cycle.
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(define_insn_reservation "r20kc_st" 2
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(and (eq_attr "cpu" "20kc")
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(eq_attr "type" "store"))
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"r20kc_imem,r20kc_icache")
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(define_insn_reservation "r20kc_fld" 3
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(and (eq_attr "cpu" "20kc")
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(eq_attr "type" "fpload"))
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"r20kc_imem")
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(define_insn_reservation "r20kc_ffst" 3
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(and (eq_attr "cpu" "20kc")
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(eq_attr "type" "fpstore"))
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"r20kc_imem,r20kc_icache*2")
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;; Integer divide latency is between 13 and 42 cycles for DIV[U] and between
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;; 13 and 72 cycles for DDIV[U]. This depends on the value of the inputs
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;; so we just choose the worst case latency.
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(define_insn_reservation "r20kc_idiv_si" 42
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(and (eq_attr "cpu" "20kc")
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(and (eq_attr "type" "idiv")
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(eq_attr "mode" "SI")))
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"r20kc_impydiv+(r20kc_impydiv_iter*42)")
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(define_insn_reservation "r20kc_idiv_di" 72
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(and (eq_attr "cpu" "20kc")
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(and (eq_attr "type" "idiv")
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(eq_attr "mode" "DI")))
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"r20kc_impydiv+(r20kc_impydiv_iter*72)")
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;; Integer multiply latency is 4 or 7 cycles for word and double-word
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;; respectively.
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(define_insn_reservation "r20kc_impy_si" 4
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(and (eq_attr "cpu" "20kc")
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(and (eq_attr "type" "imadd,imul,imul3")
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(eq_attr "mode" "SI")))
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"r20kc_impydiv+(r20kc_impydiv_iter*2)")
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(define_insn_reservation "r20kc_impy_di" 7
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(and (eq_attr "cpu" "20kc")
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(and (eq_attr "type" "imadd,imul,imul3")
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(eq_attr "mode" "DI")))
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"r20kc_impydiv+(r20kc_impydiv_iter*7)")
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;; Move to/from HI/LO.
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;; Moving to HI/LO has a 3 cycle latency while moving from only has a 1
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;; cycle latency. Repeat rate is 3 for both.
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(define_insn_reservation "r20kc_imthilo" 3
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(and (eq_attr "cpu" "20kc")
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(eq_attr "type" "mthilo"))
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"r20kc_impydiv+(r20kc_impydiv_iter*3)")
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(define_insn_reservation "r20kc_imfhilo" 1
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(and (eq_attr "cpu" "20kc")
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(eq_attr "type" "mfhilo"))
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"r20kc_impydiv+(r20kc_impydiv_iter*3)")
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;; Move to fp coprocessor.
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(define_insn_reservation "r20kc_ixfer_mt" 3
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(and (eq_attr "cpu" "20kc")
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(eq_attr "type" "mtc"))
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"r20kc_fpmove")
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;; Move from fp coprocessor.
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(define_insn_reservation "r20kc_ixfer_mf" 2
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(and (eq_attr "cpu" "20kc")
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(eq_attr "type" "mfc"))
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"r20kc_fpmove")
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;; Assume branch predicted correctly.
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(define_insn_reservation "r20kc_ibr" 1
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(and (eq_attr "cpu" "20kc")
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(eq_attr "type" "branch,jump,call"))
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"r20kc_ibranch")
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;;
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;; Describe instruction reservations for the floating-point operations.
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;;
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(define_insn_reservation "r20kc_fp_other" 4
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(and (eq_attr "cpu" "20kc")
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(eq_attr "type" "fmove,fadd,fabs,fneg,fcmp"))
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"r20kc_fpadd")
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(define_insn_reservation "r20kc_fp_cvt_a" 4
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(and (eq_attr "cpu" "20kc")
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(and (eq_attr "type" "fcvt")
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(eq_attr "cnv_mode" "I2S,I2D,S2D")))
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"r20kc_fpadd")
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(define_insn_reservation "r20kc_fp_cvt_b" 5
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(and (eq_attr "cpu" "20kc")
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(and (eq_attr "type" "fcvt")
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(eq_attr "cnv_mode" "D2S,S2I")))
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"r20kc_fpadd")
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(define_insn_reservation "r20kc_fp_divsqrt_df" 32
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(and (eq_attr "cpu" "20kc")
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(and (eq_attr "type" "fdiv,fsqrt")
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(eq_attr "mode" "DF")))
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"r20kc_fpdivsqrt+(r20kc_fpdivsqrt_iter*32)")
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(define_insn_reservation "r20kc_fp_divsqrt_sf" 17
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(and (eq_attr "cpu" "20kc")
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(and (eq_attr "type" "fdiv,fsqrt")
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(eq_attr "mode" "SF")))
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"r20kc_fpdivsqrt+(r20kc_fpdivsqrt_iter*17)")
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(define_insn_reservation "r20kc_fp_rsqrt_df" 35
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(and (eq_attr "cpu" "20kc")
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(and (eq_attr "type" "frsqrt")
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(eq_attr "mode" "DF")))
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"r20kc_fpdivsqrt+(r20kc_fpdivsqrt_iter*35)")
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(define_insn_reservation "r20kc_fp_rsqrt_sf" 17
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(and (eq_attr "cpu" "20kc")
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(and (eq_attr "type" "frsqrt")
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(eq_attr "mode" "SF")))
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"r20kc_fpdivsqrt+(r20kc_fpdivsqrt_iter*17)")
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(define_insn_reservation "r20kc_fp_mpy_sf" 4
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(and (eq_attr "cpu" "20kc")
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(and (eq_attr "type" "fmul,fmadd")
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(eq_attr "mode" "SF")))
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"r20kc_fpmpy+r20kc_fpmpy_iter")
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(define_insn_reservation "r20kc_fp_mpy_df" 5
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(and (eq_attr "cpu" "20kc")
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(and (eq_attr "type" "fmul,fmadd")
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(eq_attr "mode" "DF")))
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"r20kc_fpmpy+(r20kc_fpmpy_iter*2)")
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;; Force single-dispatch for unknown or multi.
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(define_insn_reservation "r20kc_unknown" 1
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(and (eq_attr "cpu" "20kc")
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(eq_attr "type" "unknown,multi"))
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"r20kc_single_dispatch")
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