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[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [config/] [mips/] [4130.md] - Blame information for rev 709

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1 709 jeremybenn
;; Copyright (C) 2004, 2005, 2007 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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;; GNU General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3.  If not see
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;; .  */
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;;
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;; Pipeline description for the VR4130 family.
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;;
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;; The processor issues each 8-byte aligned pair of instructions together,
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;; stalling the second instruction if it depends on the first.  Thus, if we
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;; want two instructions to issue in parallel, we need to make sure that the
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;; first one is 8-byte aligned.
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;;
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;; For the purposes of this pipeline description, we treat the processor
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;; like a standard two-way superscalar architecture.  If scheduling were
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;; the last pass to run, we could use the scheduler hooks to vary the
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;; issue rate depending on whether an instruction is at an aligned or
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;; unaligned address.  Unfortunately, delayed branch scheduling and
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;; hazard avoidance are done after the final scheduling pass, and they
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;; can change the addresses of many instructions.
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;;
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;; We get around this in two ways:
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;;
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;;   (1) By running an extra pass at the end of compilation.  This pass goes
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;;       through the function looking for pairs of instructions that could
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;;       execute in parallel.  It makes sure that the first instruction in
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;;       each pair is suitably aligned, inserting nops if necessary.  Doing
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;;       this gives the same kind of pipeline behavior we would see on a
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;;       normal superscalar target.
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;;
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;;       This pass is generally a speed improvement, but the extra nops will
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;;       obviously make the program bigger.  It is therefore unsuitable for
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;;       -Os (at the very least).
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;;
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;;   (2) By modifying the scheduler hooks so that, where possible:
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;;
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;;       (a) dependent instructions are separated by a non-dependent
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;;           instruction;
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;;
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;;       (b) instructions that use the multiplication unit are separated
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;;           by non-multiplication instructions; and
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;;
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;;       (c) memory access instructions are separated by non-memory
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;;           instructions.
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;;
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;;       The idea is to keep conflicting instructions apart wherever possible
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;;       and thus make the schedule less dependent on alignment.
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(define_automaton "vr4130_main, vr4130_muldiv, vr4130_mulpre")
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(define_cpu_unit "vr4130_alu1, vr4130_alu2, vr4130_dcache" "vr4130_main")
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(define_cpu_unit "vr4130_muldiv" "vr4130_muldiv")
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;; This is a fake unit for pre-reload scheduling of multiplications.
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;; It enforces the true post-reload repeat rate.
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(define_cpu_unit "vr4130_mulpre" "vr4130_mulpre")
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;; The scheduling hooks use this attribute for (b) above.
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(define_attr "vr4130_class" "mul,mem,alu"
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  (cond [(eq_attr "type" "load,store")
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         (const_string "mem")
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         (eq_attr "type" "mfhilo,mthilo,imul,imul3,imadd,idiv")
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         (const_string "mul")]
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        (const_string "alu")))
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(define_insn_reservation "vr4130_multi" 1
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  (and (eq_attr "cpu" "r4130")
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       (eq_attr "type" "multi,unknown"))
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  "vr4130_alu1 + vr4130_alu2 + vr4130_dcache + vr4130_muldiv")
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(define_insn_reservation "vr4130_int" 1
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  (and (eq_attr "cpu" "r4130")
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       (eq_attr "type" "arith,const,logical,move,nop,shift,signext,slt"))
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  "vr4130_alu1 | vr4130_alu2")
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(define_insn_reservation "vr4130_load" 3
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  (and (eq_attr "cpu" "r4130")
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       (eq_attr "type" "load"))
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  "vr4130_dcache")
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(define_insn_reservation "vr4130_store" 1
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  (and (eq_attr "cpu" "r4130")
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       (eq_attr "type" "store"))
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  "vr4130_dcache")
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(define_insn_reservation "vr4130_mfhilo" 3
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  (and (eq_attr "cpu" "r4130")
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       (eq_attr "type" "mfhilo"))
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  "vr4130_muldiv")
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(define_insn_reservation "vr4130_mthilo" 1
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  (and (eq_attr "cpu" "r4130")
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       (eq_attr "type" "mthilo"))
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  "vr4130_muldiv")
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;; The product is available in LO & HI after one cycle.  Moving the result
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;; into an integer register will take an additional three cycles, see mflo
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;; & mfhi above.  Note that the same latencies and repeat rates apply if we
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;; use "mtlo; macc" instead of "mult; mflo".
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(define_insn_reservation "vr4130_mulsi" 4
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  (and (eq_attr "cpu" "r4130")
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       (and (eq_attr "type" "imul,imul3")
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            (eq_attr "mode" "SI")))
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  "vr4130_muldiv + (vr4130_mulpre * 2)")
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;; As for vr4130_mulsi, but the product is available in LO and HI
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;; after 3 cycles.
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(define_insn_reservation "vr4130_muldi" 6
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  (and (eq_attr "cpu" "r4130")
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       (and (eq_attr "type" "imul,imul3")
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            (eq_attr "mode" "DI")))
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  "(vr4130_muldiv * 3) + (vr4130_mulpre * 4)")
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;; maccs can execute in consecutive cycles without stalling, but it
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;; is 3 cycles before the integer destination can be read.
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(define_insn_reservation "vr4130_macc" 3
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  (and (eq_attr "cpu" "r4130")
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       (eq_attr "type" "imadd"))
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  "vr4130_muldiv")
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(define_bypass 1 "vr4130_mulsi,vr4130_macc" "vr4130_macc" "mips_linked_madd_p")
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(define_bypass 1 "vr4130_mulsi,vr4130_macc" "vr4130_mfhilo")
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(define_bypass 3 "vr4130_muldi" "vr4130_mfhilo")
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(define_insn_reservation "vr4130_divsi" 36
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  (and (eq_attr "cpu" "r4130")
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       (and (eq_attr "type" "idiv")
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            (eq_attr "mode" "SI")))
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  "vr4130_muldiv * 36")
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(define_insn_reservation "vr4130_divdi" 72
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  (and (eq_attr "cpu" "r4130")
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       (and (eq_attr "type" "idiv")
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            (eq_attr "mode" "DI")))
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  "vr4130_muldiv * 72")
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(define_insn_reservation "vr4130_branch" 0
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  (and (eq_attr "cpu" "r4130")
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       (eq_attr "type" "branch,jump,call"))
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  "vr4130_alu1 | vr4130_alu2")

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