OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [config/] [mips/] [4600.md] - Blame information for rev 729

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 709 jeremybenn
;; R4600 and R4650 pipeline description.
2
;;   Copyright (C) 2004, 2005, 2007 Free Software Foundation, Inc.
3
;;
4
;; This file is part of GCC.
5
 
6
;; GCC is free software; you can redistribute it and/or modify it
7
;; under the terms of the GNU General Public License as published
8
;; by the Free Software Foundation; either version 3, or (at your
9
;; option) any later version.
10
 
11
;; GCC is distributed in the hope that it will be useful, but WITHOUT
12
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13
;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
14
;; License for more details.
15
 
16
;; You should have received a copy of the GNU General Public License
17
;; along with GCC; see the file COPYING3.  If not see
18
;; .
19
 
20
 
21
;; This file overrides parts of generic.md.  It is derived from the
22
;; old define_function_unit description.
23
;;
24
;; We handle the R4600 and R4650 in much the same way.  The only difference
25
;; is in the integer multiplication and division costs.
26
 
27
(define_insn_reservation "r4600_imul" 10
28
  (and (eq_attr "cpu" "r4600")
29
       (eq_attr "type" "imul,imul3,imadd"))
30
  "imuldiv*10")
31
 
32
(define_insn_reservation "r4600_idiv" 42
33
  (and (eq_attr "cpu" "r4600")
34
       (eq_attr "type" "idiv"))
35
  "imuldiv*42")
36
 
37
 
38
(define_insn_reservation "r4650_imul" 4
39
  (and (eq_attr "cpu" "r4650")
40
       (eq_attr "type" "imul,imul3,imadd"))
41
  "imuldiv*4")
42
 
43
(define_insn_reservation "r4650_idiv" 36
44
  (and (eq_attr "cpu" "r4650")
45
       (eq_attr "type" "idiv"))
46
  "imuldiv*36")
47
 
48
 
49
(define_insn_reservation "r4600_load" 2
50
  (and (eq_attr "cpu" "r4600,r4650")
51
       (eq_attr "type" "load,fpload,fpidxload"))
52
  "alu")
53
 
54
(define_insn_reservation "r4600_fmove" 1
55
  (and (eq_attr "cpu" "r4600,r4650")
56
       (eq_attr "type" "fabs,fneg,fmove"))
57
  "alu")
58
 
59
(define_insn_reservation "r4600_fmul_single" 8
60
  (and (eq_attr "cpu" "r4600,r4650")
61
       (and (eq_attr "type" "fmul,fmadd")
62
            (eq_attr "mode" "SF")))
63
  "alu")
64
 
65
(define_insn_reservation "r4600_fdiv_single" 32
66
  (and (eq_attr "cpu" "r4600,r4650")
67
       (and (eq_attr "type" "fdiv,frdiv")
68
            (eq_attr "mode" "SF")))
69
  "alu")
70
 
71
(define_insn_reservation "r4600_fdiv_double" 61
72
  (and (eq_attr "cpu" "r4600,r4650")
73
       (and (eq_attr "type" "fdiv,frdiv")
74
            (eq_attr "mode" "DF")))
75
  "alu")
76
 
77
(define_insn_reservation "r4600_fsqrt_single" 31
78
  (and (eq_attr "cpu" "r4600,r4650")
79
       (and (eq_attr "type" "fsqrt,frsqrt")
80
            (eq_attr "mode" "SF")))
81
  "alu")
82
 
83
(define_insn_reservation "r4600_fsqrt_double" 60
84
  (and (eq_attr "cpu" "r4600,r4650")
85
       (and (eq_attr "type" "fsqrt,frsqrt")
86
            (eq_attr "mode" "DF")))
87
  "alu")

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.