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;; DFA-based pipeline description for MIPS32 model 74k.
;; Contributed by MIPS Technologies and CodeSourcery.
;;
;; Reference:
;;   "MIPS32 74K Microarchitecure Specification Rev. 01.02 Jun 15, 2006"
;;   "MIPS32 74Kf Processor Core Datasheet Jun 2, 2006"
;;
;; Copyright (C) 2007 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
 
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
;; License for more details.
 
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3.  If not see
;; .
 
(define_automaton "r74k_mdu_pipe, r74k_alu_pipe, r74k_agen_pipe, r74k_fpu")
(define_cpu_unit "r74k_mul" "r74k_mdu_pipe")
(define_cpu_unit "r74k_alu" "r74k_alu_pipe")
(define_cpu_unit "r74k_agen" "r74k_agen_pipe")
(define_cpu_unit "r74k_fpu_arith" "r74k_fpu")
(define_cpu_unit "r74k_fpu_ldst" "r74k_fpu")
 
;; --------------------------------------------------------------
;; Producers
;; --------------------------------------------------------------
 
;; ALU: Logicals/Arithmetics
;; - Logicals, move (addu/addiu with rt = 0), Set less than,
;;   sign extend - 1 cycle
(define_insn_reservation "r74k_int_logical" 1
  (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
       (eq_attr "type" "logical,move,signext,slt"))
  "r74k_alu")
 
;; - Arithmetics - 2 cycles
(define_insn_reservation "r74k_int_arith" 2
  (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
       (eq_attr "type" "arith,const,shift,clz"))
  "r74k_alu")
 
(define_insn_reservation "r74k_int_nop" 0
  (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
       (eq_attr "type" "nop"))
  "nothing")
 
(define_insn_reservation "r74k_int_cmove" 4
  (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
       (eq_attr "type" "condmove"))
  "r74k_agen*2")
 
;; MDU: fully pipelined multiplier
;; mult - delivers result to hi/lo in 4 cycle (pipelined)
(define_insn_reservation "r74k_int_mult" 4
  (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
       (eq_attr "type" "imul"))
  "r74k_alu+r74k_mul")
 
;; madd, msub - delivers result to hi/lo in 4 cycle (pipelined)
(define_insn_reservation "r74k_int_madd" 4
  (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
       (eq_attr "type" "imadd"))
  "r74k_alu+r74k_mul")
 
;; mul - delivers result to general register in 7 cycles
(define_insn_reservation "r74k_int_mul3" 7
  (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
       (eq_attr "type" "imul3"))
  "r74k_alu+r74k_mul")
 
;; mfhi, mflo, mflhxu - deliver result to gpr in 7 cycles
(define_insn_reservation "r74k_int_mfhilo" 7
  (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
       (eq_attr "type" "mfhilo"))
  "r74k_alu+r74k_mul")
 
;; mthi, mtlo, mtlhx - deliver result to hi/lo, thence madd, handled as bypass
(define_insn_reservation "r74k_int_mthilo" 7
  (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
       (eq_attr "type" "mthilo"))
  "r74k_alu+r74k_mul")
 
;; div - default to 50 cycles for 32bit operands.  Faster for 8 bit,
;; but is tricky to identify.
(define_insn_reservation "r74k_int_div" 50
  (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
       (eq_attr "type" "idiv"))
  "r74k_alu+r74k_mul*50")
 
;; call
(define_insn_reservation "r74k_int_call" 1
  (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
       (eq_attr "type" "call"))
  "r74k_agen")
 
;; branch/jump
(define_insn_reservation "r74k_int_jump" 1
  (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
       (eq_attr "type" "branch,jump"))
  "r74k_agen")
 
;; loads: lb, lbu, lh, lhu, ll, lw, lwl, lwr, lwpc, lwxs
;; prefetch: prefetch, prefetchx
(define_insn_reservation "r74k_int_load" 3
  (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
       (eq_attr "type" "load,prefetch,prefetchx"))
  "r74k_agen")
 
;; stores
(define_insn_reservation "r74k_int_store" 1
  (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
       (and (eq_attr "type" "store")
            (eq_attr "mode" "!unknown")))
  "r74k_agen")
 
 
;; Unknowns - Currently these include blockage, consttable and alignment
;;            rtls.  They do not really affect scheduling latency, (blockage
;;            affects scheduling via log links, but not used here).
;;
(define_insn_reservation "r74k_unknown" 1
  (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
       (eq_attr "type" "unknown"))
  "r74k_alu")
 
(define_insn_reservation "r74k_multi" 10
  (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
       (eq_attr "type" "multi"))
  "(r74k_alu+r74k_agen)*10")
 
;; --------------------------------------------------------------
;; Bypass to Consumer
;; --------------------------------------------------------------
 
;; load->next use :  3 cycles (Default)
;; load->load base:  4 cycles
;; load->store base: 4 cycles
(define_bypass 4 "r74k_int_load" "r74k_int_load")
(define_bypass 4 "r74k_int_load" "r74k_int_store" "!store_data_bypass_p")
 
;; logical/move/slt/signext->next use :  1 cycles (Default)
;; logical/move/slt/signext->load base:  2 cycles
;; logical/move/slt/signext->store base: 2 cycles
(define_bypass 2 "r74k_int_logical" "r74k_int_load")
(define_bypass 2 "r74k_int_logical" "r74k_int_store" "!store_data_bypass_p")
 
;; arith->next use :  2 cycles (Default)
;; arith->load base:  3 cycles
;; arith->store base: 3 cycles
(define_bypass 3 "r74k_int_arith" "r74k_int_load")
(define_bypass 3 "r74k_int_arith" "r74k_int_store" "!store_data_bypass_p")
 
;; cmove->next use :  4 cycles (Default)
;; cmove->load base:  5 cycles
;; cmove->store base: 5 cycles
(define_bypass 5 "r74k_int_cmove"  "r74k_int_load")
(define_bypass 5 "r74k_int_cmove"  "r74k_int_store" "!store_data_bypass_p")
 
;; mult/madd/msub->int_mfhilo  : 4 cycles (default)
;; mult->madd/msub             : 1 cycles
;; madd/msub->madd/msub        : 1 cycles
(define_bypass 1 "r74k_int_mult,r74k_int_mul3" "r74k_int_madd"
  "mips_linked_madd_p")
(define_bypass 1 "r74k_int_madd" "r74k_int_madd"
  "mips_linked_madd_p")
 
;; --------------------------------------------------------------
;; Floating Point Instructions
;; --------------------------------------------------------------
 
;; 74Kf FPU runs at 1:1 or 2:1 core/FPU clock ratio.
 
;; fadd, fabs, fneg,
(define_insn_reservation "r74kf1_1_fadd" 4
  (and (eq_attr "cpu" "74kf1_1")
       (eq_attr "type" "fadd,fabs,fneg"))
  "r74k_fpu_arith")
 
(define_insn_reservation "r74kf2_1_fadd" 8
  (and (eq_attr "cpu" "74kf2_1")
       (eq_attr "type" "fadd,fabs,fneg"))
  "r74k_fpu_arith*2")
 
(define_insn_reservation "r74kf3_2_fadd" 6
  (and (eq_attr "cpu" "74kf3_2")
       (eq_attr "type" "fadd,fabs,fneg"))
  "r74k_fpu_arith")
 
;; fmove, fcmove
(define_insn_reservation "r74kf1_1_fmove" 4
  (and (eq_attr "cpu" "74kf1_1")
       (eq_attr "type" "fmove"))
  "r74k_fpu_arith")
 
(define_insn_reservation "r74kf2_1_fmove" 8
  (and (eq_attr "cpu" "74kf2_1")
       (eq_attr "type" "fmove"))
  "r74k_fpu_arith*2")
 
(define_insn_reservation "r74kf3_2_fmove" 6
  (and (eq_attr "cpu" "74kf3_2")
       (eq_attr "type" "fmove"))
  "r74k_fpu_arith")
 
;; fload
(define_insn_reservation "r74kf1_1_fload" 4
  (and (eq_attr "cpu" "74kf1_1")
       (eq_attr "type" "fpload,fpidxload"))
  "r74k_agen+r74k_fpu_ldst")
 
(define_insn_reservation "r74kf2_1_fload" 8
  (and (eq_attr "cpu" "74kf2_1")
       (eq_attr "type" "fpload,fpidxload"))
  "r74k_agen+(r74k_fpu_ldst*2)")
 
(define_insn_reservation "r74kf3_2_fload" 6
  (and (eq_attr "cpu" "74kf3_2")
       (eq_attr "type" "fpload,fpidxload"))
  "r74k_agen+r74k_fpu_ldst")
 
;; fstore
(define_insn_reservation "r74kf1_1_fstore" 1
  (and (eq_attr "cpu" "74kf1_1")
       (eq_attr "type" "fpstore,fpidxstore"))
  "r74k_agen+r74k_fpu_ldst")
 
(define_insn_reservation "r74kf2_1_fstore" 2
  (and (eq_attr "cpu" "74kf2_1")
       (eq_attr "type" "fpstore,fpidxstore"))
  "r74k_agen+(r74k_fpu_ldst*2)")
 
(define_insn_reservation "r74kf3_2_fstore" 1
  (and (eq_attr "cpu" "74kf3_2")
       (eq_attr "type" "fpstore,fpidxstore"))
  "r74k_agen+r74k_fpu_ldst")
 
;; fmul, fmadd
(define_insn_reservation "r74kf1_1_fmul_sf" 4
  (and (eq_attr "cpu" "74kf1_1")
       (and (eq_attr "type" "fmul,fmadd")
            (eq_attr "mode" "SF")))
  "r74k_fpu_arith")
 
(define_insn_reservation "r74kf2_1_fmul_sf" 8
  (and (eq_attr "cpu" "74kf2_1")
       (and (eq_attr "type" "fmul,fmadd")
            (eq_attr "mode" "SF")))
  "r74k_fpu_arith*2")
 
(define_insn_reservation "r74kf3_2_fmul_sf" 6
  (and (eq_attr "cpu" "74kf3_2")
       (and (eq_attr "type" "fmul,fmadd")
            (eq_attr "mode" "SF")))
  "r74k_fpu_arith")
 
(define_insn_reservation "r74kf1_1_fmul_df" 5
  (and (eq_attr "cpu" "74kf1_1")
       (and (eq_attr "type" "fmul,fmadd")
            (eq_attr "mode" "DF")))
  "r74k_fpu_arith*2")
 
(define_insn_reservation "r74kf2_1_fmul_df" 10
  (and (eq_attr "cpu" "74kf2_1")
       (and (eq_attr "type" "fmul,fmadd")
            (eq_attr "mode" "DF")))
  "r74k_fpu_arith*4")
 
(define_insn_reservation "r74kf3_2_fmul_df" 7
  (and (eq_attr "cpu" "74kf3_2")
       (and (eq_attr "type" "fmul,fmadd")
            (eq_attr "mode" "DF")))
  "r74k_fpu_arith*2")
 
;; fdiv, fsqrt
(define_insn_reservation "r74kf1_1_fdiv_sf" 17
  (and (eq_attr "cpu" "74kf1_1")
       (and (eq_attr "type" "fdiv,fsqrt")
            (eq_attr "mode" "SF")))
  "r74k_fpu_arith*14")
 
(define_insn_reservation "r74kf2_1_fdiv_sf" 34
  (and (eq_attr "cpu" "74kf2_1")
       (and (eq_attr "type" "fdiv,fsqrt")
            (eq_attr "mode" "SF")))
  "r74k_fpu_arith*28")
 
(define_insn_reservation "r74kf3_2_fdiv_sf" 25
  (and (eq_attr "cpu" "74kf3_2")
       (and (eq_attr "type" "fdiv,fsqrt")
            (eq_attr "mode" "SF")))
  "r74k_fpu_arith*14")
 
(define_insn_reservation "r74kf1_1_fdiv_df" 32
  (and (eq_attr "cpu" "74kf1_1")
       (and (eq_attr "type" "fdiv,fsqrt")
            (eq_attr "mode" "DF")))
  "r74k_fpu_arith*29")
 
(define_insn_reservation "r74kf2_1_fdiv_df" 64
  (and (eq_attr "cpu" "74kf2_1")
       (and (eq_attr "type" "fdiv,fsqrt")
            (eq_attr "mode" "DF")))
  "r74k_fpu_arith*58")
 
(define_insn_reservation "r74kf3_2_fdiv_df" 48
  (and (eq_attr "cpu" "74kf3_2")
       (and (eq_attr "type" "fdiv,fsqrt")
            (eq_attr "mode" "DF")))
  "r74k_fpu_arith*29")
 
;; frsqrt
(define_insn_reservation "r74kf1_1_frsqrt_sf" 17
  (and (eq_attr "cpu" "74kf1_1")
       (and (eq_attr "type" "frsqrt")
            (eq_attr "mode" "SF")))
  "r74k_fpu_arith*14")
 
(define_insn_reservation "r74kf2_1_frsqrt_sf" 34
  (and (eq_attr "cpu" "74kf2_1")
       (and (eq_attr "type" "frsqrt")
            (eq_attr "mode" "SF")))
  "r74k_fpu_arith*28")
 
(define_insn_reservation "r74kf3_2_frsqrt_sf" 25
  (and (eq_attr "cpu" "74kf3_2")
       (and (eq_attr "type" "frsqrt")
            (eq_attr "mode" "SF")))
  "r74k_fpu_arith*14")
 
(define_insn_reservation "r74kf1_1_frsqrt_df" 36
  (and (eq_attr "cpu" "74kf1_1")
       (and (eq_attr "type" "frsqrt")
            (eq_attr "mode" "DF")))
  "r74k_fpu_arith*31")
 
(define_insn_reservation "r74kf2_1_frsqrt_df" 72
  (and (eq_attr "cpu" "74kf2_1")
       (and (eq_attr "type" "frsqrt")
            (eq_attr "mode" "DF")))
  "r74k_fpu_arith*62")
 
(define_insn_reservation "r74kf3_2_frsqrt_df" 54
  (and (eq_attr "cpu" "74kf3_2")
       (and (eq_attr "type" "frsqrt")
            (eq_attr "mode" "DF")))
  "r74k_fpu_arith*31")
 
;; fcmp
(define_insn_reservation "r74kf1_1_fcmp" 4
  (and (eq_attr "cpu" "74kf1_1")
       (eq_attr "type" "fcmp"))
  "r74k_fpu_arith")
 
(define_insn_reservation "r74kf2_1_fcmp" 8
  (and (eq_attr "cpu" "74kf2_1")
       (eq_attr "type" "fcmp"))
  "r74k_fpu_arith*2")
 
(define_insn_reservation "r74kf3_2_fcmp" 6
  (and (eq_attr "cpu" "74kf3_2")
       (eq_attr "type" "fcmp"))
  "r74k_fpu_arith")
 
;; fcvt
(define_insn_reservation "r74kf1_1_fcvt" 4
  (and (eq_attr "cpu" "74kf1_1")
       (eq_attr "type" "fcvt"))
  "r74k_fpu_arith")
 
(define_insn_reservation "r74kf2_1_fcvt" 8
  (and (eq_attr "cpu" "74kf2_1")
       (eq_attr "type" "fcvt"))
  "r74k_fpu_arith*2")
 
(define_insn_reservation "r74kf3_2_fcvt" 6
  (and (eq_attr "cpu" "74kf3_2")
       (eq_attr "type" "fcvt"))
  "r74k_fpu_arith")
 
;; fxfer (MTC1, DMTC1: latency is 4) (MFC1, DMFC1: latency is 1)
(define_insn_reservation "r74kf1_1_fxfer_to_c1" 4
  (and (eq_attr "cpu" "74kf1_1")
       (eq_attr "type" "mtc"))
  "r74k_fpu_arith")
 
(define_insn_reservation "r74kf2_1_fxfer_to_c1" 8
  (and (eq_attr "cpu" "74kf2_1")
       (eq_attr "type" "mtc"))
  "r74k_fpu_arith*2")
 
(define_insn_reservation "r74kf3_2_fxfer_to_c1" 6
  (and (eq_attr "cpu" "74kf3_2")
       (eq_attr "type" "mtc"))
  "r74k_fpu_arith")
 
(define_insn_reservation "r74kf1_1_fxfer_from_c1" 1
  (and (eq_attr "cpu" "74kf1_1")
       (eq_attr "type" "mfc"))
  "r74k_fpu_arith")
 
(define_insn_reservation "r74kf2_1_fxfer_from_c1" 2
  (and (eq_attr "cpu" "74kf2_1")
       (eq_attr "type" "mfc"))
  "r74k_fpu_arith*2")
 
(define_insn_reservation "r74kf3_2_fxfer_from_c1" 1
  (and (eq_attr "cpu" "74kf3_2")
       (eq_attr "type" "mfc"))
  "r74k_fpu_arith")

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[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [config/] [mips/] [74k.md] - Blame information for rev 756

Line No.	Rev	Author	Line
1	709	jeremybenn	`;; DFA-based pipeline description for MIPS32 model 74k.`
2			`;; Contributed by MIPS Technologies and CodeSourcery.`
3			`;;`
4			`;; Reference:`
5			`;; "MIPS32 74K Microarchitecure Specification Rev. 01.02 Jun 15, 2006"`
6			`;; "MIPS32 74Kf Processor Core Datasheet Jun 2, 2006"`
7			`;;`
8			`;; Copyright (C) 2007 Free Software Foundation, Inc.`
9			`;;`
10			`;; This file is part of GCC.`
11			`;;`
12			`;; GCC is free software; you can redistribute it and/or modify it`
13			`;; under the terms of the GNU General Public License as published`
14			`;; by the Free Software Foundation; either version 3, or (at your`
15			`;; option) any later version.`
16
17			`;; GCC is distributed in the hope that it will be useful, but WITHOUT`
18			`;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY`
19			`;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public`
20			`;; License for more details.`
21
22			`;; You should have received a copy of the GNU General Public License`
23			`;; along with GCC; see the file COPYING3. If not see`
24			`;; .`
25
26			`(define_automaton "r74k_mdu_pipe, r74k_alu_pipe, r74k_agen_pipe, r74k_fpu")`
27			`(define_cpu_unit "r74k_mul" "r74k_mdu_pipe")`
28			`(define_cpu_unit "r74k_alu" "r74k_alu_pipe")`
29			`(define_cpu_unit "r74k_agen" "r74k_agen_pipe")`
30			`(define_cpu_unit "r74k_fpu_arith" "r74k_fpu")`
31			`(define_cpu_unit "r74k_fpu_ldst" "r74k_fpu")`
32
33			`;; --------------------------------------------------------------`
34			`;; Producers`
35			`;; --------------------------------------------------------------`
36
37			`;; ALU: Logicals/Arithmetics`
38			`;; - Logicals, move (addu/addiu with rt = 0), Set less than,`
39			`;; sign extend - 1 cycle`
40			`(define_insn_reservation "r74k_int_logical" 1`
41			`(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")`
42			`(eq_attr "type" "logical,move,signext,slt"))`
43			`"r74k_alu")`
44
45			`;; - Arithmetics - 2 cycles`
46			`(define_insn_reservation "r74k_int_arith" 2`
47			`(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")`
48			`(eq_attr "type" "arith,const,shift,clz"))`
49			`"r74k_alu")`
50
51			`(define_insn_reservation "r74k_int_nop" 0`
52			`(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")`
53			`(eq_attr "type" "nop"))`
54			`"nothing")`
55
56			`(define_insn_reservation "r74k_int_cmove" 4`
57			`(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")`
58			`(eq_attr "type" "condmove"))`
59			`"r74k_agen*2")`
60
61			`;; MDU: fully pipelined multiplier`
62			`;; mult - delivers result to hi/lo in 4 cycle (pipelined)`
63			`(define_insn_reservation "r74k_int_mult" 4`
64			`(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")`
65			`(eq_attr "type" "imul"))`
66			`"r74k_alu+r74k_mul")`
67
68			`;; madd, msub - delivers result to hi/lo in 4 cycle (pipelined)`
69			`(define_insn_reservation "r74k_int_madd" 4`
70			`(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")`
71			`(eq_attr "type" "imadd"))`
72			`"r74k_alu+r74k_mul")`
73
74			`;; mul - delivers result to general register in 7 cycles`
75			`(define_insn_reservation "r74k_int_mul3" 7`
76			`(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")`
77			`(eq_attr "type" "imul3"))`
78			`"r74k_alu+r74k_mul")`
79
80			`;; mfhi, mflo, mflhxu - deliver result to gpr in 7 cycles`
81			`(define_insn_reservation "r74k_int_mfhilo" 7`
82			`(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")`
83			`(eq_attr "type" "mfhilo"))`
84			`"r74k_alu+r74k_mul")`
85
86			`;; mthi, mtlo, mtlhx - deliver result to hi/lo, thence madd, handled as bypass`
87			`(define_insn_reservation "r74k_int_mthilo" 7`
88			`(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")`
89			`(eq_attr "type" "mthilo"))`
90			`"r74k_alu+r74k_mul")`
91
92			`;; div - default to 50 cycles for 32bit operands. Faster for 8 bit,`
93			`;; but is tricky to identify.`
94			`(define_insn_reservation "r74k_int_div" 50`
95			`(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")`
96			`(eq_attr "type" "idiv"))`
97			`"r74k_alu+r74k_mul*50")`
98
99			`;; call`
100			`(define_insn_reservation "r74k_int_call" 1`
101			`(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")`
102			`(eq_attr "type" "call"))`
103			`"r74k_agen")`
104
105			`;; branch/jump`
106			`(define_insn_reservation "r74k_int_jump" 1`
107			`(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")`
108			`(eq_attr "type" "branch,jump"))`
109			`"r74k_agen")`
110
111			`;; loads: lb, lbu, lh, lhu, ll, lw, lwl, lwr, lwpc, lwxs`
112			`;; prefetch: prefetch, prefetchx`
113			`(define_insn_reservation "r74k_int_load" 3`
114			`(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")`
115			`(eq_attr "type" "load,prefetch,prefetchx"))`
116			`"r74k_agen")`
117
118			`;; stores`
119			`(define_insn_reservation "r74k_int_store" 1`
120			`(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")`
121			`(and (eq_attr "type" "store")`
122			`(eq_attr "mode" "!unknown")))`
123			`"r74k_agen")`
124
125
126			`;; Unknowns - Currently these include blockage, consttable and alignment`
127			`;; rtls. They do not really affect scheduling latency, (blockage`
128			`;; affects scheduling via log links, but not used here).`
129			`;;`
130			`(define_insn_reservation "r74k_unknown" 1`
131			`(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")`
132			`(eq_attr "type" "unknown"))`
133			`"r74k_alu")`
134
135			`(define_insn_reservation "r74k_multi" 10`
136			`(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")`
137			`(eq_attr "type" "multi"))`
138			`"(r74k_alu+r74k_agen)*10")`
139
140			`;; --------------------------------------------------------------`
141			`;; Bypass to Consumer`
142			`;; --------------------------------------------------------------`
143
144			`;; load->next use : 3 cycles (Default)`
145			`;; load->load base: 4 cycles`
146			`;; load->store base: 4 cycles`
147			`(define_bypass 4 "r74k_int_load" "r74k_int_load")`
148			`(define_bypass 4 "r74k_int_load" "r74k_int_store" "!store_data_bypass_p")`
149
150			`;; logical/move/slt/signext->next use : 1 cycles (Default)`
151			`;; logical/move/slt/signext->load base: 2 cycles`
152			`;; logical/move/slt/signext->store base: 2 cycles`
153			`(define_bypass 2 "r74k_int_logical" "r74k_int_load")`
154			`(define_bypass 2 "r74k_int_logical" "r74k_int_store" "!store_data_bypass_p")`
155
156			`;; arith->next use : 2 cycles (Default)`
157			`;; arith->load base: 3 cycles`
158			`;; arith->store base: 3 cycles`
159			`(define_bypass 3 "r74k_int_arith" "r74k_int_load")`
160			`(define_bypass 3 "r74k_int_arith" "r74k_int_store" "!store_data_bypass_p")`
161
162			`;; cmove->next use : 4 cycles (Default)`
163			`;; cmove->load base: 5 cycles`
164			`;; cmove->store base: 5 cycles`
165			`(define_bypass 5 "r74k_int_cmove" "r74k_int_load")`
166			`(define_bypass 5 "r74k_int_cmove" "r74k_int_store" "!store_data_bypass_p")`
167
168			`;; mult/madd/msub->int_mfhilo : 4 cycles (default)`
169			`;; mult->madd/msub : 1 cycles`
170			`;; madd/msub->madd/msub : 1 cycles`
171			`(define_bypass 1 "r74k_int_mult,r74k_int_mul3" "r74k_int_madd"`
172			`"mips_linked_madd_p")`
173			`(define_bypass 1 "r74k_int_madd" "r74k_int_madd"`
174			`"mips_linked_madd_p")`
175
176			`;; --------------------------------------------------------------`
177			`;; Floating Point Instructions`
178			`;; --------------------------------------------------------------`
179
180			`;; 74Kf FPU runs at 1:1 or 2:1 core/FPU clock ratio.`
181
182			`;; fadd, fabs, fneg,`
183			`(define_insn_reservation "r74kf1_1_fadd" 4`
184			`(and (eq_attr "cpu" "74kf1_1")`
185			`(eq_attr "type" "fadd,fabs,fneg"))`
186			`"r74k_fpu_arith")`
187
188			`(define_insn_reservation "r74kf2_1_fadd" 8`
189			`(and (eq_attr "cpu" "74kf2_1")`
190			`(eq_attr "type" "fadd,fabs,fneg"))`
191			`"r74k_fpu_arith*2")`
192
193			`(define_insn_reservation "r74kf3_2_fadd" 6`
194			`(and (eq_attr "cpu" "74kf3_2")`
195			`(eq_attr "type" "fadd,fabs,fneg"))`
196			`"r74k_fpu_arith")`
197
198			`;; fmove, fcmove`
199			`(define_insn_reservation "r74kf1_1_fmove" 4`
200			`(and (eq_attr "cpu" "74kf1_1")`
201			`(eq_attr "type" "fmove"))`
202			`"r74k_fpu_arith")`
203
204			`(define_insn_reservation "r74kf2_1_fmove" 8`
205			`(and (eq_attr "cpu" "74kf2_1")`
206			`(eq_attr "type" "fmove"))`
207			`"r74k_fpu_arith*2")`
208
209			`(define_insn_reservation "r74kf3_2_fmove" 6`
210			`(and (eq_attr "cpu" "74kf3_2")`
211			`(eq_attr "type" "fmove"))`
212			`"r74k_fpu_arith")`
213
214			`;; fload`
215			`(define_insn_reservation "r74kf1_1_fload" 4`
216			`(and (eq_attr "cpu" "74kf1_1")`
217			`(eq_attr "type" "fpload,fpidxload"))`
218			`"r74k_agen+r74k_fpu_ldst")`
219
220			`(define_insn_reservation "r74kf2_1_fload" 8`
221			`(and (eq_attr "cpu" "74kf2_1")`
222			`(eq_attr "type" "fpload,fpidxload"))`
223			`"r74k_agen+(r74k_fpu_ldst*2)")`
224
225			`(define_insn_reservation "r74kf3_2_fload" 6`
226			`(and (eq_attr "cpu" "74kf3_2")`
227			`(eq_attr "type" "fpload,fpidxload"))`
228			`"r74k_agen+r74k_fpu_ldst")`
229
230			`;; fstore`
231			`(define_insn_reservation "r74kf1_1_fstore" 1`
232			`(and (eq_attr "cpu" "74kf1_1")`
233			`(eq_attr "type" "fpstore,fpidxstore"))`
234			`"r74k_agen+r74k_fpu_ldst")`
235
236			`(define_insn_reservation "r74kf2_1_fstore" 2`
237			`(and (eq_attr "cpu" "74kf2_1")`
238			`(eq_attr "type" "fpstore,fpidxstore"))`
239			`"r74k_agen+(r74k_fpu_ldst*2)")`
240
241			`(define_insn_reservation "r74kf3_2_fstore" 1`
242			`(and (eq_attr "cpu" "74kf3_2")`
243			`(eq_attr "type" "fpstore,fpidxstore"))`
244			`"r74k_agen+r74k_fpu_ldst")`
245
246			`;; fmul, fmadd`
247			`(define_insn_reservation "r74kf1_1_fmul_sf" 4`
248			`(and (eq_attr "cpu" "74kf1_1")`
249			`(and (eq_attr "type" "fmul,fmadd")`
250			`(eq_attr "mode" "SF")))`
251			`"r74k_fpu_arith")`
252
253			`(define_insn_reservation "r74kf2_1_fmul_sf" 8`
254			`(and (eq_attr "cpu" "74kf2_1")`
255			`(and (eq_attr "type" "fmul,fmadd")`
256			`(eq_attr "mode" "SF")))`
257			`"r74k_fpu_arith*2")`
258
259			`(define_insn_reservation "r74kf3_2_fmul_sf" 6`
260			`(and (eq_attr "cpu" "74kf3_2")`
261			`(and (eq_attr "type" "fmul,fmadd")`
262			`(eq_attr "mode" "SF")))`
263			`"r74k_fpu_arith")`
264
265			`(define_insn_reservation "r74kf1_1_fmul_df" 5`
266			`(and (eq_attr "cpu" "74kf1_1")`
267			`(and (eq_attr "type" "fmul,fmadd")`
268			`(eq_attr "mode" "DF")))`
269			`"r74k_fpu_arith*2")`
270
271			`(define_insn_reservation "r74kf2_1_fmul_df" 10`
272			`(and (eq_attr "cpu" "74kf2_1")`
273			`(and (eq_attr "type" "fmul,fmadd")`
274			`(eq_attr "mode" "DF")))`
275			`"r74k_fpu_arith*4")`
276
277			`(define_insn_reservation "r74kf3_2_fmul_df" 7`
278			`(and (eq_attr "cpu" "74kf3_2")`
279			`(and (eq_attr "type" "fmul,fmadd")`
280			`(eq_attr "mode" "DF")))`
281			`"r74k_fpu_arith*2")`
282
283			`;; fdiv, fsqrt`
284			`(define_insn_reservation "r74kf1_1_fdiv_sf" 17`
285			`(and (eq_attr "cpu" "74kf1_1")`
286			`(and (eq_attr "type" "fdiv,fsqrt")`
287			`(eq_attr "mode" "SF")))`
288			`"r74k_fpu_arith*14")`
289
290			`(define_insn_reservation "r74kf2_1_fdiv_sf" 34`
291			`(and (eq_attr "cpu" "74kf2_1")`
292			`(and (eq_attr "type" "fdiv,fsqrt")`
293			`(eq_attr "mode" "SF")))`
294			`"r74k_fpu_arith*28")`
295
296			`(define_insn_reservation "r74kf3_2_fdiv_sf" 25`
297			`(and (eq_attr "cpu" "74kf3_2")`
298			`(and (eq_attr "type" "fdiv,fsqrt")`
299			`(eq_attr "mode" "SF")))`
300			`"r74k_fpu_arith*14")`
301
302			`(define_insn_reservation "r74kf1_1_fdiv_df" 32`
303			`(and (eq_attr "cpu" "74kf1_1")`
304			`(and (eq_attr "type" "fdiv,fsqrt")`
305			`(eq_attr "mode" "DF")))`
306			`"r74k_fpu_arith*29")`
307
308			`(define_insn_reservation "r74kf2_1_fdiv_df" 64`
309			`(and (eq_attr "cpu" "74kf2_1")`
310			`(and (eq_attr "type" "fdiv,fsqrt")`
311			`(eq_attr "mode" "DF")))`
312			`"r74k_fpu_arith*58")`
313
314			`(define_insn_reservation "r74kf3_2_fdiv_df" 48`
315			`(and (eq_attr "cpu" "74kf3_2")`
316			`(and (eq_attr "type" "fdiv,fsqrt")`
317			`(eq_attr "mode" "DF")))`
318			`"r74k_fpu_arith*29")`
319
320			`;; frsqrt`
321			`(define_insn_reservation "r74kf1_1_frsqrt_sf" 17`
322			`(and (eq_attr "cpu" "74kf1_1")`
323			`(and (eq_attr "type" "frsqrt")`
324			`(eq_attr "mode" "SF")))`
325			`"r74k_fpu_arith*14")`
326
327			`(define_insn_reservation "r74kf2_1_frsqrt_sf" 34`
328			`(and (eq_attr "cpu" "74kf2_1")`
329			`(and (eq_attr "type" "frsqrt")`
330			`(eq_attr "mode" "SF")))`
331			`"r74k_fpu_arith*28")`
332
333			`(define_insn_reservation "r74kf3_2_frsqrt_sf" 25`
334			`(and (eq_attr "cpu" "74kf3_2")`
335			`(and (eq_attr "type" "frsqrt")`
336			`(eq_attr "mode" "SF")))`
337			`"r74k_fpu_arith*14")`
338
339			`(define_insn_reservation "r74kf1_1_frsqrt_df" 36`
340			`(and (eq_attr "cpu" "74kf1_1")`
341			`(and (eq_attr "type" "frsqrt")`
342			`(eq_attr "mode" "DF")))`
343			`"r74k_fpu_arith*31")`
344
345			`(define_insn_reservation "r74kf2_1_frsqrt_df" 72`
346			`(and (eq_attr "cpu" "74kf2_1")`
347			`(and (eq_attr "type" "frsqrt")`
348			`(eq_attr "mode" "DF")))`
349			`"r74k_fpu_arith*62")`
350
351			`(define_insn_reservation "r74kf3_2_frsqrt_df" 54`
352			`(and (eq_attr "cpu" "74kf3_2")`
353			`(and (eq_attr "type" "frsqrt")`
354			`(eq_attr "mode" "DF")))`
355			`"r74k_fpu_arith*31")`
356
357			`;; fcmp`
358			`(define_insn_reservation "r74kf1_1_fcmp" 4`
359			`(and (eq_attr "cpu" "74kf1_1")`
360			`(eq_attr "type" "fcmp"))`
361			`"r74k_fpu_arith")`
362
363			`(define_insn_reservation "r74kf2_1_fcmp" 8`
364			`(and (eq_attr "cpu" "74kf2_1")`
365			`(eq_attr "type" "fcmp"))`
366			`"r74k_fpu_arith*2")`
367
368			`(define_insn_reservation "r74kf3_2_fcmp" 6`
369			`(and (eq_attr "cpu" "74kf3_2")`
370			`(eq_attr "type" "fcmp"))`
371			`"r74k_fpu_arith")`
372
373			`;; fcvt`
374			`(define_insn_reservation "r74kf1_1_fcvt" 4`
375			`(and (eq_attr "cpu" "74kf1_1")`
376			`(eq_attr "type" "fcvt"))`
377			`"r74k_fpu_arith")`
378
379			`(define_insn_reservation "r74kf2_1_fcvt" 8`
380			`(and (eq_attr "cpu" "74kf2_1")`
381			`(eq_attr "type" "fcvt"))`
382			`"r74k_fpu_arith*2")`
383
384			`(define_insn_reservation "r74kf3_2_fcvt" 6`
385			`(and (eq_attr "cpu" "74kf3_2")`
386			`(eq_attr "type" "fcvt"))`
387			`"r74k_fpu_arith")`
388
389			`;; fxfer (MTC1, DMTC1: latency is 4) (MFC1, DMFC1: latency is 1)`
390			`(define_insn_reservation "r74kf1_1_fxfer_to_c1" 4`
391			`(and (eq_attr "cpu" "74kf1_1")`
392			`(eq_attr "type" "mtc"))`
393			`"r74k_fpu_arith")`
394
395			`(define_insn_reservation "r74kf2_1_fxfer_to_c1" 8`
396			`(and (eq_attr "cpu" "74kf2_1")`
397			`(eq_attr "type" "mtc"))`
398			`"r74k_fpu_arith*2")`
399
400			`(define_insn_reservation "r74kf3_2_fxfer_to_c1" 6`
401			`(and (eq_attr "cpu" "74kf3_2")`
402			`(eq_attr "type" "mtc"))`
403			`"r74k_fpu_arith")`
404
405			`(define_insn_reservation "r74kf1_1_fxfer_from_c1" 1`
406			`(and (eq_attr "cpu" "74kf1_1")`
407			`(eq_attr "type" "mfc"))`
408			`"r74k_fpu_arith")`
409
410			`(define_insn_reservation "r74kf2_1_fxfer_from_c1" 2`
411			`(and (eq_attr "cpu" "74kf2_1")`
412			`(eq_attr "type" "mfc"))`
413			`"r74k_fpu_arith*2")`
414
415			`(define_insn_reservation "r74kf3_2_fxfer_from_c1" 1`
416			`(and (eq_attr "cpu" "74kf3_2")`
417			`(eq_attr "type" "mfc"))`
418			`"r74k_fpu_arith")`