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jeremybenn |
;; Pipeline model for Loongson-3A cores.
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;; Copyright (C) 2011 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;;
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; .
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;; Uncomment the following line to output automata for debugging.
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;; (automata_option "v")
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;; Automaton for integer instructions.
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(define_automaton "ls3a_a_alu")
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;; Automaton for floating-point instructions.
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(define_automaton "ls3a_a_falu")
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;; Automaton for memory operations.
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(define_automaton "ls3a_a_mem")
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;; Describe the resources.
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(define_cpu_unit "ls3a_alu1" "ls3a_a_alu")
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(define_cpu_unit "ls3a_alu2" "ls3a_a_alu")
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(define_cpu_unit "ls3a_mem" "ls3a_a_mem")
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(define_cpu_unit "ls3a_falu1" "ls3a_a_falu")
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(define_cpu_unit "ls3a_falu2" "ls3a_a_falu")
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;; Describe instruction reservations.
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(define_insn_reservation "ls3a_arith" 1
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(and (eq_attr "cpu" "loongson_3a")
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(eq_attr "type" "arith,clz,const,logical,
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move,nop,shift,signext,slt"))
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"ls3a_alu1 | ls3a_alu2")
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(define_insn_reservation "ls3a_branch" 1
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(and (eq_attr "cpu" "loongson_3a")
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(eq_attr "type" "branch,jump,call,condmove,trap"))
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"ls3a_alu1")
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(define_insn_reservation "ls3a_mfhilo" 1
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(and (eq_attr "cpu" "loongson_3a")
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(eq_attr "type" "mfhilo,mthilo"))
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"ls3a_alu2")
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;; Operation imul3nc is fully pipelined.
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(define_insn_reservation "ls3a_imul3nc" 5
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(and (eq_attr "cpu" "loongson_3a")
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(eq_attr "type" "imul3nc"))
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"ls3a_alu2")
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(define_insn_reservation "ls3a_imul" 7
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(and (eq_attr "cpu" "loongson_3a")
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(eq_attr "type" "imul,imadd"))
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"ls3a_alu2 * 7")
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(define_insn_reservation "ls3a_idiv_si" 12
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(and (eq_attr "cpu" "loongson_3a")
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(and (eq_attr "type" "idiv")
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(eq_attr "mode" "SI")))
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"ls3a_alu2 * 12")
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(define_insn_reservation "ls3a_idiv_di" 25
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(and (eq_attr "cpu" "loongson_3a")
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(and (eq_attr "type" "idiv")
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(eq_attr "mode" "DI")))
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"ls3a_alu2 * 25")
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(define_insn_reservation "ls3a_load" 3
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(and (eq_attr "cpu" "loongson_3a")
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(eq_attr "type" "load"))
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"ls3a_mem")
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(define_insn_reservation "ls3a_fpload" 4
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(and (eq_attr "cpu" "loongson_3a")
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(eq_attr "type" "load,mfc,mtc"))
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"ls3a_mem")
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(define_insn_reservation "ls3a_prefetch" 0
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(and (eq_attr "cpu" "loongson_3a")
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(eq_attr "type" "prefetch,prefetchx"))
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"ls3a_mem")
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(define_insn_reservation "ls3a_store" 0
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(and (eq_attr "cpu" "loongson_3a")
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(eq_attr "type" "store,fpstore,fpidxstore"))
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"ls3a_mem")
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;; All the fp operations can be executed in FALU1. Only fp add,
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;; sub, mul, madd can be executed in FALU2. Try FALU2 firstly.
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(define_insn_reservation "ls3a_fadd" 6
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(and (eq_attr "cpu" "loongson_3a")
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(eq_attr "type" "fadd,fmul,fmadd"))
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"ls3a_falu2 | ls3a_falu1")
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(define_insn_reservation "ls3a_fcmp" 2
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(and (eq_attr "cpu" "loongson_3a")
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(eq_attr "type" "fabs,fcmp,fmove,fneg"))
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"ls3a_falu1")
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(define_insn_reservation "ls3a_fcvt" 4
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(and (eq_attr "cpu" "loongson_3a")
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(eq_attr "type" "fcvt"))
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"ls3a_falu1")
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(define_insn_reservation "ls3a_fdiv_sf" 12
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(and (eq_attr "cpu" "loongson_3a")
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(and (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt")
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(eq_attr "mode" "SF")))
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"ls3a_falu1 * 12")
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(define_insn_reservation "ls3a_fdiv_df" 19
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(and (eq_attr "cpu" "loongson_3a")
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(and (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt")
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(eq_attr "mode" "DF")))
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"ls3a_falu1 * 19")
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;; Force single-dispatch for unknown or multi.
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(define_insn_reservation "ls3a_unknown" 1
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(and (eq_attr "cpu" "loongson_3a")
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(eq_attr "type" "unknown,multi"))
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"ls3a_alu1 + ls3a_alu2 + ls3a_falu1 + ls3a_falu2 + ls3a_mem")
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;; End of DFA-based pipeline description for loongson_3a
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