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Line No. Rev Author Line
1 709 jeremybenn 
;; Copyright (C) 2007, 2010 Free Software Foundation, Inc.
2 
;;
3 
;; This file is part of GCC.
4 
;;
5 
;; GCC is free software; you can redistribute it and/or modify
6 
;; it under the terms of the GNU General Public License as published by
7 
;; the Free Software Foundation; either version 3, or (at your option)
8 
;; any later version.
9 
;;
10 
;; GCC is distributed in the hope that it will be useful,
11 
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
12 
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13 
;; GNU General Public License for more details.
14 
;;
15 
;; You should have received a copy of the GNU General Public License
16 
;; along with GCC; see the file COPYING3.  If not see
17 
;; .
18 
;;
19 
; MIPS DSP ASE REV 2 Revision 0.02 11/24/2006
20 
 
21 
(define_c_enum "unspec" [
22 
  UNSPEC_ABSQ_S_QB
23 
  UNSPEC_ADDU_PH
24 
  UNSPEC_ADDU_S_PH
25 
  UNSPEC_ADDUH_QB
26 
  UNSPEC_ADDUH_R_QB
27 
  UNSPEC_APPEND
28 
  UNSPEC_BALIGN
29 
  UNSPEC_CMPGDU_EQ_QB
30 
  UNSPEC_CMPGDU_LT_QB
31 
  UNSPEC_CMPGDU_LE_QB
32 
  UNSPEC_DPA_W_PH
33 
  UNSPEC_DPS_W_PH
34 
  UNSPEC_MADD
35 
  UNSPEC_MADDU
36 
  UNSPEC_MSUB
37 
  UNSPEC_MSUBU
38 
  UNSPEC_MUL_PH
39 
  UNSPEC_MUL_S_PH
40 
  UNSPEC_MULQ_RS_W
41 
  UNSPEC_MULQ_S_PH
42 
  UNSPEC_MULQ_S_W
43 
  UNSPEC_MULSA_W_PH
44 
  UNSPEC_MULT
45 
  UNSPEC_MULTU
46 
  UNSPEC_PRECR_QB_PH
47 
  UNSPEC_PRECR_SRA_PH_W
48 
  UNSPEC_PRECR_SRA_R_PH_W
49 
  UNSPEC_PREPEND
50 
  UNSPEC_SHRA_QB
51 
  UNSPEC_SHRA_R_QB
52 
  UNSPEC_SHRL_PH
53 
  UNSPEC_SUBU_PH
54 
  UNSPEC_SUBU_S_PH
55 
  UNSPEC_SUBUH_QB
56 
  UNSPEC_SUBUH_R_QB
57 
  UNSPEC_ADDQH_PH
58 
  UNSPEC_ADDQH_R_PH
59 
  UNSPEC_ADDQH_W
60 
  UNSPEC_ADDQH_R_W
61 
  UNSPEC_SUBQH_PH
62 
  UNSPEC_SUBQH_R_PH
63 
  UNSPEC_SUBQH_W
64 
  UNSPEC_SUBQH_R_W
65 
  UNSPEC_DPAX_W_PH
66 
  UNSPEC_DPSX_W_PH
67 
  UNSPEC_DPAQX_S_W_PH
68 
  UNSPEC_DPAQX_SA_W_PH
69 
  UNSPEC_DPSQX_S_W_PH
70 
  UNSPEC_DPSQX_SA_W_PH
71 
])
72 
 
73 
(define_insn "mips_absq_s_qb"
74 
  [(parallel
75 
    [(set (match_operand:V4QI 0 "register_operand" "=d")
76 
          (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")]
77 
                       UNSPEC_ABSQ_S_QB))
78 
     (set (reg:CCDSP CCDSP_OU_REGNUM)
79 
          (unspec:CCDSP [(match_dup 1)] UNSPEC_ABSQ_S_QB))])]
80 
  "ISA_HAS_DSPR2"
81 
  "absq_s.qb\t%0,%z1"
82 
  [(set_attr "type"     "arith")
83 
   (set_attr "mode"     "SI")])
84 
 
85 
(define_insn "mips_addu_ph"
86 
  [(parallel
87 
    [(set (match_operand:V2HI 0 "register_operand" "=d")
88 
          (plus:V2HI (match_operand:V2HI 1 "reg_or_0_operand" "dYG")
89 
                     (match_operand:V2HI 2 "reg_or_0_operand" "dYG")))
90 
     (set (reg:CCDSP CCDSP_OU_REGNUM)
91 
          (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDU_PH))])]
92 
  "ISA_HAS_DSPR2"
93 
  "addu.ph\t%0,%z1,%z2"
94 
  [(set_attr "type"     "arith")
95 
   (set_attr "mode"     "SI")])
96 
 
97 
(define_insn "mips_addu_s_ph"
98 
  [(parallel
99 
    [(set (match_operand:V2HI 0 "register_operand" "=d")
100 
          (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
101 
                        (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
102 
                       UNSPEC_ADDU_S_PH))
103 
     (set (reg:CCDSP CCDSP_OU_REGNUM)
104 
          (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDU_S_PH))])]
105 
  "ISA_HAS_DSPR2"
106 
  "addu_s.ph\t%0,%z1,%z2"
107 
  [(set_attr "type"     "arith")
108 
   (set_attr "mode"     "SI")])
109 
 
110 
(define_insn "mips_adduh_qb"
111 
  [(set (match_operand:V4QI 0 "register_operand" "=d")
112 
        (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
113 
                      (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
114 
                     UNSPEC_ADDUH_QB))]
115 
  "ISA_HAS_DSPR2"
116 
  "adduh.qb\t%0,%z1,%z2"
117 
  [(set_attr "type"     "arith")
118 
   (set_attr "mode"     "SI")])
119 
 
120 
(define_insn "mips_adduh_r_qb"
121 
  [(set (match_operand:V4QI 0 "register_operand" "=d")
122 
        (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
123 
                      (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
124 
                     UNSPEC_ADDUH_R_QB))]
125 
  "ISA_HAS_DSPR2"
126 
  "adduh_r.qb\t%0,%z1,%z2"
127 
  [(set_attr "type"     "arith")
128 
   (set_attr "mode"     "SI")])
129 
 
130 
(define_insn "mips_append"
131 
  [(set (match_operand:SI 0 "register_operand" "=d")
132 
        (unspec:SI [(match_operand:SI 1 "register_operand" "0")
133 
                    (match_operand:SI 2 "reg_or_0_operand" "dJ")
134 
                    (match_operand:SI 3 "const_int_operand" "n")]
135 
                   UNSPEC_APPEND))]
136 
  "ISA_HAS_DSPR2"
137 
{
138 
  if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31)
139 
    operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
140 
  return "append\t%0,%z2,%3";
141 
}
142 
  [(set_attr "type"     "arith")
143 
   (set_attr "mode"     "SI")])
144 
 
145 
(define_insn "mips_balign"
146 
  [(set (match_operand:SI 0 "register_operand" "=d")
147 
        (unspec:SI [(match_operand:SI 1 "register_operand" "0")
148 
                    (match_operand:SI 2 "reg_or_0_operand" "dJ")
149 
                    (match_operand:SI 3 "const_int_operand" "n")]
150 
                   UNSPEC_BALIGN))]
151 
  "ISA_HAS_DSPR2"
152 
{
153 
  if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 3)
154 
    operands[2] = GEN_INT (INTVAL (operands[2]) & 3);
155 
  return "balign\t%0,%z2,%3";
156 
}
157 
  [(set_attr "type"     "arith")
158 
   (set_attr "mode"     "SI")])
159 
 
160 
(define_insn "mips_cmpgdu_eq_qb"
161 
  [(parallel
162 
    [(set (match_operand:SI 0 "register_operand" "=d")
163 
          (unspec:SI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
164 
                      (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
165 
                     UNSPEC_CMPGDU_EQ_QB))
166 
     (set (reg:CCDSP CCDSP_CC_REGNUM)
167 
          (unspec:CCDSP [(match_dup 1) (match_dup 2)
168 
                         (reg:CCDSP CCDSP_CC_REGNUM)]
169 
                        UNSPEC_CMPGDU_EQ_QB))])]
170 
  "ISA_HAS_DSPR2"
171 
  "cmpgdu.eq.qb\t%0,%z1,%z2"
172 
  [(set_attr "type"     "arith")
173 
   (set_attr "mode"     "SI")])
174 
 
175 
(define_insn "mips_cmpgdu_lt_qb"
176 
  [(parallel
177 
    [(set (match_operand:SI 0 "register_operand" "=d")
178 
          (unspec:SI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
179 
                      (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
180 
                     UNSPEC_CMPGDU_LT_QB))
181 
     (set (reg:CCDSP CCDSP_CC_REGNUM)
182 
          (unspec:CCDSP [(match_dup 1) (match_dup 2)
183 
                         (reg:CCDSP CCDSP_CC_REGNUM)]
184 
                        UNSPEC_CMPGDU_LT_QB))])]
185 
  "ISA_HAS_DSPR2"
186 
  "cmpgdu.lt.qb\t%0,%z1,%z2"
187 
  [(set_attr "type"     "arith")
188 
   (set_attr "mode"     "SI")])
189 
 
190 
(define_insn "mips_cmpgdu_le_qb"
191 
  [(parallel
192 
    [(set (match_operand:SI 0 "register_operand" "=d")
193 
          (unspec:SI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
194 
                      (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
195 
                     UNSPEC_CMPGDU_LE_QB))
196 
     (set (reg:CCDSP CCDSP_CC_REGNUM)
197 
          (unspec:CCDSP [(match_dup 1) (match_dup 2)
198 
                         (reg:CCDSP CCDSP_CC_REGNUM)]
199 
                        UNSPEC_CMPGDU_LE_QB))])]
200 
  "ISA_HAS_DSPR2"
201 
  "cmpgdu.le.qb\t%0,%z1,%z2"
202 
  [(set_attr "type"     "arith")
203 
   (set_attr "mode"     "SI")])
204 
 
205 
(define_insn "mips_dpa_w_ph"
206 
  [(set (match_operand:DI 0 "register_operand" "=a")
207 
        (unspec:DI [(match_operand:DI 1 "register_operand" "0")
208 
                    (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
209 
                    (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
210 
                   UNSPEC_DPA_W_PH))]
211 
  "ISA_HAS_DSPR2 && !TARGET_64BIT"
212 
  "dpa.w.ph\t%q0,%z2,%z3"
213 
  [(set_attr "type"     "imadd")
214 
   (set_attr "mode"     "SI")])
215 
 
216 
(define_insn "mips_dps_w_ph"
217 
  [(set (match_operand:DI 0 "register_operand" "=a")
218 
        (unspec:DI [(match_operand:DI 1 "register_operand" "0")
219 
                    (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
220 
                    (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
221 
                   UNSPEC_DPS_W_PH))]
222 
  "ISA_HAS_DSPR2 && !TARGET_64BIT"
223 
  "dps.w.ph\t%q0,%z2,%z3"
224 
  [(set_attr "type"     "imadd")
225 
   (set_attr "mode"     "SI")])
226 
 
227 
(define_insn "mulv2hi3"
228 
  [(parallel
229 
    [(set (match_operand:V2HI 0 "register_operand" "=d")
230 
          (mult:V2HI (match_operand:V2HI 1 "register_operand" "d")
231 
                     (match_operand:V2HI 2 "register_operand" "d")))
232 
     (set (reg:CCDSP CCDSP_OU_REGNUM)
233 
          (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MUL_PH))
234 
     (clobber (match_scratch:DI 3 "=x"))])]
235 
  "ISA_HAS_DSPR2"
236 
  "mul.ph\t%0,%1,%2"
237 
  [(set_attr "type"     "imul3")
238 
   (set_attr "mode"     "SI")])
239 
 
240 
(define_insn "mips_mul_s_ph"
241 
  [(parallel
242 
    [(set (match_operand:V2HI 0 "register_operand" "=d")
243 
          (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
244 
                        (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
245 
                       UNSPEC_MUL_S_PH))
246 
     (set (reg:CCDSP CCDSP_OU_REGNUM)
247 
          (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MUL_S_PH))
248 
     (clobber (match_scratch:DI 3 "=x"))])]
249 
  "ISA_HAS_DSPR2"
250 
  "mul_s.ph\t%0,%z1,%z2"
251 
  [(set_attr "type"     "imul3")
252 
   (set_attr "mode"     "SI")])
253 
 
254 
(define_insn "mips_mulq_rs_w"
255 
  [(parallel
256 
    [(set (match_operand:SI 0 "register_operand" "=d")
257 
          (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
258 
                      (match_operand:SI 2 "reg_or_0_operand" "dJ")]
259 
                     UNSPEC_MULQ_RS_W))
260 
     (set (reg:CCDSP CCDSP_OU_REGNUM)
261 
          (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_RS_W))
262 
     (clobber (match_scratch:DI 3 "=x"))])]
263 
  "ISA_HAS_DSPR2"
264 
  "mulq_rs.w\t%0,%z1,%z2"
265 
  [(set_attr "type"     "imul3")
266 
   (set_attr "mode"     "SI")])
267 
 
268 
(define_insn "mips_mulq_s_ph"
269 
  [(parallel
270 
    [(set (match_operand:V2HI 0 "register_operand" "=d")
271 
          (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
272 
                        (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
273 
                       UNSPEC_MULQ_S_PH))
274 
     (set (reg:CCDSP CCDSP_OU_REGNUM)
275 
          (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_S_PH))
276 
     (clobber (match_scratch:DI 3 "=x"))])]
277 
  "ISA_HAS_DSPR2"
278 
  "mulq_s.ph\t%0,%z1,%z2"
279 
  [(set_attr "type"     "imul3")
280 
   (set_attr "mode"     "SI")])
281 
 
282 
(define_insn "mips_mulq_s_w"
283 
  [(parallel
284 
    [(set (match_operand:SI 0 "register_operand" "=d")
285 
          (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
286 
                      (match_operand:SI 2 "reg_or_0_operand" "dJ")]
287 
                     UNSPEC_MULQ_S_W))
288 
     (set (reg:CCDSP CCDSP_OU_REGNUM)
289 
          (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_S_W))
290 
     (clobber (match_scratch:DI 3 "=x"))])]
291 
  "ISA_HAS_DSPR2"
292 
  "mulq_s.w\t%0,%z1,%z2"
293 
  [(set_attr "type"     "imul3")
294 
   (set_attr "mode"     "SI")])
295 
 
296 
(define_insn "mips_mulsa_w_ph"
297 
  [(set (match_operand:DI 0 "register_operand" "=a")
298 
        (unspec:DI [(match_operand:DI 1 "register_operand" "0")
299 
                    (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
300 
                    (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
301 
                   UNSPEC_MULSA_W_PH))]
302 
  "ISA_HAS_DSPR2 && !TARGET_64BIT"
303 
  "mulsa.w.ph\t%q0,%z2,%z3"
304 
  [(set_attr "type"     "imadd")
305 
   (set_attr "mode"     "SI")])
306 
 
307 
(define_insn "mips_precr_qb_ph"
308 
  [(set (match_operand:V4QI 0 "register_operand" "=d")
309 
        (unspec:V4QI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
310 
                      (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
311 
                     UNSPEC_PRECR_QB_PH))]
312 
  "ISA_HAS_DSPR2"
313 
  "precr.qb.ph\t%0,%z1,%z2"
314 
  [(set_attr "type"     "arith")
315 
   (set_attr "mode"     "SI")])
316 
 
317 
(define_insn "mips_precr_sra_ph_w"
318 
  [(set (match_operand:V2HI 0 "register_operand" "=d")
319 
        (unspec:V2HI [(match_operand:SI 1 "register_operand" "0")
320 
                      (match_operand:SI 2 "reg_or_0_operand" "dJ")
321 
                      (match_operand:SI 3 "const_int_operand" "n")]
322 
                     UNSPEC_PRECR_SRA_PH_W))]
323 
  "ISA_HAS_DSPR2"
324 
{
325 
  if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31)
326 
    operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
327 
  return "precr_sra.ph.w\t%0,%z2,%3";
328 
}
329 
  [(set_attr "type"     "arith")
330 
   (set_attr "mode"     "SI")])
331 
 
332 
(define_insn "mips_precr_sra_r_ph_w"
333 
  [(set (match_operand:V2HI 0 "register_operand" "=d")
334 
        (unspec:V2HI [(match_operand:SI 1 "register_operand" "0")
335 
                      (match_operand:SI 2 "reg_or_0_operand" "dJ")
336 
                      (match_operand:SI 3 "const_int_operand" "n")]
337 
                     UNSPEC_PRECR_SRA_R_PH_W))]
338 
  "ISA_HAS_DSPR2"
339 
{
340 
  if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31)
341 
    operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
342 
  return "precr_sra_r.ph.w\t%0,%z2,%3";
343 
}
344 
  [(set_attr "type"     "arith")
345 
   (set_attr "mode"     "SI")])
346 
 
347 
(define_insn "mips_prepend"
348 
  [(set (match_operand:SI 0 "register_operand" "=d")
349 
        (unspec:SI [(match_operand:SI 1 "register_operand" "0")
350 
                    (match_operand:SI 2 "reg_or_0_operand" "dJ")
351 
                    (match_operand:SI 3 "const_int_operand" "n")]
352 
                   UNSPEC_PREPEND))]
353 
  "ISA_HAS_DSPR2"
354 
{
355 
  if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31)
356 
    operands[3] = GEN_INT (INTVAL (operands[3]) & 31);
357 
  return "prepend\t%0,%z2,%3";
358 
}
359 
  [(set_attr "type"     "arith")
360 
   (set_attr "mode"     "SI")])
361 
 
362 
(define_insn "mips_shra_qb"
363 
  [(set (match_operand:V4QI 0 "register_operand" "=d,d")
364 
        (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG,dYG")
365 
                      (match_operand:SI 2 "arith_operand" "I,d")]
366 
                     UNSPEC_SHRA_QB))]
367 
  "ISA_HAS_DSPR2"
368 
{
369 
  if (which_alternative == 0)
370 
    {
371 
      if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 7)
372 
        operands[2] = GEN_INT (INTVAL (operands[2]) & 7);
373 
      return "shra.qb\t%0,%z1,%2";
374 
    }
375 
  return "shrav.qb\t%0,%z1,%2";
376 
}
377 
  [(set_attr "type"     "shift")
378 
   (set_attr "mode"     "SI")])
379 
 
380 
 
381 
(define_insn "mips_shra_r_qb"
382 
  [(set (match_operand:V4QI 0 "register_operand" "=d,d")
383 
        (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG,dYG")
384 
                      (match_operand:SI 2 "arith_operand" "I,d")]
385 
                     UNSPEC_SHRA_R_QB))]
386 
  "ISA_HAS_DSPR2"
387 
{
388 
  if (which_alternative == 0)
389 
    {
390 
      if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 7)
391 
        operands[2] = GEN_INT (INTVAL (operands[2]) & 7);
392 
      return "shra_r.qb\t%0,%z1,%2";
393 
    }
394 
  return "shrav_r.qb\t%0,%z1,%2";
395 
}
396 
  [(set_attr "type"     "shift")
397 
   (set_attr "mode"     "SI")])
398 
 
399 
(define_insn "mips_shrl_ph"
400 
  [(set (match_operand:V2HI 0 "register_operand" "=d,d")
401 
        (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG,dYG")
402 
                      (match_operand:SI 2 "arith_operand" "I,d")]
403 
                     UNSPEC_SHRL_PH))]
404 
  "ISA_HAS_DSPR2"
405 
{
406 
  if (which_alternative == 0)
407 
    {
408 
      if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 15)
409 
        operands[2] = GEN_INT (INTVAL (operands[2]) & 15);
410 
      return "shrl.ph\t%0,%z1,%2";
411 
    }
412 
  return "shrlv.ph\t%0,%z1,%2";
413 
}
414 
  [(set_attr "type"     "shift")
415 
   (set_attr "mode"     "SI")])
416 
 
417 
(define_insn "mips_subu_ph"
418 
  [(parallel
419 
    [(set (match_operand:V2HI 0 "register_operand" "=d")
420 
          (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
421 
                        (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
422 
                       UNSPEC_SUBU_PH))
423 
     (set (reg:CCDSP CCDSP_OU_REGNUM)
424 
          (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBU_PH))])]
425 
  "ISA_HAS_DSPR2"
426 
  "subu.ph\t%0,%z1,%z2"
427 
  [(set_attr "type"     "arith")
428 
   (set_attr "mode"     "SI")])
429 
 
430 
(define_insn "mips_subu_s_ph"
431 
  [(parallel
432 
    [(set (match_operand:V2HI 0 "register_operand" "=d")
433 
          (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
434 
                        (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
435 
                       UNSPEC_SUBU_S_PH))
436 
     (set (reg:CCDSP CCDSP_OU_REGNUM)
437 
          (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBU_S_PH))])]
438 
  "ISA_HAS_DSPR2"
439 
  "subu_s.ph\t%0,%z1,%z2"
440 
  [(set_attr "type"     "arith")
441 
   (set_attr "mode"     "SI")])
442 
 
443 
(define_insn "mips_subuh_qb"
444 
  [(set (match_operand:V4QI 0 "register_operand" "=d")
445 
        (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
446 
                      (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
447 
                     UNSPEC_SUBUH_QB))]
448 
  "ISA_HAS_DSPR2"
449 
  "subuh.qb\t%0,%z1,%z2"
450 
  [(set_attr "type"     "arith")
451 
   (set_attr "mode"     "SI")])
452 
 
453 
(define_insn "mips_subuh_r_qb"
454 
  [(set (match_operand:V4QI 0 "register_operand" "=d")
455 
        (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
456 
                      (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
457 
                     UNSPEC_SUBUH_R_QB))]
458 
  "ISA_HAS_DSPR2"
459 
  "subuh_r.qb\t%0,%z1,%z2"
460 
  [(set_attr "type"     "arith")
461 
   (set_attr "mode"     "SI")])
462 
 
463 
(define_insn "mips_addqh_ph"
464 
  [(set (match_operand:V2HI 0 "register_operand" "=d")
465 
        (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
466 
                      (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
467 
                     UNSPEC_ADDQH_PH))]
468 
  "ISA_HAS_DSPR2"
469 
  "addqh.ph\t%0,%z1,%z2"
470 
  [(set_attr "type"     "arith")
471 
   (set_attr "mode"     "SI")])
472 
 
473 
(define_insn "mips_addqh_r_ph"
474 
  [(set (match_operand:V2HI 0 "register_operand" "=d")
475 
        (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
476 
                      (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
477 
                     UNSPEC_ADDQH_R_PH))]
478 
  "ISA_HAS_DSPR2"
479 
  "addqh_r.ph\t%0,%z1,%z2"
480 
  [(set_attr "type"     "arith")
481 
   (set_attr "mode"     "SI")])
482 
 
483 
(define_insn "mips_addqh_w"
484 
  [(set (match_operand:SI 0 "register_operand" "=d")
485 
        (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
486 
                    (match_operand:SI 2 "reg_or_0_operand" "dJ")]
487 
                   UNSPEC_ADDQH_W))]
488 
  "ISA_HAS_DSPR2"
489 
  "addqh.w\t%0,%z1,%z2"
490 
  [(set_attr "type"     "arith")
491 
   (set_attr "mode"     "SI")])
492 
 
493 
(define_insn "mips_addqh_r_w"
494 
  [(set (match_operand:SI 0 "register_operand" "=d")
495 
        (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
496 
                    (match_operand:SI 2 "reg_or_0_operand" "dJ")]
497 
                   UNSPEC_ADDQH_R_W))]
498 
  "ISA_HAS_DSPR2"
499 
  "addqh_r.w\t%0,%z1,%z2"
500 
  [(set_attr "type"     "arith")
501 
   (set_attr "mode"     "SI")])
502 
 
503 
(define_insn "mips_subqh_ph"
504 
  [(set (match_operand:V2HI 0 "register_operand" "=d")
505 
        (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
506 
                      (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
507 
                     UNSPEC_SUBQH_PH))]
508 
  "ISA_HAS_DSPR2"
509 
  "subqh.ph\t%0,%z1,%z2"
510 
  [(set_attr "type"     "arith")
511 
   (set_attr "mode"     "SI")])
512 
 
513 
(define_insn "mips_subqh_r_ph"
514 
  [(set (match_operand:V2HI 0 "register_operand" "=d")
515 
        (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
516 
                      (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
517 
                     UNSPEC_SUBQH_R_PH))]
518 
  "ISA_HAS_DSPR2"
519 
  "subqh_r.ph\t%0,%z1,%z2"
520 
  [(set_attr "type"     "arith")
521 
   (set_attr "mode"     "SI")])
522 
 
523 
(define_insn "mips_subqh_w"
524 
  [(set (match_operand:SI 0 "register_operand" "=d")
525 
        (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
526 
                    (match_operand:SI 2 "reg_or_0_operand" "dJ")]
527 
                   UNSPEC_SUBQH_W))]
528 
  "ISA_HAS_DSPR2"
529 
  "subqh.w\t%0,%z1,%z2"
530 
  [(set_attr "type"     "arith")
531 
   (set_attr "mode"     "SI")])
532 
 
533 
(define_insn "mips_subqh_r_w"
534 
  [(set (match_operand:SI 0 "register_operand" "=d")
535 
        (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
536 
                    (match_operand:SI 2 "reg_or_0_operand" "dJ")]
537 
                   UNSPEC_SUBQH_R_W))]
538 
  "ISA_HAS_DSPR2"
539 
  "subqh_r.w\t%0,%z1,%z2"
540 
  [(set_attr "type"     "arith")
541 
   (set_attr "mode"     "SI")])
542 
 
543 
(define_insn "mips_dpax_w_ph"
544 
  [(set (match_operand:DI 0 "register_operand" "=a")
545 
        (unspec:DI [(match_operand:DI 1 "register_operand" "0")
546 
                    (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
547 
                    (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
548 
                   UNSPEC_DPAX_W_PH))]
549 
  "ISA_HAS_DSPR2 && !TARGET_64BIT"
550 
  "dpax.w.ph\t%q0,%z2,%z3"
551 
  [(set_attr "type"     "imadd")
552 
   (set_attr "mode"     "SI")])
553 
 
554 
(define_insn "mips_dpsx_w_ph"
555 
  [(set (match_operand:DI 0 "register_operand" "=a")
556 
        (unspec:DI [(match_operand:DI 1 "register_operand" "0")
557 
                    (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
558 
                    (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
559 
                   UNSPEC_DPSX_W_PH))]
560 
  "ISA_HAS_DSPR2 && !TARGET_64BIT"
561 
  "dpsx.w.ph\t%q0,%z2,%z3"
562 
  [(set_attr "type"     "imadd")
563 
   (set_attr "mode"     "SI")])
564 
 
565 
(define_insn "mips_dpaqx_s_w_ph"
566 
  [(parallel
567 
    [(set (match_operand:DI 0 "register_operand" "=a")
568 
          (unspec:DI [(match_operand:DI 1 "register_operand" "0")
569 
                      (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
570 
                      (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
571 
                     UNSPEC_DPAQX_S_W_PH))
572 
     (set (reg:CCDSP CCDSP_OU_REGNUM)
573 
          (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
574 
                        UNSPEC_DPAQX_S_W_PH))])]
575 
  "ISA_HAS_DSPR2 && !TARGET_64BIT"
576 
  "dpaqx_s.w.ph\t%q0,%z2,%z3"
577 
  [(set_attr "type"     "imadd")
578 
   (set_attr "mode"     "SI")])
579 
 
580 
(define_insn "mips_dpaqx_sa_w_ph"
581 
  [(parallel
582 
    [(set (match_operand:DI 0 "register_operand" "=a")
583 
          (unspec:DI [(match_operand:DI 1 "register_operand" "0")
584 
                      (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
585 
                      (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
586 
                     UNSPEC_DPAQX_SA_W_PH))
587 
     (set (reg:CCDSP CCDSP_OU_REGNUM)
588 
          (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
589 
                        UNSPEC_DPAQX_SA_W_PH))])]
590 
  "ISA_HAS_DSPR2 && !TARGET_64BIT"
591 
  "dpaqx_sa.w.ph\t%q0,%z2,%z3"
592 
  [(set_attr "type"     "imadd")
593 
   (set_attr "mode"     "SI")])
594 
 
595 
(define_insn "mips_dpsqx_s_w_ph"
596 
  [(parallel
597 
    [(set (match_operand:DI 0 "register_operand" "=a")
598 
          (unspec:DI [(match_operand:DI 1 "register_operand" "0")
599 
                      (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
600 
                      (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
601 
                     UNSPEC_DPSQX_S_W_PH))
602 
     (set (reg:CCDSP CCDSP_OU_REGNUM)
603 
          (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
604 
                        UNSPEC_DPSQX_S_W_PH))])]
605 
  "ISA_HAS_DSPR2 && !TARGET_64BIT"
606 
  "dpsqx_s.w.ph\t%q0,%z2,%z3"
607 
  [(set_attr "type"     "imadd")
608 
   (set_attr "mode"     "SI")])
609 
 
610 
(define_insn "mips_dpsqx_sa_w_ph"
611 
  [(parallel
612 
    [(set (match_operand:DI 0 "register_operand" "=a")
613 
          (unspec:DI [(match_operand:DI 1 "register_operand" "0")
614 
                      (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
615 
                      (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
616 
                     UNSPEC_DPSQX_SA_W_PH))
617 
     (set (reg:CCDSP CCDSP_OU_REGNUM)
618 
          (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
619 
                        UNSPEC_DPSQX_SA_W_PH))])]
620 
  "ISA_HAS_DSPR2 && !TARGET_64BIT"
621 
  "dpsqx_sa.w.ph\t%q0,%z2,%z3"
622 
  [(set_attr "type"     "imadd")
623 
   (set_attr "mode"     "SI")])

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