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1 709 jeremybenn
/* Definitions of target machine for GNU compiler.  MIPS version.
2
   Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3
   1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009, 2010, 2011
4
   2012
5
   Free Software Foundation, Inc.
6
   Contributed by A. Lichnewsky (lich@inria.inria.fr).
7
   Changed by Michael Meissner  (meissner@osf.org).
8
   64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
9
   Brendan Eich (brendan@microunity.com).
10
 
11
This file is part of GCC.
12
 
13
GCC is free software; you can redistribute it and/or modify
14
it under the terms of the GNU General Public License as published by
15
the Free Software Foundation; either version 3, or (at your option)
16
any later version.
17
 
18
GCC is distributed in the hope that it will be useful,
19
but WITHOUT ANY WARRANTY; without even the implied warranty of
20
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
21
GNU General Public License for more details.
22
 
23
You should have received a copy of the GNU General Public License
24
along with GCC; see the file COPYING3.  If not see
25
<http://www.gnu.org/licenses/>.  */
26
 
27
 
28
#include "config/vxworks-dummy.h"
29
 
30
#ifdef GENERATOR_FILE
31
/* This is used in some insn conditions, so needs to be declared, but
32
   does not need to be defined.  */
33
extern int target_flags_explicit;
34
#endif
35
 
36
/* MIPS external variables defined in mips.c.  */
37
 
38
/* Which ABI to use.  ABI_32 (original 32, or o32), ABI_N32 (n32),
39
   ABI_64 (n64) are all defined by SGI.  ABI_O64 is o32 extended
40
   to work on a 64-bit machine.  */
41
 
42
#define ABI_32  0
43
#define ABI_N32 1
44
#define ABI_64  2
45
#define ABI_EABI 3
46
#define ABI_O64  4
47
 
48
/* Masks that affect tuning.
49
 
50
   PTF_AVOID_BRANCHLIKELY
51
        Set if it is usually not profitable to use branch-likely instructions
52
        for this target, typically because the branches are always predicted
53
        taken and so incur a large overhead when not taken.  */
54
#define PTF_AVOID_BRANCHLIKELY 0x1
55
 
56
/* Information about one recognized processor.  Defined here for the
57
   benefit of TARGET_CPU_CPP_BUILTINS.  */
58
struct mips_cpu_info {
59
  /* The 'canonical' name of the processor as far as GCC is concerned.
60
     It's typically a manufacturer's prefix followed by a numerical
61
     designation.  It should be lowercase.  */
62
  const char *name;
63
 
64
  /* The internal processor number that most closely matches this
65
     entry.  Several processors can have the same value, if there's no
66
     difference between them from GCC's point of view.  */
67
  enum processor cpu;
68
 
69
  /* The ISA level that the processor implements.  */
70
  int isa;
71
 
72
  /* A mask of PTF_* values.  */
73
  unsigned int tune_flags;
74
};
75
 
76
#include "config/mips/mips-opts.h"
77
 
78
/* Macros to silence warnings about numbers being signed in traditional
79
   C and unsigned in ISO C when compiled on 32-bit hosts.  */
80
 
81
#define BITMASK_HIGH    (((unsigned long)1) << 31)      /* 0x80000000 */
82
#define BITMASK_UPPER16 ((unsigned long)0xffff << 16)   /* 0xffff0000 */
83
#define BITMASK_LOWER16 ((unsigned long)0xffff)         /* 0x0000ffff */
84
 
85
 
86
/* Run-time compilation parameters selecting different hardware subsets.  */
87
 
88
/* True if we are generating position-independent VxWorks RTP code.  */
89
#define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
90
 
91
/* True if the output file is marked as ".abicalls; .option pic0"
92
   (-call_nonpic).  */
93
#define TARGET_ABICALLS_PIC0 \
94
  (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT)
95
 
96
/* True if the output file is marked as ".abicalls; .option pic2" (-KPIC).  */
97
#define TARGET_ABICALLS_PIC2 \
98
  (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0)
99
 
100
/* True if the call patterns should be split into a jalr followed by
101
   an instruction to restore $gp.  It is only safe to split the load
102
   from the call when every use of $gp is explicit.
103
 
104
   See mips_must_initialize_gp_p for details about how we manage the
105
   global pointer.  */
106
 
107
#define TARGET_SPLIT_CALLS \
108
  (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP && epilogue_completed)
109
 
110
/* True if we're generating a form of -mabicalls in which we can use
111
   operators like %hi and %lo to refer to locally-binding symbols.
112
   We can only do this for -mno-shared, and only then if we can use
113
   relocation operations instead of assembly macros.  It isn't really
114
   worth using absolute sequences for 64-bit symbols because GOT
115
   accesses are so much shorter.  */
116
 
117
#define TARGET_ABSOLUTE_ABICALLS        \
118
  (TARGET_ABICALLS                      \
119
   && !TARGET_SHARED                    \
120
   && TARGET_EXPLICIT_RELOCS            \
121
   && !ABI_HAS_64BIT_SYMBOLS)
122
 
123
/* True if we can optimize sibling calls.  For simplicity, we only
124
   handle cases in which call_insn_operand will reject invalid
125
   sibcall addresses.  There are two cases in which this isn't true:
126
 
127
      - TARGET_MIPS16.  call_insn_operand accepts constant addresses
128
        but there is no direct jump instruction.  It isn't worth
129
        using sibling calls in this case anyway; they would usually
130
        be longer than normal calls.
131
 
132
      - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS.  call_insn_operand
133
        accepts global constants, but all sibcalls must be indirect.  */
134
#define TARGET_SIBCALLS \
135
  (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
136
 
137
/* True if we need to use a global offset table to access some symbols.  */
138
#define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
139
 
140
/* True if TARGET_USE_GOT and if $gp is a call-clobbered register.  */
141
#define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
142
 
143
/* True if TARGET_USE_GOT and if $gp is a call-saved register.  */
144
#define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
145
 
146
/* True if we should use .cprestore to store to the cprestore slot.
147
 
148
   We continue to use .cprestore for explicit-reloc code so that JALs
149
   inside inline asms will work correctly.  */
150
#define TARGET_CPRESTORE_DIRECTIVE \
151
  (TARGET_ABICALLS_PIC2 && !TARGET_MIPS16)
152
 
153
/* True if we can use the J and JAL instructions.  */
154
#define TARGET_ABSOLUTE_JUMPS \
155
  (!flag_pic || TARGET_ABSOLUTE_ABICALLS)
156
 
157
/* True if indirect calls must use register class PIC_FN_ADDR_REG.
158
   This is true for both the PIC and non-PIC VxWorks RTP modes.  */
159
#define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
160
 
161
/* True if .gpword or .gpdword should be used for switch tables.
162
 
163
   Although GAS does understand .gpdword, the SGI linker mishandles
164
   the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64).
165
   We therefore disable GP-relative switch tables for n64 on IRIX targets.  */
166
#define TARGET_GPWORD                           \
167
  (TARGET_ABICALLS                              \
168
   && !TARGET_ABSOLUTE_ABICALLS                 \
169
   && !(mips_abi == ABI_64 && TARGET_IRIX6))
170
 
171
/* True if the output must have a writable .eh_frame.
172
   See ASM_PREFERRED_EH_DATA_FORMAT for details.  */
173
#ifdef HAVE_LD_PERSONALITY_RELAXATION
174
#define TARGET_WRITABLE_EH_FRAME 0
175
#else
176
#define TARGET_WRITABLE_EH_FRAME (flag_pic && TARGET_SHARED)
177
#endif
178
 
179
/* Test the assembler to set ISA_HAS_DSP_MULT to DSP Rev 1 or 2.  */
180
#ifdef HAVE_AS_DSPR1_MULT
181
#define ISA_HAS_DSP_MULT ISA_HAS_DSP
182
#else
183
#define ISA_HAS_DSP_MULT ISA_HAS_DSPR2
184
#endif
185
 
186
/* Generate mips16 code */
187
#define TARGET_MIPS16           ((target_flags & MASK_MIPS16) != 0)
188
/* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */
189
#define GENERATE_MIPS16E        (TARGET_MIPS16 && mips_isa >= 32)
190
/* Generate mips16e register save/restore sequences.  */
191
#define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
192
 
193
/* True if we're generating a form of MIPS16 code in which general
194
   text loads are allowed.  */
195
#define TARGET_MIPS16_TEXT_LOADS \
196
  (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
197
 
198
/* True if we're generating a form of MIPS16 code in which PC-relative
199
   loads are allowed.  */
200
#define TARGET_MIPS16_PCREL_LOADS \
201
  (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
202
 
203
/* Generic ISA defines.  */
204
#define ISA_MIPS1                   (mips_isa == 1)
205
#define ISA_MIPS2                   (mips_isa == 2)
206
#define ISA_MIPS3                   (mips_isa == 3)
207
#define ISA_MIPS4                   (mips_isa == 4)
208
#define ISA_MIPS32                  (mips_isa == 32)
209
#define ISA_MIPS32R2                (mips_isa == 33)
210
#define ISA_MIPS64                  (mips_isa == 64)
211
#define ISA_MIPS64R2                (mips_isa == 65)
212
 
213
/* Architecture target defines.  */
214
#define TARGET_LOONGSON_2E          (mips_arch == PROCESSOR_LOONGSON_2E)
215
#define TARGET_LOONGSON_2F          (mips_arch == PROCESSOR_LOONGSON_2F)
216
#define TARGET_LOONGSON_2EF         (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
217
#define TARGET_LOONGSON_3A          (mips_arch == PROCESSOR_LOONGSON_3A)
218
#define TARGET_MIPS3900             (mips_arch == PROCESSOR_R3900)
219
#define TARGET_MIPS4000             (mips_arch == PROCESSOR_R4000)
220
#define TARGET_MIPS4120             (mips_arch == PROCESSOR_R4120)
221
#define TARGET_MIPS4130             (mips_arch == PROCESSOR_R4130)
222
#define TARGET_MIPS5400             (mips_arch == PROCESSOR_R5400)
223
#define TARGET_MIPS5500             (mips_arch == PROCESSOR_R5500)
224
#define TARGET_MIPS7000             (mips_arch == PROCESSOR_R7000)
225
#define TARGET_MIPS9000             (mips_arch == PROCESSOR_R9000)
226
#define TARGET_OCTEON               (mips_arch == PROCESSOR_OCTEON      \
227
                                     || mips_arch == PROCESSOR_OCTEON2)
228
#define TARGET_OCTEON2              (mips_arch == PROCESSOR_OCTEON2)
229
#define TARGET_SB1                  (mips_arch == PROCESSOR_SB1         \
230
                                     || mips_arch == PROCESSOR_SB1A)
231
#define TARGET_SR71K                (mips_arch == PROCESSOR_SR71000)
232
 
233
/* Scheduling target defines.  */
234
#define TUNE_20KC                   (mips_tune == PROCESSOR_20KC)
235
#define TUNE_24K                    (mips_tune == PROCESSOR_24KC        \
236
                                     || mips_tune == PROCESSOR_24KF2_1  \
237
                                     || mips_tune == PROCESSOR_24KF1_1)
238
#define TUNE_74K                    (mips_tune == PROCESSOR_74KC        \
239
                                     || mips_tune == PROCESSOR_74KF2_1  \
240
                                     || mips_tune == PROCESSOR_74KF1_1  \
241
                                     || mips_tune == PROCESSOR_74KF3_2)
242
#define TUNE_LOONGSON_2EF           (mips_tune == PROCESSOR_LOONGSON_2E \
243
                                     || mips_tune == PROCESSOR_LOONGSON_2F)
244
#define TUNE_LOONGSON_3A            (mips_tune == PROCESSOR_LOONGSON_3A)
245
#define TUNE_MIPS3000               (mips_tune == PROCESSOR_R3000)
246
#define TUNE_MIPS3900               (mips_tune == PROCESSOR_R3900)
247
#define TUNE_MIPS4000               (mips_tune == PROCESSOR_R4000)
248
#define TUNE_MIPS4120               (mips_tune == PROCESSOR_R4120)
249
#define TUNE_MIPS4130               (mips_tune == PROCESSOR_R4130)
250
#define TUNE_MIPS5000               (mips_tune == PROCESSOR_R5000)
251
#define TUNE_MIPS5400               (mips_tune == PROCESSOR_R5400)
252
#define TUNE_MIPS5500               (mips_tune == PROCESSOR_R5500)
253
#define TUNE_MIPS6000               (mips_tune == PROCESSOR_R6000)
254
#define TUNE_MIPS7000               (mips_tune == PROCESSOR_R7000)
255
#define TUNE_MIPS9000               (mips_tune == PROCESSOR_R9000)
256
#define TUNE_OCTEON                 (mips_tune == PROCESSOR_OCTEON      \
257
                                     || mips_tune == PROCESSOR_OCTEON2)
258
#define TUNE_SB1                    (mips_tune == PROCESSOR_SB1         \
259
                                     || mips_tune == PROCESSOR_SB1A)
260
 
261
/* Whether vector modes and intrinsics for ST Microelectronics
262
   Loongson-2E/2F processors should be enabled.  In o32 pairs of
263
   floating-point registers provide 64-bit values.  */
264
#define TARGET_LOONGSON_VECTORS     (TARGET_HARD_FLOAT_ABI              \
265
                                     && (TARGET_LOONGSON_2EF            \
266
                                         || TARGET_LOONGSON_3A))
267
 
268
/* True if the pre-reload scheduler should try to create chains of
269
   multiply-add or multiply-subtract instructions.  For example,
270
   suppose we have:
271
 
272
        t1 = a * b
273
        t2 = t1 + c * d
274
        t3 = e * f
275
        t4 = t3 - g * h
276
 
277
   t1 will have a higher priority than t2 and t3 will have a higher
278
   priority than t4.  However, before reload, there is no dependence
279
   between t1 and t3, and they can often have similar priorities.
280
   The scheduler will then tend to prefer:
281
 
282
        t1 = a * b
283
        t3 = e * f
284
        t2 = t1 + c * d
285
        t4 = t3 - g * h
286
 
287
   which stops us from making full use of macc/madd-style instructions.
288
   This sort of situation occurs frequently in Fourier transforms and
289
   in unrolled loops.
290
 
291
   To counter this, the TUNE_MACC_CHAINS code will reorder the ready
292
   queue so that chained multiply-add and multiply-subtract instructions
293
   appear ahead of any other instruction that is likely to clobber lo.
294
   In the example above, if t2 and t3 become ready at the same time,
295
   the code ensures that t2 is scheduled first.
296
 
297
   Multiply-accumulate instructions are a bigger win for some targets
298
   than others, so this macro is defined on an opt-in basis.  */
299
#define TUNE_MACC_CHAINS            (TUNE_MIPS5500              \
300
                                     || TUNE_MIPS4120           \
301
                                     || TUNE_MIPS4130           \
302
                                     || TUNE_24K)
303
 
304
#define TARGET_OLDABI               (mips_abi == ABI_32 || mips_abi == ABI_O64)
305
#define TARGET_NEWABI               (mips_abi == ABI_N32 || mips_abi == ABI_64)
306
 
307
/* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
308
   directly accessible, while the command-line options select
309
   TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
310
   in use.  */
311
#define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
312
#define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
313
 
314
/* False if SC acts as a memory barrier with respect to itself,
315
   otherwise a SYNC will be emitted after SC for atomic operations
316
   that require ordering between the SC and following loads and
317
   stores.  It does not tell anything about ordering of loads and
318
   stores prior to and following the SC, only about the SC itself and
319
   those loads and stores follow it.  */
320
#define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON)
321
 
322
/* IRIX specific stuff.  */
323
#define TARGET_IRIX6       0
324
 
325
/* Define preprocessor macros for the -march and -mtune options.
326
   PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
327
   processor.  If INFO's canonical name is "foo", define PREFIX to
328
   be "foo", and define an additional macro PREFIX_FOO.  */
329
#define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO)                    \
330
  do                                                            \
331
    {                                                           \
332
      char *macro, *p;                                          \
333
                                                                \
334
      macro = concat ((PREFIX), "_", (INFO)->name, NULL);       \
335
      for (p = macro; *p != 0; p++)                              \
336
        if (*p == '+')                                          \
337
          *p = 'P';                                             \
338
        else                                                    \
339
          *p = TOUPPER (*p);                                    \
340
                                                                \
341
      builtin_define (macro);                                   \
342
      builtin_define_with_value ((PREFIX), (INFO)->name, 1);    \
343
      free (macro);                                             \
344
    }                                                           \
345
  while (0)
346
 
347
/* Target CPU builtins.  */
348
#define TARGET_CPU_CPP_BUILTINS()                                       \
349
  do                                                                    \
350
    {                                                                   \
351
      /* Everyone but IRIX defines this to mips.  */                    \
352
      if (!TARGET_IRIX6)                                                \
353
        builtin_assert ("machine=mips");                                \
354
                                                                        \
355
      builtin_assert ("cpu=mips");                                      \
356
      builtin_define ("__mips__");                                      \
357
      builtin_define ("_mips");                                         \
358
                                                                        \
359
      /* We do this here because __mips is defined below and so we      \
360
         can't use builtin_define_std.  We don't ever want to define    \
361
         "mips" for VxWorks because some of the VxWorks headers         \
362
         construct include filenames from a root directory macro,       \
363
         an architecture macro and a filename, where the architecture   \
364
         macro expands to 'mips'.  If we define 'mips' to 1, the        \
365
         architecture macro expands to 1 as well.  */                   \
366
      if (!flag_iso && !TARGET_VXWORKS)                                 \
367
        builtin_define ("mips");                                        \
368
                                                                        \
369
      if (TARGET_64BIT)                                                 \
370
        builtin_define ("__mips64");                                    \
371
                                                                        \
372
      if (!TARGET_IRIX6)                                                \
373
        {                                                               \
374
          /* Treat _R3000 and _R4000 like register-size                 \
375
             defines, which is how they've historically                 \
376
             been used.  */                                             \
377
          if (TARGET_64BIT)                                             \
378
            {                                                           \
379
              builtin_define_std ("R4000");                             \
380
              builtin_define ("_R4000");                                \
381
            }                                                           \
382
          else                                                          \
383
            {                                                           \
384
              builtin_define_std ("R3000");                             \
385
              builtin_define ("_R3000");                                \
386
            }                                                           \
387
        }                                                               \
388
      if (TARGET_FLOAT64)                                               \
389
        builtin_define ("__mips_fpr=64");                               \
390
      else                                                              \
391
        builtin_define ("__mips_fpr=32");                               \
392
                                                                        \
393
      if (mips_base_mips16)                                             \
394
        builtin_define ("__mips16");                                    \
395
                                                                        \
396
      if (TARGET_MIPS3D)                                                \
397
        builtin_define ("__mips3d");                                    \
398
                                                                        \
399
      if (TARGET_SMARTMIPS)                                             \
400
        builtin_define ("__mips_smartmips");                            \
401
                                                                        \
402
      if (TARGET_DSP)                                                   \
403
        {                                                               \
404
          builtin_define ("__mips_dsp");                                \
405
          if (TARGET_DSPR2)                                             \
406
            {                                                           \
407
              builtin_define ("__mips_dspr2");                          \
408
              builtin_define ("__mips_dsp_rev=2");                      \
409
            }                                                           \
410
          else                                                          \
411
            builtin_define ("__mips_dsp_rev=1");                        \
412
        }                                                               \
413
                                                                        \
414
      MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info);            \
415
      MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info);            \
416
                                                                        \
417
      if (ISA_MIPS1)                                                    \
418
        {                                                               \
419
          builtin_define ("__mips=1");                                  \
420
          builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1");                 \
421
        }                                                               \
422
      else if (ISA_MIPS2)                                               \
423
        {                                                               \
424
          builtin_define ("__mips=2");                                  \
425
          builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2");                 \
426
        }                                                               \
427
      else if (ISA_MIPS3)                                               \
428
        {                                                               \
429
          builtin_define ("__mips=3");                                  \
430
          builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3");                 \
431
        }                                                               \
432
      else if (ISA_MIPS4)                                               \
433
        {                                                               \
434
          builtin_define ("__mips=4");                                  \
435
          builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4");                 \
436
        }                                                               \
437
      else if (ISA_MIPS32)                                              \
438
        {                                                               \
439
          builtin_define ("__mips=32");                                 \
440
          builtin_define ("__mips_isa_rev=1");                          \
441
          builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32");                \
442
        }                                                               \
443
      else if (ISA_MIPS32R2)                                            \
444
        {                                                               \
445
          builtin_define ("__mips=32");                                 \
446
          builtin_define ("__mips_isa_rev=2");                          \
447
          builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32");                \
448
        }                                                               \
449
      else if (ISA_MIPS64)                                              \
450
        {                                                               \
451
          builtin_define ("__mips=64");                                 \
452
          builtin_define ("__mips_isa_rev=1");                          \
453
          builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64");                \
454
        }                                                               \
455
      else if (ISA_MIPS64R2)                                            \
456
        {                                                               \
457
          builtin_define ("__mips=64");                                 \
458
          builtin_define ("__mips_isa_rev=2");                          \
459
          builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64");                \
460
        }                                                               \
461
                                                                        \
462
      switch (mips_abi)                                                 \
463
        {                                                               \
464
        case ABI_32:                                                    \
465
          builtin_define ("_ABIO32=1");                                 \
466
          builtin_define ("_MIPS_SIM=_ABIO32");                         \
467
          break;                                                        \
468
                                                                        \
469
        case ABI_N32:                                                   \
470
          builtin_define ("_ABIN32=2");                                 \
471
          builtin_define ("_MIPS_SIM=_ABIN32");                         \
472
          break;                                                        \
473
                                                                        \
474
        case ABI_64:                                                    \
475
          builtin_define ("_ABI64=3");                                  \
476
          builtin_define ("_MIPS_SIM=_ABI64");                          \
477
          break;                                                        \
478
                                                                        \
479
        case ABI_O64:                                                   \
480
          builtin_define ("_ABIO64=4");                                 \
481
          builtin_define ("_MIPS_SIM=_ABIO64");                         \
482
          break;                                                        \
483
        }                                                               \
484
                                                                        \
485
      builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE);     \
486
      builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE);   \
487
      builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE);      \
488
      builtin_define_with_int_value ("_MIPS_FPSET",                     \
489
                                     32 / MAX_FPRS_PER_FMT);            \
490
                                                                        \
491
      /* These defines reflect the ABI in use, not whether the          \
492
         FPU is directly accessible.  */                                \
493
      if (TARGET_NO_FLOAT)                                              \
494
        builtin_define ("__mips_no_float");                             \
495
      else if (TARGET_HARD_FLOAT_ABI)                                   \
496
        builtin_define ("__mips_hard_float");                           \
497
      else                                                              \
498
        builtin_define ("__mips_soft_float");                           \
499
                                                                        \
500
      if (TARGET_SINGLE_FLOAT)                                          \
501
        builtin_define ("__mips_single_float");                         \
502
                                                                        \
503
      if (TARGET_PAIRED_SINGLE_FLOAT)                                   \
504
        builtin_define ("__mips_paired_single_float");                  \
505
                                                                        \
506
      if (TARGET_BIG_ENDIAN)                                            \
507
        {                                                               \
508
          builtin_define_std ("MIPSEB");                                \
509
          builtin_define ("_MIPSEB");                                   \
510
        }                                                               \
511
      else                                                              \
512
        {                                                               \
513
          builtin_define_std ("MIPSEL");                                \
514
          builtin_define ("_MIPSEL");                                   \
515
        }                                                               \
516
                                                                        \
517
      /* Whether calls should go through $25.  The separate __PIC__     \
518
         macro indicates whether abicalls code might use a GOT.  */     \
519
      if (TARGET_ABICALLS)                                              \
520
        builtin_define ("__mips_abicalls");                             \
521
                                                                        \
522
      /* Whether Loongson vector modes are enabled.  */                 \
523
      if (TARGET_LOONGSON_VECTORS)                                      \
524
        builtin_define ("__mips_loongson_vector_rev");                  \
525
                                                                        \
526
      /* Historical Octeon macro.  */                                   \
527
      if (TARGET_OCTEON)                                                \
528
        builtin_define ("__OCTEON__");                                  \
529
                                                                        \
530
      /* Macros dependent on the C dialect.  */                         \
531
      if (preprocessing_asm_p ())                                       \
532
        {                                                               \
533
          builtin_define_std ("LANGUAGE_ASSEMBLY");                     \
534
          builtin_define ("_LANGUAGE_ASSEMBLY");                        \
535
        }                                                               \
536
      else if (c_dialect_cxx ())                                        \
537
        {                                                               \
538
          builtin_define ("_LANGUAGE_C_PLUS_PLUS");                     \
539
          builtin_define ("__LANGUAGE_C_PLUS_PLUS");                    \
540
          builtin_define ("__LANGUAGE_C_PLUS_PLUS__");                  \
541
        }                                                               \
542
      else                                                              \
543
        {                                                               \
544
          builtin_define_std ("LANGUAGE_C");                            \
545
          builtin_define ("_LANGUAGE_C");                               \
546
        }                                                               \
547
      if (c_dialect_objc ())                                            \
548
        {                                                               \
549
          builtin_define ("_LANGUAGE_OBJECTIVE_C");                     \
550
          builtin_define ("__LANGUAGE_OBJECTIVE_C");                    \
551
          /* Bizarre, but needed at least for Irix.  */                 \
552
          builtin_define_std ("LANGUAGE_C");                            \
553
          builtin_define ("_LANGUAGE_C");                               \
554
        }                                                               \
555
                                                                        \
556
      if (mips_abi == ABI_EABI)                                         \
557
        builtin_define ("__mips_eabi");                                 \
558
                                                                        \
559
      if (TARGET_CACHE_BUILTIN)                                         \
560
        builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE");               \
561
    }                                                                   \
562
  while (0)
563
 
564
/* Default target_flags if no switches are specified  */
565
 
566
#ifndef TARGET_DEFAULT
567
#define TARGET_DEFAULT 0
568
#endif
569
 
570
#ifndef TARGET_CPU_DEFAULT
571
#define TARGET_CPU_DEFAULT 0
572
#endif
573
 
574
#ifndef TARGET_ENDIAN_DEFAULT
575
#define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
576
#endif
577
 
578
#ifndef TARGET_FP_EXCEPTIONS_DEFAULT
579
#define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
580
#endif
581
 
582
#ifdef IN_LIBGCC2
583
#undef TARGET_64BIT
584
/* Make this compile time constant for libgcc2 */
585
#ifdef __mips64
586
#define TARGET_64BIT            1
587
#else
588
#define TARGET_64BIT            0
589
#endif
590
#endif /* IN_LIBGCC2 */
591
 
592
/* Force the call stack unwinders in unwind.inc not to be MIPS16 code
593
   when compiled with hardware floating point.  This is because MIPS16
594
   code cannot save and restore the floating-point registers, which is
595
   important if in a mixed MIPS16/non-MIPS16 environment.  */
596
 
597
#ifdef IN_LIBGCC2
598
#if __mips_hard_float
599
#define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
600
#endif
601
#endif /* IN_LIBGCC2 */
602
 
603
#define TARGET_LIBGCC_SDATA_SECTION ".sdata"
604
 
605
#ifndef MULTILIB_ENDIAN_DEFAULT
606
#if TARGET_ENDIAN_DEFAULT == 0
607
#define MULTILIB_ENDIAN_DEFAULT "EL"
608
#else
609
#define MULTILIB_ENDIAN_DEFAULT "EB"
610
#endif
611
#endif
612
 
613
#ifndef MULTILIB_ISA_DEFAULT
614
#  if MIPS_ISA_DEFAULT == 1
615
#    define MULTILIB_ISA_DEFAULT "mips1"
616
#  else
617
#    if MIPS_ISA_DEFAULT == 2
618
#      define MULTILIB_ISA_DEFAULT "mips2"
619
#    else
620
#      if MIPS_ISA_DEFAULT == 3
621
#        define MULTILIB_ISA_DEFAULT "mips3"
622
#      else
623
#        if MIPS_ISA_DEFAULT == 4
624
#          define MULTILIB_ISA_DEFAULT "mips4"
625
#        else
626
#          if MIPS_ISA_DEFAULT == 32
627
#            define MULTILIB_ISA_DEFAULT "mips32"
628
#          else
629
#            if MIPS_ISA_DEFAULT == 33
630
#              define MULTILIB_ISA_DEFAULT "mips32r2"
631
#            else
632
#              if MIPS_ISA_DEFAULT == 64
633
#                define MULTILIB_ISA_DEFAULT "mips64"
634
#              else
635
#                if MIPS_ISA_DEFAULT == 65
636
#                  define MULTILIB_ISA_DEFAULT "mips64r2"
637
#                else
638
#                  define MULTILIB_ISA_DEFAULT "mips1"
639
#                endif
640
#              endif
641
#            endif
642
#          endif
643
#        endif
644
#      endif
645
#    endif
646
#  endif
647
#endif
648
 
649
#ifndef MIPS_ABI_DEFAULT
650
#define MIPS_ABI_DEFAULT ABI_32
651
#endif
652
 
653
/* Use the most portable ABI flag for the ASM specs.  */
654
 
655
#if MIPS_ABI_DEFAULT == ABI_32
656
#define MULTILIB_ABI_DEFAULT "mabi=32"
657
#endif
658
 
659
#if MIPS_ABI_DEFAULT == ABI_O64
660
#define MULTILIB_ABI_DEFAULT "mabi=o64"
661
#endif
662
 
663
#if MIPS_ABI_DEFAULT == ABI_N32
664
#define MULTILIB_ABI_DEFAULT "mabi=n32"
665
#endif
666
 
667
#if MIPS_ABI_DEFAULT == ABI_64
668
#define MULTILIB_ABI_DEFAULT "mabi=64"
669
#endif
670
 
671
#if MIPS_ABI_DEFAULT == ABI_EABI
672
#define MULTILIB_ABI_DEFAULT "mabi=eabi"
673
#endif
674
 
675
#ifndef MULTILIB_DEFAULTS
676
#define MULTILIB_DEFAULTS \
677
    { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
678
#endif
679
 
680
/* We must pass -EL to the linker by default for little endian embedded
681
   targets using linker scripts with a OUTPUT_FORMAT line.  Otherwise, the
682
   linker will default to using big-endian output files.  The OUTPUT_FORMAT
683
   line must be in the linker script, otherwise -EB/-EL will not work.  */
684
 
685
#ifndef ENDIAN_SPEC
686
#if TARGET_ENDIAN_DEFAULT == 0
687
#define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
688
#else
689
#define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
690
#endif
691
#endif
692
 
693
/* A spec condition that matches all non-mips16 -mips arguments.  */
694
 
695
#define MIPS_ISA_LEVEL_OPTION_SPEC \
696
  "mips1|mips2|mips3|mips4|mips32*|mips64*"
697
 
698
/* A spec condition that matches all non-mips16 architecture arguments.  */
699
 
700
#define MIPS_ARCH_OPTION_SPEC \
701
  MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
702
 
703
/* A spec that infers a -mips argument from an -march argument,
704
   or injects the default if no architecture is specified.  */
705
 
706
#define MIPS_ISA_LEVEL_SPEC \
707
  "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
708
     %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
709
     %{march=mips2|march=r6000:-mips2} \
710
     %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
711
     %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \
712
       |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \
713
     %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
714
     %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
715
       |march=34k*|march=74k*|march=1004k*: -mips32r2} \
716
     %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
717
       |march=xlr|march=loongson3a: -mips64} \
718
     %{march=mips64r2|march=octeon: -mips64r2} \
719
     %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
720
 
721
/* A spec that infers a -mhard-float or -msoft-float setting from an
722
   -march argument.  Note that soft-float and hard-float code are not
723
   link-compatible.  */
724
 
725
#define MIPS_ARCH_FLOAT_SPEC \
726
  "%{mhard-float|msoft-float|march=mips*:; \
727
     march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
728
     |march=34kc|march=74kc|march=1004kc|march=5kc \
729
     |march=octeon|march=xlr: -msoft-float;               \
730
     march=*: -mhard-float}"
731
 
732
/* A spec condition that matches 32-bit options.  It only works if
733
   MIPS_ISA_LEVEL_SPEC has been applied.  */
734
 
735
#define MIPS_32BIT_OPTION_SPEC \
736
  "mips1|mips2|mips32*|mgp32"
737
 
738
#if MIPS_ABI_DEFAULT == ABI_O64 \
739
  || MIPS_ABI_DEFAULT == ABI_N32 \
740
  || MIPS_ABI_DEFAULT == ABI_64
741
#define OPT_ARCH64 "mabi=32|mgp32:;"
742
#define OPT_ARCH32 "mabi=32|mgp32"
743
#else
744
#define OPT_ARCH64 "mabi=o64|mabi=n32|mabi=64|mgp64"
745
#define OPT_ARCH32 "mabi=o64|mabi=n32|mabi=64|mgp64:;"
746
#endif
747
 
748
/* Support for a compile-time default CPU, et cetera.  The rules are:
749
   --with-arch is ignored if -march is specified or a -mips is specified
750
     (other than -mips16); likewise --with-arch-32 and --with-arch-64.
751
   --with-tune is ignored if -mtune is specified; likewise
752
     --with-tune-32 and --with-tune-64.
753
   --with-abi is ignored if -mabi is specified.
754
   --with-float is ignored if -mhard-float or -msoft-float are
755
     specified.
756
   --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
757
     specified. */
758
#define OPTION_DEFAULT_SPECS \
759
  {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
760
  {"arch_32", "%{" OPT_ARCH32 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
761
  {"arch_64", "%{" OPT_ARCH64 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
762
  {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
763
  {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
764
  {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
765
  {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
766
  {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
767
  {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
768
  {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
769
  {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
770
  {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }
771
 
772
 
773
/* A spec that infers the -mdsp setting from an -march argument.  */
774
#define BASE_DRIVER_SELF_SPECS \
775
  "%{!mno-dsp: \
776
     %{march=24ke*|march=34k*|march=1004k*: -mdsp} \
777
     %{march=74k*:%{!mno-dspr2: -mdspr2 -mdsp}}}"
778
 
779
#define DRIVER_SELF_SPECS BASE_DRIVER_SELF_SPECS
780
 
781
#define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
782
                               && ISA_HAS_COND_TRAP)
783
 
784
#define GENERATE_BRANCHLIKELY   (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
785
 
786
/* True if the ABI can only work with 64-bit integer registers.  We
787
   generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
788
   otherwise floating-point registers must also be 64-bit.  */
789
#define ABI_NEEDS_64BIT_REGS    (TARGET_NEWABI || mips_abi == ABI_O64)
790
 
791
/* Likewise for 32-bit regs.  */
792
#define ABI_NEEDS_32BIT_REGS    (mips_abi == ABI_32)
793
 
794
/* True if the file format uses 64-bit symbols.  At present, this is
795
   only true for n64, which uses 64-bit ELF.  */
796
#define FILE_HAS_64BIT_SYMBOLS  (mips_abi == ABI_64)
797
 
798
/* True if symbols are 64 bits wide.  This is usually determined by
799
   the ABI's file format, but it can be overridden by -msym32.  Note that
800
   overriding the size with -msym32 changes the ABI of relocatable objects,
801
   although it doesn't change the ABI of a fully-linked object.  */
802
#define ABI_HAS_64BIT_SYMBOLS   (FILE_HAS_64BIT_SYMBOLS \
803
                                 && Pmode == DImode     \
804
                                 && !TARGET_SYM32)
805
 
806
/* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3).  */
807
#define ISA_HAS_64BIT_REGS      (ISA_MIPS3                              \
808
                                 || ISA_MIPS4                           \
809
                                 || ISA_MIPS64                          \
810
                                 || ISA_MIPS64R2)
811
 
812
/* ISA has branch likely instructions (e.g. mips2).  */
813
/* Disable branchlikely for tx39 until compare rewrite.  They haven't
814
   been generated up to this point.  */
815
#define ISA_HAS_BRANCHLIKELY    (!ISA_MIPS1)
816
 
817
/* ISA has a three-operand multiplication instruction (usually spelt "mul").  */
818
#define ISA_HAS_MUL3            ((TARGET_MIPS3900                       \
819
                                  || TARGET_MIPS5400                    \
820
                                  || TARGET_MIPS5500                    \
821
                                  || TARGET_MIPS7000                    \
822
                                  || TARGET_MIPS9000                    \
823
                                  || TARGET_MAD                         \
824
                                  || ISA_MIPS32                         \
825
                                  || ISA_MIPS32R2                       \
826
                                  || ISA_MIPS64                         \
827
                                  || ISA_MIPS64R2)                      \
828
                                 && !TARGET_MIPS16)
829
 
830
/* ISA has a three-operand multiplication instruction.  */
831
#define ISA_HAS_DMUL3           (TARGET_64BIT                           \
832
                                 && TARGET_OCTEON                       \
833
                                 && !TARGET_MIPS16)
834
 
835
/* ISA has the floating-point conditional move instructions introduced
836
   in mips4.  */
837
#define ISA_HAS_FP_CONDMOVE     ((ISA_MIPS4                             \
838
                                  || ISA_MIPS32                         \
839
                                  || ISA_MIPS32R2                       \
840
                                  || ISA_MIPS64                         \
841
                                  || ISA_MIPS64R2)                      \
842
                                 && !TARGET_MIPS5500                    \
843
                                 && !TARGET_MIPS16)
844
 
845
/* ISA has the integer conditional move instructions introduced in mips4 and
846
   ST Loongson 2E/2F.  */
847
#define ISA_HAS_CONDMOVE        (ISA_HAS_FP_CONDMOVE || TARGET_LOONGSON_2EF)
848
 
849
/* ISA has LDC1 and SDC1.  */
850
#define ISA_HAS_LDC1_SDC1       (!ISA_MIPS1 && !TARGET_MIPS16)
851
 
852
/* ISA has the mips4 FP condition code instructions: FP-compare to CC,
853
   branch on CC, and move (both FP and non-FP) on CC.  */
854
#define ISA_HAS_8CC             (ISA_MIPS4                              \
855
                                 || ISA_MIPS32                          \
856
                                 || ISA_MIPS32R2                        \
857
                                 || ISA_MIPS64                          \
858
                                 || ISA_MIPS64R2)
859
 
860
/* This is a catch all for other mips4 instructions: indexed load, the
861
   FP madd and msub instructions, and the FP recip and recip sqrt
862
   instructions.  */
863
#define ISA_HAS_FP4             ((ISA_MIPS4                             \
864
                                  || (ISA_MIPS32R2 && TARGET_FLOAT64)   \
865
                                  || ISA_MIPS64                         \
866
                                  || ISA_MIPS64R2)                      \
867
                                 && !TARGET_MIPS16)
868
 
869
/* ISA has paired-single instructions.  */
870
#define ISA_HAS_PAIRED_SINGLE   (ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2)
871
 
872
/* ISA has conditional trap instructions.  */
873
#define ISA_HAS_COND_TRAP       (!ISA_MIPS1                             \
874
                                 && !TARGET_MIPS16)
875
 
876
/* ISA has integer multiply-accumulate instructions, madd and msub.  */
877
#define ISA_HAS_MADD_MSUB       ((ISA_MIPS32                            \
878
                                  || ISA_MIPS32R2                       \
879
                                  || ISA_MIPS64                         \
880
                                  || ISA_MIPS64R2)                      \
881
                                 && !TARGET_MIPS16)
882
 
883
/* Integer multiply-accumulate instructions should be generated.  */
884
#define GENERATE_MADD_MSUB      (ISA_HAS_MADD_MSUB && !TUNE_74K)
885
 
886
/* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'.  */
887
#define ISA_HAS_FP_MADD4_MSUB4  ISA_HAS_FP4
888
 
889
/* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'.  */
890
#define ISA_HAS_FP_MADD3_MSUB3  TARGET_LOONGSON_2EF
891
 
892
/* ISA has floating-point nmadd and nmsub instructions
893
   'd = -((a * b) [+-] c)'.  */
894
#define ISA_HAS_NMADD4_NMSUB4(MODE)                                     \
895
                                ((ISA_MIPS4                             \
896
                                  || (ISA_MIPS32R2 && (MODE) == V2SFmode) \
897
                                  || ISA_MIPS64                         \
898
                                  || ISA_MIPS64R2)                      \
899
                                 && (!TARGET_MIPS5400 || TARGET_MAD)    \
900
                                 && !TARGET_MIPS16)
901
 
902
/* ISA has floating-point nmadd and nmsub instructions
903
   'c = -((a * b) [+-] c)'.  */
904
#define ISA_HAS_NMADD3_NMSUB3(MODE)                                     \
905
                                TARGET_LOONGSON_2EF
906
 
907
/* ISA has count leading zeroes/ones instruction (not implemented).  */
908
#define ISA_HAS_CLZ_CLO         ((ISA_MIPS32                            \
909
                                  || ISA_MIPS32R2                       \
910
                                  || ISA_MIPS64                         \
911
                                  || ISA_MIPS64R2)                      \
912
                                 && !TARGET_MIPS16)
913
 
914
/* ISA has three operand multiply instructions that put
915
   the high part in an accumulator: mulhi or mulhiu.  */
916
#define ISA_HAS_MULHI           ((TARGET_MIPS5400                        \
917
                                  || TARGET_MIPS5500                     \
918
                                  || TARGET_SR71K)                       \
919
                                 && !TARGET_MIPS16)
920
 
921
/* ISA has three operand multiply instructions that
922
   negates the result and puts the result in an accumulator.  */
923
#define ISA_HAS_MULS            ((TARGET_MIPS5400                       \
924
                                  || TARGET_MIPS5500                    \
925
                                  || TARGET_SR71K)                      \
926
                                 && !TARGET_MIPS16)
927
 
928
/* ISA has three operand multiply instructions that subtracts the
929
   result from a 4th operand and puts the result in an accumulator.  */
930
#define ISA_HAS_MSAC            ((TARGET_MIPS5400                       \
931
                                  || TARGET_MIPS5500                    \
932
                                  || TARGET_SR71K)                      \
933
                                 && !TARGET_MIPS16)
934
 
935
/* ISA has three operand multiply instructions that  the result
936
   from a 4th operand and puts the result in an accumulator.  */
937
#define ISA_HAS_MACC            ((TARGET_MIPS4120                       \
938
                                  || TARGET_MIPS4130                    \
939
                                  || TARGET_MIPS5400                    \
940
                                  || TARGET_MIPS5500                    \
941
                                  || TARGET_SR71K)                      \
942
                                 && !TARGET_MIPS16)
943
 
944
/* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions.  */
945
#define ISA_HAS_MACCHI          ((TARGET_MIPS4120                       \
946
                                  || TARGET_MIPS4130)                   \
947
                                 && !TARGET_MIPS16)
948
 
949
/* ISA has the "ror" (rotate right) instructions.  */
950
#define ISA_HAS_ROR             ((ISA_MIPS32R2                          \
951
                                  || ISA_MIPS64R2                       \
952
                                  || TARGET_MIPS5400                    \
953
                                  || TARGET_MIPS5500                    \
954
                                  || TARGET_SR71K                       \
955
                                  || TARGET_SMARTMIPS)                  \
956
                                 && !TARGET_MIPS16)
957
 
958
/* ISA has data prefetch instructions.  This controls use of 'pref'.  */
959
#define ISA_HAS_PREFETCH        ((ISA_MIPS4                             \
960
                                  || TARGET_LOONGSON_2EF                \
961
                                  || ISA_MIPS32                         \
962
                                  || ISA_MIPS32R2                       \
963
                                  || ISA_MIPS64                         \
964
                                  || ISA_MIPS64R2)                      \
965
                                 && !TARGET_MIPS16)
966
 
967
/* ISA has data indexed prefetch instructions.  This controls use of
968
   'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
969
   (prefx is a cop1x instruction, so can only be used if FP is
970
   enabled.)  */
971
#define ISA_HAS_PREFETCHX       ((ISA_MIPS4                             \
972
                                  || ISA_MIPS32R2                       \
973
                                  || ISA_MIPS64                         \
974
                                  || ISA_MIPS64R2)                      \
975
                                 && !TARGET_MIPS16)
976
 
977
/* True if trunc.w.s and trunc.w.d are real (not synthetic)
978
   instructions.  Both require TARGET_HARD_FLOAT, and trunc.w.d
979
   also requires TARGET_DOUBLE_FLOAT.  */
980
#define ISA_HAS_TRUNC_W         (!ISA_MIPS1)
981
 
982
/* ISA includes the MIPS32r2 seb and seh instructions.  */
983
#define ISA_HAS_SEB_SEH         ((ISA_MIPS32R2          \
984
                                  || ISA_MIPS64R2)      \
985
                                 && !TARGET_MIPS16)
986
 
987
/* ISA includes the MIPS32/64 rev 2 ext and ins instructions.  */
988
#define ISA_HAS_EXT_INS         ((ISA_MIPS32R2          \
989
                                  || ISA_MIPS64R2)      \
990
                                 && !TARGET_MIPS16)
991
 
992
/* ISA has instructions for accessing top part of 64-bit fp regs.  */
993
#define ISA_HAS_MXHC1           (TARGET_FLOAT64         \
994
                                 && (ISA_MIPS32R2       \
995
                                     || ISA_MIPS64R2))
996
 
997
/* ISA has lwxs instruction (load w/scaled index address.  */
998
#define ISA_HAS_LWXS            (TARGET_SMARTMIPS && !TARGET_MIPS16)
999
 
1000
/* ISA has lbx, lbux, lhx, lhx, lhux, lwx, lwux, or ldx instruction. */
1001
#define ISA_HAS_LBX             (TARGET_OCTEON2)
1002
#define ISA_HAS_LBUX            (ISA_HAS_DSP || TARGET_OCTEON2)
1003
#define ISA_HAS_LHX             (ISA_HAS_DSP || TARGET_OCTEON2)
1004
#define ISA_HAS_LHUX            (TARGET_OCTEON2)
1005
#define ISA_HAS_LWX             (ISA_HAS_DSP || TARGET_OCTEON2)
1006
#define ISA_HAS_LWUX            (TARGET_OCTEON2 && TARGET_64BIT)
1007
#define ISA_HAS_LDX             ((ISA_HAS_DSP || TARGET_OCTEON2) \
1008
                                 && TARGET_64BIT)
1009
 
1010
/* The DSP ASE is available.  */
1011
#define ISA_HAS_DSP             (TARGET_DSP && !TARGET_MIPS16)
1012
 
1013
/* Revision 2 of the DSP ASE is available.  */
1014
#define ISA_HAS_DSPR2           (TARGET_DSPR2 && !TARGET_MIPS16)
1015
 
1016
/* True if the result of a load is not available to the next instruction.
1017
   A nop will then be needed between instructions like "lw $4,..."
1018
   and "addiu $4,$4,1".  */
1019
#define ISA_HAS_LOAD_DELAY      (ISA_MIPS1                              \
1020
                                 && !TARGET_MIPS3900                    \
1021
                                 && !TARGET_MIPS16)
1022
 
1023
/* Likewise mtc1 and mfc1.  */
1024
#define ISA_HAS_XFER_DELAY      (mips_isa <= 3                  \
1025
                                 && !TARGET_LOONGSON_2EF)
1026
 
1027
/* Likewise floating-point comparisons.  */
1028
#define ISA_HAS_FCMP_DELAY      (mips_isa <= 3                  \
1029
                                 && !TARGET_LOONGSON_2EF)
1030
 
1031
/* True if mflo and mfhi can be immediately followed by instructions
1032
   which write to the HI and LO registers.
1033
 
1034
   According to MIPS specifications, MIPS ISAs I, II, and III need
1035
   (at least) two instructions between the reads of HI/LO and
1036
   instructions which write them, and later ISAs do not.  Contradicting
1037
   the MIPS specifications, some MIPS IV processor user manuals (e.g.
1038
   the UM for the NEC Vr5000) document needing the instructions between
1039
   HI/LO reads and writes, as well.  Therefore, we declare only MIPS32,
1040
   MIPS64 and later ISAs to have the interlocks, plus any specific
1041
   earlier-ISA CPUs for which CPU documentation declares that the
1042
   instructions are really interlocked.  */
1043
#define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32                             \
1044
                                 || ISA_MIPS32R2                        \
1045
                                 || ISA_MIPS64                          \
1046
                                 || ISA_MIPS64R2                        \
1047
                                 || TARGET_MIPS5500                     \
1048
                                 || TARGET_LOONGSON_2EF)
1049
 
1050
/* ISA includes synci, jr.hb and jalr.hb.  */
1051
#define ISA_HAS_SYNCI ((ISA_MIPS32R2            \
1052
                        || ISA_MIPS64R2)        \
1053
                       && !TARGET_MIPS16)
1054
 
1055
/* ISA includes sync.  */
1056
#define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
1057
#define GENERATE_SYNC                   \
1058
  (target_flags_explicit & MASK_LLSC    \
1059
   ? TARGET_LLSC && !TARGET_MIPS16      \
1060
   : ISA_HAS_SYNC)
1061
 
1062
/* ISA includes ll and sc.  Note that this implies ISA_HAS_SYNC
1063
   because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
1064
   instructions.  */
1065
#define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS16)
1066
#define GENERATE_LL_SC                  \
1067
  (target_flags_explicit & MASK_LLSC    \
1068
   ? TARGET_LLSC && !TARGET_MIPS16      \
1069
   : ISA_HAS_LL_SC)
1070
 
1071
/* ISA includes the baddu instruction.  */
1072
#define ISA_HAS_BADDU           (TARGET_OCTEON && !TARGET_MIPS16)
1073
 
1074
/* ISA includes the bbit* instructions.  */
1075
#define ISA_HAS_BBIT            (TARGET_OCTEON && !TARGET_MIPS16)
1076
 
1077
/* ISA includes the cins instruction.  */
1078
#define ISA_HAS_CINS            (TARGET_OCTEON && !TARGET_MIPS16)
1079
 
1080
/* ISA includes the exts instruction.  */
1081
#define ISA_HAS_EXTS            (TARGET_OCTEON && !TARGET_MIPS16)
1082
 
1083
/* ISA includes the seq and sne instructions.  */
1084
#define ISA_HAS_SEQ_SNE         (TARGET_OCTEON && !TARGET_MIPS16)
1085
 
1086
/* ISA includes the pop instruction.  */
1087
#define ISA_HAS_POP             (TARGET_OCTEON && !TARGET_MIPS16)
1088
 
1089
/* The CACHE instruction is available in non-MIPS16 code.  */
1090
#define TARGET_CACHE_BUILTIN (mips_isa >= 3)
1091
 
1092
/* The CACHE instruction is available.  */
1093
#define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16)
1094
 
1095
/* Tell collect what flags to pass to nm.  */
1096
#ifndef NM_FLAGS
1097
#define NM_FLAGS "-Bn"
1098
#endif
1099
 
1100
 
1101
/* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1102
   the assembler.  It may be overridden by subtargets.
1103
 
1104
   Beginning with gas 2.13, -mdebug must be passed to correctly handle
1105
   COFF debugging info.  */
1106
 
1107
#ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1108
#define SUBTARGET_ASM_DEBUGGING_SPEC "\
1109
%{g} %{g0} %{g1} %{g2} %{g3} \
1110
%{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1111
%{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1112
%{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1113
%{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1114
%{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
1115
#endif
1116
 
1117
/* SUBTARGET_ASM_SPEC is always passed to the assembler.  It may be
1118
   overridden by subtargets.  */
1119
 
1120
#ifndef SUBTARGET_ASM_SPEC
1121
#define SUBTARGET_ASM_SPEC ""
1122
#endif
1123
 
1124
#undef ASM_SPEC
1125
#define ASM_SPEC "\
1126
%{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1127
%{mips32*} %{mips64*} \
1128
%{mips16} %{mno-mips16:-no-mips16} \
1129
%{mips3d} %{mno-mips3d:-no-mips3d} \
1130
%{mdmx} %{mno-mdmx:-no-mdmx} \
1131
%{mdsp} %{mno-dsp} \
1132
%{mdspr2} %{mno-dspr2} \
1133
%{msmartmips} %{mno-smartmips} \
1134
%{mmt} %{mno-mt} \
1135
%{mfix-vr4120} %{mfix-vr4130} \
1136
%{mfix-24k} \
1137
%{noasmopt:-O0; O0|fno-delayed-branch:-O1; O*:-O2; :-O1} \
1138
%(subtarget_asm_debugging_spec) \
1139
%{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \
1140
%{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1141
%{mfp32} %{mfp64} \
1142
%{mshared} %{mno-shared} \
1143
%{msym32} %{mno-sym32} \
1144
%{mtune=*} \
1145
%(subtarget_asm_spec)"
1146
 
1147
/* Extra switches sometimes passed to the linker.  */
1148
 
1149
#ifndef LINK_SPEC
1150
#define LINK_SPEC "\
1151
%(endian_spec) \
1152
%{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \
1153
%{shared}"
1154
#endif  /* LINK_SPEC defined */
1155
 
1156
 
1157
/* Specs for the compiler proper */
1158
 
1159
/* SUBTARGET_CC1_SPEC is passed to the compiler proper.  It may be
1160
   overridden by subtargets.  */
1161
#ifndef SUBTARGET_CC1_SPEC
1162
#define SUBTARGET_CC1_SPEC ""
1163
#endif
1164
 
1165
/* CC1_SPEC is the set of arguments to pass to the compiler proper.  */
1166
 
1167
#undef CC1_SPEC
1168
#define CC1_SPEC "\
1169
%{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1170
%(subtarget_cc1_spec)"
1171
 
1172
/* Preprocessor specs.  */
1173
 
1174
/* SUBTARGET_CPP_SPEC is passed to the preprocessor.  It may be
1175
   overridden by subtargets.  */
1176
#ifndef SUBTARGET_CPP_SPEC
1177
#define SUBTARGET_CPP_SPEC ""
1178
#endif
1179
 
1180
#define CPP_SPEC "%(subtarget_cpp_spec)"
1181
 
1182
/* This macro defines names of additional specifications to put in the specs
1183
   that can be used in various specifications like CC1_SPEC.  Its definition
1184
   is an initializer with a subgrouping for each command option.
1185
 
1186
   Each subgrouping contains a string constant, that defines the
1187
   specification name, and a string constant that used by the GCC driver
1188
   program.
1189
 
1190
   Do not define this macro if it does not need to do anything.  */
1191
 
1192
#define EXTRA_SPECS                                                     \
1193
  { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC },                         \
1194
  { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC },                         \
1195
  { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC },     \
1196
  { "subtarget_asm_spec", SUBTARGET_ASM_SPEC },                         \
1197
  { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT },                 \
1198
  { "endian_spec", ENDIAN_SPEC },                                       \
1199
  SUBTARGET_EXTRA_SPECS
1200
 
1201
#ifndef SUBTARGET_EXTRA_SPECS
1202
#define SUBTARGET_EXTRA_SPECS
1203
#endif
1204
 
1205
#define DBX_DEBUGGING_INFO 1            /* generate stabs (OSF/rose) */
1206
#define DWARF2_DEBUGGING_INFO 1         /* dwarf2 debugging info */
1207
 
1208
#ifndef PREFERRED_DEBUGGING_TYPE
1209
#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1210
#endif
1211
 
1212
/* The size of DWARF addresses should be the same as the size of symbols
1213
   in the target file format.  They shouldn't depend on things like -msym32,
1214
   because many DWARF consumers do not allow the mixture of address sizes
1215
   that one would then get from linking -msym32 code with -msym64 code.
1216
 
1217
   Note that the default POINTER_SIZE test is not appropriate for MIPS.
1218
   EABI64 has 64-bit pointers but uses 32-bit ELF.  */
1219
#define DWARF2_ADDR_SIZE (FILE_HAS_64BIT_SYMBOLS ? 8 : 4)
1220
 
1221
/* By default, turn on GDB extensions.  */
1222
#define DEFAULT_GDB_EXTENSIONS 1
1223
 
1224
/* Local compiler-generated symbols must have a prefix that the assembler
1225
   understands.   By default, this is $, although some targets (e.g.,
1226
   NetBSD-ELF) need to override this.  */
1227
 
1228
#ifndef LOCAL_LABEL_PREFIX
1229
#define LOCAL_LABEL_PREFIX      "$"
1230
#endif
1231
 
1232
/* By default on the mips, external symbols do not have an underscore
1233
   prepended, but some targets (e.g., NetBSD) require this.  */
1234
 
1235
#ifndef USER_LABEL_PREFIX
1236
#define USER_LABEL_PREFIX       ""
1237
#endif
1238
 
1239
/* On Sun 4, this limit is 2048.  We use 1500 to be safe,
1240
   since the length can run past this up to a continuation point.  */
1241
#undef DBX_CONTIN_LENGTH
1242
#define DBX_CONTIN_LENGTH 1500
1243
 
1244
/* How to renumber registers for dbx and gdb.  */
1245
#define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1246
 
1247
/* The mapping from gcc register number to DWARF 2 CFA column number.  */
1248
#define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1249
 
1250
/* The DWARF 2 CFA column which tracks the return address.  */
1251
#define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
1252
 
1253
/* Before the prologue, RA lives in r31.  */
1254
#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM)
1255
 
1256
/* Describe how we implement __builtin_eh_return.  */
1257
#define EH_RETURN_DATA_REGNO(N) \
1258
  ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1259
 
1260
#define EH_RETURN_STACKADJ_RTX  gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1261
 
1262
#define EH_USES(N) mips_eh_uses (N)
1263
 
1264
/* Offsets recorded in opcodes are a multiple of this alignment factor.
1265
   The default for this in 64-bit mode is 8, which causes problems with
1266
   SFmode register saves.  */
1267
#define DWARF_CIE_DATA_ALIGNMENT -4
1268
 
1269
/* Correct the offset of automatic variables and arguments.  Note that
1270
   the MIPS debug format wants all automatic variables and arguments
1271
   to be in terms of the virtual frame pointer (stack pointer before
1272
   any adjustment in the function), while the MIPS 3.0 linker wants
1273
   the frame pointer to be the stack pointer after the initial
1274
   adjustment.  */
1275
 
1276
#define DEBUGGER_AUTO_OFFSET(X)                         \
1277
  mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1278
#define DEBUGGER_ARG_OFFSET(OFFSET, X)                  \
1279
  mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1280
 
1281
/* Target machine storage layout */
1282
 
1283
#define BITS_BIG_ENDIAN 0
1284
#define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1285
#define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1286
 
1287
#define MAX_BITS_PER_WORD 64
1288
 
1289
/* Width of a word, in units (bytes).  */
1290
#define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1291
#ifndef IN_LIBGCC2
1292
#define MIN_UNITS_PER_WORD 4
1293
#endif
1294
 
1295
/* For MIPS, width of a floating point register.  */
1296
#define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1297
 
1298
/* The number of consecutive floating-point registers needed to store the
1299
   largest format supported by the FPU.  */
1300
#define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1301
 
1302
/* The number of consecutive floating-point registers needed to store the
1303
   smallest format supported by the FPU.  */
1304
#define MIN_FPRS_PER_FMT \
1305
  (ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2 \
1306
   ? 1 : MAX_FPRS_PER_FMT)
1307
 
1308
/* The largest size of value that can be held in floating-point
1309
   registers and moved with a single instruction.  */
1310
#define UNITS_PER_HWFPVALUE \
1311
  (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1312
 
1313
/* The largest size of value that can be held in floating-point
1314
   registers.  */
1315
#define UNITS_PER_FPVALUE                       \
1316
  (TARGET_SOFT_FLOAT_ABI ? 0                    \
1317
   : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG      \
1318
   : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1319
 
1320
/* The number of bytes in a double.  */
1321
#define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1322
 
1323
/* Set the sizes of the core types.  */
1324
#define SHORT_TYPE_SIZE 16
1325
#define INT_TYPE_SIZE 32
1326
#define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1327
#define LONG_LONG_TYPE_SIZE 64
1328
 
1329
#define FLOAT_TYPE_SIZE 32
1330
#define DOUBLE_TYPE_SIZE 64
1331
#define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1332
 
1333
/* Define the sizes of fixed-point types.  */
1334
#define SHORT_FRACT_TYPE_SIZE 8
1335
#define FRACT_TYPE_SIZE 16
1336
#define LONG_FRACT_TYPE_SIZE 32
1337
#define LONG_LONG_FRACT_TYPE_SIZE 64
1338
 
1339
#define SHORT_ACCUM_TYPE_SIZE 16
1340
#define ACCUM_TYPE_SIZE 32
1341
#define LONG_ACCUM_TYPE_SIZE 64
1342
/* FIXME.  LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1343
   doesn't support 128-bit integers for MIPS32 currently.  */
1344
#define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1345
 
1346
/* long double is not a fixed mode, but the idea is that, if we
1347
   support long double, we also want a 128-bit integer type.  */
1348
#define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1349
 
1350
#ifdef IN_LIBGCC2
1351
#if  (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1352
  || (defined _ABI64 && _MIPS_SIM == _ABI64)
1353
#  define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1354
# else
1355
#  define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1356
# endif
1357
#endif
1358
 
1359
/* Width in bits of a pointer.  */
1360
#ifndef POINTER_SIZE
1361
#define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1362
#endif
1363
 
1364
/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
1365
#define PARM_BOUNDARY BITS_PER_WORD
1366
 
1367
/* Allocation boundary (in *bits*) for the code of a function.  */
1368
#define FUNCTION_BOUNDARY 32
1369
 
1370
/* Alignment of field after `int : 0' in a structure.  */
1371
#define EMPTY_FIELD_BOUNDARY 32
1372
 
1373
/* Every structure's size must be a multiple of this.  */
1374
/* 8 is observed right on a DECstation and on riscos 4.02.  */
1375
#define STRUCTURE_SIZE_BOUNDARY 8
1376
 
1377
/* There is no point aligning anything to a rounder boundary than this.  */
1378
#define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1379
 
1380
/* All accesses must be aligned.  */
1381
#define STRICT_ALIGNMENT 1
1382
 
1383
/* Define this if you wish to imitate the way many other C compilers
1384
   handle alignment of bitfields and the structures that contain
1385
   them.
1386
 
1387
   The behavior is that the type written for a bit-field (`int',
1388
   `short', or other integer type) imposes an alignment for the
1389
   entire structure, as if the structure really did contain an
1390
   ordinary field of that type.  In addition, the bit-field is placed
1391
   within the structure so that it would fit within such a field,
1392
   not crossing a boundary for it.
1393
 
1394
   Thus, on most machines, a bit-field whose type is written as `int'
1395
   would not cross a four-byte boundary, and would force four-byte
1396
   alignment for the whole structure.  (The alignment used may not
1397
   be four bytes; it is controlled by the other alignment
1398
   parameters.)
1399
 
1400
   If the macro is defined, its definition should be a C expression;
1401
   a nonzero value for the expression enables this behavior.  */
1402
 
1403
#define PCC_BITFIELD_TYPE_MATTERS 1
1404
 
1405
/* If defined, a C expression to compute the alignment given to a
1406
   constant that is being placed in memory.  CONSTANT is the constant
1407
   and ALIGN is the alignment that the object would ordinarily have.
1408
   The value of this macro is used instead of that alignment to align
1409
   the object.
1410
 
1411
   If this macro is not defined, then ALIGN is used.
1412
 
1413
   The typical use of this macro is to increase alignment for string
1414
   constants to be word aligned so that `strcpy' calls that copy
1415
   constants can be done inline.  */
1416
 
1417
#define CONSTANT_ALIGNMENT(EXP, ALIGN)                                  \
1418
  ((TREE_CODE (EXP) == STRING_CST  || TREE_CODE (EXP) == CONSTRUCTOR)   \
1419
   && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1420
 
1421
/* If defined, a C expression to compute the alignment for a static
1422
   variable.  TYPE is the data type, and ALIGN is the alignment that
1423
   the object would ordinarily have.  The value of this macro is used
1424
   instead of that alignment to align the object.
1425
 
1426
   If this macro is not defined, then ALIGN is used.
1427
 
1428
   One use of this macro is to increase alignment of medium-size
1429
   data to make it all fit in fewer cache lines.  Another is to
1430
   cause character arrays to be word-aligned so that `strcpy' calls
1431
   that copy constants to character arrays can be done inline.  */
1432
 
1433
#undef DATA_ALIGNMENT
1434
#define DATA_ALIGNMENT(TYPE, ALIGN)                                     \
1435
  ((((ALIGN) < BITS_PER_WORD)                                           \
1436
    && (TREE_CODE (TYPE) == ARRAY_TYPE                                  \
1437
        || TREE_CODE (TYPE) == UNION_TYPE                               \
1438
        || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1439
 
1440
/* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1441
   character arrays to be word-aligned so that `strcpy' calls that copy
1442
   constants to character arrays can be done inline, and 'strcmp' can be
1443
   optimised to use word loads. */
1444
#define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1445
  DATA_ALIGNMENT (TYPE, ALIGN)
1446
 
1447
#define PAD_VARARGS_DOWN \
1448
  (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1449
 
1450
/* Define if operations between registers always perform the operation
1451
   on the full register even if a narrower mode is specified.  */
1452
#define WORD_REGISTER_OPERATIONS
1453
 
1454
/* When in 64-bit mode, move insns will sign extend SImode and CCmode
1455
   moves.  All other references are zero extended.  */
1456
#define LOAD_EXTEND_OP(MODE) \
1457
  (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1458
   ? SIGN_EXTEND : ZERO_EXTEND)
1459
 
1460
/* Define this macro if it is advisable to hold scalars in registers
1461
   in a wider mode than that declared by the program.  In such cases,
1462
   the value is constrained to be within the bounds of the declared
1463
   type, but kept valid in the wider mode.  The signedness of the
1464
   extension may differ from that of the type.  */
1465
 
1466
#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)     \
1467
  if (GET_MODE_CLASS (MODE) == MODE_INT         \
1468
      && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1469
    {                                           \
1470
      if ((MODE) == SImode)                     \
1471
        (UNSIGNEDP) = 0;                        \
1472
      (MODE) = Pmode;                           \
1473
    }
1474
 
1475
/* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1476
   Extensions of pointers to word_mode must be signed.  */
1477
#define POINTERS_EXTEND_UNSIGNED false
1478
 
1479
/* Define if loading short immediate values into registers sign extends.  */
1480
#define SHORT_IMMEDIATES_SIGN_EXTEND
1481
 
1482
/* The [d]clz instructions have the natural values at 0.  */
1483
 
1484
#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1485
  ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1486
 
1487
/* Standard register usage.  */
1488
 
1489
/* Number of hardware registers.  We have:
1490
 
1491
   - 32 integer registers
1492
   - 32 floating point registers
1493
   - 8 condition code registers
1494
   - 2 accumulator registers (hi and lo)
1495
   - 32 registers each for coprocessors 0, 2 and 3
1496
   - 4 fake registers:
1497
        - ARG_POINTER_REGNUM
1498
        - FRAME_POINTER_REGNUM
1499
        - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
1500
        - CPRESTORE_SLOT_REGNUM
1501
   - 2 dummy entries that were used at various times in the past.
1502
   - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1503
   - 6 DSP control registers  */
1504
 
1505
#define FIRST_PSEUDO_REGISTER 188
1506
 
1507
/* By default, fix the kernel registers ($26 and $27), the global
1508
   pointer ($28) and the stack pointer ($29).  This can change
1509
   depending on the command-line options.
1510
 
1511
   Regarding coprocessor registers: without evidence to the contrary,
1512
   it's best to assume that each coprocessor register has a unique
1513
   use.  This can be overridden, in, e.g., mips_option_override or
1514
   TARGET_CONDITIONAL_REGISTER_USAGE should the assumption be
1515
   inappropriate for a particular target.  */
1516
 
1517
#define FIXED_REGISTERS                                                 \
1518
{                                                                       \
1519
  1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
1520
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0,                       \
1521
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
1522
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
1523
  0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1,                       \
1524
  /* COP0 registers */                                                  \
1525
  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
1526
  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
1527
  /* COP2 registers */                                                  \
1528
  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
1529
  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
1530
  /* COP3 registers */                                                  \
1531
  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
1532
  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
1533
  /* 6 DSP accumulator registers & 6 control registers */               \
1534
  0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1                                    \
1535
}
1536
 
1537
 
1538
/* Set up this array for o32 by default.
1539
 
1540
   Note that we don't mark $31 as a call-clobbered register.  The idea is
1541
   that it's really the call instructions themselves which clobber $31.
1542
   We don't care what the called function does with it afterwards.
1543
 
1544
   This approach makes it easier to implement sibcalls.  Unlike normal
1545
   calls, sibcalls don't clobber $31, so the register reaches the
1546
   called function in tact.  EPILOGUE_USES says that $31 is useful
1547
   to the called function.  */
1548
 
1549
#define CALL_USED_REGISTERS                                             \
1550
{                                                                       \
1551
  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
1552
  0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0,                       \
1553
  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
1554
  1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
1555
  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
1556
  /* COP0 registers */                                                  \
1557
  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
1558
  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
1559
  /* COP2 registers */                                                  \
1560
  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
1561
  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
1562
  /* COP3 registers */                                                  \
1563
  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
1564
  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
1565
  /* 6 DSP accumulator registers & 6 control registers */               \
1566
  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1                                    \
1567
}
1568
 
1569
 
1570
/* Define this since $28, though fixed, is call-saved in many ABIs.  */
1571
 
1572
#define CALL_REALLY_USED_REGISTERS                                      \
1573
{ /* General registers.  */                                             \
1574
  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
1575
  0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0,                       \
1576
  /* Floating-point registers.  */                                      \
1577
  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
1578
  1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
1579
  /* Others.  */                                                        \
1580
  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,                       \
1581
  /* COP0 registers */                                                  \
1582
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
1583
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
1584
  /* COP2 registers */                                                  \
1585
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
1586
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
1587
  /* COP3 registers */                                                  \
1588
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
1589
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
1590
  /* 6 DSP accumulator registers & 6 control registers */               \
1591
  1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0                                    \
1592
}
1593
 
1594
/* Internal macros to classify a register number as to whether it's a
1595
   general purpose register, a floating point register, a
1596
   multiply/divide register, or a status register.  */
1597
 
1598
#define GP_REG_FIRST 0
1599
#define GP_REG_LAST  31
1600
#define GP_REG_NUM   (GP_REG_LAST - GP_REG_FIRST + 1)
1601
#define GP_DBX_FIRST 0
1602
#define K0_REG_NUM   (GP_REG_FIRST + 26)
1603
#define K1_REG_NUM   (GP_REG_FIRST + 27)
1604
#define KERNEL_REG_P(REGNO)     (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM))
1605
 
1606
#define FP_REG_FIRST 32
1607
#define FP_REG_LAST  63
1608
#define FP_REG_NUM   (FP_REG_LAST - FP_REG_FIRST + 1)
1609
#define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1610
 
1611
#define MD_REG_FIRST 64
1612
#define MD_REG_LAST  65
1613
#define MD_REG_NUM   (MD_REG_LAST - MD_REG_FIRST + 1)
1614
#define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1615
 
1616
/* The DWARF 2 CFA column which tracks the return address from a
1617
   signal handler context.  This means that to maintain backwards
1618
   compatibility, no hard register can be assigned this column if it
1619
   would need to be handled by the DWARF unwinder.  */
1620
#define DWARF_ALT_FRAME_RETURN_COLUMN 66
1621
 
1622
#define ST_REG_FIRST 67
1623
#define ST_REG_LAST  74
1624
#define ST_REG_NUM   (ST_REG_LAST - ST_REG_FIRST + 1)
1625
 
1626
 
1627
/* FIXME: renumber.  */
1628
#define COP0_REG_FIRST 80
1629
#define COP0_REG_LAST 111
1630
#define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1631
 
1632
#define COP0_STATUS_REG_NUM     (COP0_REG_FIRST + 12)
1633
#define COP0_CAUSE_REG_NUM      (COP0_REG_FIRST + 13)
1634
#define COP0_EPC_REG_NUM        (COP0_REG_FIRST + 14)
1635
 
1636
#define COP2_REG_FIRST 112
1637
#define COP2_REG_LAST 143
1638
#define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1639
 
1640
#define COP3_REG_FIRST 144
1641
#define COP3_REG_LAST 175
1642
#define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1643
/* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively.  */
1644
#define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1645
 
1646
#define DSP_ACC_REG_FIRST 176
1647
#define DSP_ACC_REG_LAST 181
1648
#define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1649
 
1650
#define AT_REGNUM       (GP_REG_FIRST + 1)
1651
#define HI_REGNUM       (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1652
#define LO_REGNUM       (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1653
 
1654
/* A few bitfield locations for the coprocessor registers.  */
1655
/* Request Interrupt Priority Level is from bit 10 to bit 15 of
1656
   the cause register for the EIC interrupt mode.  */
1657
#define CAUSE_IPL       10
1658
/* Interrupt Priority Level is from bit 10 to bit 15 of the status register.  */
1659
#define SR_IPL          10
1660
/* Exception Level is at bit 1 of the status register.  */
1661
#define SR_EXL          1
1662
/* Interrupt Enable is at bit 0 of the status register.  */
1663
#define SR_IE           0
1664
 
1665
/* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1666
   If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1667
   should be used instead.  */
1668
#define FPSW_REGNUM     ST_REG_FIRST
1669
 
1670
#define GP_REG_P(REGNO) \
1671
  ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1672
#define M16_REG_P(REGNO) \
1673
  (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1674
#define FP_REG_P(REGNO)  \
1675
  ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1676
#define MD_REG_P(REGNO) \
1677
  ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1678
#define ST_REG_P(REGNO) \
1679
  ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1680
#define COP0_REG_P(REGNO) \
1681
  ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1682
#define COP2_REG_P(REGNO) \
1683
  ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1684
#define COP3_REG_P(REGNO) \
1685
  ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1686
#define ALL_COP_REG_P(REGNO) \
1687
  ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1688
/* Test if REGNO is one of the 6 new DSP accumulators.  */
1689
#define DSP_ACC_REG_P(REGNO) \
1690
  ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1691
/* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators.  */
1692
#define ACC_REG_P(REGNO) \
1693
  (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1694
 
1695
#define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1696
 
1697
/* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)).  This is used
1698
   to initialize the mips16 gp pseudo register.  */
1699
#define CONST_GP_P(X)                           \
1700
  (GET_CODE (X) == CONST                        \
1701
   && GET_CODE (XEXP (X, 0)) == UNSPEC          \
1702
   && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1703
 
1704
/* Return coprocessor number from register number.  */
1705
 
1706
#define COPNUM_AS_CHAR_FROM_REGNUM(REGNO)                               \
1707
  (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2'                  \
1708
   : COP3_REG_P (REGNO) ? '3' : '?')
1709
 
1710
 
1711
#define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1712
 
1713
#define HARD_REGNO_MODE_OK(REGNO, MODE)                                 \
1714
  mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1715
 
1716
#define MODES_TIEABLE_P mips_modes_tieable_p
1717
 
1718
/* Register to use for pushing function arguments.  */
1719
#define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1720
 
1721
/* These two registers don't really exist: they get eliminated to either
1722
   the stack or hard frame pointer.  */
1723
#define ARG_POINTER_REGNUM 77
1724
#define FRAME_POINTER_REGNUM 78
1725
 
1726
/* $30 is not available on the mips16, so we use $17 as the frame
1727
   pointer.  */
1728
#define HARD_FRAME_POINTER_REGNUM \
1729
  (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1730
 
1731
#define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
1732
#define HARD_FRAME_POINTER_IS_ARG_POINTER 0
1733
 
1734
/* Register in which static-chain is passed to a function.  */
1735
#define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15)
1736
 
1737
/* Registers used as temporaries in prologue/epilogue code:
1738
 
1739
   - If a MIPS16 PIC function needs access to _gp, it first loads
1740
     the value into MIPS16_PIC_TEMP and then copies it to $gp.
1741
 
1742
   - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary
1743
     register.  The register must not conflict with MIPS16_PIC_TEMP.
1744
 
1745
   - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary
1746
     register.
1747
 
1748
   If we're generating MIPS16 code, these registers must come from the
1749
   core set of 8.  The prologue registers mustn't conflict with any
1750
   incoming arguments, the static chain pointer, or the frame pointer.
1751
   The epilogue temporary mustn't conflict with the return registers,
1752
   the PIC call register ($25), the frame pointer, the EH stack adjustment,
1753
   or the EH data registers.
1754
 
1755
   If we're generating interrupt handlers, we use K0 as a temporary register
1756
   in prologue/epilogue code.  */
1757
 
1758
#define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2)
1759
#define MIPS_PROLOGUE_TEMP_REGNUM \
1760
  (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3)
1761
#define MIPS_EPILOGUE_TEMP_REGNUM               \
1762
  (cfun->machine->interrupt_handler_p           \
1763
   ? K0_REG_NUM                                 \
1764
   : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1765
 
1766
#define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM)
1767
#define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1768
#define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1769
 
1770
/* Define this macro if it is as good or better to call a constant
1771
   function address than to call an address kept in a register.  */
1772
#define NO_FUNCTION_CSE 1
1773
 
1774
/* The ABI-defined global pointer.  Sometimes we use a different
1775
   register in leaf functions: see PIC_OFFSET_TABLE_REGNUM.  */
1776
#define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1777
 
1778
/* We normally use $28 as the global pointer.  However, when generating
1779
   n32/64 PIC, it is better for leaf functions to use a call-clobbered
1780
   register instead.  They can then avoid saving and restoring $28
1781
   and perhaps avoid using a frame at all.
1782
 
1783
   When a leaf function uses something other than $28, mips_expand_prologue
1784
   will modify pic_offset_table_rtx in place.  Take the register number
1785
   from there after reload.  */
1786
#define PIC_OFFSET_TABLE_REGNUM \
1787
  (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1788
 
1789
/* Define the classes of registers for register constraints in the
1790
   machine description.  Also define ranges of constants.
1791
 
1792
   One of the classes must always be named ALL_REGS and include all hard regs.
1793
   If there is more than one class, another class must be named NO_REGS
1794
   and contain no registers.
1795
 
1796
   The name GENERAL_REGS must be the name of a class (or an alias for
1797
   another name such as ALL_REGS).  This is the class of registers
1798
   that is allowed by "g" or "r" in a register constraint.
1799
   Also, registers outside this class are allocated only when
1800
   instructions express preferences for them.
1801
 
1802
   The classes must be numbered in nondecreasing order; that is,
1803
   a larger-numbered class must never be contained completely
1804
   in a smaller-numbered class.
1805
 
1806
   For any two classes, it is very desirable that there be another
1807
   class that represents their union.  */
1808
 
1809
enum reg_class
1810
{
1811
  NO_REGS,                      /* no registers in set */
1812
  M16_REGS,                     /* mips16 directly accessible registers */
1813
  T_REG,                        /* mips16 T register ($24) */
1814
  M16_T_REGS,                   /* mips16 registers plus T register */
1815
  PIC_FN_ADDR_REG,              /* SVR4 PIC function address register */
1816
  V1_REG,                       /* Register $v1 ($3) used for TLS access.  */
1817
  LEA_REGS,                     /* Every GPR except $25 */
1818
  GR_REGS,                      /* integer registers */
1819
  FP_REGS,                      /* floating point registers */
1820
  MD0_REG,                      /* first multiply/divide register */
1821
  MD1_REG,                      /* second multiply/divide register */
1822
  MD_REGS,                      /* multiply/divide registers (hi/lo) */
1823
  COP0_REGS,                    /* generic coprocessor classes */
1824
  COP2_REGS,
1825
  COP3_REGS,
1826
  ST_REGS,                      /* status registers (fp status) */
1827
  DSP_ACC_REGS,                 /* DSP accumulator registers */
1828
  ACC_REGS,                     /* Hi/Lo and DSP accumulator registers */
1829
  FRAME_REGS,                   /* $arg and $frame */
1830
  GR_AND_MD0_REGS,              /* union classes */
1831
  GR_AND_MD1_REGS,
1832
  GR_AND_MD_REGS,
1833
  GR_AND_ACC_REGS,
1834
  ALL_REGS,                     /* all registers */
1835
  LIM_REG_CLASSES               /* max value + 1 */
1836
};
1837
 
1838
#define N_REG_CLASSES (int) LIM_REG_CLASSES
1839
 
1840
#define GENERAL_REGS GR_REGS
1841
 
1842
/* An initializer containing the names of the register classes as C
1843
   string constants.  These names are used in writing some of the
1844
   debugging dumps.  */
1845
 
1846
#define REG_CLASS_NAMES                                                 \
1847
{                                                                       \
1848
  "NO_REGS",                                                            \
1849
  "M16_REGS",                                                           \
1850
  "T_REG",                                                              \
1851
  "M16_T_REGS",                                                         \
1852
  "PIC_FN_ADDR_REG",                                                    \
1853
  "V1_REG",                                                             \
1854
  "LEA_REGS",                                                           \
1855
  "GR_REGS",                                                            \
1856
  "FP_REGS",                                                            \
1857
  "MD0_REG",                                                            \
1858
  "MD1_REG",                                                            \
1859
  "MD_REGS",                                                            \
1860
  /* coprocessor registers */                                           \
1861
  "COP0_REGS",                                                          \
1862
  "COP2_REGS",                                                          \
1863
  "COP3_REGS",                                                          \
1864
  "ST_REGS",                                                            \
1865
  "DSP_ACC_REGS",                                                       \
1866
  "ACC_REGS",                                                           \
1867
  "FRAME_REGS",                                                         \
1868
  "GR_AND_MD0_REGS",                                                    \
1869
  "GR_AND_MD1_REGS",                                                    \
1870
  "GR_AND_MD_REGS",                                                     \
1871
  "GR_AND_ACC_REGS",                                                    \
1872
  "ALL_REGS"                                                            \
1873
}
1874
 
1875
/* An initializer containing the contents of the register classes,
1876
   as integers which are bit masks.  The Nth integer specifies the
1877
   contents of class N.  The way the integer MASK is interpreted is
1878
   that register R is in the class if `MASK & (1 << R)' is 1.
1879
 
1880
   When the machine has more than 32 registers, an integer does not
1881
   suffice.  Then the integers are replaced by sub-initializers,
1882
   braced groupings containing several integers.  Each
1883
   sub-initializer must be suitable as an initializer for the type
1884
   `HARD_REG_SET' which is defined in `hard-reg-set.h'.  */
1885
 
1886
#define REG_CLASS_CONTENTS                                                                              \
1887
{                                                                                                       \
1888
  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },   /* NO_REGS */           \
1889
  { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },   /* M16_REGS */          \
1890
  { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },   /* T_REG */             \
1891
  { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },   /* M16_T_REGS */        \
1892
  { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },   /* PIC_FN_ADDR_REG */   \
1893
  { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },   /* V1_REG */            \
1894
  { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },   /* LEA_REGS */          \
1895
  { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },   /* GR_REGS */           \
1896
  { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },   /* FP_REGS */           \
1897
  { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 },   /* MD0_REG */           \
1898
  { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 },   /* MD1_REG */           \
1899
  { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 },   /* MD_REGS */           \
1900
  { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 },   /* COP0_REGS */         \
1901
  { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 },   /* COP2_REGS */         \
1902
  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff },   /* COP3_REGS */         \
1903
  { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 },   /* ST_REGS */           \
1904
  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 },   /* DSP_ACC_REGS */      \
1905
  { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 },   /* ACC_REGS */          \
1906
  { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 },   /* FRAME_REGS */        \
1907
  { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 },   /* GR_AND_MD0_REGS */   \
1908
  { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 },   /* GR_AND_MD1_REGS */   \
1909
  { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 },   /* GR_AND_MD_REGS */    \
1910
  { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 },   /* GR_AND_ACC_REGS */   \
1911
  { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff }    /* ALL_REGS */          \
1912
}
1913
 
1914
 
1915
/* A C expression whose value is a register class containing hard
1916
   register REGNO.  In general there is more that one such class;
1917
   choose a class which is "minimal", meaning that no smaller class
1918
   also contains the register.  */
1919
 
1920
#define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1921
 
1922
/* A macro whose definition is the name of the class to which a
1923
   valid base register must belong.  A base register is one used in
1924
   an address which is the register value plus a displacement.  */
1925
 
1926
#define BASE_REG_CLASS  (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1927
 
1928
/* A macro whose definition is the name of the class to which a
1929
   valid index register must belong.  An index register is one used
1930
   in an address where its value is either multiplied by a scale
1931
   factor or added to another register (as well as added to a
1932
   displacement).  */
1933
 
1934
#define INDEX_REG_CLASS NO_REGS
1935
 
1936
/* We generally want to put call-clobbered registers ahead of
1937
   call-saved ones.  (IRA expects this.)  */
1938
 
1939
#define REG_ALLOC_ORDER                                                 \
1940
{ /* Accumulator registers.  When GPRs and accumulators have equal      \
1941
     cost, we generally prefer to use accumulators.  For example,       \
1942
     a division of multiplication result is better allocated to LO,     \
1943
     so that we put the MFLO at the point of use instead of at the      \
1944
     point of definition.  It's also needed if we're to take advantage  \
1945
     of the extra accumulators available with -mdspr2.  In some cases,  \
1946
     it can also help to reduce register pressure.  */                  \
1947
  64, 65,176,177,178,179,180,181,                                       \
1948
  /* Call-clobbered GPRs.  */                                           \
1949
  1,  2,  3,  4,  5,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15,            \
1950
  24, 25, 31,                                                           \
1951
  /* The global pointer.  This is call-clobbered for o32 and o64        \
1952
     abicalls, call-saved for n32 and n64 abicalls, and a program       \
1953
     invariant otherwise.  Putting it between the call-clobbered        \
1954
     and call-saved registers should cope with all eventualities.  */   \
1955
  28,                                                                   \
1956
  /* Call-saved GPRs.  */                                               \
1957
  16, 17, 18, 19, 20, 21, 22, 23, 30,                                   \
1958
  /* GPRs that can never be exposed to the register allocator.  */      \
1959
  0,  26, 27, 29,                                                       \
1960
  /* Call-clobbered FPRs.  */                                           \
1961
  32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,       \
1962
  48, 49, 50, 51,                                                       \
1963
  /* FPRs that are usually call-saved.  The odd ones are actually       \
1964
     call-clobbered for n32, but listing them ahead of the even         \
1965
     registers might encourage the register allocator to fragment       \
1966
     the available FPR pairs.  We need paired FPRs to store long        \
1967
     doubles, so it isn't clear that using a different order            \
1968
     for n32 would be a win.  */                                        \
1969
  52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,                       \
1970
  /* None of the remaining classes have defined call-saved              \
1971
     registers.  */                                                     \
1972
  66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79,               \
1973
  80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95,       \
1974
  96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111,      \
1975
  112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,      \
1976
  128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,      \
1977
  144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,      \
1978
  160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175,      \
1979
  182,183,184,185,186,187                                               \
1980
}
1981
 
1982
/* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
1983
   to be rearranged based on a particular function.  On the mips16, we
1984
   want to allocate $24 (T_REG) before other registers for
1985
   instructions for which it is possible.  */
1986
 
1987
#define ADJUST_REG_ALLOC_ORDER mips_order_regs_for_local_alloc ()
1988
 
1989
/* True if VALUE is an unsigned 6-bit number.  */
1990
 
1991
#define UIMM6_OPERAND(VALUE) \
1992
  (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
1993
 
1994
/* True if VALUE is a signed 10-bit number.  */
1995
 
1996
#define IMM10_OPERAND(VALUE) \
1997
  ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
1998
 
1999
/* True if VALUE is a signed 16-bit number.  */
2000
 
2001
#define SMALL_OPERAND(VALUE) \
2002
  ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
2003
 
2004
/* True if VALUE is an unsigned 16-bit number.  */
2005
 
2006
#define SMALL_OPERAND_UNSIGNED(VALUE) \
2007
  (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
2008
 
2009
/* True if VALUE can be loaded into a register using LUI.  */
2010
 
2011
#define LUI_OPERAND(VALUE)                                      \
2012
  (((VALUE) | 0x7fff0000) == 0x7fff0000                         \
2013
   || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2014
 
2015
/* Return a value X with the low 16 bits clear, and such that
2016
   VALUE - X is a signed 16-bit value.  */
2017
 
2018
#define CONST_HIGH_PART(VALUE) \
2019
  (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2020
 
2021
#define CONST_LOW_PART(VALUE) \
2022
  ((VALUE) - CONST_HIGH_PART (VALUE))
2023
 
2024
#define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2025
#define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2026
#define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2027
 
2028
/* The HI and LO registers can only be reloaded via the general
2029
   registers.  Condition code registers can only be loaded to the
2030
   general registers, and from the floating point registers.  */
2031
 
2032
#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X)                    \
2033
  mips_secondary_reload_class (CLASS, MODE, X, true)
2034
#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X)                   \
2035
  mips_secondary_reload_class (CLASS, MODE, X, false)
2036
 
2037
/* Return the maximum number of consecutive registers
2038
   needed to represent mode MODE in a register of class CLASS.  */
2039
 
2040
#define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2041
 
2042
#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2043
  mips_cannot_change_mode_class (FROM, TO, CLASS)
2044
 
2045
/* Stack layout; function entry, exit and calling.  */
2046
 
2047
#define STACK_GROWS_DOWNWARD
2048
 
2049
#define FRAME_GROWS_DOWNWARD flag_stack_protect
2050
 
2051
/* Size of the area allocated in the frame to save the GP.  */
2052
 
2053
#define MIPS_GP_SAVE_AREA_SIZE \
2054
  (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0)
2055
 
2056
/* The offset of the first local variable from the frame pointer.  See
2057
   mips_compute_frame_info for details about the frame layout.  */
2058
 
2059
#define STARTING_FRAME_OFFSET                           \
2060
  (FRAME_GROWS_DOWNWARD                                 \
2061
   ? 0                                                  \
2062
   : crtl->outgoing_args_size + MIPS_GP_SAVE_AREA_SIZE)
2063
 
2064
#define RETURN_ADDR_RTX mips_return_addr
2065
 
2066
/* Mask off the MIPS16 ISA bit in unwind addresses.
2067
 
2068
   The reason for this is a little subtle.  When unwinding a call,
2069
   we are given the call's return address, which on most targets
2070
   is the address of the following instruction.  However, what we
2071
   actually want to find is the EH region for the call itself.
2072
   The target-independent unwind code therefore searches for "RA - 1".
2073
 
2074
   In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address.
2075
   RA - 1 is therefore the real (even-valued) start of the return
2076
   instruction.  EH region labels are usually odd-valued MIPS16 symbols
2077
   too, so a search for an even address within a MIPS16 region would
2078
   usually work.
2079
 
2080
   However, there is an exception.  If the end of an EH region is also
2081
   the end of a function, the end label is allowed to be even.  This is
2082
   necessary because a following non-MIPS16 function may also need EH
2083
   information for its first instruction.
2084
 
2085
   Thus a MIPS16 region may be terminated by an ISA-encoded or a
2086
   non-ISA-encoded address.  This probably isn't ideal, but it is
2087
   the traditional (legacy) behavior.  It is therefore only safe
2088
   to search MIPS EH regions for an _odd-valued_ address.
2089
 
2090
   Masking off the ISA bit means that the target-independent code
2091
   will search for "(RA & -2) - 1", which is guaranteed to be odd.  */
2092
#define MASK_RETURN_ADDR GEN_INT (-2)
2093
 
2094
 
2095
/* Similarly, don't use the least-significant bit to tell pointers to
2096
   code from vtable index.  */
2097
 
2098
#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2099
 
2100
/* The eliminations to $17 are only used for mips16 code.  See the
2101
   definition of HARD_FRAME_POINTER_REGNUM.  */
2102
 
2103
#define ELIMINABLE_REGS                                                 \
2104
{{ ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM},                         \
2105
 { ARG_POINTER_REGNUM,   GP_REG_FIRST + 30},                            \
2106
 { ARG_POINTER_REGNUM,   GP_REG_FIRST + 17},                            \
2107
 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM},                         \
2108
 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30},                            \
2109
 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2110
 
2111
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2112
  (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2113
 
2114
/* Allocate stack space for arguments at the beginning of each function.  */
2115
#define ACCUMULATE_OUTGOING_ARGS 1
2116
 
2117
/* The argument pointer always points to the first argument.  */
2118
#define FIRST_PARM_OFFSET(FNDECL) 0
2119
 
2120
/* o32 and o64 reserve stack space for all argument registers.  */
2121
#define REG_PARM_STACK_SPACE(FNDECL)                    \
2122
  (TARGET_OLDABI                                        \
2123
   ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD)           \
2124
   : 0)
2125
 
2126
/* Define this if it is the responsibility of the caller to
2127
   allocate the area reserved for arguments passed in registers.
2128
   If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2129
   of this macro is to determine whether the space is included in
2130
   `crtl->outgoing_args_size'.  */
2131
#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
2132
 
2133
#define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
2134
 
2135
/* Symbolic macros for the registers used to return integer and floating
2136
   point values.  */
2137
 
2138
#define GP_RETURN (GP_REG_FIRST + 2)
2139
#define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2140
 
2141
#define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2142
 
2143
/* Symbolic macros for the first/last argument registers.  */
2144
 
2145
#define GP_ARG_FIRST (GP_REG_FIRST + 4)
2146
#define GP_ARG_LAST  (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2147
#define FP_ARG_FIRST (FP_REG_FIRST + 12)
2148
#define FP_ARG_LAST  (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2149
 
2150
/* 1 if N is a possible register number for function argument passing.
2151
   We have no FP argument registers when soft-float.  When FP registers
2152
   are 32 bits, we can't directly reference the odd numbered ones.  */
2153
 
2154
#define FUNCTION_ARG_REGNO_P(N)                                 \
2155
  ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST)                    \
2156
    || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST)))              \
2157
   && !fixed_regs[N])
2158
 
2159
/* This structure has to cope with two different argument allocation
2160
   schemes.  Most MIPS ABIs view the arguments as a structure, of which
2161
   the first N words go in registers and the rest go on the stack.  If I
2162
   < N, the Ith word might go in Ith integer argument register or in a
2163
   floating-point register.  For these ABIs, we only need to remember
2164
   the offset of the current argument into the structure.
2165
 
2166
   The EABI instead allocates the integer and floating-point arguments
2167
   separately.  The first N words of FP arguments go in FP registers,
2168
   the rest go on the stack.  Likewise, the first N words of the other
2169
   arguments go in integer registers, and the rest go on the stack.  We
2170
   need to maintain three counts: the number of integer registers used,
2171
   the number of floating-point registers used, and the number of words
2172
   passed on the stack.
2173
 
2174
   We could keep separate information for the two ABIs (a word count for
2175
   the standard ABIs, and three separate counts for the EABI).  But it
2176
   seems simpler to view the standard ABIs as forms of EABI that do not
2177
   allocate floating-point registers.
2178
 
2179
   So for the standard ABIs, the first N words are allocated to integer
2180
   registers, and mips_function_arg decides on an argument-by-argument
2181
   basis whether that argument should really go in an integer register,
2182
   or in a floating-point one.  */
2183
 
2184
typedef struct mips_args {
2185
  /* Always true for varargs functions.  Otherwise true if at least
2186
     one argument has been passed in an integer register.  */
2187
  int gp_reg_found;
2188
 
2189
  /* The number of arguments seen so far.  */
2190
  unsigned int arg_number;
2191
 
2192
  /* The number of integer registers used so far.  For all ABIs except
2193
     EABI, this is the number of words that have been added to the
2194
     argument structure, limited to MAX_ARGS_IN_REGISTERS.  */
2195
  unsigned int num_gprs;
2196
 
2197
  /* For EABI, the number of floating-point registers used so far.  */
2198
  unsigned int num_fprs;
2199
 
2200
  /* The number of words passed on the stack.  */
2201
  unsigned int stack_words;
2202
 
2203
  /* On the mips16, we need to keep track of which floating point
2204
     arguments were passed in general registers, but would have been
2205
     passed in the FP regs if this were a 32-bit function, so that we
2206
     can move them to the FP regs if we wind up calling a 32-bit
2207
     function.  We record this information in fp_code, encoded in base
2208
     four.  A zero digit means no floating point argument, a one digit
2209
     means an SFmode argument, and a two digit means a DFmode argument,
2210
     and a three digit is not used.  The low order digit is the first
2211
     argument.  Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2212
     an SFmode argument.  ??? A more sophisticated approach will be
2213
     needed if MIPS_ABI != ABI_32.  */
2214
  int fp_code;
2215
 
2216
  /* True if the function has a prototype.  */
2217
  int prototype;
2218
} CUMULATIVE_ARGS;
2219
 
2220
/* Initialize a variable CUM of type CUMULATIVE_ARGS
2221
   for a call to a function whose data type is FNTYPE.
2222
   For a library call, FNTYPE is 0.  */
2223
 
2224
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2225
  mips_init_cumulative_args (&CUM, FNTYPE)
2226
 
2227
#define FUNCTION_ARG_PADDING(MODE, TYPE) \
2228
  (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2229
 
2230
#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2231
  (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2232
 
2233
/* True if using EABI and varargs can be passed in floating-point
2234
   registers.  Under these conditions, we need a more complex form
2235
   of va_list, which tracks GPR, FPR and stack arguments separately.  */
2236
#define EABI_FLOAT_VARARGS_P \
2237
        (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2238
 
2239
 
2240
#define EPILOGUE_USES(REGNO)    mips_epilogue_uses (REGNO)
2241
 
2242
/* Treat LOC as a byte offset from the stack pointer and round it up
2243
   to the next fully-aligned offset.  */
2244
#define MIPS_STACK_ALIGN(LOC) \
2245
  (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2246
 
2247
 
2248
/* Output assembler code to FILE to increment profiler label # LABELNO
2249
   for profiling a function entry.  */
2250
 
2251
#define FUNCTION_PROFILER(FILE, LABELNO) mips_function_profiler ((FILE))
2252
 
2253
/* The profiler preserves all interesting registers, including $31.  */
2254
#define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2255
 
2256
/* No mips port has ever used the profiler counter word, so don't emit it
2257
   or the label for it.  */
2258
 
2259
#define NO_PROFILE_COUNTERS 1
2260
 
2261
/* Define this macro if the code for function profiling should come
2262
   before the function prologue.  Normally, the profiling code comes
2263
   after.  */
2264
 
2265
/* #define PROFILE_BEFORE_PROLOGUE */
2266
 
2267
/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2268
   the stack pointer does not matter.  The value is tested only in
2269
   functions that have frame pointers.
2270
   No definition is equivalent to always zero.  */
2271
 
2272
#define EXIT_IGNORE_STACK 1
2273
 
2274
 
2275
/* Trampolines are a block of code followed by two pointers.  */
2276
 
2277
#define TRAMPOLINE_SIZE \
2278
  (mips_trampoline_code_size () + GET_MODE_SIZE (ptr_mode) * 2)
2279
 
2280
/* Forcing a 64-bit alignment for 32-bit targets allows us to load two
2281
   pointers from a single LUI base.  */
2282
 
2283
#define TRAMPOLINE_ALIGNMENT 64
2284
 
2285
/* mips_trampoline_init calls this library function to flush
2286
   program and data caches.  */
2287
 
2288
#ifndef CACHE_FLUSH_FUNC
2289
#define CACHE_FLUSH_FUNC "_flush_cache"
2290
#endif
2291
 
2292
#define MIPS_ICACHE_SYNC(ADDR, SIZE)                                    \
2293
  /* Flush both caches.  We need to flush the data cache in case        \
2294
     the system has a write-back cache.  */                             \
2295
  emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2296
                     LCT_NORMAL, VOIDmode, 3, ADDR, Pmode, SIZE, Pmode, \
2297
                     GEN_INT (3), TYPE_MODE (integer_type_node))
2298
 
2299
 
2300
/* Addressing modes, and classification of registers for them.  */
2301
 
2302
#define REGNO_OK_FOR_INDEX_P(REGNO) 0
2303
#define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2304
  mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2305
 
2306
/* Maximum number of registers that can appear in a valid memory address.  */
2307
 
2308
#define MAX_REGS_PER_ADDRESS 1
2309
 
2310
/* Check for constness inline but use mips_legitimate_address_p
2311
   to check whether a constant really is an address.  */
2312
 
2313
#define CONSTANT_ADDRESS_P(X) \
2314
  (CONSTANT_P (X) && memory_address_p (SImode, X))
2315
 
2316
/* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2317
   'the start of the function that this code is output in'.  */
2318
 
2319
#define ASM_OUTPUT_LABELREF(FILE,NAME)  \
2320
  if (strcmp (NAME, "..CURRENT_FUNCTION") == 0)                         \
2321
    asm_fprintf ((FILE), "%U%s",                                        \
2322
                 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2323
  else                                                                  \
2324
    asm_fprintf ((FILE), "%U%s", (NAME))
2325
 
2326
/* Flag to mark a function decl symbol that requires a long call.  */
2327
#define SYMBOL_FLAG_LONG_CALL   (SYMBOL_FLAG_MACH_DEP << 0)
2328
#define SYMBOL_REF_LONG_CALL_P(X)                                       \
2329
  ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2330
 
2331
/* This flag marks functions that cannot be lazily bound.  */
2332
#define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1)
2333
#define SYMBOL_REF_BIND_NOW_P(RTX) \
2334
  ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0)
2335
 
2336
/* True if we're generating a form of MIPS16 code in which jump tables
2337
   are stored in the text section and encoded as 16-bit PC-relative
2338
   offsets.  This is only possible when general text loads are allowed,
2339
   since the table access itself will be an "lh" instruction.  */
2340
/* ??? 16-bit offsets can overflow in large functions.  */
2341
#define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2342
 
2343
#define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2344
 
2345
#define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? HImode : ptr_mode)
2346
 
2347
#define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2348
 
2349
/* Define this as 1 if `char' should by default be signed; else as 0.  */
2350
#ifndef DEFAULT_SIGNED_CHAR
2351
#define DEFAULT_SIGNED_CHAR 1
2352
#endif
2353
 
2354
/* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets,
2355
   we generally don't want to use them for copying arbitrary data.
2356
   A single N-word move is usually the same cost as N single-word moves.  */
2357
#define MOVE_MAX UNITS_PER_WORD
2358
#define MAX_MOVE_MAX 8
2359
 
2360
/* Define this macro as a C expression which is nonzero if
2361
   accessing less than a word of memory (i.e. a `char' or a
2362
   `short') is no faster than accessing a word of memory, i.e., if
2363
   such access require more than one instruction or if there is no
2364
   difference in cost between byte and (aligned) word loads.
2365
 
2366
   On RISC machines, it tends to generate better code to define
2367
   this as 1, since it avoids making a QI or HI mode register.
2368
 
2369
   But, generating word accesses for -mips16 is generally bad as shifts
2370
   (often extended) would be needed for byte accesses.  */
2371
#define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2372
 
2373
/* Standard MIPS integer shifts truncate the shift amount to the
2374
   width of the shifted operand.  However, Loongson vector shifts
2375
   do not truncate the shift amount at all.  */
2376
#define SHIFT_COUNT_TRUNCATED (!TARGET_LOONGSON_VECTORS)
2377
 
2378
/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2379
   is done just by pretending it is already truncated.  */
2380
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2381
  (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2382
 
2383
 
2384
/* Specify the machine mode that pointers have.
2385
   After generation of rtl, the compiler makes no further distinction
2386
   between pointers and any other objects of this machine mode.  */
2387
 
2388
#ifndef Pmode
2389
#define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2390
#endif
2391
 
2392
/* Give call MEMs SImode since it is the "most permissive" mode
2393
   for both 32-bit and 64-bit targets.  */
2394
 
2395
#define FUNCTION_MODE SImode
2396
 
2397
 
2398
 
2399
/* Define if copies to/from condition code registers should be avoided.
2400
 
2401
   This is needed for the MIPS because reload_outcc is not complete;
2402
   it needs to handle cases where the source is a general or another
2403
   condition code register.  */
2404
#define AVOID_CCMODE_COPIES
2405
 
2406
/* A C expression for the cost of a branch instruction.  A value of
2407
   1 is the default; other values are interpreted relative to that.  */
2408
 
2409
#define BRANCH_COST(speed_p, predictable_p) mips_branch_cost
2410
#define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2411
 
2412
/* If defined, modifies the length assigned to instruction INSN as a
2413
   function of the context in which it is used.  LENGTH is an lvalue
2414
   that contains the initially computed length of the insn and should
2415
   be updated with the correct length of the insn.  */
2416
#define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2417
  ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2418
 
2419
/* Return the asm template for a non-MIPS16 conditional branch instruction.
2420
   OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2421
   its operands.  */
2422
#define MIPS_BRANCH(OPCODE, OPERANDS) \
2423
  "%*" OPCODE "%?\t" OPERANDS "%/"
2424
 
2425
/* Return an asm string that forces INSN to be treated as an absolute
2426
   J or JAL instruction instead of an assembler macro.  */
2427
#define MIPS_ABSOLUTE_JUMP(INSN) \
2428
  (TARGET_ABICALLS_PIC2                                         \
2429
   ? ".option\tpic0\n\t" INSN "\n\t.option\tpic2"               \
2430
   : INSN)
2431
 
2432
/* Return the asm template for a call.  INSN is the instruction's mnemonic
2433
   ("j" or "jal"), OPERANDS are its operands, TARGET_OPNO is the operand
2434
   number of the target.  SIZE_OPNO is the operand number of the argument size
2435
   operand that can optionally hold the call attributes.  If SIZE_OPNO is not
2436
   -1 and the call is indirect, use the function symbol from the call
2437
   attributes to attach a R_MIPS_JALR relocation to the call.
2438
 
2439
   When generating GOT code without explicit relocation operators,
2440
   all calls should use assembly macros.  Otherwise, all indirect
2441
   calls should use "jr" or "jalr"; we will arrange to restore $gp
2442
   afterwards if necessary.  Finally, we can only generate direct
2443
   calls for -mabicalls by temporarily switching to non-PIC mode.  */
2444
#define MIPS_CALL(INSN, OPERANDS, TARGET_OPNO, SIZE_OPNO)       \
2445
  (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS                    \
2446
   ? "%*" INSN "\t%" #TARGET_OPNO "%/"                          \
2447
   : (REG_P (OPERANDS[TARGET_OPNO])                             \
2448
      && mips_get_pic_call_symbol (OPERANDS, SIZE_OPNO))        \
2449
   ? ("%*.reloc\t1f,R_MIPS_JALR,%" #SIZE_OPNO "\n"              \
2450
      "1:\t" INSN "r\t%" #TARGET_OPNO "%/")                     \
2451
   : REG_P (OPERANDS[TARGET_OPNO])                              \
2452
   ? "%*" INSN "r\t%" #TARGET_OPNO "%/"                         \
2453
   : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #TARGET_OPNO "%/"))
2454
 
2455
/* Control the assembler format that we output.  */
2456
 
2457
/* Output to assembler file text saying following lines
2458
   may contain character constants, extra white space, comments, etc.  */
2459
 
2460
#ifndef ASM_APP_ON
2461
#define ASM_APP_ON " #APP\n"
2462
#endif
2463
 
2464
/* Output to assembler file text saying following lines
2465
   no longer contain unusual constructs.  */
2466
 
2467
#ifndef ASM_APP_OFF
2468
#define ASM_APP_OFF " #NO_APP\n"
2469
#endif
2470
 
2471
#define REGISTER_NAMES                                                     \
2472
{ "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",            \
2473
  "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",           \
2474
  "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",           \
2475
  "$24",  "$25",  "$26",  "$27",  "$28",  "$sp",  "$fp",  "$31",           \
2476
  "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",           \
2477
  "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",          \
2478
  "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",          \
2479
  "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",          \
2480
  "hi",   "lo",   "",     "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",         \
2481
  "$fcc5","$fcc6","$fcc7","", "$cprestore", "$arg", "$frame", "$fakec",    \
2482
  "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",  \
2483
  "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2484
  "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2485
  "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2486
  "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",  \
2487
  "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2488
  "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2489
  "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2490
  "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",  \
2491
  "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2492
  "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2493
  "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2494
  "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2495
  "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2496
 
2497
/* List the "software" names for each register.  Also list the numerical
2498
   names for $fp and $sp.  */
2499
 
2500
#define ADDITIONAL_REGISTER_NAMES                                       \
2501
{                                                                       \
2502
  { "$29",      29 + GP_REG_FIRST },                                    \
2503
  { "$30",      30 + GP_REG_FIRST },                                    \
2504
  { "at",        1 + GP_REG_FIRST },                                    \
2505
  { "v0",        2 + GP_REG_FIRST },                                    \
2506
  { "v1",        3 + GP_REG_FIRST },                                    \
2507
  { "a0",        4 + GP_REG_FIRST },                                    \
2508
  { "a1",        5 + GP_REG_FIRST },                                    \
2509
  { "a2",        6 + GP_REG_FIRST },                                    \
2510
  { "a3",        7 + GP_REG_FIRST },                                    \
2511
  { "t0",        8 + GP_REG_FIRST },                                    \
2512
  { "t1",        9 + GP_REG_FIRST },                                    \
2513
  { "t2",       10 + GP_REG_FIRST },                                    \
2514
  { "t3",       11 + GP_REG_FIRST },                                    \
2515
  { "t4",       12 + GP_REG_FIRST },                                    \
2516
  { "t5",       13 + GP_REG_FIRST },                                    \
2517
  { "t6",       14 + GP_REG_FIRST },                                    \
2518
  { "t7",       15 + GP_REG_FIRST },                                    \
2519
  { "s0",       16 + GP_REG_FIRST },                                    \
2520
  { "s1",       17 + GP_REG_FIRST },                                    \
2521
  { "s2",       18 + GP_REG_FIRST },                                    \
2522
  { "s3",       19 + GP_REG_FIRST },                                    \
2523
  { "s4",       20 + GP_REG_FIRST },                                    \
2524
  { "s5",       21 + GP_REG_FIRST },                                    \
2525
  { "s6",       22 + GP_REG_FIRST },                                    \
2526
  { "s7",       23 + GP_REG_FIRST },                                    \
2527
  { "t8",       24 + GP_REG_FIRST },                                    \
2528
  { "t9",       25 + GP_REG_FIRST },                                    \
2529
  { "k0",       26 + GP_REG_FIRST },                                    \
2530
  { "k1",       27 + GP_REG_FIRST },                                    \
2531
  { "gp",       28 + GP_REG_FIRST },                                    \
2532
  { "sp",       29 + GP_REG_FIRST },                                    \
2533
  { "fp",       30 + GP_REG_FIRST },                                    \
2534
  { "ra",       31 + GP_REG_FIRST },                                    \
2535
  ALL_COP_ADDITIONAL_REGISTER_NAMES                                     \
2536
}
2537
 
2538
/* This is meant to be redefined in the host dependent files.  It is a
2539
   set of alternative names and regnums for mips coprocessors.  */
2540
 
2541
#define ALL_COP_ADDITIONAL_REGISTER_NAMES
2542
 
2543
#define DBR_OUTPUT_SEQEND(STREAM)                                       \
2544
do                                                                      \
2545
  {                                                                     \
2546
    /* Undo the effect of '%*'.  */                                     \
2547
    mips_pop_asm_switch (&mips_nomacro);                                \
2548
    mips_pop_asm_switch (&mips_noreorder);                              \
2549
    /* Emit a blank line after the delay slot for emphasis.  */         \
2550
    fputs ("\n", STREAM);                                               \
2551
  }                                                                     \
2552
while (0)
2553
 
2554
/* Use .loc directives for SDB line numbers.  */
2555
#define SDB_OUTPUT_SOURCE_LINE(STREAM, LINE)                    \
2556
  fprintf (STREAM, "\t.loc\t%d %d\n", num_source_filenames, LINE)
2557
 
2558
/* The MIPS implementation uses some labels for its own purpose.  The
2559
   following lists what labels are created, and are all formed by the
2560
   pattern $L[a-z].*.  The machine independent portion of GCC creates
2561
   labels matching:  $L[A-Z][0-9]+ and $L[0-9]+.
2562
 
2563
        LM[0-9]+        Silicon Graphics/ECOFF stabs label before each stmt.
2564
        $Lb[0-9]+       Begin blocks for MIPS debug support
2565
        $Lc[0-9]+       Label for use in s<xx> operation.
2566
        $Le[0-9]+       End blocks for MIPS debug support  */
2567
 
2568
#undef ASM_DECLARE_OBJECT_NAME
2569
#define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2570
  mips_declare_object (STREAM, NAME, "", ":\n")
2571
 
2572
/* Globalizing directive for a label.  */
2573
#define GLOBAL_ASM_OP "\t.globl\t"
2574
 
2575
/* This says how to define a global common symbol.  */
2576
 
2577
#define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2578
 
2579
/* This says how to define a local common symbol (i.e., not visible to
2580
   linker).  */
2581
 
2582
#ifndef ASM_OUTPUT_ALIGNED_LOCAL
2583
#define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2584
  mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2585
#endif
2586
 
2587
/* This says how to output an external.  It would be possible not to
2588
   output anything and let undefined symbol become external. However
2589
   the assembler uses length information on externals to allocate in
2590
   data/sdata bss/sbss, thereby saving exec time.  */
2591
 
2592
#undef ASM_OUTPUT_EXTERNAL
2593
#define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2594
  mips_output_external(STREAM,DECL,NAME)
2595
 
2596
/* This is how to declare a function name.  The actual work of
2597
   emitting the label is moved to function_prologue, so that we can
2598
   get the line number correctly emitted before the .ent directive,
2599
   and after any .file directives.  Define as empty so that the function
2600
   is not declared before the .ent directive elsewhere.  */
2601
 
2602
#undef ASM_DECLARE_FUNCTION_NAME
2603
#define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2604
 
2605
/* This is how to store into the string LABEL
2606
   the symbol_ref name of an internal numbered label where
2607
   PREFIX is the class of label and NUM is the number within the class.
2608
   This is suitable for output with `assemble_name'.  */
2609
 
2610
#undef ASM_GENERATE_INTERNAL_LABEL
2611
#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)                   \
2612
  sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2613
 
2614
/* Print debug labels as "foo = ." rather than "foo:" because they should
2615
   represent a byte pointer rather than an ISA-encoded address.  This is
2616
   particularly important for code like:
2617
 
2618
        $LFBxxx = .
2619
                .cfi_startproc
2620
                ...
2621
                .section .gcc_except_table,...
2622
                ...
2623
                .uleb128 foo-$LFBxxx
2624
 
2625
   The .uleb128 requies $LFBxxx to match the FDE start address, which is
2626
   likewise a byte pointer rather than an ISA-encoded address.
2627
 
2628
   At the time of writing, this hook is not used for the function end
2629
   label:
2630
 
2631
        $LFExxx:
2632
                .end foo
2633
 
2634
   But this doesn't matter, because GAS doesn't treat a pre-.end label
2635
   as a MIPS16 one anyway.  */
2636
 
2637
#define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM)                       \
2638
  fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
2639
 
2640
/* This is how to output an element of a case-vector that is absolute.  */
2641
 
2642
#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE)                          \
2643
  fprintf (STREAM, "\t%s\t%sL%d\n",                                     \
2644
           ptr_mode == DImode ? ".dword" : ".word",                     \
2645
           LOCAL_LABEL_PREFIX,                                          \
2646
           VALUE)
2647
 
2648
/* This is how to output an element of a case-vector.  We can make the
2649
   entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2650
   is supported.  */
2651
 
2652
#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL)              \
2653
do {                                                                    \
2654
  if (TARGET_MIPS16_SHORT_JUMP_TABLES)                                  \
2655
    fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n",                          \
2656
             LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL);       \
2657
  else if (TARGET_GPWORD)                                               \
2658
    fprintf (STREAM, "\t%s\t%sL%d\n",                                   \
2659
             ptr_mode == DImode ? ".gpdword" : ".gpword",               \
2660
             LOCAL_LABEL_PREFIX, VALUE);                                \
2661
  else if (TARGET_RTP_PIC)                                              \
2662
    {                                                                   \
2663
      /* Make the entry relative to the start of the function.  */      \
2664
      rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0);            \
2665
      fprintf (STREAM, "\t%s\t%sL%d-",                                  \
2666
               Pmode == DImode ? ".dword" : ".word",                    \
2667
               LOCAL_LABEL_PREFIX, VALUE);                              \
2668
      assemble_name (STREAM, XSTR (fnsym, 0));                           \
2669
      fprintf (STREAM, "\n");                                           \
2670
    }                                                                   \
2671
  else                                                                  \
2672
    fprintf (STREAM, "\t%s\t%sL%d\n",                                   \
2673
             ptr_mode == DImode ? ".dword" : ".word",                   \
2674
             LOCAL_LABEL_PREFIX, VALUE);                                \
2675
} while (0)
2676
 
2677
/* This is how to output an assembler line
2678
   that says to advance the location counter
2679
   to a multiple of 2**LOG bytes.  */
2680
 
2681
#define ASM_OUTPUT_ALIGN(STREAM,LOG)                                    \
2682
  fprintf (STREAM, "\t.align\t%d\n", (LOG))
2683
 
2684
/* This is how to output an assembler line to advance the location
2685
   counter by SIZE bytes.  */
2686
 
2687
#undef ASM_OUTPUT_SKIP
2688
#define ASM_OUTPUT_SKIP(STREAM,SIZE)                                    \
2689
  fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2690
 
2691
/* This is how to output a string.  */
2692
#undef ASM_OUTPUT_ASCII
2693
#define ASM_OUTPUT_ASCII mips_output_ascii
2694
 
2695
/* Output #ident as a in the read-only data section.  */
2696
#undef  ASM_OUTPUT_IDENT
2697
#define ASM_OUTPUT_IDENT(FILE, STRING)                                  \
2698
{                                                                       \
2699
  const char *p = STRING;                                               \
2700
  int size = strlen (p) + 1;                                            \
2701
  switch_to_section (readonly_data_section);                            \
2702
  assemble_string (p, size);                                            \
2703
}
2704
 
2705
/* Default to -G 8 */
2706
#ifndef MIPS_DEFAULT_GVALUE
2707
#define MIPS_DEFAULT_GVALUE 8
2708
#endif
2709
 
2710
/* Define the strings to put out for each section in the object file.  */
2711
#define TEXT_SECTION_ASM_OP     "\t.text"       /* instructions */
2712
#define DATA_SECTION_ASM_OP     "\t.data"       /* large data */
2713
 
2714
#undef READONLY_DATA_SECTION_ASM_OP
2715
#define READONLY_DATA_SECTION_ASM_OP    "\t.rdata"      /* read-only data */
2716
 
2717
#define ASM_OUTPUT_REG_PUSH(STREAM,REGNO)                               \
2718
do                                                                      \
2719
  {                                                                     \
2720
    fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n",                \
2721
             TARGET_64BIT ? "daddiu" : "addiu",                         \
2722
             reg_names[STACK_POINTER_REGNUM],                           \
2723
             reg_names[STACK_POINTER_REGNUM],                           \
2724
             TARGET_64BIT ? "sd" : "sw",                                \
2725
             reg_names[REGNO],                                          \
2726
             reg_names[STACK_POINTER_REGNUM]);                          \
2727
  }                                                                     \
2728
while (0)
2729
 
2730
#define ASM_OUTPUT_REG_POP(STREAM,REGNO)                                \
2731
do                                                                      \
2732
  {                                                                     \
2733
    mips_push_asm_switch (&mips_noreorder);                             \
2734
    fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n",                 \
2735
             TARGET_64BIT ? "ld" : "lw",                                \
2736
             reg_names[REGNO],                                          \
2737
             reg_names[STACK_POINTER_REGNUM],                           \
2738
             TARGET_64BIT ? "daddu" : "addu",                           \
2739
             reg_names[STACK_POINTER_REGNUM],                           \
2740
             reg_names[STACK_POINTER_REGNUM]);                          \
2741
    mips_pop_asm_switch (&mips_noreorder);                              \
2742
  }                                                                     \
2743
while (0)
2744
 
2745
/* How to start an assembler comment.
2746
   The leading space is important (the mips native assembler requires it).  */
2747
#ifndef ASM_COMMENT_START
2748
#define ASM_COMMENT_START " #"
2749
#endif
2750
 
2751
#undef SIZE_TYPE
2752
#define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2753
 
2754
#undef PTRDIFF_TYPE
2755
#define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2756
 
2757
/* The maximum number of bytes that can be copied by one iteration of
2758
   a movmemsi loop; see mips_block_move_loop.  */
2759
#define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \
2760
  (UNITS_PER_WORD * 4)
2761
 
2762
/* The maximum number of bytes that can be copied by a straight-line
2763
   implementation of movmemsi; see mips_block_move_straight.  We want
2764
   to make sure that any loop-based implementation will iterate at
2765
   least twice.  */
2766
#define MIPS_MAX_MOVE_BYTES_STRAIGHT \
2767
  (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
2768
 
2769
/* The base cost of a memcpy call, for MOVE_RATIO and friends.  These
2770
   values were determined experimentally by benchmarking with CSiBE.
2771
   In theory, the call overhead is higher for TARGET_ABICALLS (especially
2772
   for o32 where we have to restore $gp afterwards as well as make an
2773
   indirect call), but in practice, bumping this up higher for
2774
   TARGET_ABICALLS doesn't make much difference to code size.  */
2775
 
2776
#define MIPS_CALL_RATIO 8
2777
 
2778
/* Any loop-based implementation of movmemsi will have at least
2779
   MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
2780
   moves, so allow individual copies of fewer elements.
2781
 
2782
   When movmemsi is not available, use a value approximating
2783
   the length of a memcpy call sequence, so that move_by_pieces
2784
   will generate inline code if it is shorter than a function call.
2785
   Since move_by_pieces_ninsns counts memory-to-memory moves, but
2786
   we'll have to generate a load/store pair for each, halve the
2787
   value of MIPS_CALL_RATIO to take that into account.  */
2788
 
2789
#define MOVE_RATIO(speed)                               \
2790
  (HAVE_movmemsi                                        \
2791
   ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX            \
2792
   : MIPS_CALL_RATIO / 2)
2793
 
2794
#define MOVE_BY_PIECES_P(SIZE, ALIGN) \
2795
  mips_move_by_pieces_p (SIZE, ALIGN)
2796
 
2797
/* For CLEAR_RATIO, when optimizing for size, give a better estimate
2798
   of the length of a memset call, but use the default otherwise.  */
2799
 
2800
#define CLEAR_RATIO(speed)\
2801
  ((speed) ? 15 : MIPS_CALL_RATIO)
2802
 
2803
/* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
2804
   optimizing for size adjust the ratio to account for the overhead of
2805
   loading the constant and replicating it across the word.  */
2806
 
2807
#define SET_RATIO(speed) \
2808
  ((speed) ? 15 : MIPS_CALL_RATIO - 2)
2809
 
2810
#define STORE_BY_PIECES_P(SIZE, ALIGN) \
2811
  mips_store_by_pieces_p (SIZE, ALIGN)
2812
 
2813
#ifndef __mips16
2814
/* Since the bits of the _init and _fini function is spread across
2815
   many object files, each potentially with its own GP, we must assume
2816
   we need to load our GP.  We don't preserve $gp or $ra, since each
2817
   init/fini chunk is supposed to initialize $gp, and crti/crtn
2818
   already take care of preserving $ra and, when appropriate, $gp.  */
2819
#if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
2820
#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC)      \
2821
   asm (SECTION_OP "\n\
2822
        .set noreorder\n\
2823
        bal 1f\n\
2824
        nop\n\
2825
1:      .cpload $31\n\
2826
        .set reorder\n\
2827
        jal " USER_LABEL_PREFIX #FUNC "\n\
2828
        " TEXT_SECTION_ASM_OP);
2829
#endif /* Switch to #elif when we're no longer limited by K&R C.  */
2830
#if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
2831
   || (defined _ABI64 && _MIPS_SIM == _ABI64)
2832
#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC)      \
2833
   asm (SECTION_OP "\n\
2834
        .set noreorder\n\
2835
        bal 1f\n\
2836
        nop\n\
2837
1:      .set reorder\n\
2838
        .cpsetup $31, $2, 1b\n\
2839
        jal " USER_LABEL_PREFIX #FUNC "\n\
2840
        " TEXT_SECTION_ASM_OP);
2841
#endif
2842
#endif
2843
 
2844
#ifndef HAVE_AS_TLS
2845
#define HAVE_AS_TLS 0
2846
#endif
2847
 
2848
#ifndef USED_FOR_TARGET
2849
/* Information about ".set noFOO; ...; .set FOO" blocks.  */
2850
struct mips_asm_switch {
2851
  /* The FOO in the description above.  */
2852
  const char *name;
2853
 
2854
  /* The current block nesting level, or 0 if we aren't in a block.  */
2855
  int nesting_level;
2856
};
2857
 
2858
extern const enum reg_class mips_regno_to_class[];
2859
extern bool mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
2860
extern const char *current_function_file; /* filename current function is in */
2861
extern int num_source_filenames;        /* current .file # */
2862
extern struct mips_asm_switch mips_noreorder;
2863
extern struct mips_asm_switch mips_nomacro;
2864
extern struct mips_asm_switch mips_noat;
2865
extern int mips_dbx_regno[];
2866
extern int mips_dwarf_regno[];
2867
extern bool mips_split_p[];
2868
extern bool mips_split_hi_p[];
2869
extern bool mips_use_pcrel_pool_p[];
2870
extern const char *mips_lo_relocs[];
2871
extern const char *mips_hi_relocs[];
2872
extern enum processor mips_arch;        /* which cpu to codegen for */
2873
extern enum processor mips_tune;        /* which cpu to schedule for */
2874
extern int mips_isa;                    /* architectural level */
2875
extern const struct mips_cpu_info *mips_arch_info;
2876
extern const struct mips_cpu_info *mips_tune_info;
2877
extern bool mips_base_mips16;
2878
extern GTY(()) struct target_globals *mips16_globals;
2879
#endif
2880
 
2881
/* Enable querying of DFA units.  */
2882
#define CPU_UNITS_QUERY 1
2883
 
2884
#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS)      \
2885
  mips_final_prescan_insn (INSN, OPVEC, NOPERANDS)
2886
 
2887
/* As on most targets, we want the .eh_frame section to be read-only where
2888
   possible.  And as on most targets, this means two things:
2889
 
2890
     (a) Non-locally-binding pointers must have an indirect encoding,
2891
         so that the addresses in the .eh_frame section itself become
2892
         locally-binding.
2893
 
2894
     (b) A shared library's .eh_frame section must encode locally-binding
2895
         pointers in a relative (relocation-free) form.
2896
 
2897
   However, MIPS has traditionally not allowed directives like:
2898
 
2899
        .long   x-.
2900
 
2901
   in cases where "x" is in a different section, or is not defined in the
2902
   same assembly file.  We are therefore unable to emit the PC-relative
2903
   form required by (b) at assembly time.
2904
 
2905
   Fortunately, the linker is able to convert absolute addresses into
2906
   PC-relative addresses on our behalf.  Unfortunately, only certain
2907
   versions of the linker know how to do this for indirect pointers,
2908
   and for personality data.  We must fall back on using writable
2909
   .eh_frame sections for shared libraries if the linker does not
2910
   support this feature.  */
2911
#define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
2912
  (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr)
2913
 
2914
/* For switching between MIPS16 and non-MIPS16 modes.  */
2915
#define SWITCHABLE_TARGET 1
2916
 
2917
/* Several named MIPS patterns depend on Pmode.  These patterns have the
2918
   form <NAME>_si for Pmode == SImode and <NAME>_di for Pmode == DImode.
2919
   Add the appropriate suffix to generator function NAME and invoke it
2920
   with arguments ARGS.  */
2921
#define PMODE_INSN(NAME, ARGS) \
2922
  (Pmode == SImode ? NAME ## _si ARGS : NAME ## _di ARGS)

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