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;;  Mips.md          Machine Description for MIPS based processors

;;  Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,

;;  1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,

;;  2011, 2012

;;  Free Software Foundation, Inc.

;;  Contributed by   A. Lichnewsky, lich@inria.inria.fr

;;  Changes by       Michael Meissner, meissner@osf.org

;;  64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and

;;  Brendan Eich, brendan@microunity.com.

;; This file is part of GCC.

;; GCC is free software; you can redistribute it and/or modify

;; it under the terms of the GNU General Public License as published by

;; the Free Software Foundation; either version 3, or (at your option)

;; any later version.

;; GCC is distributed in the hope that it will be useful,

;; but WITHOUT ANY WARRANTY; without even the implied warranty of

;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

;; GNU General Public License for more details.

;; You should have received a copy of the GNU General Public License

;; along with GCC; see the file COPYING3.  If not see

;; .

(define_enum "processor" [

  r3000

  4kc

  4kp

  5kc

  5kf

  20kc

  24kc

  24kf2_1

  24kf1_1

  74kc

  74kf2_1

  74kf1_1

  74kf3_2

  loongson_2e

  loongson_2f

  loongson_3a

  m4k

  octeon

  octeon2

  r3900

  r6000

  r4000

  r4100

  r4111

  r4120

  r4130

  r4300

  r4600

  r4650

  r5000

  r5400

  r5500

  r7000

  r8000

  r9000

  r10000

  sb1

  sb1a

  sr71000

  xlr

])

(define_c_enum "unspec" [

  ;; Unaligned accesses.

  UNSPEC_LOAD_LEFT

  UNSPEC_LOAD_RIGHT

  UNSPEC_STORE_LEFT

  UNSPEC_STORE_RIGHT

  ;; Floating-point moves.

  UNSPEC_LOAD_LOW

  UNSPEC_LOAD_HIGH

  UNSPEC_STORE_WORD

  UNSPEC_MFHC1

  UNSPEC_MTHC1

  ;; HI/LO moves.

  UNSPEC_MFHI

  UNSPEC_MTHI

  UNSPEC_SET_HILO

  ;; GP manipulation.

  UNSPEC_LOADGP

  UNSPEC_COPYGP

  UNSPEC_MOVE_GP

  UNSPEC_POTENTIAL_CPRESTORE

  UNSPEC_CPRESTORE

  UNSPEC_RESTORE_GP

  UNSPEC_EH_RETURN

  UNSPEC_GP

  UNSPEC_SET_GOT_VERSION

  UNSPEC_UPDATE_GOT_VERSION

  ;; Symbolic accesses.

  UNSPEC_LOAD_CALL

  UNSPEC_LOAD_GOT

  UNSPEC_TLS_LDM

  UNSPEC_TLS_GET_TP

  UNSPEC_UNSHIFTED_HIGH

  ;; MIPS16 constant pools.

  UNSPEC_ALIGN

  UNSPEC_CONSTTABLE_INT

  UNSPEC_CONSTTABLE_FLOAT

  ;; Blockage and synchronisation.

  UNSPEC_BLOCKAGE

  UNSPEC_CLEAR_HAZARD

  UNSPEC_RDHWR

  UNSPEC_SYNCI

  UNSPEC_SYNC

  ;; Cache manipulation.

  UNSPEC_MIPS_CACHE

  UNSPEC_R10K_CACHE_BARRIER

  ;; Interrupt handling.

  UNSPEC_ERET

  UNSPEC_DERET

  UNSPEC_DI

  UNSPEC_EHB

  UNSPEC_RDPGPR

  UNSPEC_COP0

  ;; Used in a call expression in place of args_size.  It's present for PIC

  ;; indirect calls where it contains args_size and the function symbol.

  UNSPEC_CALL_ATTR

])

(define_constants

  [(TLS_GET_TP_REGNUM           3)

   (PIC_FUNCTION_ADDR_REGNUM    25)

   (RETURN_ADDR_REGNUM          31)

   (CPRESTORE_SLOT_REGNUM       76)

   (GOT_VERSION_REGNUM          79)

   ;; PIC long branch sequences are never longer than 100 bytes.

   (MAX_PIC_BRANCH_LENGTH       100)

  ]

)

(include "predicates.md")

(include "constraints.md")

;; ....................

;;

;;      Attributes

;;

;; ....................

(define_attr "got" "unset,xgot_high,load"

  (const_string "unset"))

;; For jal instructions, this attribute is DIRECT when the target address

;; is symbolic and INDIRECT when it is a register.

(define_attr "jal" "unset,direct,indirect"

  (const_string "unset"))

;; This attribute is YES if the instruction is a jal macro (not a

;; real jal instruction).

;;

;; jal is always a macro for TARGET_CALL_CLOBBERED_GP because it includes

;; an instruction to restore $gp.  Direct jals are also macros for

;; !TARGET_ABSOLUTE_JUMPS because they first load the target address

;; into a register.

(define_attr "jal_macro" "no,yes"

  (cond [(eq_attr "jal" "direct")

         (symbol_ref "(TARGET_CALL_CLOBBERED_GP || !TARGET_ABSOLUTE_JUMPS

                       ? JAL_MACRO_YES : JAL_MACRO_NO)")

         (eq_attr "jal" "indirect")

         (symbol_ref "(TARGET_CALL_CLOBBERED_GP

                       ? JAL_MACRO_YES : JAL_MACRO_NO)")]

        (const_string "no")))

;; Classification of moves, extensions and truncations.  Most values

;; are as for "type" (see below) but there are also the following

;; move-specific values:

;;

;; constN       move an N-constraint integer into a MIPS16 register

;; sll0         "sll DEST,SRC,0", which on 64-bit targets is guaranteed

;;              to produce a sign-extended DEST, even if SRC is not

;;              properly sign-extended

;; ext_ins      EXT, DEXT, INS or DINS instruction

;; andi         a single ANDI instruction

;; loadpool     move a constant into a MIPS16 register by loading it

;;              from the pool

;; shift_shift  a shift left followed by a shift right

;; lui_movf     an LUI followed by a MOVF (for d<-z CC moves)

;;

;; This attribute is used to determine the instruction's length and

;; scheduling type.  For doubleword moves, the attribute always describes

;; the split instructions; in some cases, it is more appropriate for the

;; scheduling type to be "multi" instead.

(define_attr "move_type"

  "unknown,load,fpload,store,fpstore,mtc,mfc,mthilo,mfhilo,move,fmove,

   const,constN,signext,ext_ins,logical,arith,sll0,andi,loadpool,

   shift_shift,lui_movf"

  (const_string "unknown"))

(define_attr "alu_type" "unknown,add,sub,not,nor,and,or,xor"

  (const_string "unknown"))

;; Main data type used by the insn

(define_attr "mode" "unknown,none,QI,HI,SI,DI,TI,SF,DF,TF,FPSW"

  (const_string "unknown"))

;; True if the main data type is twice the size of a word.

(define_attr "dword_mode" "no,yes"

  (cond [(and (eq_attr "mode" "DI,DF")

              (not (match_test "TARGET_64BIT")))

         (const_string "yes")

         (and (eq_attr "mode" "TI,TF")

              (match_test "TARGET_64BIT"))

         (const_string "yes")]

        (const_string "no")))

;; Classification of each insn.

;; branch       conditional branch

;; jump         unconditional jump

;; call         unconditional call

;; load         load instruction(s)

;; fpload       floating point load

;; fpidxload    floating point indexed load

;; store        store instruction(s)

;; fpstore      floating point store

;; fpidxstore   floating point indexed store

;; prefetch     memory prefetch (register + offset)

;; prefetchx    memory indexed prefetch (register + register)

;; condmove     conditional moves

;; mtc          transfer to coprocessor

;; mfc          transfer from coprocessor

;; mthilo       transfer to hi/lo registers

;; mfhilo       transfer from hi/lo registers

;; const        load constant

;; arith        integer arithmetic instructions

;; logical      integer logical instructions

;; shift        integer shift instructions

;; slt          set less than instructions

;; signext      sign extend instructions

;; clz          the clz and clo instructions

;; pop          the pop instruction

;; trap         trap if instructions

;; imul         integer multiply 2 operands

;; imul3        integer multiply 3 operands

;; imul3nc      integer multiply 3 operands without clobbering HI/LO

;; imadd        integer multiply-add

;; idiv         integer divide 2 operands

;; idiv3        integer divide 3 operands

;; move         integer register move ({,D}ADD{,U} with rt = 0)

;; fmove        floating point register move

;; fadd         floating point add/subtract

;; fmul         floating point multiply

;; fmadd        floating point multiply-add

;; fdiv         floating point divide

;; frdiv        floating point reciprocal divide

;; frdiv1       floating point reciprocal divide step 1

;; frdiv2       floating point reciprocal divide step 2

;; fabs         floating point absolute value

;; fneg         floating point negation

;; fcmp         floating point compare

;; fcvt         floating point convert

;; fsqrt        floating point square root

;; frsqrt       floating point reciprocal square root

;; frsqrt1      floating point reciprocal square root step1

;; frsqrt2      floating point reciprocal square root step2

;; multi        multiword sequence (or user asm statements)

;; nop          no operation

;; ghost        an instruction that produces no real code

(define_attr "type"

  "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,

   prefetch,prefetchx,condmove,mtc,mfc,mthilo,mfhilo,const,arith,logical,

   shift,slt,signext,clz,pop,trap,imul,imul3,imul3nc,imadd,idiv,idiv3,move,

   fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,

   frsqrt,frsqrt1,frsqrt2,multi,nop,ghost"

  (cond [(eq_attr "jal" "!unset") (const_string "call")

         (eq_attr "got" "load") (const_string "load")

         (eq_attr "alu_type" "add,sub") (const_string "arith")

         (eq_attr "alu_type" "not,nor,and,or,xor") (const_string "logical")

         ;; If a doubleword move uses these expensive instructions,

         ;; it is usually better to schedule them in the same way

         ;; as the singleword form, rather than as "multi".

         (eq_attr "move_type" "load") (const_string "load")

         (eq_attr "move_type" "fpload") (const_string "fpload")

         (eq_attr "move_type" "store") (const_string "store")

         (eq_attr "move_type" "fpstore") (const_string "fpstore")

         (eq_attr "move_type" "mtc") (const_string "mtc")

         (eq_attr "move_type" "mfc") (const_string "mfc")

         (eq_attr "move_type" "mthilo") (const_string "mthilo")

         (eq_attr "move_type" "mfhilo") (const_string "mfhilo")

         ;; These types of move are always single insns.

         (eq_attr "move_type" "fmove") (const_string "fmove")

         (eq_attr "move_type" "loadpool") (const_string "load")

         (eq_attr "move_type" "signext") (const_string "signext")

         (eq_attr "move_type" "ext_ins") (const_string "arith")

         (eq_attr "move_type" "arith") (const_string "arith")

         (eq_attr "move_type" "logical") (const_string "logical")

         (eq_attr "move_type" "sll0") (const_string "shift")

         (eq_attr "move_type" "andi") (const_string "logical")

         ;; These types of move are always split.

         (eq_attr "move_type" "constN,shift_shift")

           (const_string "multi")

         ;; These types of move are split for doubleword modes only.

         (and (eq_attr "move_type" "move,const")

              (eq_attr "dword_mode" "yes"))

           (const_string "multi")

         (eq_attr "move_type" "move") (const_string "move")

         (eq_attr "move_type" "const") (const_string "const")]

        ;; We classify "lui_movf" as "unknown" rather than "multi"

        ;; because we don't split it.  FIXME: we should split instead.

        (const_string "unknown")))

;; Mode for conversion types (fcvt)

;; I2S          integer to float single (SI/DI to SF)

;; I2D          integer to float double (SI/DI to DF)

;; S2I          float to integer (SF to SI/DI)

;; D2I          float to integer (DF to SI/DI)

;; D2S          double to float single

;; S2D          float single to double

(define_attr "cnv_mode" "unknown,I2S,I2D,S2I,D2I,D2S,S2D"

  (const_string "unknown"))

;; Is this an extended instruction in mips16 mode?

(define_attr "extended_mips16" "no,yes"

  (if_then_else (ior (eq_attr "move_type" "sll0")

                     (eq_attr "type" "branch")

                     (eq_attr "jal" "direct"))

                (const_string "yes")

                (const_string "no")))

;; Attributes describing a sync loop.  These loops have the form:

;;

;;       if (RELEASE_BARRIER == YES) sync

;;    1: OLDVAL = *MEM

;;       if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2

;;       $TMP1 = OLDVAL & EXCLUSIVE_MASK

;;       $TMP2 = INSN1 (OLDVAL, INSN1_OP2)

;;       $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK)

;;       $AT |= $TMP1 | $TMP3

;;       if (!commit (*MEM = $AT)) goto 1.

;;         if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]

;;       sync

;;    2:

;;

;; where "$" values are temporaries and where the other values are

;; specified by the attributes below.  Values are specified as operand

;; numbers and insns are specified as enums.  If no operand number is

;; specified, the following values are used instead:

;;

;;    - OLDVAL: $AT

;;    - NEWVAL: $AT

;;    - INCLUSIVE_MASK: -1

;;    - REQUIRED_OLDVAL: OLDVAL & INCLUSIVE_MASK

;;    - EXCLUSIVE_MASK: 0

;;

;; MEM and INSN1_OP2 are required.

;;

;; Ideally, the operand attributes would be integers, with -1 meaning "none",

;; but the gen* programs don't yet support that.

(define_attr "sync_mem" "none,0,1,2,3,4,5" (const_string "none"))

(define_attr "sync_oldval" "none,0,1,2,3,4,5" (const_string "none"))

(define_attr "sync_newval" "none,0,1,2,3,4,5" (const_string "none"))

(define_attr "sync_inclusive_mask" "none,0,1,2,3,4,5" (const_string "none"))

(define_attr "sync_exclusive_mask" "none,0,1,2,3,4,5" (const_string "none"))

(define_attr "sync_required_oldval" "none,0,1,2,3,4,5" (const_string "none"))

(define_attr "sync_insn1_op2" "none,0,1,2,3,4,5" (const_string "none"))

(define_attr "sync_insn1" "move,li,addu,addiu,subu,and,andi,or,ori,xor,xori"

  (const_string "move"))

(define_attr "sync_insn2" "nop,and,xor,not"

  (const_string "nop"))

(define_attr "sync_release_barrier" "yes,no"

  (const_string "yes"))

;; Length of instruction in bytes.

(define_attr "length" ""

   (cond [(and (eq_attr "extended_mips16" "yes")

               (match_test "TARGET_MIPS16"))

          (const_int 8)

          ;; Direct branch instructions have a range of [-0x20000,0x1fffc],

          ;; relative to the address of the delay slot.  If a branch is

          ;; outside this range, we have a choice of two sequences.

          ;; For PIC, an out-of-range branch like:

          ;;

          ;;    bne     r1,r2,target

          ;;    dslot

          ;;

          ;; becomes the equivalent of:

          ;;

          ;;    beq     r1,r2,1f

          ;;    dslot

          ;;    la      $at,target

          ;;    jr      $at

          ;;    nop

          ;; 1:

          ;;

          ;; The non-PIC case is similar except that we use a direct

          ;; jump instead of an la/jr pair.  Since the target of this

          ;; jump is an absolute 28-bit bit address (the other bits

          ;; coming from the address of the delay slot) this form cannot

          ;; cross a 256MB boundary.  We could provide the option of

          ;; using la/jr in this case too, but we do not do so at

          ;; present.

          ;;

          ;; Note that this value does not account for the delay slot

          ;; instruction, whose length is added separately.  If the RTL

          ;; pattern has no explicit delay slot, mips_adjust_insn_length

          ;; will add the length of the implicit nop.  The values for

          ;; forward and backward branches will be different as well.

          (eq_attr "type" "branch")

          (cond [(and (le (minus (match_dup 0) (pc)) (const_int 131064))

                          (le (minus (pc) (match_dup 0)) (const_int 131068)))

                   (const_int 4)

                 ;; The non-PIC case: branch, first delay slot, and J.

                 (match_test "TARGET_ABSOLUTE_JUMPS")

                   (const_int 12)]

                 ;; Use MAX_PIC_BRANCH_LENGTH as a (gross) overestimate.

                 ;; mips_adjust_insn_length substitutes the correct length.

                 ;;

                 ;; Note that we can't simply use (symbol_ref ...) here

                 ;; because genattrtab needs to know the maximum length

                 ;; of an insn.

                 (const_int MAX_PIC_BRANCH_LENGTH))

          ;; "Ghost" instructions occupy no space.

          (eq_attr "type" "ghost")

          (const_int 0)

          (eq_attr "got" "load")

          (if_then_else (match_test "TARGET_MIPS16")

                        (const_int 8)

                        (const_int 4))

          (eq_attr "got" "xgot_high")

          (const_int 8)

          ;; In general, constant-pool loads are extended instructions.

          (eq_attr "move_type" "loadpool")

          (const_int 8)

          ;; LUI_MOVFs are decomposed into two separate instructions.

          (eq_attr "move_type" "lui_movf")

          (const_int 8)

          ;; SHIFT_SHIFTs are decomposed into two separate instructions.

          ;; They are extended instructions on MIPS16 targets.

          (eq_attr "move_type" "shift_shift")

          (if_then_else (match_test "TARGET_MIPS16")

                        (const_int 16)

                        (const_int 8))

          ;; Check for doubleword moves that are decomposed into two

          ;; instructions.

          (and (eq_attr "move_type" "mtc,mfc,mthilo,mfhilo,move")

               (eq_attr "dword_mode" "yes"))

          (const_int 8)

          ;; Doubleword CONST{,N} moves are split into two word

          ;; CONST{,N} moves.

          (and (eq_attr "move_type" "const,constN")

               (eq_attr "dword_mode" "yes"))

          (symbol_ref "mips_split_const_insns (operands[1]) * 4")

          ;; Otherwise, constants, loads and stores are handled by external

          ;; routines.

          (eq_attr "move_type" "const,constN")

          (symbol_ref "mips_const_insns (operands[1]) * 4")

          (eq_attr "move_type" "load,fpload")

          (symbol_ref "mips_load_store_insns (operands[1], insn) * 4")

          (eq_attr "move_type" "store,fpstore")

          (cond [(not (match_test "TARGET_FIX_24K"))

                 (symbol_ref "mips_load_store_insns (operands[0], insn) * 4")]

                 (symbol_ref "mips_load_store_insns (operands[0], insn) * 4 + 4"))

          ;; In the worst case, a call macro will take 8 instructions:

          ;;

          ;;     lui $25,%call_hi(FOO)

          ;;     addu $25,$25,$28

          ;;     lw $25,%call_lo(FOO)($25)

          ;;     nop

          ;;     jalr $25

          ;;     nop

          ;;     lw $gp,X($sp)

          ;;     nop

          (eq_attr "jal_macro" "yes")

          (const_int 32)

          ;; Various VR4120 errata require a nop to be inserted after a macc

          ;; instruction.  The assembler does this for us, so account for

          ;; the worst-case length here.

          (and (eq_attr "type" "imadd")

               (match_test "TARGET_FIX_VR4120"))

          (const_int 8)

          ;; VR4120 errata MD(4): if there are consecutive dmult instructions,

          ;; the result of the second one is missed.  The assembler should work

          ;; around this by inserting a nop after the first dmult.

          (and (eq_attr "type" "imul,imul3")

               (and (eq_attr "mode" "DI")

                    (match_test "TARGET_FIX_VR4120")))

          (const_int 8)

          (eq_attr "type" "idiv,idiv3")

          (symbol_ref "mips_idiv_insns () * 4")

          (not (eq_attr "sync_mem" "none"))

          (symbol_ref "mips_sync_loop_insns (insn, operands) * 4")

          ] (const_int 4)))

;; Attribute describing the processor.

(define_enum_attr "cpu" "processor"

  (const (symbol_ref "mips_tune")))

;; The type of hardware hazard associated with this instruction.

;; DELAY means that the next instruction cannot read the result

;; of this one.  HILO means that the next two instructions cannot

;; write to HI or LO.

(define_attr "hazard" "none,delay,hilo"

  (cond [(and (eq_attr "type" "load,fpload,fpidxload")

              (match_test "ISA_HAS_LOAD_DELAY"))

         (const_string "delay")

         (and (eq_attr "type" "mfc,mtc")

              (match_test "ISA_HAS_XFER_DELAY"))

         (const_string "delay")

         (and (eq_attr "type" "fcmp")

              (match_test "ISA_HAS_FCMP_DELAY"))

         (const_string "delay")

         ;; The r4000 multiplication patterns include an mflo instruction.

         (and (eq_attr "type" "imul")

              (match_test "TARGET_FIX_R4000"))

         (const_string "hilo")

         (and (eq_attr "type" "mfhilo")

              (not (match_test "ISA_HAS_HILO_INTERLOCKS")))

         (const_string "hilo")]

        (const_string "none")))

;; Is it a single instruction?

(define_attr "single_insn" "no,yes"

  (symbol_ref "(get_attr_length (insn) == (TARGET_MIPS16 ? 2 : 4)

                ? SINGLE_INSN_YES : SINGLE_INSN_NO)"))

;; Can the instruction be put into a delay slot?

(define_attr "can_delay" "no,yes"

  (if_then_else (and (eq_attr "type" "!branch,call,jump")

                     (and (eq_attr "hazard" "none")

                          (eq_attr "single_insn" "yes")))

                (const_string "yes")

                (const_string "no")))

;; Attribute defining whether or not we can use the branch-likely

;; instructions.

(define_attr "branch_likely" "no,yes"

  (if_then_else (match_test "GENERATE_BRANCHLIKELY")

                (const_string "yes")

                (const_string "no")))

;; True if an instruction might assign to hi or lo when reloaded.

;; This is used by the TUNE_MACC_CHAINS code.

(define_attr "may_clobber_hilo" "no,yes"

  (if_then_else (eq_attr "type" "imul,imul3,imadd,idiv,mthilo")

                (const_string "yes")

                (const_string "no")))

;; Describe a user's asm statement.

(define_asm_attributes

  [(set_attr "type" "multi")

   (set_attr "can_delay" "no")])

;; This mode iterator allows 32-bit and 64-bit GPR patterns to be generated

;; from the same template.

(define_mode_iterator GPR [SI (DI "TARGET_64BIT")])

;; A copy of GPR that can be used when a pattern has two independent

;; modes.

(define_mode_iterator GPR2 [SI (DI "TARGET_64BIT")])

;; This mode iterator allows :HILO to be used as the mode of the

;; concatenated HI and LO registers.

(define_mode_iterator HILO [(DI "!TARGET_64BIT") (TI "TARGET_64BIT")])

;; This mode iterator allows :P to be used for patterns that operate on

;; pointer-sized quantities.  Exactly one of the two alternatives will match.

(define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])

;; This mode iterator allows :MOVECC to be used anywhere that a

;; conditional-move-type condition is needed.

(define_mode_iterator MOVECC [SI (DI "TARGET_64BIT")

                              (CC "TARGET_HARD_FLOAT && !TARGET_LOONGSON_2EF")])

;; 32-bit integer moves for which we provide move patterns.

(define_mode_iterator IMOVE32

  [SI

   (V2HI "TARGET_DSP")

   (V4QI "TARGET_DSP")

   (V2HQ "TARGET_DSP")

   (V2UHQ "TARGET_DSP")

   (V2HA "TARGET_DSP")

   (V2UHA "TARGET_DSP")

   (V4QQ "TARGET_DSP")

   (V4UQQ "TARGET_DSP")])

;; 64-bit modes for which we provide move patterns.

(define_mode_iterator MOVE64

  [DI DF

   (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")

   (V2SI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")

   (V4HI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")

   (V8QI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")])

;; 128-bit modes for which we provide move patterns on 64-bit targets.

(define_mode_iterator MOVE128 [TI TF])

;; This mode iterator allows the QI and HI extension patterns to be

;; defined from the same template.

(define_mode_iterator SHORT [QI HI])

;; Likewise the 64-bit truncate-and-shift patterns.

(define_mode_iterator SUBDI [QI HI SI])

;; This mode iterator allows :ANYF to be used wherever a scalar or vector

;; floating-point mode is allowed.

(define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT")

                            (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")

                            (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")])

;; Like ANYF, but only applies to scalar modes.

(define_mode_iterator SCALARF [(SF "TARGET_HARD_FLOAT")

                               (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")])

;; A floating-point mode for which moves involving FPRs may need to be split.

(define_mode_iterator SPLITF

  [(DF "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")

   (DI "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")

   (V2SF "!TARGET_64BIT && TARGET_PAIRED_SINGLE_FLOAT")

   (V2SI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")

   (V4HI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")

   (V8QI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")

   (TF "TARGET_64BIT && TARGET_FLOAT64")])

;; In GPR templates, a string like "subu" will expand to "subu" in the

;; 32-bit version and "dsubu" in the 64-bit version.

(define_mode_attr d [(SI "") (DI "d")

                     (QQ "") (HQ "") (SQ "") (DQ "d")

                     (UQQ "") (UHQ "") (USQ "") (UDQ "d")

                     (HA "") (SA "") (DA "d")

                     (UHA "") (USA "") (UDA "d")])

;; Same as d but upper-case.

(define_mode_attr D [(SI "") (DI "D")

                     (QQ "") (HQ "") (SQ "") (DQ "D")

                     (UQQ "") (UHQ "") (USQ "") (UDQ "D")

                     (HA "") (SA "") (DA "D")

                     (UHA "") (USA "") (UDA "D")])

;; This attribute gives the length suffix for a load or store instruction.

;; The same suffixes work for zero and sign extensions.

(define_mode_attr size [(QI "b") (HI "h") (SI "w") (DI "d")])

(define_mode_attr SIZE [(QI "B") (HI "H") (SI "W") (DI "D")])

;; This attributes gives the mode mask of a SHORT.

(define_mode_attr mask [(QI "0x00ff") (HI "0xffff")])

;; Mode attributes for GPR loads.

(define_mode_attr load [(SI "lw") (DI "ld")])

;; Instruction names for stores.

(define_mode_attr store [(QI "sb") (HI "sh") (SI "sw") (DI "sd")])

;; Similarly for MIPS IV indexed FPR loads and stores.

(define_mode_attr loadx [(SF "lwxc1") (DF "ldxc1") (V2SF "ldxc1")])

(define_mode_attr storex [(SF "swxc1") (DF "sdxc1") (V2SF "sdxc1")])

;; The unextended ranges of the MIPS16 addiu and daddiu instructions

;; are different.  Some forms of unextended addiu have an 8-bit immediate

;; field but the equivalent daddiu has only a 5-bit field.

(define_mode_attr si8_di5 [(SI "8") (DI "5")])

;; This attribute gives the best constraint to use for registers of

;; a given mode.

(define_mode_attr reg [(SI "d") (DI "d") (CC "z")])

;; This attribute gives the format suffix for floating-point operations.

(define_mode_attr fmt [(SF "s") (DF "d") (V2SF "ps")])

;; This attribute gives the upper-case mode name for one unit of a

;; floating-point mode.

(define_mode_attr UNITMODE [(SF "SF") (DF "DF") (V2SF "SF")])

;; This attribute gives the integer mode that has the same size as a

;; fixed-point mode.

(define_mode_attr IMODE [(QQ "QI") (HQ "HI") (SQ "SI") (DQ "DI")

                         (UQQ "QI") (UHQ "HI") (USQ "SI") (UDQ "DI")

                         (HA "HI") (SA "SI") (DA "DI")

                         (UHA "HI") (USA "SI") (UDA "DI")

                         (V4UQQ "SI") (V2UHQ "SI") (V2UHA "SI")

                         (V2HQ "SI") (V2HA "SI")])

;; This attribute gives the integer mode that has half the size of

;; the controlling mode.

(define_mode_attr HALFMODE [(DF "SI") (DI "SI") (V2SF "SI")

                            (V2SI "SI") (V4HI "SI") (V8QI "SI")

                            (TF "DI")])

;; This attribute works around the early SB-1 rev2 core "F2" erratum:

;;

;; In certain cases, div.s and div.ps may have a rounding error

;; and/or wrong inexact flag.

;;

;; Therefore, we only allow div.s if not working around SB-1 rev2

;; errata or if a slight loss of precision is OK.

(define_mode_attr divide_condition

  [DF (SF "!TARGET_FIX_SB1 || flag_unsafe_math_optimizations")

   (V2SF "TARGET_SB1 && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)")])

;; This attribute gives the conditions under which SQRT.fmt instructions

;; can be used.

(define_mode_attr sqrt_condition

  [(SF "!ISA_MIPS1") (DF "!ISA_MIPS1") (V2SF "TARGET_SB1")])

;; This attribute gives the conditions under which RECIP.fmt and RSQRT.fmt

;; instructions can be used.  The MIPS32 and MIPS64 ISAs say that RECIP.D

;; and RSQRT.D are unpredictable when doubles are stored in pairs of FPRs,

;; so for safety's sake, we apply this restriction to all targets.

(define_mode_attr recip_condition

  [(SF "ISA_HAS_FP4")

   (DF "ISA_HAS_FP4 && TARGET_FLOAT64")

   (V2SF "TARGET_SB1")])

;; This code iterator allows signed and unsigned widening multiplications

;; to use the same template.

(define_code_iterator any_extend [sign_extend zero_extend])

;; This code iterator allows the two right shift instructions to be

;; generated from the same template.

(define_code_iterator any_shiftrt [ashiftrt lshiftrt])

;; This code iterator allows the three shift instructions to be generated

;; from the same template.

(define_code_iterator any_shift [ashift ashiftrt lshiftrt])

;; This code iterator allows unsigned and signed division to be generated

;; from the same template.

(define_code_iterator any_div [div udiv])

;; This code iterator allows unsigned and signed modulus to be generated

;; from the same template.

(define_code_iterator any_mod [mod umod])

;; This code iterator allows all native floating-point comparisons to be

;; generated from the same template.

(define_code_iterator fcond [unordered uneq unlt unle eq lt le])

;; This code iterator is used for comparisons that can be implemented

;; by swapping the operands.

(define_code_iterator swapped_fcond [ge gt unge ungt])

;; Equality operators.

(define_code_iterator equality_op [eq ne])

;; These code iterators allow the signed and unsigned scc operations to use

;; the same template.

(define_code_iterator any_gt [gt gtu])

(define_code_iterator any_ge [ge geu])

(define_code_iterator any_lt [lt ltu])

(define_code_iterator any_le [le leu])

(define_code_iterator any_return [return simple_return])

;;  expands to an empty string when doing a signed operation and

;; "u" when doing an unsigned operation.

(define_code_attr u [(sign_extend "") (zero_extend "u")

                     (div "") (udiv "u")

                     (mod "") (umod "u")

                     (gt "") (gtu "u")

                     (ge "") (geu "u")

                     (lt "") (ltu "u")

                     (le "") (leu "u")])

;;  is like  except uppercase.

(define_code_attr U [(sign_extend "") (zero_extend "U")])

;;  is like , but the signed form expands to "s" rather than "".

(define_code_attr su [(sign_extend "s") (zero_extend "u")])

;;  expands to the name of the optab for a particular code.

(define_code_attr optab [(ashift "ashl")

                         (ashiftrt "ashr")

                         (lshiftrt "lshr")

                         (ior "ior")

                         (xor "xor")

                         (and "and")

                         (plus "add")

                         (minus "sub")

                         (return "return")

                         (simple_return "simple_return")])

;;  expands to the name of the insn that implements a particular code.

(define_code_attr insn [(ashift "sll")

                        (ashiftrt "sra")

                        (lshiftrt "srl")

                        (ior "or")

                        (xor "xor")

                        (and "and")

                        (plus "addu")

                        (minus "subu")])

;;  expands to the name of the insn that implements

;; a particular code to operate on immediate values.

(define_code_attr immediate_insn [(ior "ori")

                                  (xor "xori")

                                  (and "andi")])

;;  is the c.cond.fmt condition associated with a particular code.

(define_code_attr fcond [(unordered "un")

                         (uneq "ueq")

                         (unlt "ult")

                         (unle "ule")

                         (eq "eq")

                         (lt "lt")

                         (le "le")])

;; Similar, but for swapped conditions.

(define_code_attr swapped_fcond [(ge "le")

                                 (gt "lt")

                                 (unge "ule")

                                 (ungt "ult")])

;; The value of the bit when the branch is taken for branch_bit patterns.

;; Comparison is always against zero so this depends on the operator.

(define_code_attr bbv [(eq "0") (ne "1")])

;; This is the inverse value of bbv.

(define_code_attr bbinv [(eq "1") (ne "0")])

;; .........................

;;

;;      Branch, call and jump delay slots

;;

;; .........................

(define_delay (and (eq_attr "type" "branch")

                   (not (match_test "TARGET_MIPS16"))

                   (eq_attr "branch_likely" "yes"))

  [(eq_attr "can_delay" "yes")

   (nil)

   (eq_attr "can_delay" "yes")])

;; Branches that don't have likely variants do not annul on false.

(define_delay (and (eq_attr "type" "branch")

                   (not (match_test "TARGET_MIPS16"))

                   (eq_attr "branch_likely" "no"))

  [(eq_attr "can_delay" "yes")

   (nil)

   (nil)])

(define_delay (eq_attr "type" "jump")

  [(eq_attr "can_delay" "yes")

   (nil)

   (nil)])

(define_delay (and (eq_attr "type" "call")

                   (eq_attr "jal_macro" "no"))

  [(eq_attr "can_delay" "yes")

   (nil)

   (nil)])

;; Pipeline descriptions.

;;

;; generic.md provides a fallback for processors without a specific

;; pipeline description.  It is derived from the old define_function_unit

;; version and uses the "alu" and "imuldiv" units declared below.

;;

;; Some of the processor-specific files are also derived from old

;; define_function_unit descriptions and simply override the parts of

;; generic.md that don't apply.  The other processor-specific files

;; are self-contained.

(define_automaton "alu,imuldiv")

(define_cpu_unit "alu" "alu")

(define_cpu_unit "imuldiv" "imuldiv")

;; Ghost instructions produce no real code and introduce no hazards.

;; They exist purely to express an effect on dataflow.

(define_insn_reservation "ghost" 0

  (eq_attr "type" "ghost")

  "nothing")

(include "4k.md")

(include "5k.md")

(include "20kc.md")

(include "24k.md")

(include "74k.md")

(include "3000.md")

(include "4000.md")

(include "4100.md")

(include "4130.md")

(include "4300.md")

(include "4600.md")

(include "5000.md")

(include "5400.md")

(include "5500.md")

(include "6000.md")

(include "7000.md")

(include "9000.md")

(include "10000.md")

(include "loongson2ef.md")

(include "loongson3a.md")

(include "octeon.md")

(include "sb1.md")

(include "sr71k.md")

(include "xlr.md")

(include "generic.md")

;;

;;  ....................

;;

;;      CONDITIONAL TRAPS

;;

;;  ....................